JP2008098624A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Semiconductor apparatus and manufacturing method thereof Download PDF

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JP2008098624A
JP2008098624A JP2007235676A JP2007235676A JP2008098624A JP 2008098624 A JP2008098624 A JP 2008098624A JP 2007235676 A JP2007235676 A JP 2007235676A JP 2007235676 A JP2007235676 A JP 2007235676A JP 2008098624 A JP2008098624 A JP 2008098624A
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layer
concentration drain
concentration
drain layer
insulating film
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JP5431663B2 (en
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Toshisuke Yatsuyanagi
俊祐 八柳
Masabumi Uehara
正文 上原
Katsuyoshi Anzai
勝義 安齊
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor structure capable of improving an ESD resistance. <P>SOLUTION: In the semiconductor apparatus, a drain layer 12 with high concentration is formed apart from an edge of drain side of a gate electrode 7 on a surface of a drain layer 10 with intermediate concentration. A P-type impurity layer 13 is formed on a surface of a substrate between the gate electrode 7 and the drain layer 12 with high concentration so as to surround the drain layer 12 with high concentration. During a parasitic bipolar transistor 30 turns on due to abnormal surge voltage, electrons move from a source electrode 15 side to a drain electrode 16 side. In this case, electrons avoid the vicinity of the surface of the substrate X on which the P-type impurity layer 13 is formed, as shown by the arrow 25 in Fig. 4, electrons are dispersed and moved so as to infiltrate into a side of drain electrode 16 from deeper location. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置及びその製造方法に関し、特に、高耐圧ＭＯＳトランジスタ及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a high voltage MOS transistor and a manufacturing method thereof.

高耐圧ＭＯＳトランジスタは、高いソース・ドレイン耐圧(BVDS)，あるいは高いゲート耐圧を有しており、ＬＣＤドライバー，ＥＬドライバー等の各種のドライバーや電源回路等に広く用いられている。   High breakdown voltage MOS transistors have a high source / drain breakdown voltage (BVDS) or a high gate breakdown voltage, and are widely used in various drivers such as LCD drivers and EL drivers, power supply circuits, and the like.

図６は、従来例に係るＮチャネル型の高耐圧ＭＯＳトランジスタの構造を示す断面図である。Ｐ型の半導体基板１００の表面にゲート絶縁膜１０１，厚いフィールド絶縁膜１０２が形成されている。ゲート絶縁膜１０１上から、隣接するフィールド絶縁膜１０２の一部上にはゲート電極１０３が形成されている。半導体基板１００の表面領域には、ゲート電極１０３の一方の端に隣接して高濃度（Ｎ＋＋型）のソース層１０４及び低濃度のソース層１０５が形成されている。   FIG. 6 is a cross-sectional view showing the structure of an N-channel high voltage MOS transistor according to a conventional example. A gate insulating film 101 and a thick field insulating film 102 are formed on the surface of a P-type semiconductor substrate 100. A gate electrode 103 is formed on the gate insulating film 101 and on a part of the adjacent field insulating film 102. In the surface region of the semiconductor substrate 100, a high concentration (N ++ type) source layer 104 and a low concentration source layer 105 are formed adjacent to one end of the gate electrode 103.

また、ゲート電極１０３の他方の端から離間した半導体基板１００の表面には高濃度（Ｎ＋＋型）のドレイン層１０６が形成されている。また、ゲート電極１０３の下方からフィールド絶縁膜１０２及び高濃度のドレイン層１０６の下方に至る領域には、高濃度のドレイン層１０６よりも濃度が低く、深くまで拡散した低濃度（Ｎ−型）のドレイン層１０７が形成されている。高濃度のドレイン層１０６は低濃度のドレイン層１０７内に形成されている。このように、ソース領域及びドレイン領域が高濃度部分と低濃度部分とから構成されたいわゆるＬＤＤ(Lightly Doped Drain)構造になっている。また、ゲート電極１０３の側壁には、シリコン窒化膜等のサイドウォールスペーサ膜１０８が形成されている。   A high concentration (N ++ type) drain layer 106 is formed on the surface of the semiconductor substrate 100 spaced from the other end of the gate electrode 103. Further, in a region extending from below the gate electrode 103 to below the field insulating film 102 and the high-concentration drain layer 106, the concentration is lower than that of the high-concentration drain layer 106, and the low concentration (N-type) diffused deeply. The drain layer 107 is formed. The high concentration drain layer 106 is formed in the low concentration drain layer 107. Thus, the source region and the drain region have a so-called LDD (Lightly Doped Drain) structure in which a high concentration portion and a low concentration portion are configured. A sidewall spacer film 108 such as a silicon nitride film is formed on the sidewall of the gate electrode 103.

上述した従来の高耐圧ＭＯＳトランジスタでは、高濃度のドレイン層１０６に高電圧を印加した場合に、低濃度のドレイン層１０７の中に空乏層が広がることでドレイン電界が緩和されるため、高いソース・ドレイン耐圧を得ることができる。また、ゲート電極１０３はゲート絶縁膜１０１から隣接するフィールド絶縁膜１０２の一部上に延在しているため、ゲート絶縁膜１０１の破壊にも強い構造を有している。   In the conventional high-voltage MOS transistor described above, when a high voltage is applied to the high-concentration drain layer 106, the depletion layer spreads in the low-concentration drain layer 107, so that the drain electric field is relaxed. -A drain breakdown voltage can be obtained. Further, since the gate electrode 103 extends from the gate insulating film 101 onto a part of the adjacent field insulating film 102, the gate electrode 103 has a structure that is resistant to the breakdown of the gate insulating film 101.

なお、本発明に関連する技術は、以下の特許文献に記載されている。
特開２００２−１３４７３８号公報 The technique related to the present invention is described in the following patent documents.
JP 2002-134738 A

しかしながら、上述した従来のトランジスタ構造では、静電破壊耐量（以下、ＥＳＤ耐量という）が十分でないという問題があった。例えば、本発明者が行ったヒューマンボディモデル（ＨＢＭ）に基づく一般的な静電破壊試験によれば２００ボルト（Ｖ）未満のＥＳＤ耐量であり、マシーンモデル（ＭＭ）に基づく静電破壊試験では５０ボルト（Ｖ）未満のＥＳＤ耐量であり、これでは不十分であった。そこで、本発明はＥＳＤ耐量を向上させたトランジスタ構造を提供することを目的とする。   However, the conventional transistor structure described above has a problem that the electrostatic breakdown resistance (hereinafter referred to as ESD resistance) is not sufficient. For example, according to a general electrostatic breakdown test based on the human body model (HBM) conducted by the present inventor, the ESD resistance is less than 200 volts (V). In the electrostatic breakdown test based on the machine model (MM), The ESD resistance was less than 50 volts (V), which was insufficient. Therefore, an object of the present invention is to provide a transistor structure with improved ESD tolerance.

本発明の主な特徴は以下のとおりである。すなわち、本発明の半導体装置は、第１導電型の半導体層の表面に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、前記半導体層の表面に形成された第２導電型のソース層と、前記ゲート電極のドレイン側の端部から離間し、前記半導体層の表面に形成された第２導電型の高濃度のドレイン層と、前記ゲート電極と前記高濃度のドレイン層との間における前記半導体層の表面に、前記高濃度のドレイン層に隣接する第１導電型の不純物層とを備えることを特徴とする。   The main features of the present invention are as follows. That is, the semiconductor device of the present invention includes a gate insulating film formed on the surface of the first conductivity type semiconductor layer, a gate electrode formed on the gate insulating film, and a first electrode formed on the surface of the semiconductor layer. A second conductivity type source layer, a second conductivity type high-concentration drain layer formed on the surface of the semiconductor layer and spaced from an end of the gate electrode on the drain side, the gate electrode and the high concentration An impurity layer of a first conductivity type adjacent to the high concentration drain layer is provided on the surface of the semiconductor layer between the drain layer and the drain layer.

また、本発明の半導体装置の製造方法は、第１導電型の半導体層の表面上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上にゲート電極を形成する工程と、前記ゲート電極から離間した前記半導体層の表面に第２導電型の高濃度のドレイン層を形成する工程と、第１導電型の不純物層を、前記高濃度のドレイン層に隣接させて、前記半導体層の表面に形成する工程とを有することを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: forming a gate insulating film on a surface of a first conductivity type semiconductor layer; forming a gate electrode on the gate insulating film; Forming a second conductive type high-concentration drain layer on the surface of the semiconductor layer that is spaced apart; and adhering a first conductive type impurity layer adjacent to the high-concentration drain layer on the surface of the semiconductor layer. And a step of forming.

本発明では、ゲート電極と高濃度のドレイン層との間における半導体層の表面に、高濃度のドレイン層に隣接した、当該ドレイン層と逆導電型の不純物層が形成されている。このように構成することで、異常なサージが発生したときの電子は、前記不純物層が形成された付近を避けるようにして移動し、より深い位置からドレイン電極へと回り込む。つまり、半導体層の表面付近の電子の移動が抑えられる。そのため、ＥＳＤ耐量を向上させることができる。   In the present invention, on the surface of the semiconductor layer between the gate electrode and the high concentration drain layer, an impurity layer having a conductivity type opposite to that of the drain layer is formed adjacent to the high concentration drain layer. With this configuration, electrons when an abnormal surge occurs move so as to avoid the vicinity where the impurity layer is formed, and wrap around from the deeper position to the drain electrode. That is, the movement of electrons near the surface of the semiconductor layer is suppressed. Therefore, ESD tolerance can be improved.

次に、本発明の実施形態に係る半導体装置について図面を参照しながら説明する。図１乃至図４は、本発明の実施形態に係る半導体装置を製造工程順に示す断面図である。   Next, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 1 to 4 are sectional views showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

まず、図１に示すように、Ｐ型の半導体基板１の表面にＮ型不純物を注入し、熱拡散させることでＮ型のウェル層２（ＮＷ）を形成する。当該イオン注入は、例えばリンイオン（３１Ｐ＋）を加速電圧８０ＫｅＶ，注入量１．０×１０１３／ｃｍ２の条件で行う。なお、本発明では、前記Ｎ型のウェル層２（ＮＷ）の形成を省略するものであっても構わない。 First, as shown in FIG. 1, an N-type well layer 2 (NW) is formed by implanting an N-type impurity into the surface of a P-type semiconductor substrate 1 and thermally diffusing it. The ion implantation is performed, for example, using phosphorus ions ( 31 P + ) under the conditions of an acceleration voltage of 80 KeV and an implantation amount of 1.0 × 10 13 / cm 2 . In the present invention, the formation of the N-type well layer 2 (NW) may be omitted.

次に、ウェル層２の表面にＰ型不純物を注入し、熱拡散させることでＰ型のウェル層３（ＰＷ）を形成する。当該イオン注入は、例えばボロンイオン（１１Ｂ＋）を加速電圧８０ＫｅＶ，注入量２．３×１０１３／ｃｍ２の条件で行う。 Next, P-type impurities are implanted into the surface of the well layer 2 and thermally diffused to form a P-type well layer 3 (PW). The ion implantation is performed, for example, using boron ions ( 11 B + ) under the conditions of an acceleration voltage of 80 KeV and an implantation amount of 2.3 × 10 13 / cm 2 .

次に、ウェル層３の表面にＮ型不純物を選択的に注入することで、低濃度（Ｎ−型）のドレイン層４ａ，４ｂを形成する。低濃度のドレイン層４ａ，４ｂの間は離間している。すなわち、ドレイン層４ａ，４ｂの間にはイオン注入がなされないように所定のマスクを用いて当該イオン注入が行われる。このイオン注入は、例えばリンイオン（３１Ｐ＋）を加速電圧１００ＫｅＶ，注入量１．５×１０１３／ｃｍ２の条件で行う。 Next, by selectively injecting N-type impurities into the surface of the well layer 3, low concentration (N− type) drain layers 4a and 4b are formed. The low concentration drain layers 4a and 4b are spaced apart. That is, the ion implantation is performed using a predetermined mask so that the ion implantation is not performed between the drain layers 4a and 4b. This ion implantation is performed, for example, with phosphorus ions ( 31 P + ) under the conditions of an acceleration voltage of 100 KeV and an implantation amount of 1.5 × 10 13 / cm 2 .

次に、図２に示すように、ＬＯＣＯＳ（Ｌｏｃａｌ Ｏｘｉｄａｔｉｏｎ Ｏｆ Ｓｉｌｉｃｏｎ）法を用いて、ウェル層３の所定領域上に厚いフィールド絶縁膜５ａ，５ｂ，５ｃを形成する。このうちフィールド絶縁膜５ａ，５ｂはそれぞれ低濃度のドレイン層４ａ，４ｂと重畳した領域に形成されている。フィールド絶縁膜は一般に素子分離用に形成されるが、この半導体装置におけるフィールド絶縁膜５ａ，５ｂはトランジスタの耐圧向上に利用されている。フィールド絶縁膜５ａ，５ｂ，５ｃの膜厚は目標耐圧によって異なるが、例えば３００ｎｍ〜６００ｎｍ程度である。なお、フィールド絶縁膜の形成はＬＯＣＯＳ法に限定されず、例えばＳＴＩ（Ｓｈａｌｌｏｗ Ｔｒｅｎｃｈ Ｉｓｏｌａｔｉｏｎ）法を含め他の素子分離法を用いてもよい。   Next, as shown in FIG. 2, thick field insulating films 5a, 5b, and 5c are formed on a predetermined region of the well layer 3 by using a LOCOS (Local Oxidation Of Silicon) method. Of these, the field insulating films 5a and 5b are formed in regions overlapping the low-concentration drain layers 4a and 4b, respectively. The field insulating film is generally formed for element isolation, but the field insulating films 5a and 5b in this semiconductor device are used to improve the breakdown voltage of the transistor. The film thickness of the field insulating films 5a, 5b, and 5c varies depending on the target breakdown voltage, but is about 300 nm to 600 nm, for example. The formation of the field insulating film is not limited to the LOCOS method, and other element isolation methods including, for example, an STI (Shallow Trench Isolation) method may be used.

次に、例えば熱酸化法によりゲート絶縁膜６を形成する。ゲート絶縁膜６の膜厚は目標耐圧によって異なるが例えば１５〜２００ｎｍ程度である。なお、フィールド絶縁膜５ａ，５ｂ，５ｃは、ゲート絶縁膜６よりも厚い絶縁膜である。   Next, the gate insulating film 6 is formed by, eg, thermal oxidation. The thickness of the gate insulating film 6 varies depending on the target breakdown voltage, but is about 15 to 200 nm, for example. The field insulating films 5a, 5b, and 5c are insulating films thicker than the gate insulating film 6.

次に、半導体基板１上の全面に導電材料としてポリシリコン層を例えばＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法により形成する。その後、当該ポリシリコン層及びゲート絶縁膜６を選択的に除去することで、ゲート電極７を形成する。ゲート電極７は、ゲート絶縁膜６上から隣接するフィールド絶縁膜５ａの一部上に延在するようにパターニングされる。これによって耐圧が向上する。その膜厚は例えば３００ｎｍである。なお、必要に応じてリンイオン等の不純物を注入して拡散させることで、ゲート電極７を低抵抗化させる。   Next, a polysilicon layer as a conductive material is formed on the entire surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, the polysilicon layer and the gate insulating film 6 are selectively removed to form the gate electrode 7. The gate electrode 7 is patterned so as to extend from the gate insulating film 6 onto a part of the adjacent field insulating film 5a. This improves the breakdown voltage. The film thickness is, for example, 300 nm. Note that the resistance of the gate electrode 7 is reduced by injecting and diffusing impurities such as phosphorus ions as necessary.

次に、ゲート電極７をマスクの一部として、ゲート電極７の左側のウェル層３の表面領域にＮ型不純物を注入し、低濃度のソース層８（ＬＮ）を形成する。このイオン注入は、例えばリンイオン（３１Ｐ＋）を加速電圧２０ＫｅＶ，注入量４．２×１０１３／ｃｍ２の条件で行う。なお、低濃度のソース層８の形成は、後述するサイドウォールスペーサ膜９ａ，９ｂの形成後であってもよい。 Next, using the gate electrode 7 as a part of the mask, an N-type impurity is implanted into the surface region of the well layer 3 on the left side of the gate electrode 7 to form a low concentration source layer 8 (LN). This ion implantation is performed, for example, using phosphorus ions ( 31 P + ) under the conditions of an acceleration voltage of 20 KeV and an implantation amount of 4.2 × 10 13 / cm 2 . Note that the low-concentration source layer 8 may be formed after formation of sidewall spacer films 9a and 9b described later.

次に、図３（ａ）に示すように、半導体基板１上の全面に例えばシリコン窒化膜をＣＶＤ法により形成し、次に当該シリコン窒化膜をエッチバックすることで、ゲート電極７の周囲を囲むサイドウォールスペーサ膜９ａ，９ｂを形成する。なお、前記シリコン窒化膜に代えて、例えばＴＥＯＳ膜等から成るシリコン酸化膜をＣＶＤ法により形成するものでも良い。また、当該サイドウォールスペーサ膜９ａ，９ｂがポリシリコン等の導電材料から成る場合にはゲート電極７とサイドウォールスペーサ膜９ａ，９ｂの全体がゲート電極となる。   Next, as shown in FIG. 3A, for example, a silicon nitride film is formed on the entire surface of the semiconductor substrate 1 by the CVD method, and then the silicon nitride film is etched back so that the periphery of the gate electrode 7 is formed. Surrounding sidewall spacer films 9a and 9b are formed. Instead of the silicon nitride film, a silicon oxide film made of, for example, a TEOS film or the like may be formed by a CVD method. When the sidewall spacer films 9a and 9b are made of a conductive material such as polysilicon, the gate electrode 7 and the entire sidewall spacer films 9a and 9b are gate electrodes.

次に、不図示のホトレジスト層およびフィールド絶縁膜５ａ，５ｂをマスクとして、フィールド絶縁膜５ａ，５ｂで囲まれたウェル層３の表面領域にＮ型不純物を注入し、低濃度のドレイン層４ａ，４ｂよりも高い不純物濃度であり、かつ深くまで不純物が注入された中濃度のドレイン層１０（Ｎ）を形成する。中濃度のドレイン層１０は、低濃度のドレイン層４ａ，４ｂと隣接する。このイオン注入は、例えばリンイオン（３１Ｐ＋）を加速電圧１０００ＫｅＶ，注入量８．０×１０１３／ｃｍ２の条件で行う。なお、中濃度のドレイン層１０と低濃度のドレイン層４ａ，４ｂとは離間していてもよいし、一部重畳していてもよい。 Next, N-type impurities are implanted into the surface region of the well layer 3 surrounded by the field insulating films 5a and 5b using a photoresist layer (not shown) and the field insulating films 5a and 5b as masks, and the low-concentration drain layers 4a and 5b are formed. An intermediate concentration drain layer 10 (N) having an impurity concentration higher than 4b and deeply doped with impurities is formed. The medium concentration drain layer 10 is adjacent to the low concentration drain layers 4a and 4b. This ion implantation is performed, for example, using phosphorus ions ( 31 P + ) under the conditions of an acceleration voltage of 1000 KeV and an implantation amount of 8.0 × 10 13 / cm 2 . The medium concentration drain layer 10 and the low concentration drain layers 4a and 4b may be separated from each other, or may be partially overlapped.

次に、不図示のホトレジスト層及びサイドウォールスペーサ膜９ａをマスクとしてＮ型不純物を注入し、低濃度のソース層８と重畳する領域に高濃度のソース層１１（Ｎ＋）を形成するとともに、中濃度のドレイン層１０と重畳する領域に高濃度のドレイン層１２（Ｎ＋）を形成する。このイオン注入は、例えばヒ素イオン（７５Ａｓ＋）を加速電圧１００ＫｅＶ，注入量５．０×１０１３／ｃｍ２の条件で行う。高濃度のドレイン層１２は、中濃度のドレイン層１０の表面の全面に形成されるのではなく、図３（ａ）（ｂ）に示すようにフィールド絶縁膜５ａ，５ｂとは離間し、後述するドレイン電極１６が形成される領域の近傍に形成される。なお、図３（ｂ）は、図３（ａ）のフィールド絶縁膜５ａ，５ｂや高濃度のドレイン層１２の形成領域を示す部分平面図である。 Next, N-type impurities are implanted using a photoresist layer and sidewall spacer film 9a (not shown) as a mask to form a high concentration source layer 11 (N +) in a region overlapping with the low concentration source layer 8, and A high concentration drain layer 12 (N +) is formed in a region overlapping with the concentration drain layer 10. This ion implantation is performed, for example, with arsenic ions ( 75 As + ) under conditions of an acceleration voltage of 100 KeV and an implantation amount of 5.0 × 10 13 / cm 2 . The high-concentration drain layer 12 is not formed on the entire surface of the medium-concentration drain layer 10, but is separated from the field insulating films 5a and 5b as shown in FIGS. The drain electrode 16 is formed in the vicinity of the region where the drain electrode 16 is formed. FIG. 3B is a partial plan view showing regions where the field insulating films 5a and 5b and the high-concentration drain layer 12 shown in FIG.

次に、不図示のホトレジスト層をマスクとしてＰ型不純物を中濃度のドレイン層１０に注入し、高濃度のＰ型不純物層１３を形成する。Ｐ型不純物層１３はＥＳＤ耐量を向上させることに寄与する層である。この点については後述する。このイオン注入は、例えば二フッ化ボロン（４９ＢＦ２ ＋）イオンを加速電圧４０ＫｅＶ，注入量２．０×１０１５／ｃｍ２の条件で行う。本実施形態のＰ型不純物層１３は、図３（ｂ）に示すように、高濃度のドレイン層１２の周囲をリング状に囲むとともに、高濃度のドレイン層１２と隣接している。なお、ＥＳＤ耐量を向上させる観点から、Ｐ型不純物層１３は、少なくとも高濃度のドレイン層１２よりも深く形成することが好ましいと考えられる。なお、ＥＳＤ耐量を向上させる観点からは、図３（ａ），（ｂ）に示すように、Ｐ型不純物層１３が高濃度のドレイン層１２と接していることが好ましいと考えるが離間させることもできる。また、本実施形態ではＰ型不純物層１３はフィールド絶縁膜５ａ，５ｂと隣接している。次に、アニール処理を行う。 Next, using a photoresist layer (not shown) as a mask, P-type impurities are implanted into the medium-concentration drain layer 10 to form a high-concentration P-type impurity layer 13. The P-type impurity layer 13 is a layer that contributes to improving the ESD tolerance. This point will be described later. This ion implantation is performed, for example, using boron difluoride ( 49 BF 2 + ) ions under the conditions of an acceleration voltage of 40 KeV and an implantation amount of 2.0 × 10 15 / cm 2 . As shown in FIG. 3B, the P-type impurity layer 13 of the present embodiment surrounds the periphery of the high concentration drain layer 12 in a ring shape and is adjacent to the high concentration drain layer 12. From the viewpoint of improving the ESD tolerance, it is considered that the P-type impurity layer 13 is preferably formed deeper than at least the high-concentration drain layer 12. From the viewpoint of improving the ESD tolerance, it is preferable that the P-type impurity layer 13 is in contact with the high-concentration drain layer 12 as shown in FIGS. 3A and 3B. You can also. In the present embodiment, the P-type impurity layer 13 is adjacent to the field insulating films 5a and 5b. Next, an annealing process is performed.

なお、高濃度のドレイン層１２の形成のためのイオン注入を中濃度のドレイン層１０の表面領域の全面に注入し、その後当該領域にＰ型不純物層１３の形成のためのイオン注入を一部重畳させることで、高濃度のドレイン層１２とＰ型不純物層１３を形成してもよい。   Note that ion implantation for forming the high-concentration drain layer 12 is implanted into the entire surface region of the medium-concentration drain layer 10, and then part of the ion implantation for forming the P-type impurity layer 13 is performed in the region. By overlapping, the high-concentration drain layer 12 and the P-type impurity layer 13 may be formed.

次に、図４に示すように、半導体基板１上の全面に層間絶縁膜１４（例えば、ＣＶＤ法によるＢＰＳＧ膜やシリコン窒化膜）を形成する。次に、高濃度のソース層１１及び高濃度のドレイン層１２に至るコンタクトホールを形成し、各コンタクトホールにそれぞれソース電極１５とドレイン電極１６を形成する。   Next, as shown in FIG. 4, an interlayer insulating film 14 (for example, a BPSG film or a silicon nitride film by a CVD method) is formed on the entire surface of the semiconductor substrate 1. Next, contact holes reaching the high concentration source layer 11 and the high concentration drain layer 12 are formed, and the source electrode 15 and the drain electrode 16 are formed in each contact hole.

以上の製造工程から、本実施形態に係る半導体装置２０を得る事ができる。このようにして完成した半導体装置２０のドレイン電極１６に過大な正のサージ電圧が生じると、図４に示すように寄生ＮＰＮバイポーラトランジスタ３０がオンし、ドレイン電極１６側からソース電極１５側へと電流が流れる。この寄生バイポーラ動作は、ドレイン層４ａとウェル３との接合がブレークダウンしてウェル層３を電流が流れると、ウェル層３の電圧が上昇し、そしてウェル層３からソース層（８，１１）側にベース電流が流れ、これによって寄生バイポーラトランジスタ３０がオンする現象である。   From the above manufacturing process, the semiconductor device 20 according to the present embodiment can be obtained. When an excessive positive surge voltage is generated at the drain electrode 16 of the semiconductor device 20 thus completed, the parasitic NPN bipolar transistor 30 is turned on as shown in FIG. 4, and the drain electrode 16 side to the source electrode 15 side is turned on. Current flows. In this parasitic bipolar operation, when the junction between the drain layer 4a and the well 3 breaks down and a current flows through the well layer 3, the voltage of the well layer 3 rises and the well layer 3 to the source layer (8, 11). This is a phenomenon in which a base current flows to the side and the parasitic bipolar transistor 30 is turned on.

寄生バイポーラ動作が起きている間、電子はソース電極１５側からドレイン電極１６側へと移動する。ここで、Ｐ型不純物層１３が形成されていない従来構造（図６参照）では、電子が基板表面付近を集中的に流れ、発熱し、これによって破壊に至ると考えられる。これに対して、本実施形態の構成ではＰ型不純物層１３が形成されている。そのため、電子はＰ型不純物層１３が形成された基板表面付近Ｘを避け、図４の矢印２５に示すように電子は分散して流れ、より深い位置からドレイン電極１６側へと回り込むように移動すると考えられる。つまり、Ｐ型不純物層１３の作用によって、基板表面よりもより深い位置を電子（＝電流）が分散して流れ、熱が集中せず、その結果として静電破壊が起き難くなっていると考えられる。   During the parasitic bipolar operation, electrons move from the source electrode 15 side to the drain electrode 16 side. Here, in the conventional structure in which the P-type impurity layer 13 is not formed (see FIG. 6), it is considered that electrons flow intensively near the substrate surface and generate heat, thereby causing destruction. On the other hand, the P-type impurity layer 13 is formed in the configuration of the present embodiment. Therefore, the electrons avoid the vicinity of the substrate surface X on which the P-type impurity layer 13 is formed, and the electrons flow in a dispersed manner as indicated by an arrow 25 in FIG. 4 so that they move from a deeper position to the drain electrode 16 side. I think that. That is, the action of the P-type impurity layer 13 causes electrons (= currents) to flow in a deeper position than the substrate surface, so that heat does not concentrate, and as a result, electrostatic breakdown is unlikely to occur. It is done.

本発明者が行った静電破壊試験によれば、ＥＳＤ耐量の向上が確認できた。具体的には、従来構造（図６参照）で２００ボルト未満だったヒューマンボディモデルのＥＳＤ耐量が３０００〜３５００ボルト程度に向上し、従来構造で５０ボルト未満だったマシーンモデルのＥＳＤ耐量が約４００ボルトに向上した。また、Ｐ型不純物層１３を形成しない点を除いて本実施形態と同様の構成を有する半導体装置について静電破壊試験を行ったところ、ヒューマンボディモデルのＥＳＤ耐量が２０００〜２２５０ボルトであり、マシーンモデルのＥＳＤ耐量が２００ボルト〜２２０ボルトであった。これらの実験から、本実施形態の構造は、従来構造に比してＥＳＤ耐量が飛躍的に向上する構造であること、及びＰ型不純物層１３がＥＳＤ耐量の向上に大きく寄与していることが判った。   According to the electrostatic breakdown test conducted by the present inventor, it was confirmed that the ESD resistance was improved. Specifically, the ESD resistance of the human body model that was less than 200 volts in the conventional structure (see FIG. 6) is improved to about 3000 to 3500 volts, and the ESD resistance of the machine model that was less than 50 volts in the conventional structure is about 400. Improved to bolts. Further, when an electrostatic breakdown test was performed on a semiconductor device having the same configuration as that of the present embodiment except that the P-type impurity layer 13 was not formed, the ESD resistance of the human body model was 2000 to 2250 volts, and the machine The ESD tolerance of the model was 200 to 220 volts. From these experiments, it can be seen that the structure of this embodiment has a structure in which the ESD resistance is dramatically improved as compared with the conventional structure, and that the P-type impurity layer 13 greatly contributes to the improvement of the ESD resistance. understood.

なお、本発明は上記実施形態に限定されることはなくその要旨を逸脱しない範囲で設計変更が可能であることは言うまでも無い。例えば、上記した構成では、断面図に示された低濃度のドレイン層４ａ，４ｂに離間した部分があったが、離間させずに低濃度ドレイン領域を切れ目なく形成してもよい。また、フィールド絶縁膜５ａの下部に別のＰ型不純物層を配置することで更にＥＳＤ耐量を向上させることも考えられる。また、本実施形態ではゲート電極７の一部下にフィールド絶縁膜５ａが形成されていたが、図５（ａ）に示すようにフィールド絶縁膜５ａを形成しない構造に設計変更することも可能である。   Needless to say, the present invention is not limited to the above-described embodiment, and the design can be changed without departing from the gist thereof. For example, in the above-described configuration, the low-concentration drain layers 4a and 4b shown in the cross-sectional view have a separated portion, but the low-concentration drain region may be formed without a gap without being separated. It is also conceivable to further improve the ESD tolerance by disposing another P-type impurity layer below the field insulating film 5a. In the present embodiment, the field insulating film 5a is formed under a part of the gate electrode 7. However, as shown in FIG. 5A, the design can be changed to a structure in which the field insulating film 5a is not formed. .

さらに、図５（ｂ）に示すように、中濃度のドレイン層１０のソース側の端部がゲート電極７あるいはサイドウォールスペーサ膜９ｂの下に位置するように構成し、低濃度のドレイン層４ａを形成しない構造に設計変更することも可能である。   Further, as shown in FIG. 5B, the end portion on the source side of the medium concentration drain layer 10 is located below the gate electrode 7 or the sidewall spacer film 9b, so that the low concentration drain layer 4a is formed. It is also possible to change the design to a structure that does not form the.

また、製造工程の順番や条件を変更することも当然可能である。例えば、上記ではサイドウォールスペーサ膜９ａ，９ｂの形成の後に中濃度のドレイン層１０を形成しているが、これよりも以前に形成することもできる。具体的には、フィールド絶縁膜５ａ〜５ｃ形成後に、所定のマスクを用いて中濃度のドレイン層１０形成のためのイオン注入を行い、その後に注入されたイオンを熱拡散させることで中濃度のドレイン層１０を形成してもよい。そして、その後ゲート絶縁膜６やゲート電極７を形成することができる。なお、中濃度のドレイン層１０を熱拡散によって深く形成する観点から、この場合の中濃度のドレイン層１０の形成に係るイオン注入は、注入量を比較的多くすることで、高加速ではない条件で行うことができる。このときの注入条件は、例えばヒ素イオン（７５Ａｓ＋）を用いた場合には、加速電圧９０〜１５０ＫｅＶ，注入量１．０×１０１５〜６．０×１０１５／ｃｍ２であり、また、リンイオン（３１Ｐ＋）を用いた場合には、加速電圧４０〜８０ＫｅＶ，注入量１．０×１０１５〜６．０×１０１５／ｃｍ２の条件である。 Of course, it is also possible to change the order and conditions of the manufacturing process. For example, although the intermediate concentration drain layer 10 is formed after the formation of the sidewall spacer films 9a and 9b in the above description, it may be formed before this. Specifically, after the field insulating films 5a to 5c are formed, ion implantation for forming the medium concentration drain layer 10 is performed using a predetermined mask, and then the implanted ions are thermally diffused to thermally diffuse. The drain layer 10 may be formed. Thereafter, the gate insulating film 6 and the gate electrode 7 can be formed. From the viewpoint of forming the intermediate concentration drain layer 10 deeply by thermal diffusion, ion implantation related to the formation of the intermediate concentration drain layer 10 in this case is a condition that is not highly accelerated by relatively increasing the implantation amount. Can be done. The implantation conditions at this time are, for example, an acceleration voltage of 90 to 150 KeV and an implantation amount of 1.0 × 10 15 to 6.0 × 10 15 / cm 2 when arsenic ions ( 75 As + ) are used. When phosphorus ions ( 31 P + ) are used, the acceleration voltage is 40 to 80 KeV and the injection amount is 1.0 × 10 15 to 6.0 × 10 15 / cm 2 .

また、Ｐチャネル型のＭＯＳトランジスタに関する説明は省略するが、導電型が異なるだけで同様の構造であることは周知のとおりである。   In addition, although description on the P-channel MOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different.

本発明の実施形態に係る半導体装置及びその製造方法を説明する断面図である。It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. 本発明の実施形態に係る半導体装置及びその製造方法を説明する断面図である。It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. 本発明の実施形態に係る半導体装置及びその製造方法を説明する断面図及び平面図である。It is sectional drawing and the top view explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. 本発明の実施形態に係る半導体装置及びその製造方法を説明する断面図である。It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. 本発明の実施形態に係る半導体装置の変更例を説明する断面図である。It is sectional drawing explaining the example of a change of the semiconductor device which concerns on embodiment of this invention. 従来の半導体装置を説明する断面図である。It is sectional drawing explaining the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体基板 ２ ウェル層 ３ ウェル層 ４ａ，４ｂ 低濃度のドレイン層 ５ａ，５ｂ，５ｃ フィールド絶縁膜 ６ ゲート絶縁膜 ７ ゲート電極 ８ 低濃度のソース層 ９ａ，９ｂ サイドウォールスペーサ膜 １０ 中濃度のドレイン層 １１ 高濃度のソース層 １２ 高濃度のドレイン層 １３ Ｐ型不純物層 １４ 層間絶縁膜 １５ ソース電極 １６ ドレイン電極 ２０ 半導体装置 ２５ 電子の流れ ３０ 寄生バイポーラトランジスタ １００ 半導体基板 １０１ ゲート絶縁膜 １０２ フィールド絶縁膜 １０３ ゲート電極 １０４ ソース層 １０５ 低濃度のソース層 １０６ 高濃度のドレイン層 １０７ 低濃度のドレイン層 １０８ サイドウォールスペーサ膜 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Well layer 3 Well layer 4a, 4b Low concentration drain layer 5a, 5b, 5c Field insulating film 6 Gate insulating film 7 Gate electrode 8 Low concentration source layer 9a, 9b Side wall spacer film 10 Medium concentration drain Layer 11 High-concentration source layer 12 High-concentration drain layer 13 P-type impurity layer 14 Interlayer insulating film 15 Source electrode 16 Drain electrode 20 Semiconductor device 25 Electron flow 30 Parasitic bipolar transistor 100 Semiconductor substrate 101 Gate insulating film 102 Field insulating film 103 Gate electrode 104 Source layer 105 Low concentration source layer 106 High concentration drain layer 107 Low concentration drain layer 108 Side wall spacer film

Claims (9)

第１導電型の半導体層の表面に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記半導体層の表面に形成された第２導電型のソース層と、
前記ゲート電極のドレイン側の端部から離間し、前記半導体層の表面に形成された第２導電型の高濃度のドレイン層と、
前記ゲート電極と前記高濃度のドレイン層との間における前記半導体層の表面に、前記高濃度のドレイン層に隣接する第１導電型の不純物層とを備えることを特徴とする半導体装置。 A gate insulating film formed on the surface of the first conductivity type semiconductor layer;
A gate electrode formed on the gate insulating film;
A second conductivity type source layer formed on the surface of the semiconductor layer;
A second conductivity type high-concentration drain layer formed on the surface of the semiconductor layer, spaced from the drain side end of the gate electrode;
A semiconductor device comprising: a first conductivity type impurity layer adjacent to the high concentration drain layer on a surface of the semiconductor layer between the gate electrode and the high concentration drain layer. 前記高濃度のドレイン層よりも低濃度であり、かつ深く拡散し、前記ゲート電極の下方から前記高濃度のドレイン層との間の前記半導体層の表面に形成された第２導電型の低濃度のドレイン層を有することを特徴とする請求項１に記載の半導体装置。   Low concentration of the second conductivity type, which has a lower concentration than the high concentration drain layer and diffuses deeply and is formed on the surface of the semiconductor layer between the lower concentration gate layer and the high concentration drain layer. The semiconductor device according to claim 1, further comprising: a drain layer. 前記高濃度のドレイン層及び前記不純物層と重畳し、前記高濃度のドレイン層よりも低濃度であって、かつ深く拡散した中濃度のドレイン層を備えることを特徴とする請求項１または請求項２に記載の半導体装置。   2. The intermediate-concentration drain layer that overlaps with the high-concentration drain layer and the impurity layer, has a lower concentration than the high-concentration drain layer, and is deeply diffused. 2. The semiconductor device according to 2. 前記半導体層上に前記ゲート絶縁膜よりも厚い絶縁膜が形成され、前記ゲート電極は前記厚い絶縁膜の一部上に延在していることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置。   4. The semiconductor device according to claim 1, wherein an insulating film thicker than the gate insulating film is formed on the semiconductor layer, and the gate electrode extends on a part of the thick insulating film. A semiconductor device according to claim 1. 前記不純物層は、前記厚い絶縁膜のドレイン側の一端と隣接していることを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein the impurity layer is adjacent to one end of the thick insulating film on a drain side. 第１導電型の半導体層の表面上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上にゲート電極を形成する工程と、
前記ゲート電極から離間した前記半導体層の表面に第２導電型の高濃度のドレイン層を形成する工程と、
第１導電型の不純物層を、前記高濃度のドレイン層に隣接させて、前記半導体層の表面に形成する工程とを有することを特徴とする半導体装置の製造方法。 Forming a gate insulating film on the surface of the first conductivity type semiconductor layer;
Forming a gate electrode on the gate insulating film;
Forming a second conductivity type high-concentration drain layer on the surface of the semiconductor layer spaced from the gate electrode;
Forming a first conductivity type impurity layer on the surface of the semiconductor layer adjacent to the high-concentration drain layer. 前記高濃度のドレイン層よりも低濃度であり、かつ深く拡散し、前記ゲート電極の下方から前記高濃度のドレイン層との間の前記半導体層の表面に低濃度のドレイン層を形成する工程を有することを特徴とする請求項６に記載の半導体装置の製造方法。   Forming a low-concentration drain layer on the surface of the semiconductor layer between the high-concentration drain layer and a lower concentration than the high-concentration drain layer and diffusing deeply; A method for manufacturing a semiconductor device according to claim 6, comprising: 前記低濃度のドレイン層に隣接し、前記高濃度のドレイン層及び前記不純物層と重畳する領域に、前記高濃度のドレイン層よりも深く、かつ低い濃度の中濃度のドレイン層を形成する工程を有することを特徴とする請求項７に記載の半導体装置の製造方法。   Forming a low-concentration medium-concentration drain layer deeper than the high-concentration drain layer and in a region adjacent to the low-concentration drain layer and overlapping the high-concentration drain layer and the impurity layer; 8. The method of manufacturing a semiconductor device according to claim 7, further comprising: 前記低濃度のドレイン層上に前記ゲート絶縁膜よりも厚い絶縁膜を形成する工程を有し、前記不純物層を形成する工程は、
前記不純物層が、前記厚い絶縁膜のドレイン側の一端と隣接するように行うことを特徴とする請求項７または請求項８に記載の半導体装置の製造方法。 A step of forming an insulating film thicker than the gate insulating film on the low-concentration drain layer, and the step of forming the impurity layer includes:
9. The method for manufacturing a semiconductor device according to claim 7, wherein the impurity layer is formed so as to be adjacent to one end on the drain side of the thick insulating film.
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