Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F8/00—Arrangements for software engineering
  • G06F8/40—Transformation of program code
  • G06F8/54—Link editing before load time
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/44—Arrangements for executing specific programs
  • G06F9/4401—Bootstrapping
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/22—Microcontrol or microprogram arrangements

Definitions

• the invention relates to an apparatus for data processing comprising a central processing unit and a non volatile random access memory.
• FIG. 4 a typical architecture of an apparatus 10 for data processing, especially a computer system, home entertainment device or the like is shown.
• a central processing unit 12 in the following referred to as a CPU, is connected via a front side bus 14 to a Northbridge 16.
• a random access memory 18, also referred to as a RAM, is connected to the Northbridge 16.
• the Northbridge 16 and a Southbridge 20 build a bus system of the apparatus 10 for data processing, shown in Fig. 4.
• the Northbridge 16 and the Southbridge 20 are connected e. g. via a direct media interface 22.
• a data storage device 24, e.g. a hard disk or the like, is connected to the Southbridge 20 via an S-ATA interface 26. Further, several USB-ports 28 and PCI-slots 30 are connected to the Southbridge 20.
• a standard random access memory device e.g. a synchronous dynamic random access memory (SDRAM) or a double data rate synchronous dynamic random access memory (DDR-SDRAM,
• SDRAM synchronous dynamic random access memory
• DDR-SDRAM double data rate synchronous dynamic random access memory
• DDRAM DDRAM
• the random access memory 18 DDRAM
• these devices provide high-speed data transfer rates.
• these memories are volatile memories and have a rather limited storage capacity.
• the data storage device 24, e.g. a conventional hard disc drive or a flash memory device offers a low data transfer rate, but it is non-volatile and has a large storage capacity.
• US 2003/0028708 Al discloses a device, a method and a system for direct execution of code from a flash memory arrangement.
• the system comprises a flash based unit that communicates with a CPU and a RAM via a bus system.
• the CPU reads it from the RAM, however the code is stored in the flash based unit.
• Said flash based unit differs from known units in that it features a volatile memory component in direct communication with a flash memory.
• a further data storage device is known from US 2005/0050261 Al.
• the disclosed device comprises a controller, a FeRAM unit and a flash memory unit.
• An enhanced data transfer rate may be achieved by storing incoming data in the FeRAM that offers a high data transfer rate. Later on, the controller is shifting data to the flash memory unit that offers a much higher data capacity.
• a computer system's booting speed may be enhanced by providing a large RAM storage, however a separate power source for the RAM is needed.
• An object of the invention is to provide an apparatus for data processing that is improved with respect to the deficiencies known from prior art.
• An apparatus for data processing according to the invention comprises a central processing unit and a memory bus for attaching a non volatile random access memory. Data related to an operating system used for running said apparatus is at least partly stored in said non volatile random access memory. The memory used by the operating system for operating said apparatus is at least partly said non volatile random access memory. - A - The concept of the apparatus according to the invention is based on the following considerations:
• Computer systems known from prior art comprise a plurality of different types of memories and storage devices. This is due to the fact every type of storage has its own very specific advantages and disadvantages, e.g. a hard disc provides a huge storage capacity but it offers limited data transfer rates and no random access characteristics. On the other hand, e.g. a DDR-SDRAM offers high data rates but its storage capacity is rather limited due to the high costs for the storage space. While the hard disc stores data permanently, a typical random access memory is volatile.
• Nonvolatile random access memories offer the possibly for a completely new computer architecture that overcomes the aforementioned problems.
• the memory used for permanent mass storage of data typically a hard disc for storage of e.g. user data, data relating to the operating system, application programs etc. and the random access memory used for data processing e.g. a DDR-SDRAM device can be designed as one single integrated memory.
• a nonvolatile random access memory may serve as a memory for permanent mass storage of data as well as a memory for data processing by the CPU.
• the access time for data related, e.g. to a further application program typically stored on a hard disc drive in computers known from prior art is significantly reduced.
• the CPU may directly access the desired data in the nonvolatile random access memory. The result is a faster booting sequence and improved system performance.
• an apparatus wherein the only recordable memory comprised by said apparatus is said non volatile random access memory.
• a recordable memory is a memory used for frequent read-write processes, i.e. during standard operation of the computer.
• a main random access memory e.g. a SDRAM
• a mass storage device e.g. a hard disc
• a rewritable CD or DVD as well as a memory stick or the like is not understood as such a recordable memory here.
• a computer system according to the invention comprises only one type of recordable memory.
• the computer's architecture is simplified.
• an apparatus wherein the non volatile random access memory is located in a component of the apparatus that is physically detachable from said apparatus.
• Nonvolatile random access memory User data as well as data related to application programs and the operating system is stored in the nonvolatile random access memory.
• detaching said nonvolatile random access memory from a first computer system and attaching it to a second and further computer system computer work started with the first computer system may be continued using the second computer system.
• the suggested computer architecture allows a very flexible change of computer systems, even no start-up sequence is necessary due to the fact the main memory in its present state is safeguarded by the non volatility of the random access memory.
• the different computer systems in question may comprise different peripherals, e.g. different I/O-hardware like display or input devices etc.
• hardware profiles assigned to the respective systems may be stored in the nonvolatile random access memory.
• the random access memory is the only recordable memory comprised by said apparatus and is located in a component of the apparatus that is physically detachable from said apparatus.
• User data can only be stored in the non volatile random access memory; simply due to the fact that no further memory is available in the computer system. By detaching the memory from the computer system, the user can take all personal data with him or her. Consequently, there is no risk of accidental distribution or loss of personal data in case an external computer system is temporarily used or the computer system is temporarily used by another user.
• an apparatus wherein the memory bus connection is realized by a direct wire or plug connection of pins between the central processing unit and the non volatile random access memory.
• the memory bus is a PCI - Express connection.
• an apparatus wherein the non volatile random access memory is divided into different virtual sections.
• at least one virtual section is used for data storage and a further virtual section is used as a primary memory for processing data.
• a size of the virtual sections is dynamically allocatable .
• the non volatile random access memory is a phase change random access memory (PCRAM) , a magnetic random access memory (MRAM) , a ferroelectric random access memory (FRAM) or a NanotubeRAM device.
• PCRAM phase change random access memory
• MRAM magnetic random access memory
• FRAM ferroelectric random access memory
• non volatile random access memory devices are promising candidates for present and future application. They are or they will be commercially available and they fulfill the requirements for a reliable random access memory of the inventive apparatus.
• an apparatus is provided, wherein said apparatus is one of a personal computer, a microprocessor, an embedded platform, a set-top box or a media recorder.
• said apparatus is one of a personal computer, a microprocessor, an embedded platform, a set-top box or a media recorder.
• a computer architecture as previously described is advantageous for these electronic devices.
• FIG. 1 and 2 each show a comparison between a schematic computer architecture known from prior art (Fig. Ia, 2a) in contrast to a schematic computer architecture according an embodiment of the invention (Fig. Ib, Ic, Id, 2b) .
• Fig. 3 schematically shows an allocation of a nonvolatile memory
• Fig. 4 shows a computer architecture known from prior art. Detailed Description of the Invention
• Fig. Ia shows a schematic sketch of a computer architecture known from prior art.
• a central processing unit (CPU) 12 is connected to a bus system 32.
• a bus system is understood as being a connection means to connect two or more devices having one or multiple connection pins, for example a CPU and a memory.
• the bus system connects the connection pins of the devices either in a parallel manner, in a serial manner or with multiple serial connections, which are arranged in a parallel manner.
• An SDRAM device as a random access memory 18 and a hard disc drive as a data storage device 24 are also connected to the bus system 32.
• both the random access memory 18 and the data storage device 24 are substituted by a single nonvolatile random access memory 34, i.e. an PCRAM - device.
• the CPU 12 in turn is connected to the bus system 32. Said CPU 12 and the nonvolatile random access memory 34 communicate via the bus system 32.
• the connection between the memory bus 32 and the non volatile random access memory 34 is a direct wire connection 50 or a connection realized by a plug 46 as shown in Fig. Ic.
• the non volatile random access memory 34 is in a physically detachable component 42.
• the component 42 is connectable to the memory bus 32 via a plug connection 46 of pins 44.
• a wireless connection between the memory bus 32 and the non volatile random access memory 34 as depicted in Fig. Id is useable.
• the component 42 comprising the non volatile random access memory 34 has an antenna 48 and means for preparing the data to be transmitted via a wireless connection (not shown) attached to it.
• a wireless connection means for preparing the data to be transmitted via a wireless connection (not shown) attached to it.
• the memory bus 32 (not shown) and an antenna (not shown) are connected to the memory bus 32.
• the data communication from the CPU 12 is performed over the memory bus 32 to the wireless connection means (not shown) , and subsequently over the wireless path to the antenna 48 attached component 42 comprising the non volatile random access memory 34.
• the connection between the CPU 12 and the non volatile random access memory 34 is realized as an optical connection.
• Fig. 2a shows a further schematic computer architecture known from prior art.
• the bus system is divided in a Northbridge 16 and a Southbridge 20.
• the CPU 12 is connected via a front side bus 14 to the Northbridge 16.
• the random access memory 18 is connected to the Northbridge 16.
• a data storage device 24, e.g. a hard disc drive and peripherals 36, e.g. a printer, network card, etc. are connected to the Southbridge 20.
• the nonvolatile random access memory 34 serving as a random access memory as well as a data storage device is directly connected to the Northbridge 16 as it is shown in Fig. 2b. Therefore, a high speed data bus is available for communication between the CPU 12 and the nonvolatile random access memory 34. Further peripherals are connected to the Southbridge 20 as it is known from Fig. 2a.
• Fig. 3 shows a schematic sketch of an allocation of the nonvolatile random access memory 34.
• the capacity of the non volatile random access memory 34 should be 100 GByte, as it is shown in the left part of Fig. 3.
• the storage space of the nonvolatile random access memory 34 is allocated into a first section 38 having a size of 1 GByte and a second section 40 having a size of 99 GByte as it is shown in the right part of Fig. 3.
• the first and smaller section 38 is used for data processing while the second and larger section 40 is used for permanent storage of data, e.g. user data, data related to the operating system, etc.
• Dividing the unified storage memory into a part predetermined for data processing 38 and a part predetermined for storage 40 has the advantage that a file system structure can be used in the larger section 40 used for storage. This facilitates addressing of the larger section 40 of the memory. Copying data between the storage part 40 of the memory and the processing part 38 of the memory is performed fast because the copying process is realized within one memory 34. Therefore, also by structuring the memory in a storage part 40 and a processing part 38 the benefits of the combined device are realized.
• the size of the first and second section 38, 40 is allocated dynamically.
• the allocation between the first and second section 38, 40 depends on the actual workload of the computer system or the present use of the nonvolatile random access memory 34 in case said memory is located in a physically detachable entity.
• the size of the first section 38 of the nonvolatile memory used for processing data may be enlarged in order to improve the performance of the system in case the computer is confronted with a high workload.
• the nonvolatile random access memory 34 is used as a personal workbench for a user working on a plurality of different computer systems, the performance of the system is not the main focus. Consequently, the size of the second section 40 of the nonvolatile random access memory 34 may be chosen as large as possible in order to provide a high storage capacity to the user.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Software Systems (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Security & Cryptography (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
• Stored Programmes (AREA)

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• 2009
  • 2009-06-26 EP EP09305609A patent/EP2273365A1/en not_active Withdrawn
• 2010
  • 2010-06-15 EP EP10725439A patent/EP2446350A1/en not_active Withdrawn
  • 2010-06-15 KR KR1020117030846A patent/KR20120031017A/ko not_active Withdrawn
  • 2010-06-15 US US13/380,811 patent/US20120110253A1/en not_active Abandoned
  • 2010-06-15 JP JP2012516639A patent/JP2012530991A/ja active Pending
  • 2010-06-15 CN CN2010800283532A patent/CN102804141A/zh active Pending
  • 2010-06-15 WO PCT/EP2010/058375 patent/WO2010149538A1/en not_active Ceased

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