WO2010144282A1 - Heterojunction iii-v photovoltaic cell fabrication - Google Patents

Heterojunction iii-v photovoltaic cell fabrication Download PDF

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Publication number
WO2010144282A1
WO2010144282A1 PCT/US2010/037029 US2010037029W WO2010144282A1 WO 2010144282 A1 WO2010144282 A1 WO 2010144282A1 US 2010037029 W US2010037029 W US 2010037029W WO 2010144282 A1 WO2010144282 A1 WO 2010144282A1
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layer
amorphous silicon
substrate
cell
base layer
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French (fr)
Inventor
Stephen W. Bedell
Norma Sosa Cortes
Keith E. Fogel
Devendra Sadana
Ghavam Shahidi
Davood Shahrjerdi
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International Business Machines Corp
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International Business Machines Corp
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Priority to CN201080021165.7A priority Critical patent/CN102428577B/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/161—Photovoltaic cells having only PN heterojunction potential barriers comprising multiple PN heterojunctions, e.g. tandem cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H10F10/172—Photovoltaic cells having only PIN junction potential barriers comprising multiple PIN junctions, e.g. tandem cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/139—Manufacture or treatment of devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162—Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
    • H10F77/166—Amorphous semiconductors
    • H10F77/1662—Amorphous semiconductors including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This disclosure relates generally to the field of heterojunction photovoltaic cell fabrication.
  • Silicon (Si) based heterojunction intrinsic thin layer (HIT) photovoltaic (PV) cells may comprise a bulk single-crystalline silicon (sc-Si) base layer sandwiched between two layers of amorphous Si (a-Si).
  • sc-Si bulk single-crystalline silicon
  • a-Si amorphous Si
  • the use of a-Si layers in an HIT cell gives the HIT cell a wider bandgap than a cell comprising only sc-Si.
  • the a-Si layer also creates an energy barrier at the interface between the a-Si and the sc-Si base layer, which keeps minority carriers away from the interface, thereby reducing the recombination rate in the cell.
  • a-Si may be processed at a relatively low temperature.
  • the HIT cell structure may have a sc-Si substrate thickness in the range of a few tens of microns ( ⁇ m). This substrate thickness is smaller than the diffusion length of the minority carriers in the PV cell, while being sufficiently thick to allow maximum absorption of the solar spectrum.
  • a method for forming a heteroj unction IH-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a HI-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer.
  • a heterojunction IH-V photovoltaic (PV) cell includes a base layer comprising a IH-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.
  • FIG. 1 illustrates an embodiment of a method of forming a single heterojunction
  • III-V PV cell via spalling.
  • FIG. 2 illustrates an embodiment of a substrate having a back surface field, metal layer, and a flexible substrate layer.
  • FIG. 3 illustrates an embodiment of spalling using a flexible substrate layer.
  • FIG. 4 illustrates an embodiment of a single heterojunction HI-V PV cell.
  • FIG. 5 illustrates an embodiment of a method of forming a double heterojunction
  • FIG. 6 illustrates an embodiment of a substrate having an intrinsic layer, a back surface field, an amorphous silicon layer, a metal layer, and a flexible substrate layer.
  • FIG. 7 illustrates an embodiment of spalling using a flexible substrate layer.
  • FIG. 8 illustrates an embodiment of a double heterojunction IH-V PV cell.
  • An HJ solar cell may be formed using a base layer comprising a IH-V based substrate, such as germanium (Ge) or gallium arsenide (GaAs), in place of sc-Si.
  • a IH-V based substrate such as germanium (Ge) or gallium arsenide (GaAs)
  • the diffusion length of the minority carriers is relatively small in comparison to the substrate thickness. Due to its direct band gap, a relatively thin layer (a few microns thick) of a III-V based substrate is capable of effectively absorbing a large portion of the solar spectrum, unlike sc-Si.
  • An HJ III-V PV cell structure comprises a base layer comprising a III-V substrate that is less than about 20 ⁇ m thick in some embodiments. Deposition of a-Si on one side of the base layer forms a single HJ cell, and deposition of a-Si on both sides of the base layer forms a double HJ cell.
  • An HJ III-V PV cell may be relatively lightweight and/or flexible, allowing use of the HJ III-V PV cell in diverse applications.
  • the formation of the relatively thin base layer of the III-V base substrate may be achieved by any appropriate layer transfer method including smart cut layer transfer, epitaxial layer transfer, or spalling.
  • Smart cut layer transfer is appropriate for formation of a base layer for a single HJ cell.
  • Smart cut layer transfer comprises hydrogen (H) implantation into the IH-V substrate, followed by an annealing in order to initiate cracks within the H-implanted region that then travel into the substrate.
  • H hydrogen
  • smart cut layer transfer has some limitations for producing layers thicker than couple of microns. Smart cut layer transfer requires for relatively high implantation energies, which tend to be costly.
  • Smart cut layer transfer is not suitable for double HJ cells, as the a-Si layer formed on the substrate prior to layer transfer cannot withstand the relatively high annealing temperature.
  • Epitaxial layer transfer is appropriate for formation of both single and double HJ cells, and comprises growth of a sacrificial layer below the base layer in the substrate. The sacrificial layer is removed using a wet chemical etch, in order to release the relatively thin base layer from the substrate.
  • spalling offers a relatively inexpensive, low-temperature method for separation of a relatively thin base layer from a substrate. The low-temperature nature of spalling allows use in fabrication of both single and double HJ HI-V cells.
  • FIG. 1 illustrates an embodiment of a method 100 of forming a single HJ HI-V
  • a optional back surface field (BSF) 202 is formed on a wafer of a IH-V substrate 201, as shown in FIG. 2.
  • Substrate 201 may comprise germanium (Ge) and/or gallium arsenide (GaAs) in some embodiments.
  • Substrate 201 may comprise an n-type or a p-type substrate.
  • the optional BSF 202 may be formed by depositing a layer of a dopant on the substrate 201, and diffusing the dopant into the substrate 201 in some embodiments, or the optional BSF 202 may comprise a localized back contact.
  • optional BSF 202 may comprise zinc (Zn), indium (In), or aluminum (Al) in some embodiments.
  • Optional BSF 202 may alternately comprise another material that deposited directly on the substrate 201; the BSF material may have a wider band gap than that of the substrate 201.
  • Some examples of an appropriate BSF material may comprise InGaP (for a Ge substrate), or AlGaAs (for a GaAs substrate).
  • a tensile stressed metal layer 203 is formed, and a flexible substrate layer 204 is adhered to the metal layer 203, as shown in FIG. 2.
  • metal layer 203 is formed directly on substrate 201.
  • Metal layer 203 may comprise nickel (Ni) in some embodiments.
  • Flexible substrate layer 204 may comprise a flexible adhesive, which may be water-soluble in some embodiments. Use of a rigid material for the flexible substrate layer 204 may render the spalling mode of fracture unworkable. Therefore, flexible substrate layer 204 may further comprise a material having a radius of curvature of less than 5 meters in some embodiments, and less than 1 meter in some exemplary embodiments.
  • base layer 301 is spalled from substrate 201, as shown in FIG. 3.
  • the flexible substrate 204 is used to cause the tensile stress in metal layer 203 to form fracture 302 in substrate 201, separating base layer 301 from substrate 201.
  • Base layer 301 comprises the same material as substrate 201, and may be less than about 20 ⁇ m thick in some embodiments.
  • the thickness of the base layer 301 is determined by the tensile stress and thickness of metal layer 203.
  • optional BSF 202 is spalled from substrate 201 along with base layer 301.
  • flexible substrate layer 204 is removed from metal layer 203.
  • a single HJ IH-V PV cell 400 is formed using base layer 301, as shown in FIG. 4.
  • Single HJ IH-V cell 400 comprises optional BSF 202; however, in some embodiments, base layer 301 may be located directly on metal layer 203, and optional BSF 202 may be absent.
  • Metal layer 203 may comprise a back contact for the single HJ H-IV cell 400.
  • Intrinsic layer 401 is formed on base layer 301
  • a-Si layer 402 is formed on intrinsic layer 401
  • TCO transparent conducting oxide
  • the a-Si layer 402 may have a doping type (n-type or p-type) that is opposite the doping type of substrate 201; in such an embodiment, the a-Si layer 402 is configured to act as an emitter for the HJ TII-V cell 400.
  • an a-Si layer 402 configured to act as an emitter may be formed on subtrate 201 or BSF 202 before spalling instead of after spalling.
  • TCO layer 403 may comprise zinc oxide (ZnO) doped with aluminum (Al) in some embodiments. Finger or bus bars (not shown) may be formed on TCO layer 403 in some embodiments.
  • single HJ IH-V PV cell 400 may comprise a base layer 301 formed by spalling
  • other embodiments of cell 400 may comprise a base layer 301 formed by smart cut or epitaxial layer transfer.
  • BSF 202 and/or a-Si layer 402 configured to act as an emitter may optionally be formed on substrate 201, then either smart cut or epitaxial layer transfer are used to separate the base layer 301 from the substrate 201.
  • a single HJ HI-V cell 400 may then be formed using base layer 301 in the same manner discussed above with respect to block 105.
  • FIG. 5 illustrates an embodiment of a method 500 of forming a double HJ IH-V
  • an intrinsic layer 602 is formed in a wafer of a IH-V substrate 201, as shown in FIG. 6.
  • Substrate 601 may comprise Ge and/or GaAs in some embodiments.
  • Substrate 601 may comprise an n-type or a p- type substrate.
  • An optional BSF 603 may be formed on intrinsic layer 602 in some embodiments.
  • Optional BSF 603 may comprise a material having a wider band gap than that of the substrate 601.
  • Some examples of an appropriate BSF material may comprise InGaP (for a Ge substrate) or AlGaAs (for a GaAs substrate).
  • a-Si layer 604 is then formed on intrinsic layer 602 in embodiments not comprising optional BSF 603; in such embodiments, a-Si layer 604 and intrinsic layer 602 may function together as a back surface field.
  • a-Si layer 604 is formed on optional BSF 603.
  • the a-Si layer 604 may comprise a doping type (n-type or p-type) that is the same as that of substrate 601; in such an embodiment, the a-Si layer 604 may act as a BSF.
  • the a-Si layer 604 may alternately comprise a doping type that is opposite that of substrate 601 ; in such an embodiment, a-Si layer 604 may act as an emitter.
  • a tensile stressed metal layer 605 is formed on a-Si layer 604, and a flexible substrate layer 606 is adhered to the metal layer 605, as shown in FIG. 6.
  • Metal layer 605 may comprise nickel (Ni) in some embodiments.
  • Flexible substrate layer 606 may comprise a flexible adhesive, which may be water-soluble in some embodiments. Use of a rigid material for the flexible substrate layer 606 may render the spalling mode of fracture unworkable. Therefore, flexible substrate layer 606 may further comprise a material having a radius of curvature of less than 5 meters in some embodiments, and less than 1 meter in some exemplary embodiments.
  • a base layer 701 is spalled from substrate 601, as shown in FIG. 7.
  • the flexible substrate 606 is used to cause the tensile stress in metal layer 605 to form fracture 702 in substrate 601, separating base layer 701 from substrate 601.
  • Base layer 601 comprises the same material as substrate 601, and may be less than about 20 ⁇ m thick in some embodiments.
  • the thickness of the base layer 701 is determined by the tensile stress and thickness of metal layer 605.
  • Intrinsic layer 602, optional BSF 603 (in embodiments comprising optional BSF 603), and a-Si layer 604 are spalled from substrate 601 along with base layer 701.
  • flexible substrate layer 606 is removed from metal layer 605.
  • a double HJ HI-V PV cell 800 is formed using base layer 701 , as shown in FIG. 8.
  • Double HJ HI-V cell 800 comprises optional BSF 603; however, in some embodiments, intrinsic layer 602 may be located directly on a-Si layer 604, and optional BSF 603 may be absent.
  • Metal layer 605 may comprise a back contact for the single HJ H-IV cell
  • Intrinsic layer 801 is formed on base layer 701, a-Si layer 802 is formed on intrinsic layer
  • TCO layer 803 is formed on amorphous silicon layer 802.
  • the a-Si layer 802 may comprise a doping type (n-type or p-type) that is opposite the doping type of substrate 601 ; in such an embodiment, a-Si layer 802 may act as an emitter for double HJ IH-I V cell 800.
  • TCO layer 803 may comprise zinc oxide (ZnO) doped with aluminum (Al) in some embodiments.
  • Finger or bus bars (not shown) may be formed on TCO layer 803 in some embodiments.
  • double HJ III-V PV cell 800 may comprise a base layer 701 formed by spalling
  • other embodiments of cell 800 may comprise a base layer 701 formed by epitaxial layer transfer.
  • a sacrificial layer is formed in the substrate 601, then intrinsic layer 602, optional BSF 603, and a-Si layer 604 are formed on substrate 601.
  • the base layer 701, intrinsic layer 602, optional BSF 203, and a-Si layer 604 are separated from the substrate 601 at the sacrificial layer.
  • a double HJ IH-V cell 800 may then be formed using base layer 701, intrinsic layer 602, optional BSF 203, and a-Si layer 604 in the same manner discussed above with respect to block 505.

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  • Photovoltaic Devices (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A method for forming a heterojunction III-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer. A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.

Description

HETEROJUNCTION IH-V PHOTOVOLTAIC CELL FABRICATION
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No.
61/185,247, filed June 9, 2009. This application is also related to attorney docket numbers YOR920100058US1, YOR920100060US1, FIS920100005US1, and FIS920100006US1, each assigned to International Business Machines Corporation (IBM) and filed on the same day as the instant application, all of which are herein incorporated by reference in their entirety.
FIELD
[0002] This disclosure relates generally to the field of heterojunction photovoltaic cell fabrication.
DESCRIPTION OF RELATED ART
[0003] Silicon (Si) based heterojunction intrinsic thin layer (HIT) photovoltaic (PV) cells may comprise a bulk single-crystalline silicon (sc-Si) base layer sandwiched between two layers of amorphous Si (a-Si). The use of a-Si layers in an HIT cell gives the HIT cell a wider bandgap than a cell comprising only sc-Si. The a-Si layer also creates an energy barrier at the interface between the a-Si and the sc-Si base layer, which keeps minority carriers away from the interface, thereby reducing the recombination rate in the cell. Additionally, a-Si may be processed at a relatively low temperature. The HIT cell structure may have a sc-Si substrate thickness in the range of a few tens of microns (μm). This substrate thickness is smaller than the diffusion length of the minority carriers in the PV cell, while being sufficiently thick to allow maximum absorption of the solar spectrum. SUMMARY
[0004] In one aspect, a method for forming a heteroj unction IH-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a HI-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer.
[0005] In one aspect, a heterojunction IH-V photovoltaic (PV) cell includes a base layer comprising a IH-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer.
[0006] Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0007] Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:
[0008] FIG. 1 illustrates an embodiment of a method of forming a single heterojunction
III-V PV cell via spalling.
[0009] FIG. 2 illustrates an embodiment of a substrate having a back surface field, metal layer, and a flexible substrate layer.
[0010] FIG. 3 illustrates an embodiment of spalling using a flexible substrate layer. [0011] FIG. 4 illustrates an embodiment of a single heterojunction HI-V PV cell.
[0012] FIG. 5 illustrates an embodiment of a method of forming a double heterojunction
HI-V cell via spalling.
[0013] FIG. 6 illustrates an embodiment of a substrate having an intrinsic layer, a back surface field, an amorphous silicon layer, a metal layer, and a flexible substrate layer.
[0014] FIG. 7 illustrates an embodiment of spalling using a flexible substrate layer.
[0015] FIG. 8 illustrates an embodiment of a double heterojunction IH-V PV cell.
DETAILED DESCRIPTION
[0016] Embodiments of systems and methods for heterojunction (HJ) UI-V PV cell fabrication are provided, with exemplary embodiments being discussed below in detail. An HJ solar cell may be formed using a base layer comprising a IH-V based substrate, such as germanium (Ge) or gallium arsenide (GaAs), in place of sc-Si. In a IH-V based substrate, the diffusion length of the minority carriers is relatively small in comparison to the substrate thickness. Due to its direct band gap, a relatively thin layer (a few microns thick) of a III-V based substrate is capable of effectively absorbing a large portion of the solar spectrum, unlike sc-Si. An HJ III-V PV cell structure comprises a base layer comprising a III-V substrate that is less than about 20μm thick in some embodiments. Deposition of a-Si on one side of the base layer forms a single HJ cell, and deposition of a-Si on both sides of the base layer forms a double HJ cell. An HJ III-V PV cell may be relatively lightweight and/or flexible, allowing use of the HJ III-V PV cell in diverse applications.
[0017] The formation of the relatively thin base layer of the III-V base substrate may be achieved by any appropriate layer transfer method including smart cut layer transfer, epitaxial layer transfer, or spalling. Smart cut layer transfer is appropriate for formation of a base layer for a single HJ cell. Smart cut layer transfer comprises hydrogen (H) implantation into the IH-V substrate, followed by an annealing in order to initiate cracks within the H-implanted region that then travel into the substrate. However, smart cut layer transfer has some limitations for producing layers thicker than couple of microns. Smart cut layer transfer requires for relatively high implantation energies, which tend to be costly. In addition, the use of high implantation energy may result in implantation damage within the thin film, resulting in degradation of the crystalline quality of the film, which severely degrades cell performance. Smart cut layer transfer is not suitable for double HJ cells, as the a-Si layer formed on the substrate prior to layer transfer cannot withstand the relatively high annealing temperature. Epitaxial layer transfer is appropriate for formation of both single and double HJ cells, and comprises growth of a sacrificial layer below the base layer in the substrate. The sacrificial layer is removed using a wet chemical etch, in order to release the relatively thin base layer from the substrate. Lastly, spalling offers a relatively inexpensive, low-temperature method for separation of a relatively thin base layer from a substrate. The low-temperature nature of spalling allows use in fabrication of both single and double HJ HI-V cells.
[0018] FIG. 1 illustrates an embodiment of a method 100 of forming a single HJ HI-V
PV cell via spalling. FIG. 1 is discussed with reference to FIGs. 2-4. In block 101, a optional back surface field (BSF) 202 is formed on a wafer of a IH-V substrate 201, as shown in FIG. 2. Substrate 201 may comprise germanium (Ge) and/or gallium arsenide (GaAs) in some embodiments. Substrate 201 may comprise an n-type or a p-type substrate. The optional BSF 202 may be formed by depositing a layer of a dopant on the substrate 201, and diffusing the dopant into the substrate 201 in some embodiments, or the optional BSF 202 may comprise a localized back contact. The dopant used to form optional BSF 202 may comprise zinc (Zn), indium (In), or aluminum (Al) in some embodiments. Optional BSF 202 may alternately comprise another material that deposited directly on the substrate 201; the BSF material may have a wider band gap than that of the substrate 201. Some examples of an appropriate BSF material may comprise InGaP (for a Ge substrate), or AlGaAs (for a GaAs substrate). [0019] In block 102, a tensile stressed metal layer 203 is formed, and a flexible substrate layer 204 is adhered to the metal layer 203, as shown in FIG. 2. In embodiments that do not comprise optional BSF 202, metal layer 203 is formed directly on substrate 201. Metal layer 203 may comprise nickel (Ni) in some embodiments. Flexible substrate layer 204 may comprise a flexible adhesive, which may be water-soluble in some embodiments. Use of a rigid material for the flexible substrate layer 204 may render the spalling mode of fracture unworkable. Therefore, flexible substrate layer 204 may further comprise a material having a radius of curvature of less than 5 meters in some embodiments, and less than 1 meter in some exemplary embodiments.
[0020] In block 103, base layer 301 is spalled from substrate 201, as shown in FIG. 3.
The flexible substrate 204 is used to cause the tensile stress in metal layer 203 to form fracture 302 in substrate 201, separating base layer 301 from substrate 201. Base layer 301 comprises the same material as substrate 201, and may be less than about 20μm thick in some embodiments. The thickness of the base layer 301 is determined by the tensile stress and thickness of metal layer 203. In embodiments comprising optional BSF 202, optional BSF 202 is spalled from substrate 201 along with base layer 301. In block 104, flexible substrate layer 204 is removed from metal layer 203.
[0021] In block 105, a single HJ IH-V PV cell 400 is formed using base layer 301, as shown in FIG. 4. Single HJ IH-V cell 400 comprises optional BSF 202; however, in some embodiments, base layer 301 may be located directly on metal layer 203, and optional BSF 202 may be absent. Metal layer 203 may comprise a back contact for the single HJ H-IV cell 400. Intrinsic layer 401 is formed on base layer 301, a-Si layer 402 is formed on intrinsic layer 401, and transparent conducting oxide (TCO) layer 403 is formed on amorphous silicon layer 402. The a-Si layer 402 may have a doping type (n-type or p-type) that is opposite the doping type of substrate 201; in such an embodiment, the a-Si layer 402 is configured to act as an emitter for the HJ TII-V cell 400. In some embodiments, an a-Si layer 402 configured to act as an emitter may be formed on subtrate 201 or BSF 202 before spalling instead of after spalling. TCO layer 403 may comprise zinc oxide (ZnO) doped with aluminum (Al) in some embodiments. Finger or bus bars (not shown) may be formed on TCO layer 403 in some embodiments.
[0022] While some embodiments of single HJ IH-V PV cell 400 may comprise a base layer 301 formed by spalling, other embodiments of cell 400 may comprise a base layer 301 formed by smart cut or epitaxial layer transfer. In embodiments using smart cut or epitaxial layer transfer methods, BSF 202 and/or a-Si layer 402 configured to act as an emitter may optionally be formed on substrate 201, then either smart cut or epitaxial layer transfer are used to separate the base layer 301 from the substrate 201. A single HJ HI-V cell 400 may then be formed using base layer 301 in the same manner discussed above with respect to block 105.
[0023] FIG. 5 illustrates an embodiment of a method 500 of forming a double HJ IH-V
PV cell via spalling. FIG. 5 is discussed with reference to FIGs. 6-8. In block 501, an intrinsic layer 602 is formed in a wafer of a IH-V substrate 201, as shown in FIG. 6. Substrate 601 may comprise Ge and/or GaAs in some embodiments. Substrate 601 may comprise an n-type or a p- type substrate. An optional BSF 603 may be formed on intrinsic layer 602 in some embodiments. Optional BSF 603 may comprise a material having a wider band gap than that of the substrate 601. Some examples of an appropriate BSF material may comprise InGaP (for a Ge substrate) or AlGaAs (for a GaAs substrate). An a-Si layer 604 is then formed on intrinsic layer 602 in embodiments not comprising optional BSF 603; in such embodiments, a-Si layer 604 and intrinsic layer 602 may function together as a back surface field. In embodiments comprising optional BSF 603, a-Si layer 604 is formed on optional BSF 603. The a-Si layer 604 may comprise a doping type (n-type or p-type) that is the same as that of substrate 601; in such an embodiment, the a-Si layer 604 may act as a BSF. The a-Si layer 604 may alternately comprise a doping type that is opposite that of substrate 601 ; in such an embodiment, a-Si layer 604 may act as an emitter.
[0024] In block 502, a tensile stressed metal layer 605 is formed on a-Si layer 604, and a flexible substrate layer 606 is adhered to the metal layer 605, as shown in FIG. 6. Metal layer 605 may comprise nickel (Ni) in some embodiments. Flexible substrate layer 606 may comprise a flexible adhesive, which may be water-soluble in some embodiments. Use of a rigid material for the flexible substrate layer 606 may render the spalling mode of fracture unworkable. Therefore, flexible substrate layer 606 may further comprise a material having a radius of curvature of less than 5 meters in some embodiments, and less than 1 meter in some exemplary embodiments.
[0025] In block 503, a base layer 701 is spalled from substrate 601, as shown in FIG. 7.
The flexible substrate 606 is used to cause the tensile stress in metal layer 605 to form fracture 702 in substrate 601, separating base layer 701 from substrate 601. Base layer 601 comprises the same material as substrate 601, and may be less than about 20μm thick in some embodiments. The thickness of the base layer 701 is determined by the tensile stress and thickness of metal layer 605. Intrinsic layer 602, optional BSF 603 (in embodiments comprising optional BSF 603), and a-Si layer 604 are spalled from substrate 601 along with base layer 701. In block 504, flexible substrate layer 606 is removed from metal layer 605.
[0026] In block 505, a double HJ HI-V PV cell 800 is formed using base layer 701 , as shown in FIG. 8. Double HJ HI-V cell 800 comprises optional BSF 603; however, in some embodiments, intrinsic layer 602 may be located directly on a-Si layer 604, and optional BSF 603 may be absent. Metal layer 605 may comprise a back contact for the single HJ H-IV cell
800. Intrinsic layer 801 is formed on base layer 701, a-Si layer 802 is formed on intrinsic layer
801, and TCO layer 803 is formed on amorphous silicon layer 802. The a-Si layer 802 may comprise a doping type (n-type or p-type) that is opposite the doping type of substrate 601 ; in such an embodiment, a-Si layer 802 may act as an emitter for double HJ IH-I V cell 800. TCO layer 803 may comprise zinc oxide (ZnO) doped with aluminum (Al) in some embodiments. Finger or bus bars (not shown) may be formed on TCO layer 803 in some embodiments.
[0027] While some embodiments of double HJ III-V PV cell 800 may comprise a base layer 701 formed by spalling, other embodiments of cell 800 may comprise a base layer 701 formed by epitaxial layer transfer. In embodiments using epitaxial layer transfer to form base layer 701, a sacrificial layer is formed in the substrate 601, then intrinsic layer 602, optional BSF 603, and a-Si layer 604 are formed on substrate 601. The base layer 701, intrinsic layer 602, optional BSF 203, and a-Si layer 604 are separated from the substrate 601 at the sacrificial layer. A double HJ IH-V cell 800 may then be formed using base layer 701, intrinsic layer 602, optional BSF 203, and a-Si layer 604 in the same manner discussed above with respect to block 505.
[0028] The technical effects and benefits of exemplary embodiments include formation of a lightweight, flexible solar cell.
[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0030] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A method for forming a heteroj unction III-V photovoltaic (PV) cell, the method comprising:
performing layer transfer of a base layer from a wafer of a IH-V substrate, the base layer being less than about 20 microns thick;
forming an intrinsic layer on the base layer;
forming an amorphous silicon layer on the intrinsic layer; and
forming a transparent conducting oxide layer on the amorphous silicon layer.
2. The method of claim 1, wherein the layer transfer comprises smart cut, and wherein smart cut comprises:
performing hydrogen implantation in the wafer below the base layer; and
annealing the wafer to initiate a fracture below the base layer.
3. The method of claim 1, wherein the layer transfer comprises epitaxial layer transfer, and wherein epitaxial layer transfer comprises:
forming a sacrificial layer in the wafer below the base layer; and
using a wet chemical etch of the sacrificial layer to remove the base layer from the wafer.
4. The method of claim 1, wherein the layer transfer comprises spalling, and wherein spalling comprises:
forming a metal layer having a tensile stress on the wafer;
adhering a flexible substrate to the metal layer;
using the tensile stress in the metal layer to cause a fracture in the wafer below the base layer; and
removing the flexible substrate from the metal layer.
5. The method of claim 4, wherein the metal layer comprises nickel.
6. The method of claim 4, wherein the flexible substrate comprises a material having a radius of curvature of less than 5 meters.
7. The method of claim 1, further comprising forming a back surface field on the wafer before performing layer transfer, wherein the back surface field comprises at least one of zinc, indium, and wherein the back surface field is layer transferred from the wafer with the base layer.
8. The method of claim 1, wherein the amorphous silicon layer comprises a doping type that is opposite a doping type of the substrate, and the amorphous silicon layer is configured to act as an emitter.
9. The method of claim 1, further comprising forming a second intrinsic layer on the wafer and forming a second amorphous silicon layer on the second intrinsic layer before performing layer transfer, wherein the second intrinsic layer and second amorphous silicon layer are layer transferred from the wafer with the base layer.
10. The method of claim 10, wherein the second amorphous silicon layer comprises a doping type that is the same as a doping type of the substrate, and the second amorphous silicon layer is configured to act as a back surface field.
11. The method of claim 1, The method of claim 10, wherein the second amorphous silicon layer comprises a doping type that is the opposite to a doping type of the substrate, and the second amorphous silicon layer is configured to act as an emitter.
12. The method of claim 1, wherein the wafer comprises one of germanium or gallium arsenide.
13. A heteroj unction IH-V photovoltaic (PV) cell, comprising:
a base layer comprising a IH-V substrate, the base layer being less than about 20 microns thick;
an intrinsic layer located on the base layer;
an amorphous silicon layer located on the intrinsic layer; and
a transparent conducting oxide layer located on the amorphous silicon layer.
14. The heterojunction IH-V PV cell of claim 13, further comprising a back surface field located under the base layer, wherein the back surface field comprises at least one of zinc, indium, or aluminum.
15. The heterojunction IH-V PV cell of claim 13, wherein the amorphous silicon layer comprises a doping type that is opposite a doping type of the substrate, and the amorphous silicon layer is configured to act as an emitter.
16. The heterojunction HI-V PV cell of claim 13, further comprising a second intrinsic layer located under the base layer, and a second amorphous silicon layer located under the second intrinsic layer.
17. The heterojunction HI-V PV cell of claim 16, wherein the second amorphous silicon layer comprises a doping type that is the same as a doping type of the substrate, and the second amorphous silicon layer is configured to act as a back surface field.
18. The heterojunction III-V PV cell of claim 16, wherein the second amorphous silicon layer comprises a doping type that is opposite to a doping type of the substrate, and the second amorphous silicon layer is configured to act as an emitter.
19. The heterojunction III-V PV cell of claim 13, further comprising a metal layer located under the base layer, the metal layer comprising nickel.
20. The heterojunction III-V PV cell of claim 13, wherein the III-V substrate comprises one of germanium or gallium arsenide.
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