WO2010137683A1 - Procédé de production de substrat soi - Google Patents

Procédé de production de substrat soi Download PDF

Info

Publication number
WO2010137683A1
WO2010137683A1 PCT/JP2010/059073 JP2010059073W WO2010137683A1 WO 2010137683 A1 WO2010137683 A1 WO 2010137683A1 JP 2010059073 W JP2010059073 W JP 2010059073W WO 2010137683 A1 WO2010137683 A1 WO 2010137683A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
heat treatment
ion
handle
manufacturing
Prior art date
Application number
PCT/JP2010/059073
Other languages
English (en)
Japanese (ja)
Inventor
優二 飛坂
厚雄 伊藤
昌次 秋山
信 川合
Original Assignee
信越化学工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 信越化学工業株式会社 filed Critical 信越化学工業株式会社
Publication of WO2010137683A1 publication Critical patent/WO2010137683A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • a plasma gas when processing a single crystal silicon substrate, when oxidizing the surface, plasma of oxygen gas, when not oxidizing, hydrogen gas, argon gas, or a mixed gas thereof or hydrogen gas and helium gas. Examples thereof include mixed gas.
  • any gas may be used.
  • a single crystal silicon substrate and / or a handle substrate is placed in a chamber into which air is introduced, and after introducing a plasma gas such as nitrogen gas or argon gas, high-frequency plasma is generated, The surface is subjected to ozone treatment by converting atmospheric oxygen into ozone. Either or both of plasma treatment and ozone treatment can be performed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

La présente invention concerne un substrat de silicium sur isolant (SOI), l'occurrence de craquage provoqué par la différence des coefficients de dilatation thermique entre un substrat de manipulation et un substrat de silicium monocristallin ou analogue pouvant être empêchée dans ledit substrat. L'invention porte en outre sur un procédé de production d'un substrat de SOI, qui comprend les étapes suivantes : une étape d'implantation d'un ion hydrogène ou d'un ion de gaz rare dans une surface d'un substrat de silicium monocristallin qui sert de substrat donneur, pour former une couche à ion implanté ; une étape de soumission du substrat donneur doté de la couche à ion implanté à un premier traitement thermique ; une étape de soumission de la surface à ion implanté du substrat donneur ayant été soumis au premier traitement thermique et/ou d'une surface d'un substrat de manipulation à un traitement d'activation de surface ; suite au traitement de l'activation de surface, une étape de liaison de la surface à ion implanté du substrat donneur à la surface du substrat de manipulation ; une étape de soumission des substrats liés à un second traitement thermique ; et une étape de déstratification consistant à appliquer un impact mécanique à la couche à ion implanté des substrats liés qui ont été soumis au second traitement thermique, pour entraîner la déstratification des substrats liés dans le sens de la couche à ion implanté d'hydrogène, provoquant ainsi le transfert d'une mince pellicule de silicium sur le substrat de manipulation.
PCT/JP2010/059073 2009-05-29 2010-05-28 Procédé de production de substrat soi WO2010137683A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-130974 2009-05-29
JP2009130974A JP2010278342A (ja) 2009-05-29 2009-05-29 Ｓｏｉ基板の製造方法

Publications (1)

Publication Number Publication Date
WO2010137683A1 true WO2010137683A1 (fr) 2010-12-02

Family

ID=43222788

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/059073 WO2010137683A1 (fr) 2009-05-29 2010-05-28 Procédé de production de substrat soi

Country Status (2)

Country Link
JP (1) JP2010278342A (fr)
WO (1) WO2010137683A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016508291A (ja) * 2012-12-28 2016-03-17 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101219358B1 (ko) * 2011-07-26 2013-01-21 삼성코닝정밀소재 주식회사 기판 분리 방법 및 이를 이용한 접합기판 제조방법
WO2014013980A1 (fr) 2012-07-18 2014-01-23 日本碍子株式会社 Tranche composite et son procédé de fabrication

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016508291A (ja) * 2012-12-28 2016-03-17 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法
JP2018085536A (ja) * 2012-12-28 2018-05-31 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 多層半導体デバイス作製時の低温層転写方法

Also Published As

Publication number Publication date
JP2010278342A (ja) 2010-12-09

Similar Documents

Publication Publication Date Title
KR101575917B1 (ko) 실리콘 박막 전사 절연성 웨이퍼의 제조 방법
EP1986219A1 (fr) Substrat soi et procede de fabrication d'un substrat soi
US7977209B2 (en) Method for manufacturing SOI substrate
KR101335713B1 (ko) 접합 기판의 제조방법 및 접합 기판
TWI492275B (zh) The method of manufacturing the bonded substrate
WO2007074550A1 (fr) Procede de production de tranches soi et tranches soi ainsi produites
WO2007072632A1 (fr) Substrat de silicium sur isolant et son procede de fabrication
JP2008153411A (ja) Ｓｏｉ基板の製造方法
JP2007227415A (ja) 貼り合わせ基板の製造方法および貼り合わせ基板
JP5536465B2 (ja) 高温貼り合わせ法による貼り合わせウェーハの製造方法
EP2757574B1 (fr) Procédé de fabrication d'une plaquette composite
WO2007074551A1 (fr) Procede de production de tranches soi et tranches soi ainsi produites
TW201140662A (en) Method for the preparation of a multi-layered crystalline structure
WO2010137682A1 (fr) Procédé de production de tranche stratifiée
WO2010137683A1 (fr) Procédé de production de substrat soi
JP2018085536A (ja) 多層半導体デバイス作製時の低温層転写方法
JP5019852B2 (ja) 歪シリコン基板の製造方法
JP2008263010A (ja) Ｓｏｉ基板の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10780637

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10780637

Country of ref document: EP

Kind code of ref document: A1