WO2010135945A1

WO2010135945A1 - System on chip and starting method thereof

Info

Publication number: WO2010135945A1
Application number: PCT/CN2010/072346
Authority: WO
Inventors: 熊江; 刘永根
Original assignee: 炬才微电子（深圳）有限公司
Priority date: 2009-05-25
Filing date: 2010-04-29
Publication date: 2010-12-02
Also published as: CN101566974B; CN101566974A

Abstract

A system on chip (SOC) (1) and a starting method thereof are provided, which are suitable for the field of integrate circuit. The SOC includes an on-chip power supply device (11), a reset device (12) and a functional device (13), wherein the on-chip power supply device (11) includes a clock generator (111) for generating a clock signal, a first reference voltage generating circuit (112) for generating the first reference voltage and a power supply regulator (113) for providing a power supply voltage required by other device during working; the reset device (12) keeps the functional device (13) in a reset state in a preset delay time and when the delay time is over, releases the functional device (13) from the reset state and outputs a clock signal (20) in order to set the functional device (13) to work. Once the external power source (2) connects to the SOC, the on-chip power supply device (11) starts immediately under the action of the first reference voltage, and is not controlled by any reset signal and enable signal of other devices inside the system, so the start speed of the SOC is improved greatly.

Description

System on chip and startup method thereof

Technical field

The invention belongs to the field of integrated circuits, and in particular relates to a system on chip and a method for starting the same.

Background technique

a system on chip (System On The Chip, SOC) system usually includes four parts: a reference voltage generating circuit, a power generating circuit, a clock generating circuit, and a digital-analog hybrid circuit. In general, the reference voltage generating circuit requires a power generating circuit to supply power thereto, and the power generating circuit requires a reference voltage generating circuit to supply a reference voltage thereto; the clock generating circuit requires a power generating circuit to supply power thereto, and the power generating circuit requires a clock The generating device provides a clock signal for it; the digital-analog hybrid circuit requires both a power supply, a reference voltage, and a clock signal, and the digital-analog hybrid circuit may also control or regulate the power supply, the reference voltage, and the clock signal. The traditional starting method in the industry is: when the external power supply is connected to the SOC on-chip system, first establish a standby state, at least reset a part of the circuit; when receiving a power enable signal, generate a clock signal; when the clock signal reaches a stable state, The reference voltage signal can be started, and then the internal power supply starts under the action of the clock signal and the reference signal; when the internal power supply is stabilized, the function module is enabled, and the system enters the normal working state. The power-on time of the conventional method is almost equal to the sum of the startup times of the modules, resulting in a slow system startup time, which is not suitable for applications requiring a quick start system.

technical problem

It is an object of embodiments of the present invention to provide a system on a chip and a method for starting the same, so that the SOC system can be started up correctly and quickly.

Technical solution

The embodiment of the present invention is implemented in this manner, and a system on chip includes:

On-chip power supply device, reset device and functional device;

The on-chip power supply device includes a first reference voltage generating circuit and a power regulator for generating a first reference voltage, and the power regulator generates other device internals of the system on chip under the action of the first reference voltage Required power supply voltage;

The reset device causes the function device to be in a reset state within a preset delay time. When the delay time is completed, the reset state of the function device is released and a clock signal is output, and the function device is adjusted at the power source. The operation is started by the power supply voltage generated by the device, the first reference voltage, and the clock signal.

An embodiment of the present invention further provides a method for starting a system on a chip, the system on chip comprising an on-chip power supply device, a reset device, and a function device; the on-chip power supply device includes a first reference voltage for generating a first reference voltage Generating a circuit and a power regulator; the reset device includes a reset circuit and a delay circuit;

The startup method includes the following steps:

1): the power regulator in the on-chip power supply device is activated by the first reference voltage, and the reset circuit issues a reset signal to cause the function device to be in a reset state, and the delay circuit starts to work;

2): After the delay circuit completes the set time delay, the clock signal is transmitted to the function device, and the reset signal of the reset circuit disappears, and the function device starts to work normally.

Beneficial effect

In the embodiment of the present invention, once the external power source is connected to the system on chip, the on-chip power supply device starts to start immediately under the action of the first reference voltage, and is not controlled by any reset signal and enable signal of other devices in the system, that is, no need is needed. Waiting for other reset signals or enable signals from other devices on the system, thus greatly improving the startup speed of the system on chip; and the functional device does not need to wait until the power generated by the on-chip power supply device is completely stabilized, as long as the control device is controlled. After the delay circuit corresponding to a sub-function unit realizes the set time delay, the sub-function unit can work normally, further improving the startup speed of the system on chip; when the power supply voltage generated by the on-chip power supply device rises to a certain extent Before the functional device is enabled, the performance evaluation device is used to evaluate the power performance generated by the on-chip power supply device to improve the internal power supply performance.

DRAWINGS

1 is a schematic structural diagram of a system on chip provided by an embodiment of the present invention;

2 is a flow chart showing an implementation of the method for starting the system on chip shown in FIG. 1;

3 is a flow chart showing an implementation of another method for starting the system on chip shown in FIG. 1;

4 is a flow chart showing an implementation of another method for starting the system on chip shown in FIG. 1;

Figure 5 is a diagram showing an example of the structure of a clock generator 111 in the on-chip power supply unit 11 shown in Figure 1;

6 is a diagram showing an example of the structure of a first reference voltage generating circuit 112 in the on-chip power supply device 11 shown in FIG. 1;

Fig. 7 is a view showing an example of the structure of the delay circuit 121 and the reset circuit 122 in the reset device 12 shown in Fig. 1.

Embodiments of the invention

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the embodiment of the present invention, once the external power source is connected to the system on chip, the on-chip power supply device starts to start immediately under the action of the first reference voltage, and is not controlled by any reset signal and enable signal of other devices in the system.

FIG. 1 shows the structural principle of the system on chip provided by the embodiment of the present invention. For the convenience of description, only parts related to the present invention are shown.

Referring to FIG. 1, the system on chip 1 includes four parts of an on-chip power supply device 11, a reset device 12, a function device 13, and a performance evaluation device 14. The system-on-chip is connected to an external power supply 2, which can be a battery or other power generator, but it can only provide the correct supply voltage for some of the circuits in the system on a chip.

The on-chip power supply device 11 includes a clock generator 111, a first reference voltage generating circuit 112, and a power conditioner 113. The clock generator 111, the first reference voltage generating circuit 112, and the power conditioner 113 are all connected to the external power source 2, and the power supply is adjusted. The device 113 can be a linear adjustment tube (Low Dropout Regulator, LDO), switching power supply or charge pump. Once the external power source 2 is connected to the system on chip 1, the clock generator 111 and the first reference voltage generating circuit 112 are immediately energized to start operation, and the clock generator 111 generates a clock signal required by the power conditioner 113, and the first reference voltage generating circuit 112 A first reference voltage required by the power conditioner 113 is generated. Then, the power regulator 113 normally starts to generate the power supply voltage under the action of the clock signal and the first reference voltage, and after a certain time, the on-chip power supply device 11 reaches a steady state. That is, once the external power source 2 is connected to the system on chip 1, the power conditioner 113 in the on-chip power supply unit 11 can generate at least one stable power supply voltage signal to supply power to other devices in the system on chip 1. Since the clock generator 111 of the on-chip power supply device 11 and the first reference voltage generating circuit 112 are not controlled by any of the reset signal and the enable signal, once the external power source 2 is connected to the system on chip 1, the clock generator 111 and the first reference The voltage generating circuit 112 can work normally, and immediately activates the power conditioner 113 of the on-chip power supply device 11, that is, the power regulator 113 of the power supply device 11 does not need to wait for other signals from the on-chip system 1 to issue any signal, and thus starts to be started, thus greatly The startup speed of the system on chip 1 is increased.

It should be understood that the above description regarding the structure of the on-chip power supply device 11 is only described by taking an application requiring a clock generator as an example, and for an application that does not require a clock generator, the on-chip power supply device 11 may not include a clock generator.

The reset device 12 includes a delay circuit 121, a reset circuit 122, a clock masker 123, and a clock generator 124. The delay circuit 121, the reset circuit 122, and the clock mask 123 are directly powered by the external power source 2, and the clock generator 124 is The power supply voltage generated by the power conditioner 113 in the on-chip power supply device 11 is supplied with power. When the external power source 2 is connected to the system on chip 1, the reset circuit 122 immediately generates a reset signal to reset the function device 13 to prevent the function device 13 from starting to operate during the startup of the on-chip power source device 12, resulting in malfunction. At the same time, the reset circuit 122 controls the clock mask 123 connected thereto to shield the clock signal generated by the clock generator 124 from being transmitted to the functional device 13. When the power supply voltage output from the on-chip power supply unit 11 rises to enable the clock generator 124 to start operating, the clock generator 124 starts generating the clock signal required by the functional device 13. After the external power source 2 is connected to the system on chip 1, the delay circuit 121 starts to work. After the set time delay, the delay circuit 121 sends a control signal to the reset circuit 122 to stop the reset circuit 122 from outputting to the function device 13. The reset signal, the reset circuit 122, in turn sends a control signal to the clock mask 123, causing the clock mask 123 to send the clock signal generated by the clock generator 124 to the functional device 13, and the functional device 13 starts operating. That is to say, the time from when the external power source 2 is connected to the system on chip 1 to when the function device 13 starts to operate is completely controlled by the delay circuit 121, and the function device 13 can be started as long as the delay circuit 121 has passed the set time delay.

The functional device 13 includes a plurality of sub-function units having different operating voltages, such as the first sub-function unit 131 and the second sub-function unit 132 in FIG. 1, and each of the sub-function units may be a digital circuit, an analog circuit, or a digital-analog hybrid circuit. Used to implement the functions set by the system on chip 1. When the external power source 2 is connected to the system on chip 1, the reset signal generated by the reset circuit 122 resets the function device 13. The on-chip power supply unit 11 supplies the functional device 13 with the power supply voltage and reference voltage required for operation. Corresponding to the plurality of sub-function units in the function device 13, the delay circuit 121 is provided with a plurality of delay times. When the delay circuit 121 generates the first delay completion signal, the clock masker 123 sets the clock generator 124. The generated clock signal is sent to the first sub-function unit 131, so that the first sub-function unit 131 starts normal operation; when the delay circuit 121 generates the second delay completion signal, the clock masker 123 generates the clock generator 124. The clock signal is sent to the second sub-function unit 132 so that the second sub-function unit 132 starts normal. That is to say, the function device 13 does not need to wait for the on-chip power supply device 11 to be completely stable before starting operation, which can be sequentially controlled according to the characteristics of each sub-function unit in the functional device 13 during the rise of the power supply voltage outputted by the power supply device 11 start working.

In the embodiment of the present invention, the performance evaluation device 14 includes a performance evaluation circuit 141. When the on-chip power supply device 11 issues a power supply primary stabilization signal, the performance evaluation circuit 141 starts to evaluate the power supply voltage performance output by the power conditioner 113, and if it detects The power supply voltage performance index output by the on-chip power supply device 11 does not meet the setting requirement (if it is detected that the power supply voltage value changes sharply with temperature or the power supply voltage value does not accurately reach the set target), the performance evaluation circuit 141 adjusts to the power supply. The device 113 issues a performance adjustment signal. The power regulator 113 adjusts the power supply voltage outputted by itself, and returns a performance detection signal to the performance evaluation circuit 141. The performance evaluation circuit 141 evaluates the power supply voltage performance outputted by the power conditioner 113 again, and repeats the above steps until the power supply voltage. Performance meets the requirements. The power primary stabilization signal is sent by the clock generator 111 or the power conditioner 113 of the on-chip power supply unit 11.

Further, the performance evaluation device 14 further includes a second reference voltage generation circuit 142 and a voltage reference selector 143 that are simultaneously connected to the first reference voltage generation circuit 112 and the second reference voltage generation circuit 142. The first reference voltage generating circuit 112 controls the power conditioner 113 and the function device 13 of the on-chip power supply device 11 before the performance evaluation device 14 starts operating. After the system is started, if the performance evaluation circuit 141 detects that the first reference voltage of the first reference voltage generating circuit 112 cannot satisfy the performance requirement of a certain sub-function unit of the on-chip power supply device 11 or the functional device 13, the performance evaluation circuit 141 The second reference voltage generated by the second reference voltage generating circuit 142 is controlled by the voltage reference selector 143 in place of the first reference voltage, thereby optimizing the performance of a power source or a sub-function unit in the functional device 13 output from the on-chip power supply device 11. If the performance evaluation circuit 141 detects that the first reference voltage performance satisfies the requirements of the on-chip power supply device 11 and the functional device 13, it is not necessary to switch the reference voltage, and the second reference voltage generation circuit 142 can be turned off to save system power consumption. Of course, the performance evaluation device 14 does not necessarily need to wait for the on-chip power supply device 11 to be completely stable before starting to work, and can also start working after the power supply voltage output from the on-chip power supply device 11 rises to a certain level, thereby further improving the system on chip 1 Startup speed.

FIG. 2 shows an implementation flow of the startup method of the system on chip shown in FIG. 1, which is detailed as follows:

In step S21, the power conditioner in the on-chip power supply device is immediately activated; the reset circuit issues a reset signal to cause the function device to be in a reset state, and the delay circuit starts operating.

Once the external power source is connected to the system-on-chip, the clock generator and the first reference voltage generating circuit in the on-chip power supply device are immediately powered, and the clock generator generates a clock signal required by the power regulator, and the first reference voltage generating circuit generates The first reference voltage required by the power regulator, and then the power regulator is normally started under the control of the clock signal and the first reference voltage. Since the on-chip power supply device is activated without any control of the reset signal and the enable signal, It does not need to wait for other signals from other devices on the system to start the startup, thus greatly improving the startup speed of the system on chip.

When the external power supply is connected to the system on chip, the reset circuit immediately generates a reset signal to reset the function device, preventing the function device from starting to work during the startup of the on-chip power supply device, causing malfunction, and the delay circuit starts to work and is delaying. The time-waiting control masks the clock signal required for the functional device to operate normally.

In step S22, the delay circuit completes the set time delay, and the function device starts normal operation.

In the embodiment of the present invention, the function device includes a plurality of sub-function units having different operating voltages. To further improve the startup speed of the system on chip, the function device does not need to wait until the power supply voltage generated by the on-chip power supply device is completely stable, and then starts to work. According to different working voltages of each sub-function unit in the functional device, a plurality of delay times are correspondingly set in the delay circuit, and after the delay circuit completes the set time delay, the clock signal is transmitted to the function device, and reset. The reset signal of the circuit disappears, so that the sub-function unit starts to work normally.

In addition, to ensure the performance of the power supply voltage of the on-chip power supply device to the functional device, the system on chip further includes a performance evaluation device, the performance evaluation device including a performance evaluation circuit; as shown in FIG. 3, in steps S21 and S22 In addition, the following steps are also included:

In step S2111, the performance evaluation circuit evaluates whether the power supply voltage performance generated by the power supply regulator meets the requirements, such as whether the power supply voltage value changes sharply with temperature or the power supply voltage value does not accurately reach the set target, and then proceeds to step S2112. Otherwise proceed to step S2113;

Among them, the performance evaluation circuit does not necessarily need to wait for the on-chip power supply device to be completely stable before starting to work. It can start working after the power supply voltage output from the on-chip power supply device rises to a certain level, which can further improve the startup speed of the system on chip.

In step S2112, the performance evaluation circuit stops working, the power supply voltage of the power regulator maintains the original performance, proceeds to step S22;

In step S2113, the power conditioner adjusts the signal according to the performance of the performance evaluation circuit to boost the generated power performance, and proceeds to step S2111.

After adjusting the power supply voltage of the self-output, the power regulator returns a performance detection signal to the performance evaluation circuit, and the performance evaluation circuit evaluates the power supply voltage performance of the power regulator output again, and repeats the above steps until the power supply voltage performance meets the requirements.

Further, the performance evaluation device further includes a second reference voltage generating circuit and a voltage reference selector for generating the second reference voltage. At this time, the startup process of the system on chip is as shown in FIG. 4, and after step S21, the method further includes The evaluation result of the performance evaluation circuit selects the step of outputting the reference voltage circuit, specifically:

In step S2114, the performance evaluation circuit evaluates whether the first reference voltage meets the requirements, if not, the process proceeds to step S2115, otherwise proceeds to step S22;

In step S2115, the voltage reference selector controls the output of the second reference voltage to the functional device, and proceeds to step S22.

It should be understood that the step markings of the embodiments of the present invention and the claims are only used to refer to the steps, and are not intended to limit the order in which the steps are performed.

FIG. 5 shows a structural example of the clock generator 111 in the on-chip power supply device 11 shown in FIG. 1, which is a ring oscillator with RC delay, in which T1, T2, and T3 are inverters, and output clock signals. The frequency is about . The power supply of the clock generator 111 is supplied from the external power supply 2. As long as the external power supply 2 is connected to the system on chip 1, the clock generator 111 can immediately generate a clock signal 2 to drive the power conditioner 113 to start.

6 shows a structural example of the first reference voltage generating circuit 112 in the on-chip power supply device 11 shown in FIG. 1, whose input voltage is the external power source 2, and outputs a reference voltage signal as long as the external power source 2 is connected to the system on chip 1 The first reference voltage generating circuit 112 can generate a reference voltage signal having a magnitude of the gate voltage of the NMOS transistor Q, that is, the sum of the threshold voltage of the NMOS transistor Q and its overdrive voltage. If the overdrive voltage is designed to be much smaller than the threshold voltage of the NMOS transistor 21, the reference voltage signal is approximately the threshold voltage of the NMOS transistor Q, so that the first reference voltage generating circuit 112 generates a relatively stable reference voltage signal.

FIG. 7 is a structural example of the delay circuit 121 and the reset circuit 122 in the reset device 12 shown in FIG. 1. The input signal is the signal of the external power source 2, and the output signal is the reset signal. When the external power supply 2 is connected to the system on chip 1, the external power supply 2 immediately gives the D flip-flop 1, D flip-flop 2 The D flip-flop 3 and the inverter T are powered, but due to the delay of the resistor R and the capacitor C, the input of the inverter T remains low after the external power source 2 is connected to the system on chip 1 for a certain period of time, thereby During the period of time, the output of the inverter T is kept high, so the D flip-flop 1, D flip-flop 2 and D flip-flop 3 are cleared under the control of the clear signal, so that the reset signal remains low. The function device 13 is placed in the reset state. When the input terminal of the inverter T rises slowly to a high level, the clear signal outputs a low level, so that the D flip-flop 1, the D flip-flop 2, and the D flip-flop 3 stop the clearing operation, and start the control of the clock signal. Work under. The reset signal is held low until the function of the fourth rising edge signal from the start of the clock signal, so that the functional device 13 is always in the reset state. When the fourth rising edge signal of the clock signal arrives, the delay circuit 121 outputs a rising edge signal to the reset circuit 122 to cause the reset signal to transition from a low level to a high level, so that the function device 13 exits the reset state and starts. normal work. It should be understood that, in specific implementation, the number of D flip-flops in the delay circuit 121 can be set according to the time condition.

In the embodiment of the present invention, once the external power source is connected to the system on chip, the on-chip power supply device can start to start immediately, without any reset signal and enable signal control of other devices in the system, that is, there is no need to wait for other devices of the system on the chip to issue any The reset signal or the enable signal greatly increases the startup speed of the system on the chip; and the functional device does not need to wait for the power generated by the on-chip power supply device to be fully stabilized, as long as the control device corresponds to a sub-function unit. After the delay circuit realizes the set time delay, the sub-function unit can work normally, further improving the startup speed of the system on chip; when the power supply voltage generated by the on-chip power supply device rises to a certain extent and before the functional device is enabled The performance evaluation device is used to evaluate the power performance generated by the on-chip power supply unit to improve the internal power supply performance.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims

A system on a chip, characterized in that the system on a chip comprises:

On-chip power supply device, reset device and functional device;

The on-chip power supply device includes a first reference voltage generating circuit and a power regulator for generating a first reference voltage, and the power regulator generates other device internals of the system on chip under the action of the first reference voltage Required power supply voltage;

The reset device causes the function device to be in a reset state within a preset delay time. When the delay time is completed, the reset state of the function device is released and a clock signal is output, and the function device is adjusted at the power source. The operation is started by the power supply voltage generated by the device, the first reference voltage, and the clock signal.
A system-on-chip according to claim 1, wherein said on-chip power supply device further comprises a clock generator for generating a clock signal, said power regulator having a clock signal at said clock generator and said A reference voltage produces the supply voltage required for operation of other devices within the system on the chip.
The system-on-chip according to claim 1, wherein said functional device comprises a plurality of sub-functional units having different operating voltages, said resetting means being pre-configured with a delay corresponding to said plurality of said sub-functional units Time, each time a delay time is completed, the reset device releases the reset state of the corresponding sub-function unit and outputs a clock signal, and the power supply voltage generated by the sub-function unit at the power regulator and the function of the clock signal Start working.
The system-on-chip of claim 1, 2 or 3, wherein said resetting means comprises:

a delay circuit for presetting one or more delay times;

a reset circuit, configured to output a reset signal to the function device, and stop outputting the reset signal when the delay circuit completes the delay time;

a clock generator for generating a clock signal;

a clock mask connected to the reset circuit for shielding a clock signal generated by the clock generator when the reset circuit outputs a reset signal to the function device, and stopping outputting a reset signal at the reset circuit The clock signal generated by the clock generator is sent to the functional device.
The system-on-chip of claim 1, wherein said system on chip further comprises a performance evaluation device, said performance evaluation device comprising:

a performance evaluation circuit, configured to evaluate a power supply voltage performance of the power regulator output, and if it is detected that the power supply voltage performance indicator does not meet the set requirement, send a performance adjustment signal to the power regulator to enable the power supply The regulator adjusts the power supply voltage of its own output.
The system-on-chip according to claim 5, wherein the performance evaluation circuit is further configured to check whether the first reference voltage meets a requirement of the functional device; the performance evaluation device further comprises:

a second reference voltage generating circuit for generating a second reference voltage;

a voltage reference selector connected to the first reference voltage generating circuit and the second reference voltage generating circuit, when the performance evaluation circuit detects that the first reference voltage cannot meet the requirement after the system is started, Controlling the output of the second reference voltage to the functional device.
A method for starting a system on a chip, characterized in that the system on chip includes an on-chip power supply device, a reset device, and a functional device; the on-chip power supply device includes a first reference voltage generating circuit for generating a first reference voltage and a power regulator; the reset device includes a reset circuit and a delay circuit;

The startup method includes the following steps:

1): the power regulator in the on-chip power supply device is activated by the first reference voltage, and the reset circuit issues a reset signal to cause the function device to be in a reset state, and the delay circuit starts to work;

2): After the delay circuit completes the set time delay, the clock signal is transmitted to the function device, and the reset signal of the reset circuit disappears, and the function device starts to work normally.
The startup method according to claim 7, wherein the function device of the system on chip comprises a plurality of sub-function units having different operating voltages, and the delay circuit is pre-configured with a plurality of the sub-function units Corresponding delay time; the step 2) is specifically:

Whenever the delay circuit completes a time delay, the clock signal is transmitted to the corresponding sub-function unit, and the reset signal of the sub-function unit disappears, and the sub-function unit starts normal operation.
The booting method according to claim 7 or 8, wherein said system on chip further comprises a performance evaluation device, said performance evaluation device comprising a performance evaluation circuit; after said step 1), said method further Including the following steps:

1a), the performance evaluation circuit evaluates whether the power supply voltage performance generated by the power regulator meets the requirements;

1b), if the power supply voltage performance generated by the power regulator can meet the requirements, the power supply voltage of the power regulator maintains the original performance, proceeds to step 2);

1c), if the power supply voltage performance generated by the power regulator is not satisfactory, the performance evaluation device sends a performance adjustment signal to the power regulator to adjust the power voltage output by the power regulator to the step 1a).
The startup method according to claim 7 or 8, wherein said performance evaluation means further comprises a second reference voltage generation circuit and a voltage reference selector for generating a second reference voltage; after said step 1) The method further includes the steps of:

1d), the performance evaluation circuit evaluates whether the first reference voltage can meet the requirements, if the requirements are not met, then proceeds to step 1e), otherwise proceeds to step 2);

1e), the voltage reference selector controls the output of the second reference voltage to the functional device, and proceeds to step 2).