WO2010111825A1 - Electronic package and method of fabrication thereof - Google Patents

Electronic package and method of fabrication thereof Download PDF

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Publication number
WO2010111825A1
WO2010111825A1 PCT/CN2009/071083 CN2009071083W WO2010111825A1 WO 2010111825 A1 WO2010111825 A1 WO 2010111825A1 CN 2009071083 W CN2009071083 W CN 2009071083W WO 2010111825 A1 WO2010111825 A1 WO 2010111825A1
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WO
WIPO (PCT)
Prior art keywords
module
dice
channels
electronic package
layer
Prior art date
Application number
PCT/CN2009/071083
Other languages
French (fr)
Inventor
Chi Kuen Leung
Peng Sun
Xunqing Shi
Chang Hwa Chung
Original Assignee
Hong Kong Applied Science And Technology Research Institute Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hong Kong Applied Science And Technology Research Institute Co., Ltd. filed Critical Hong Kong Applied Science And Technology Research Institute Co., Ltd.
Priority to CN2009800000263A priority Critical patent/CN101681903B/en
Priority to PCT/CN2009/071083 priority patent/WO2010111825A1/en
Publication of WO2010111825A1 publication Critical patent/WO2010111825A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention is concerned with an electronic package, an electronic package assembly and a method of fabrication thereof.
  • Electronic packages containing multiple chips are not new. Electronic packages may be classified into different ways. For example, some prior art electronic packages can be classified to include but not limited to (i) wire bonding (WB) die stacking, (ii) package-on-package or package stacking (PoP) and (iii) through-silicon-via (TSV). While these different classes of electronic packages may be advantageous in some ways, they are often deficient in others. For example, although WB die stacking may be considered relatively simple conceptually in their structure and is relatively mature as a technology their signal performance (due to the requirement of using a large amount of external wire connections), form factor and testability is generally considered to be unsatisfactory.
  • WB die stacking may be considered relatively simple conceptually in their structure and is relatively mature as a technology their signal performance (due to the requirement of using a large amount of external wire connections), form factor and testability is generally considered to be unsatisfactory.
  • WB die stacking often results a rather bulky package which would be undesirable in compact electronic device environment.
  • PoP may have a better testability but still their electrical performance and form factor are also not satisfactory.
  • Prior art TSV based die stacking packages have better electrical performance and form factor but yet they suffer from poor testability and high manufacturing cost due to complications in their fabrication.
  • the present invention seeks to provide a type of three-dimensional electronic package which can address some if not all the above problems, or at least to provide the general public with an alternative.
  • an electronic package comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, at least one of the modules includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over the die or dice, in the at least one of the modules the die or dice are bonded on the substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layer and arranged adjacent to the die or dice in the at least one of the modules or in the module stack, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, communication externally and connected to the channels. While the first and second modules are
  • the second module may be provided with a lower surface connected to an upper surface of the first module, with the lower surface being substantially planar and free of recesses.
  • the absence of recesses allows manufacture thereof to be relatively easy, of lower cost and predictable.
  • the dice in one module and the dice in another module from above or below may share a similar physical profile in terms of size and shape, they do not have to share the same profile. More specifically, dice of different kinds, functionalities or sizes may be stacked together. For example, a logic chip in some module may be arranged above a memory chip on another module from below.
  • one or more of the channels may extend across a substantial height of the module stack.
  • One or more of the channels may have a generally cylindrical, triangular prism or rectangular prism profile to suit a specific need.
  • the channels may be formed by mechanical drilling or laser drilling.
  • the conductive material layer may be coated on the inner surface of the channels by a single step of electroplating.
  • some or all of the channels may be filled entirely with a conductive material.
  • the inner surface of some or all of the channels may be filled with a conductive material layer followed by a step of filling the channels with a non-conductive material.
  • the intermediary may be a bonding pad.
  • the intermediary may be arranged at a bottom surface of the electronic package.
  • an electronic package assembly comprising a plurality of electronic packages, at least one of which is an electronic package as described above.
  • a method of fabrication of an electronic package assembly or an electronic package comprising the steps of (a) providing a substrate layer supported on a holding means, (b) bonding a plurality of dice on the substrate layer, with the dice separated by a predetermined distance and at pre-determined locations on the substrate layer, (c) over-molding a plastic(s) package molding compound over the dice and forming a first module, (d) forming a second module by repeating steps (a) to (c) but without introducing the holding means or with the holding means layer removed therefrom, (e) stacking the second module on the first module in a predetermined configuration and bonding the modules together, forming a module stack, (f) placing a film on the module stack for patterning and patterning the module stack, (g) forming substantially vertical channels through the module stack at locations whereby metal layers on which the dice rest are connected, and (h) coating inner surface of some or all of the channels with a conductive material layer or filling some
  • the holding means on which the first module is supported acts as a holder.
  • the dice may be bonded to the substrate at the metal layers via inner bonding pads.
  • the channels may be formed by mechanical drilling or laser drilling.
  • the holding means of the first module is removed, means serving as an intermediary connected to the channels for providing electrical, mechanical and thermal connectivity and for communication externally is exposed.
  • the intermediary may be in the form of outer bonding pads arranged on a bottom surface of the first module.
  • the dice on the second module are generally vertically aligned with the dice on the first module, they do not have to be.
  • the assembly may be divided and individual electronic packages are formed.
  • the inner surface when the inner surface of some or all of the channels is coated, the inner surface may be coated by a single step of electroplating. Specifically, after coating the inner surface with conductive material layer, the channels may be filled with a non-conductive material. Alternatively, in step (h) some or all of the channels may be filled with a conductive material only and without any coating.
  • the dice in each module or the dice from different modules do not share the same profile.
  • Figure 1 is schematic diagram showing an embodiment of a three-dimensional electronic package assembly according to the present invention
  • FIG. 2 is a schematic diagram showing an embodiment of an electronic package from the electronic package assembly of Figure 1 according to the present invention
  • Figures 3a to 3g are a series of schematic diagrams showing fabrication of the electronic package assembly of Figure 1;
  • Figure 4 is a schematic diagram showing another embodiment of a three-dimensional electronic package assembly according to the present invention.
  • Figure 5 is a schematic assembly showing an embodiment of an electronic package from the electronic package assembly of Figure 4.
  • US Patent No. 5,128,831 discloses a package containing a stack of modules interleaved by spacers.
  • US Patent No. 7,279,786 discloses a package on package system in which an upper substrate is provided with a recess at its bottom surface for accommodating one or more semiconductor die from below.
  • US Patent No. 7,317,256 discloses an electronic device package containing dice, each of which has a through-silicon via formed therethrough and with two layers of the packaged connected by solder joints.
  • US Patent Publication No. 2007/0216004 discloses a semiconductor device with chips thereon embedded in a plastic material.
  • 2008/0169546 discloses a semiconductor chip package stack showing one wafer mold stacked on top of the other.
  • the present invention proposes a different electronic package which possesses advantages over the prior devices at least in some respects.
  • electronic package and electronic package assembly carry generally the same meaning. It is also to be noted that for reason of brevity, contents in at least the above prior publications are not repeated but instead are included herein by reference in their entirety.
  • FIG. 1 schematically illustrates a first embodiment of an electronic package assembly 1 which has a three-dimensional structure.
  • the package assembly comprises three modules 2, 4, 6 which are generally in the form three layers.
  • the modules include a first layer 2a at the bottom, a second layer 4a in the middle and a third layer 6a on the top.
  • a substrate 8 which is generally planar acting as an interconnect layer
  • a predefined metal layer 10 arranged on the substrate at predetermined locations.
  • the modules are arranged in a configuration such that the dice in one module are arranged above the dice in the module therebelow such that the dice (when considered alone) are aligned and multiple columns of such dice are created.
  • column of dice it generally refers to at least two dice with one die in one module arranged above the other in the module from below. It is to be noted that while from Figure 1 each column appears to have equally three dice it is however not necessarily the case in practice. In other embodiments, it is possible that some columns may have more dice than others. It is also possible that certain module(s) may have more dice than others. It is also to be noted that the dice in each column do not have to share the same physical form or configuration.
  • FIG. 1 shows that the dice 18, 20, 22 in the second module have a smaller width than that the first and third modules 2, 6.
  • the design of the electronic package assembly 1 in accordance with the present invention provides a large degree of freedom on the size of the dice and yet the cost of assembly of the modules still remains relatively low.
  • Each module layer includes a material 32 molded over the dice such that the dice are encapsulated between the molding material 32 and the substrate 8.
  • the molding material in this embodiment is substantially organic plastic.
  • channels 34, 36, 38, 40, 42, 44 which are vertically arranged. It is to be noted that the particular locations of the channels are such that they pass through and connect the metal layer 10 in each module. More specifically, there is a pair of channels (e.g. 34, 36) on opposite sides of each column of dice (e.g. 24, 18, 12).
  • the channels can be considered as through-mold-via (TMV) which is relatively easy to form due to its substantially cylindrical profile and its passing through a substantial height of the modules stacked together.
  • TMV through-mold-via
  • the first module 2 is further provided with a bonding pad 46 at the bottom surface of the substrate and this bonding pad is an outer bonding pad.
  • the lower ends of the channels 34, 36, 38, 40, 42, 44 actually are connected to the outer bonding pad 46 for providing electrical, mechanical and thermal connectivity.
  • the channels are provided with an inner surface coated with a copper layer with high conductive properties. Thus, for example, heat can be dissipated from the dice to the external environment via the channels and the outer bonding pad. Electrical signals are of course transmissible along the channels to or from the outer bonding pad.
  • FIG 2 shows an electronic package divided from the electronic package assembly of Figure 1 in accordance with another embodiment of the present invention.
  • Some common reliability problems associated with conventional electronic packages include pop-corn, stress due to low standoff and handling.
  • pop-corn studies have shown that industry standard baking method can be used to successfully remove the moisture before the reflow in the present invention. Testing studies on the electronic package of Figure 2 shows that the problem of moisture is absent or negligible.
  • FIGs 3a to 3g are concerned with yet another embodiment of the present invention.
  • a method for fabrication of, for example, an electronic package assembly 1 as described above Referring firstly to Figure 3a, there is provided a wafer holder 50.
  • the use of the wafer holder 50 allows a reliable handling of the package as it is being fabricated.
  • the wafer holder 50 is then applied with an adhesive 52 and then a pre-fabricated interconnect layer 54 is connected on the wafer holder 50.
  • Figure 3b illustrates that a plurality of dice 56, 58, 60 are then bonded to the interconnect layer 54 at pre-determined locations such that the dice are separated by a pre- determined distance.
  • FIG. 3b further illustrates that an over-molding material 64 (BCB) is then applied by over-molding on the dice, thus encapsulating the dice on the wafer holder.
  • the over-molding of the material 64 may be performed by using a mold for defining the shape of the desired the encapsulated dice.
  • This encapsulated dice has formed a first layer or first module 66.
  • a second module 68 and a third module 70 are then similarly fabricated, except after they are formed the wafer holder is removed. Alternatively, they may be formed without the wafer holder at all. Please see Figure 3 c.
  • each module When each module has been made, it is firstly subjected to a testing step to ensure that it has met pre-defined testing parameters.
  • the testing of individual modules separately is relatively easy. It is to also be noted that the fabrication of individual modules undergoes a uniform step and this makes large scale manufacture simple and cost effective.
  • Figure 3c illustrates that the second module 68 is then placed on top of and bonded to the first module.
  • the wafer holder of the second module 68 is of course to be removed before it is bonded to the first module.
  • the dice in the first and second module stack 66, 68 are configured such that a plurality of columns of dice are provided with each die in the second module generally above and vertically align with a corresponding die in the first module.
  • column of dice it generally refers to at least two dice with one die in one module arranged above and align with the other in the module from below. However, such alignment is not necessary. In other embodiments, the dice from one module may not align with the dice from the module from above or below.
  • Figure 3c further illustrates that the third module 70 is similarly placed on top of and bonded to the second module 68.
  • the dice in the module stack 66, 68, 70 are configured such that a plurality of columns of dice are provided with each die in the third module arranged above and vertically align with corresponding dice in the first and second modules. It is however to be noted that while there are equal number of dice in each die column in this embodiment, in alternative embodiments, this does not have to be the case. For example, in one die column there may be three dice while in another column there may be only one die. Further, the dice in each die column may have different functionalities. Regardless of the arrangement of the dice in the module stack, the functionalities of the dice or the number of die columns in the module stack, the electronic package that is finally formed has a relatively preferable form factor.
  • Figure 3d illustrates that once the module stack with three die columns has been formed, the wafer holder is de-bonded and removed.
  • Figure 3e illustrates that a film 74 is placed on top of the third module and then the film illuminated for patterning purposes.
  • Figure 3f illustrates that subsequently holes 76, 78. 80, 82, 84, 86 are drilled at pre-determined locations on the third modules through the module stack.
  • the holes are substantially vertical and cylindrical in shape and they pass the metal layer on each module. It is schematically shown that each die column is sandwiched by a pair of the cylindrical hole (e.g. 76, 78). It is however to be noted that in other embodiments the number of holes may vary and can be many surrounding the columns of dice.
  • the holes provided with an inner surface are then electroplated with a copper later serving a conductive lining, as shown in Figure 3g. It is understood that communication is established between the modules and the module stack and the external environment. This relatively simple connection allows much better electrical performance.
  • the holes may be filled with a conductive material.
  • the holes may be coated with a layer of conductive material and filled with a non-conductive material.
  • the electronic package assembly in the first embodiment has three layers of modules and three columns of dice, the present invention is of course not limited to this specific configuration. For example, an electronic package assembly having five layers of modules is equally possible, as shown in Figure 4. From a mass production point of view, an electronic package assembly may be made to be of relative large size and with as many columns as possible because one assembly can yield many separate three-dimensional electronic packages.
  • a number of electronic packages may be formed from the assembly by cutting the assembly at predetermined locations.
  • Figure 5 shows one such electric package.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

An electronic package is provided, which comprises at least a first module (2) and a second module (4) arranged on top of the first module (2), wherein the first and second modules (2, 4) are adhesively connected together and in the form of a module stack. Each of the modules (2,4) includes a substrate layer (8) with at least one metal layer (10), at least one die (16, 22) and a plastic package molding compound layer (32) molded over the die or dice (16, 22), wherein the die or dice (16, 22) are bonded on the substrate layer (8) via the metal layer (10), and a plurality of channels (34, 36, 38, 40, 42, 44) are formed generally vertically acting as vias to connect the metal layers (10) in different modules. Some or all the channels (34, 36, 38, 40, 42, 44) are provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection, whereby the dice (16, 22) in the module stack are electrically connected together. At least one module (2) includes a means (46) which is connected to the channels (34, 36, 38, 40, 42, 44) and serves as an intermediary for providing electrical, mechanical and thermal connectivity, and communication externally. A method for fabricating the electronic package is also provided.

Description

ELECTRONIC PACKAGE AND METHOD OF FABRICATION THEREOF
FIELD OF THE PRESENTION INVENTION
The present invention is concerned with an electronic package, an electronic package assembly and a method of fabrication thereof.
BACKGROUND OF THE PRESENT INVENTION
Electronic packages containing multiple chips are not new. Electronic packages may be classified into different ways. For example, some prior art electronic packages can be classified to include but not limited to (i) wire bonding (WB) die stacking, (ii) package-on-package or package stacking (PoP) and (iii) through-silicon-via (TSV). While these different classes of electronic packages may be advantageous in some ways, they are often deficient in others. For example, although WB die stacking may be considered relatively simple conceptually in their structure and is relatively mature as a technology their signal performance (due to the requirement of using a large amount of external wire connections), form factor and testability is generally considered to be unsatisfactory. Also, WB die stacking often results a rather bulky package which would be undesirable in compact electronic device environment. PoP may have a better testability but still their electrical performance and form factor are also not satisfactory. Prior art TSV based die stacking packages have better electrical performance and form factor but yet they suffer from poor testability and high manufacturing cost due to complications in their fabrication.
The present invention seeks to provide a type of three-dimensional electronic package which can address some if not all the above problems, or at least to provide the general public with an alternative.
SUMMARY OF THE PRESENT INVENTION According to a first aspect of the present invention, there is provided an electronic package, comprising at least a first module and a second module arranged on top of the first module, the modules together in the form of a module stack, wherein the first and second modules are adhesively connected together, at least one of the modules includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over the die or dice, in the at least one of the modules the die or dice are bonded on the substrate layer via the metal layer, a plurality of channels formed generally vertically acting as vias to connect the metal layer and arranged adjacent to the die or dice in the at least one of the modules or in the module stack, some or all the channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby the dice are electrically connected together, and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, communication externally and connected to the channels. While the first and second modules are connected together adhesively, this would often mean that they are also mechanically and electrically connected together. The electronic package as described has a relatively simple which leads to a more reliable performance.
Preferably, the second module may be provided with a lower surface connected to an upper surface of the first module, with the lower surface being substantially planar and free of recesses. The absence of recesses allows manufacture thereof to be relatively easy, of lower cost and predictable.
In some embodiments, while the dice in one module and the dice in another module from above or below may share a similar physical profile in terms of size and shape, they do not have to share the same profile. More specifically, dice of different kinds, functionalities or sizes may be stacked together. For example, a logic chip in some module may be arranged above a memory chip on another module from below.
In some embodiments, one or more of the channels may extend across a substantial height of the module stack. One or more of the channels may have a generally cylindrical, triangular prism or rectangular prism profile to suit a specific need.
Preferably, the channels may be formed by mechanical drilling or laser drilling.
In a preferred embodiment, wherein when the inner surface of some or all of the channels is coated by said conductive material layer, the conductive material layer may be coated on the inner surface of the channels by a single step of electroplating. Alternatively, some or all of the channels may be filled entirely with a conductive material. Yet alternatively, the inner surface of some or all of the channels may be filled with a conductive material layer followed by a step of filling the channels with a non-conductive material.
The intermediary may be a bonding pad. The intermediary may be arranged at a bottom surface of the electronic package.
According to a second aspect of the present invention, there is provided an electronic package assembly, comprising a plurality of electronic packages, at least one of which is an electronic package as described above.
According to a third aspect of the present invention, there is provided a method of fabrication of an electronic package assembly or an electronic package, comprising the steps of (a) providing a substrate layer supported on a holding means, (b) bonding a plurality of dice on the substrate layer, with the dice separated by a predetermined distance and at pre-determined locations on the substrate layer, (c) over-molding a plastic(s) package molding compound over the dice and forming a first module, (d) forming a second module by repeating steps (a) to (c) but without introducing the holding means or with the holding means layer removed therefrom, (e) stacking the second module on the first module in a predetermined configuration and bonding the modules together, forming a module stack, (f) placing a film on the module stack for patterning and patterning the module stack, (g) forming substantially vertical channels through the module stack at locations whereby metal layers on which the dice rest are connected, and (h) coating inner surface of some or all of the channels with a conductive material layer or filling some or all the channels with a conductive material.
Preferably, the holding means on which the first module is supported acts as a holder.
Suitably, the dice may be bonded to the substrate at the metal layers via inner bonding pads.
Preferably, the channels may be formed by mechanical drilling or laser drilling.
After the module stack has been formed the holding means of the first module is removed, means serving as an intermediary connected to the channels for providing electrical, mechanical and thermal connectivity and for communication externally is exposed. The intermediary may be in the form of outer bonding pads arranged on a bottom surface of the first module.
Preferably, there may be provided with a step after the patterning of removing the film.
In some embodiments, while at least some of the dice on the second module are generally vertically aligned with the dice on the first module, they do not have to be.
After the electronic package assembly is formed, the assembly may be divided and individual electronic packages are formed.
In one embodiment, in step (h), when the inner surface of some or all of the channels is coated, the inner surface may be coated by a single step of electroplating. Specifically, after coating the inner surface with conductive material layer, the channels may be filled with a non-conductive material. Alternatively, in step (h) some or all of the channels may be filled with a conductive material only and without any coating.
In some embodiments, the dice in each module or the dice from different modules do not share the same profile.
BRIEF DESCRIPTION OF THE DRAWINGS Some embodiments of the present invention will now be described by way of example and with reference to the accompanying drawings, in which:-
Figure 1 is schematic diagram showing an embodiment of a three-dimensional electronic package assembly according to the present invention;
Figure 2 is a schematic diagram showing an embodiment of an electronic package from the electronic package assembly of Figure 1 according to the present invention;
Figures 3a to 3g are a series of schematic diagrams showing fabrication of the electronic package assembly of Figure 1;
Figure 4 is a schematic diagram showing another embodiment of a three-dimensional electronic package assembly according to the present invention; and
Figure 5 is a schematic assembly showing an embodiment of an electronic package from the electronic package assembly of Figure 4.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE PRESENT INVENTION
The prior art has disclosed many different types of electronic package system. For example, US Patent No. 5,128,831 discloses a package containing a stack of modules interleaved by spacers. US Patent No. 7,279,786 discloses a package on package system in which an upper substrate is provided with a recess at its bottom surface for accommodating one or more semiconductor die from below. US Patent No. 7,317,256 discloses an electronic device package containing dice, each of which has a through-silicon via formed therethrough and with two layers of the packaged connected by solder joints. US Patent Publication No. 2007/0216004 discloses a semiconductor device with chips thereon embedded in a plastic material. US Patent Publication No. 2008/0169546 discloses a semiconductor chip package stack showing one wafer mold stacked on top of the other. The present invention proposes a different electronic package which possesses advantages over the prior devices at least in some respects. For sake of clarity, it is to be noted that in this description electronic package and electronic package assembly carry generally the same meaning. It is also to be noted that for reason of brevity, contents in at least the above prior publications are not repeated but instead are included herein by reference in their entirety.
Figure 1 schematically illustrates a first embodiment of an electronic package assembly 1 which has a three-dimensional structure. In this embodiment, the package assembly comprises three modules 2, 4, 6 which are generally in the form three layers. Specifically, the modules include a first layer 2a at the bottom, a second layer 4a in the middle and a third layer 6a on the top. In each module, there are generally provided a substrate 8 (which is generally planar acting as an interconnect layer) and a predefined metal layer 10 arranged on the substrate at predetermined locations. There is also provided a predetermined number of rows of dice separated by a predetermined distance on the substrate 8, with each row having three dice (e.g. 12, 14, 16 on the first layer). The dice are bonded to the metal layer 10 via inner bonding pads 30.
The modules are arranged in a configuration such that the dice in one module are arranged above the dice in the module therebelow such that the dice (when considered alone) are aligned and multiple columns of such dice are created. By "column of dice", it generally refers to at least two dice with one die in one module arranged above the other in the module from below. It is to be noted that while from Figure 1 each column appears to have equally three dice it is however not necessarily the case in practice. In other embodiments, it is possible that some columns may have more dice than others. It is also possible that certain module(s) may have more dice than others. It is also to be noted that the dice in each column do not have to share the same physical form or configuration. Figure 1 shows that the dice 18, 20, 22 in the second module have a smaller width than that the first and third modules 2, 6. In fact, the design of the electronic package assembly 1 in accordance with the present invention provides a large degree of freedom on the size of the dice and yet the cost of assembly of the modules still remains relatively low. Each module layer includes a material 32 molded over the dice such that the dice are encapsulated between the molding material 32 and the substrate 8. The molding material in this embodiment is substantially organic plastic.
Across the package assembly, there is provided a plurality of channels 34, 36, 38, 40, 42, 44 which are vertically arranged. It is to be noted that the particular locations of the channels are such that they pass through and connect the metal layer 10 in each module. More specifically, there is a pair of channels (e.g. 34, 36) on opposite sides of each column of dice (e.g. 24, 18, 12). The channels can be considered as through-mold-via (TMV) which is relatively easy to form due to its substantially cylindrical profile and its passing through a substantial height of the modules stacked together. It is to be noted that while Figure 1 only shows two channels 34, 36 on opposite sides of the dice 12, 18, 24, in practice there are or may be many such channels surrounding the dice 12, 18, 24. However, for brevity and clarity reason only the channels 34, 36 are shown.
The first module 2 is further provided with a bonding pad 46 at the bottom surface of the substrate and this bonding pad is an outer bonding pad. The lower ends of the channels 34, 36, 38, 40, 42, 44 actually are connected to the outer bonding pad 46 for providing electrical, mechanical and thermal connectivity. The channels are provided with an inner surface coated with a copper layer with high conductive properties. Thus, for example, heat can be dissipated from the dice to the external environment via the channels and the outer bonding pad. Electrical signals are of course transmissible along the channels to or from the outer bonding pad.
Figure 2 shows an electronic package divided from the electronic package assembly of Figure 1 in accordance with another embodiment of the present invention.
Some common reliability problems associated with conventional electronic packages include pop-corn, stress due to low standoff and handling. With regard to the problem of pop-corn, studies have shown that industry standard baking method can be used to successfully remove the moisture before the reflow in the present invention. Testing studies on the electronic package of Figure 2 shows that the problem of moisture is absent or negligible.
It is to be noted that electronic packages or assemblies which are complex in structure often do have reliability issues. The electronic package and electronic package assembly described above are actually relatively simple and studies have shown that minimal reliability issues have arisen. This may be due to the use of generally vertical interconnections between top and bottom layers, the generally planar bottom surface of each layer and the lack of the use of, for example, solder balls for connection purposes. The studies have also shown that electronic packages made in accordance in the present invention have a good balance of desirable characteristics (e.g. functionality/testability, form factor, electrical performance, wafer area usage, manufacturing cost and throughput). The following table summaries these characteristics in comparison with conventional packages made by PoP and TSV.
Figure imgf000009_0001
Table 1 : Comparison of Characteristics of Different Types of Electronic Packages
From the above table, it is apparent that electronic packages made in accordance with the present invention have a good balance of characteristics.
Figures 3a to 3g are concerned with yet another embodiment of the present invention. In this embodiment, there is illustrated a method for fabrication of, for example, an electronic package assembly 1 as described above. Referring firstly to Figure 3a, there is provided a wafer holder 50. The use of the wafer holder 50 allows a reliable handling of the package as it is being fabricated. The wafer holder 50 is then applied with an adhesive 52 and then a pre-fabricated interconnect layer 54 is connected on the wafer holder 50. Figure 3b illustrates that a plurality of dice 56, 58, 60 are then bonded to the interconnect layer 54 at pre-determined locations such that the dice are separated by a pre- determined distance. It can be seen that the dice are bonded to the interconnect layer 54 via a bonding pad or inner bonding pad 62. Figure 3b further illustrates that an over-molding material 64 (BCB) is then applied by over-molding on the dice, thus encapsulating the dice on the wafer holder. The over-molding of the material 64 may be performed by using a mold for defining the shape of the desired the encapsulated dice. This encapsulated dice has formed a first layer or first module 66.
A second module 68 and a third module 70 are then similarly fabricated, except after they are formed the wafer holder is removed. Alternatively, they may be formed without the wafer holder at all. Please see Figure 3 c.
When each module has been made, it is firstly subjected to a testing step to ensure that it has met pre-defined testing parameters. The testing of individual modules separately is relatively easy. It is to also be noted that the fabrication of individual modules undergoes a uniform step and this makes large scale manufacture simple and cost effective.
Once the dice of the first module 66 have been over-molded and have taken shape, an adhesive is applied on top of the first module.
Figure 3c illustrates that the second module 68 is then placed on top of and bonded to the first module. The wafer holder of the second module 68 is of course to be removed before it is bonded to the first module. It is to be noted that the dice in the first and second module stack 66, 68 are configured such that a plurality of columns of dice are provided with each die in the second module generally above and vertically align with a corresponding die in the first module. Again, by "column of dice", it generally refers to at least two dice with one die in one module arranged above and align with the other in the module from below. However, such alignment is not necessary. In other embodiments, the dice from one module may not align with the dice from the module from above or below. In such case, no distinct column of dice would be seen. Figure 3c further illustrates that the third module 70 is similarly placed on top of and bonded to the second module 68. Similarly, the dice in the module stack 66, 68, 70 are configured such that a plurality of columns of dice are provided with each die in the third module arranged above and vertically align with corresponding dice in the first and second modules. It is however to be noted that while there are equal number of dice in each die column in this embodiment, in alternative embodiments, this does not have to be the case. For example, in one die column there may be three dice while in another column there may be only one die. Further, the dice in each die column may have different functionalities. Regardless of the arrangement of the dice in the module stack, the functionalities of the dice or the number of die columns in the module stack, the electronic package that is finally formed has a relatively preferable form factor.
Figure 3d illustrates that once the module stack with three die columns has been formed, the wafer holder is de-bonded and removed.
Figure 3e illustrates that a film 74 is placed on top of the third module and then the film illuminated for patterning purposes.
Figure 3f illustrates that subsequently holes 76, 78. 80, 82, 84, 86 are drilled at pre-determined locations on the third modules through the module stack. The holes are substantially vertical and cylindrical in shape and they pass the metal layer on each module. It is schematically shown that each die column is sandwiched by a pair of the cylindrical hole (e.g. 76, 78). It is however to be noted that in other embodiments the number of holes may vary and can be many surrounding the columns of dice.
The holes provided with an inner surface are then electroplated with a copper later serving a conductive lining, as shown in Figure 3g. It is understood that communication is established between the modules and the module stack and the external environment. This relatively simple connection allows much better electrical performance. Alternatively, the holes may be filled with a conductive material. Yet, alternatively, the holes may be coated with a layer of conductive material and filled with a non-conductive material. While the electronic package assembly in the first embodiment has three layers of modules and three columns of dice, the present invention is of course not limited to this specific configuration. For example, an electronic package assembly having five layers of modules is equally possible, as shown in Figure 4. From a mass production point of view, an electronic package assembly may be made to be of relative large size and with as many columns as possible because one assembly can yield many separate three-dimensional electronic packages.
After the electronic package assembly has been fabricated in accordance with the above described method, a number of electronic packages may be formed from the assembly by cutting the assembly at predetermined locations. Figure 5 shows one such electric package.

Claims

CLAIMS:
1. An electronic package, comprising at least a first module and a second module arranged on top of said first module, the modules together in the form of a module stack; wherein said first and second modules are adhesively connected together; at least one of said modules includes a substrate layer having at least one metal layer, at least one die and a plastic(s) package molding compound layer molded over said die or dice; in said at least one of said modules said die or dice are bonded on said substrate layer via said metal layer; a plurality of channels formed generally vertically acting as vias to connect said metal layer and arranged adjacent said die or dice in said at least one of said modules or in said module stack, some or all said channels provided with an inner surface coated with a conductive material layer or filled with a conductive material for electrical connection whereby said dice are electrically connected together; and means serving as an intermediary for providing electrical, mechanical and thermal connectivity, communication externally and connected to said channels.
2. An electronic package as claimed in Claim 1 , wherein said second module is provided with a lower surface connected to an upper surface of the first module, with said lower surface being substantially planar and free of recesses.
3. An electronic package as claimed in Claim 1, wherein said dice in each said module stack do not share the same profile.
4. An electronic package as claimed in Claim 1 , comprising at least a logic chip and/or a memory chip.
5. An electronic package as claimed in Claim 1, wherein one or more said channels extend across a substantial height of said module stack.
6. An electronic package as claimed in Claim 1, wherein one or more said channels have a generally cylindrical, triangular prism or rectangular prism profile.
7. An electronic package as claimed in Claim 1 , wherein said channels are formed by mechanical drilling or laser drilling.
8. An electronic package as claimed in Claim 1, wherein when said inner surface of said channels is coated by said conductive material layer, said conductive material layer is coated on said inner surface of said channels by a single step of electroplating.
9. An electronic package as claimed in Claim 1, wherein said intermediary is a bonding pad.
10. An electronic package as claimed in Claim 1, wherein said intermediary is arranged at a bottom surface of said electronic package.
11. An electronic package assembly, comprising a plurality of electronic packages, at least one of which is an electronic package as claimed in Claim 1.
12. A method of fabrication of an electronic package assembly or an electronic package, comprising the steps of :
(a) providing a substrate layer supported on a holding means;
(b) bonding a plurality of dice on the substrate layer, with the dice separated by a predetermined distance and at pre-determined locations on the substrate layer;
(c) over-molding a plastic(s) package molding compound over the dice and forming a first module;
(d) forming a second module by repeating steps (a) to (c) but without introducing the holding means or with the holding means layer removed therefrom;
(e) stacking the second module on the first module in a predetermined configuration and bonding the modules together, forming a module stack;
(f) placing a film on the module stack for patterning and patterning the module stack;
(g) forming substantially vertical channels through the module stack at locations whereby metal layers on which the dice rest are connected; and
(h) coating inner surface of some or all of the channels with a conductive material layer or filling said some or all of the channels with a conductive material.
13. A method as claimed in Claim 12, wherein the holding means on which said first module is supported acts as a holder.
14. A method as claimed in Claim 12, wherein the dice are bonded to the substrate at the metal layers via inner bonding pads.
15. A method as claimed in Claim 12, wherein the channels are formed by mechanical drilling or laser drilling.
16. A method as claimed in Claim 12, wherein after the module stack has been formed the holding means of the first module is removed whereby means serving as an intermediary connected to the channels for providing electrical, mechanical and thermal connectivity and for communication externally are exposed.
17. A method as claimed in Claim 16, wherein the intermediary are outer bonding pads arranged on a bottom surface of the first module.
18. A method as claimed in Claim 12, wherein after the patterning the film is removed.
19. A method as claimed in Claim 12, wherein in step (e) at least some of the dice on the second module are generally vertically aligned with the dice on the first module.
20. A method as claimed in Claim 12, wherein in step (h) when the inner surface of the channels is coated, the inner surface is coated by a single step of electroplating.
21. A method as claimed in Claim 12, wherein in step (h) when the inner surface of the channels is coated, comprising a further step of filling some or all of the channels with a non-conductive material.
22. A method as claimed in Claim 12, wherein the dice in each said module or the dice from different modules do not share the same profile.
PCT/CN2009/071083 2009-03-30 2009-03-30 Electronic package and method of fabrication thereof WO2010111825A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016530720A (en) * 2013-09-27 2016-09-29 インテル・コーポレーション Method for interconnecting multiple stacked semiconductor devices
CN107275323A (en) * 2017-07-25 2017-10-20 睿力集成电路有限公司 A kind of chip stack stereo encapsulation structure
US9985005B2 (en) 2013-03-15 2018-05-29 Intel Deutschland Gmbh Chip package-in-package
US12033983B2 (en) 2023-05-12 2024-07-09 Intel Corporation Method for interconnecting stacked semiconductor devices

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103400830B (en) * 2013-08-02 2015-12-09 华进半导体封装先导技术研发中心有限公司 Multilayer chiop stacked structure and its implementation
CN107579011A (en) * 2013-09-27 2018-01-12 英特尔公司 Method for the semiconductor devices of interconnection stack
CN105280615B (en) * 2014-06-11 2019-07-19 旺宏电子股份有限公司 A kind of multichip packaging structure and the method for preparing this multi-chip package
CN105047657A (en) * 2015-08-13 2015-11-11 陈明涵 AIO packaged structure and packaging method
CN111326503B (en) * 2019-12-31 2021-03-12 诺思(天津)微系统有限责任公司 Semiconductor structure with stacked units, manufacturing method and electronic equipment
CN111130493B (en) * 2019-12-31 2021-03-12 诺思(天津)微系统有限责任公司 Semiconductor structure with stacked units, manufacturing method and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000183283A (en) * 1998-12-18 2000-06-30 Denso Corp Laminated-type circuit module and its manufacturing method
US6469374B1 (en) * 1999-08-26 2002-10-22 Kabushiki Kaisha Toshiba Superposed printed substrates and insulating substrates having semiconductor elements inside
JP2003163324A (en) * 2001-11-27 2003-06-06 Nec Corp Unit semiconductor device and manufacturing method thereof, and three-dimensional laminated semiconductor device
CN101312172A (en) * 2007-05-22 2008-11-26 三星电子株式会社 Semiconductor package with reinforced joint reliability and its manufacture method
CN101330068A (en) * 2007-06-18 2008-12-24 海力士半导体有限公司 Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3531573B2 (en) * 2000-03-17 2004-05-31 株式会社村田製作所 Multilayer ceramic electronic component, method of manufacturing the same, and electronic device
CN103199017B (en) * 2003-12-30 2016-08-03 飞兆半导体公司 Form buried conductive layer method, material thickness control methods, form transistor method
US20060202269A1 (en) * 2005-03-08 2006-09-14 Semiconductor Energy Laboratory Co., Ltd. Wireless chip and electronic appliance having the same
US8715839B2 (en) * 2005-06-30 2014-05-06 L. Pierre de Rochemont Electrical components and method of manufacture
ITMI20070933A1 (en) * 2007-05-08 2008-11-09 St Microelectronics Srl MULTI PIASTRINA ELECTRONIC SYSTEM

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000183283A (en) * 1998-12-18 2000-06-30 Denso Corp Laminated-type circuit module and its manufacturing method
US6469374B1 (en) * 1999-08-26 2002-10-22 Kabushiki Kaisha Toshiba Superposed printed substrates and insulating substrates having semiconductor elements inside
JP2003163324A (en) * 2001-11-27 2003-06-06 Nec Corp Unit semiconductor device and manufacturing method thereof, and three-dimensional laminated semiconductor device
CN101312172A (en) * 2007-05-22 2008-11-26 三星电子株式会社 Semiconductor package with reinforced joint reliability and its manufacture method
CN101330068A (en) * 2007-06-18 2008-12-24 海力士半导体有限公司 Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9985005B2 (en) 2013-03-15 2018-05-29 Intel Deutschland Gmbh Chip package-in-package
JP2016530720A (en) * 2013-09-27 2016-09-29 インテル・コーポレーション Method for interconnecting multiple stacked semiconductor devices
US9627358B2 (en) 2013-09-27 2017-04-18 Intel Corporation Method for interconnecting stacked semiconductor devices
US9899354B2 (en) 2013-09-27 2018-02-20 Intel Corporation Method for interconnecting stacked semiconductor devices
US10643975B2 (en) 2013-09-27 2020-05-05 Intel Corporation Method for interconnecting stacked semiconductor devices
US11024607B2 (en) 2013-09-27 2021-06-01 Intel Corporation Method for interconnecting stacked semiconductor devices
US11676944B2 (en) 2013-09-27 2023-06-13 Intel Corporation Method for interconnecting stacked semiconductor devices
DE102014113299B4 (en) 2013-09-27 2024-02-22 Intel Corporation METHOD FOR CONNECTING STACKED SEMICONDUCTOR COMPONENTS AND STACKED SEMICONDUCTOR COMPONENT
CN107275323A (en) * 2017-07-25 2017-10-20 睿力集成电路有限公司 A kind of chip stack stereo encapsulation structure
US12033983B2 (en) 2023-05-12 2024-07-09 Intel Corporation Method for interconnecting stacked semiconductor devices

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