WO2010101130A1 - High frequency module - Google Patents

High frequency module Download PDF

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Publication number
WO2010101130A1
WO2010101130A1 PCT/JP2010/053284 JP2010053284W WO2010101130A1 WO 2010101130 A1 WO2010101130 A1 WO 2010101130A1 JP 2010053284 W JP2010053284 W JP 2010053284W WO 2010101130 A1 WO2010101130 A1 WO 2010101130A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
signal
signal line
filter
diode
Prior art date
Application number
PCT/JP2010/053284
Other languages
French (fr)
Japanese (ja)
Inventor
早川昌志
Original Assignee
株式会社村田製作所
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Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN201080010829.XA priority Critical patent/CN102342028B/en
Priority to JP2011502753A priority patent/JP5201260B2/en
Publication of WO2010101130A1 publication Critical patent/WO2010101130A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
    • H04B1/006—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/24—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection
    • H03J5/242—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection used exclusively for band selection
    • H03J5/244—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection used exclusively for band selection using electronic means

Definitions

  • This invention relates to a high frequency module employed in a front end portion of a mobile phone.
  • a multi-band compatible high-frequency module may be employed in order to enable use of the mobile phone in a plurality of communication systems having different frequency bands (for example, see FIG. 1). 2).
  • the high-frequency module disclosed in the above document is a triple band compatible one that uses three communication systems of PCS, DCS, and EGSM.
  • the high-frequency module includes a plurality of signal lines that connect the individual signal input / output ports and the common antenna port.
  • a diplexer is connected to the shared antenna port.
  • the diplexer separates PCS and DCS signals from EGSM signals.
  • the branch portion at a stage subsequent to the diplexer in the signal line includes first and second diodes.
  • the first diode is connected in series to one of the branched signal lines.
  • the second diode is connected to the shunt to the other branched signal line.
  • a low-pass filter is provided in the signal line through which the transmission signal propagates. The low-pass filter excludes harmonics of the transmission signal.
  • the ON / OFF switching of the first and second diodes of each branching unit is synchronized.
  • the inductance component of the second diode and the capacitor constitute a series resonance circuit.
  • the impedance of the signal line provided with the second diode as viewed from the branch is set to be infinite at the time of series resonance at the frequency of the signal passing through one signal line. This suppresses unnecessary signal propagation to the signal line in which the second diode is provided. Further, when the first and second diodes are OFF, the first diode is cut off. This suppresses unnecessary signal propagation to the signal line provided with the first diode.
  • the PCS and DCS received and transmitted signals are separated at the first branch.
  • a second branch is provided in the signal line through which the PCS and DCS received signals propagate.
  • the present invention provides a high-frequency module capable of ensuring isolation between desired signals without adding a new switch circuit or filter for improving isolation between desired signals to the circuit configuration. With the goal.
  • the present invention is a high-frequency module including a plurality of individual signal input / output ports, a shared antenna port, a switch circuit, a first signal line, and a second signal line, and includes a filter and a filter adjusting capacitor.
  • the switch circuit switches the connection between the shared antenna port and the plurality of individual signal input / output ports.
  • the first and second signal lines connect the individual signal input / output port and the shared antenna port.
  • the switch circuit includes a switch element connected to each of the first and second signal lines.
  • the filter is connected in series to the individual signal input / output port side from the connection position of the switch circuit in the first signal line.
  • the filter adjustment capacitor has a first end connected to the individual signal input / output port side of the filter connection position in the first signal line. The second end is connected to the switch element connected to the second signal line.
  • the filter of the present invention includes a parallel resonant capacitor and a parallel resonant inductor connected in parallel, and the resonance frequency of the parallel resonance caused by the parallel resonant capacitor and the parallel resonant inductor is higher order of the signal propagating through the first signal line. It may be set to a harmonic frequency. With this configuration, high-order harmonics in the first signal line can be removed. In addition, the resonance frequency of the resonance circuit including the filter adjustment capacitor and the parallel resonance inductor may be set to the fundamental wave or higher harmonic frequency of the signal propagating through the first signal line. With this configuration, the isolation between the signal propagating through the first signal line and the signal propagating through the second signal line can be improved.
  • the switch element connected to the first signal line of the present invention may be a first diode
  • the switch element connected to the second signal line may be a second diode.
  • the first diode has an anode connected to the shared antenna port side in the first signal line and a cathode connected to the individual signal input / output port side.
  • the second diode has a cathode connected to the second signal line and an anode connected to the control terminal.
  • the anode of this second diode is connected to ground through a series resonant capacitor.
  • the filter adjustment capacitor has a second end connected to a connection position between the second diode and the series resonance capacitor.
  • the diode connected to the first signal line is also turned on.
  • a series resonance occurs in the switch circuit connected to the second signal line, and it is possible to suppress the propagation of a signal to flow into the second signal line using the series resonance.
  • the diode connected to the first signal line is also turned off, and the connection between the second signal line and the filter adjustment capacitor is disconnected. The signal can be propagated to the second signal line. Therefore, it is possible to disconnect the filter adjustment capacitor at the time of signal propagation in the second signal line, and remove the influence on the pass characteristic of the second signal line by the filter adjustment capacitor.
  • the high-frequency module according to the present invention adjusts a filter by making a pattern electrode constituting at least a part of a parallel resonant capacitor and a pattern electrode constituting at least a part of a series resonant capacitor face each other in the normal direction of the main surface of the multilayer substrate It is preferable to construct a capacitor for use. Alternatively, it is preferable that the filter adjustment capacitor is configured such that the wiring electrode connected to the parallel resonance capacitor and the wiring electrode connected to the series resonance capacitor face each other in the normal direction of the main surface of the multilayer substrate.
  • the filter adjustment capacitor By configuring the filter adjustment capacitor in this manner, it is possible to provide the filter adjustment capacitor while suppressing an increase in module size. In addition, the generation of parasitic capacitance due to the connection wiring of the filter adjustment capacitor can be suppressed, the series resonance between the series resonance capacitor and the diode can be stabilized, and the fluctuation of the pass characteristic in the second signal line can be suppressed.
  • a desired change can be given to the frequency characteristics of the high-frequency module by providing the filter adjusting capacitor and adjusting the capacitance. Specifically, it is possible to ensure isolation between the first signal line and the second signal line connecting the filter adjustment capacitors.
  • FIG. 1 is a schematic circuit diagram of a high-frequency module according to a first embodiment of the present invention. It is a characteristic view of the high frequency module shown in FIG.
  • FIG. 2 is a stacking diagram of the high-frequency module shown in FIG. 1.
  • FIG. 2 is a stacking diagram of the high-frequency module shown in FIG. 1.
  • It is a schematic circuit diagram of the high frequency module which concerns on the 2nd Embodiment of this invention.
  • It is a characteristic view of the high frequency module shown in FIG.
  • FIG. is a schematic circuit diagram of the high frequency module which concerns on the 3rd Embodiment of this invention.
  • It is a characteristic view of the high frequency module shown in FIG.
  • the high-frequency module of this embodiment is adopted for the front-end part of an EDGE type mobile phone, and is compatible with a triple band using three communication systems of PCS, DCS, and EGSM.
  • FIG. 1 is a schematic circuit diagram of the high-frequency module according to the present embodiment.
  • the high-frequency module 1 includes a diplexer DPX, branch portions 11A to 11C, low-pass filters LPF1 and LPF2, and a filter adjustment capacitor CCC. Further, as external connection ports, an antenna port ANT corresponding to the shared antenna port of the present invention, and a signal port 1800 / 1900-Tx, 1900-Rx, 1800-Rx, 850 / 900-Tx, 850 / 900-Rx, and control ports Vc1 to Vc3 corresponding to the control terminals of the present invention.
  • the diplexer DPX includes a low-pass filter LPF and a high-pass filter HPF, and an antenna port ANT is connected to a connection point between the low-pass filter LPF and the high-pass filter HPF via a DC cut capacitor.
  • the diplexer DPX passes the EGSM signal through the low-pass filter LPF and attenuates the PCS and DCS signals. Further, the PCS and DCS signals are passed through the high-pass filter HPF, and the EGSM signals are attenuated.
  • the low pass filter LPF is connected between the antenna port ANT and the branch part 11C.
  • This low-pass filter LPF includes a capacitor Ct1, an inductor Lt1, and a capacitor Cu1, and constitutes a low-pass filter that uses the signal band of EGSM as a pass band.
  • the inductor Lt1 has a first end connected to the antenna port ANT and a second end connected to the branch portion 11C.
  • Capacitor Ct1 is connected in parallel to inductor Lt1. The second end of the inductor Lt1 is connected to the ground via the capacitor Cu1.
  • the high pass filter HPF is connected between the antenna port ANT and the branch part 11A.
  • the high-pass filter HPF includes capacitors Cc1 and Cc2, an inductor Lt2, and a capacitor Ct2, and constitutes a high-pass filter having the PCS and DCS signal bands as pass bands.
  • the capacitor Cc1 has a first end connected to the antenna port ANT and a second end connected to the capacitor Cc2.
  • Capacitor Cc2 has a first end connected to capacitor Cc1 and a second end connected to branch portion 11A.
  • the first end of the inductor Lt2 is connected to the second end of the capacitor Cc1 and the first end of the capacitor Cc2.
  • the second end of the inductor Lt2 is connected to the ground via the capacitor Ct2.
  • the branch section 11C includes switch circuits SW5 and SW6, and is connected to the low-pass filter LPF at a connection point between the switch circuit SW5 and the switch circuit SW6.
  • the branching unit 11C switches between an EGSM transmission state and an EGSM reception state based on a voltage input to the control port Vc1 from the outside.
  • the switch circuit SW5 is connected between the low pass filter LPF and the low pass filter LPF2.
  • the switch circuit SW5 includes a diode GD1 and an inductor GSL1.
  • the diode GD1 has an anode connected to the low-pass filter LPF and a cathode connected to the low-pass filter LPF2.
  • the cathode of the diode GD1 is connected to the ground via the inductor GSL1.
  • Switch circuit SW6 is connected between low pass filter LPF and signal port 850 / 900-Rx.
  • the switch circuit SW6 includes an inductor GSL2, a capacitor GCu3, a diode GD2, a capacitor GC5, and a resistor Rg.
  • the inductor GSL2 has a first end connected to the low pass filter LPF and a second end connected to the signal port 850 / 900-Rx via a DC cut capacitor.
  • the second end of the inductor GSL2 is connected to the ground via the capacitor GCu3 and the cathode of the diode GD2 is connected.
  • the anode of the diode GD2 is connected to the control port Vc1 through the resistor Rg, and is connected to the ground through the capacitor GC5.
  • the switch circuit SW6 suppresses the propagation of the EGSM transmission signal, and the switch circuit SW5 propagates the EGSM transmission signal.
  • a voltage higher than the switching voltage is applied to the anode of the diode GD2 by applying a voltage from the control port Vc1.
  • the diode GD2 is turned on, the second end of the inductor GSL2 is connected to the ground via the capacitor GC5, and the inductance component of the diode GD2 and the capacitor GC5 resonate in series.
  • the line length of the inductor GSL2 is set to approximately 1 ⁇ 4 of the wavelength in the transmission signal frequency band of EGSM, and the diode GD2 side of the inductor GSL2 is grounded by series resonance, so that the inductor GSL2 is connected from the switch circuit SW5 side. It is set so that the impedance becomes infinite when viewed from the side. Therefore, propagation of the EGSM transmission signal in the switch circuit SW6 is suppressed.
  • the switch circuit SW5 a voltage higher than the switching voltage is applied to the anode of the diode GD1. For this reason, the diode GD1 is turned ON, and the transmission signal of EGSM propagates through the switch circuit SW5.
  • the switch circuit SW6 propagates the EGSM reception signal, and the switch circuit SW5 suppresses the propagation of the EGSM reception signal.
  • a voltage lower than the switching voltage is applied to the anode of the diode GD2 by applying a voltage from the control port Vc1.
  • the diode GD2 is turned OFF.
  • the received signal of EGSM propagates through the switch circuit SW6.
  • the switch circuit SW5 a voltage lower than the switching voltage is applied to the anode of the diode GD1. For this reason, the diode GD1 is turned OFF, and the propagation of the reception signal of the EGSM in the switch circuit SW5 is suppressed.
  • the low pass filter LPF2 is connected between the switch circuit SW5 and the signal port 850 / 900-Tx.
  • the low-pass filter LPF2 includes an inductor GLt1, a capacitor GCc1, and capacitors GCu1 and GCu2, and constitutes a low-pass filter that removes second and third harmonic components of the EGSM transmission signal.
  • the inductor GLt1 has a first end connected to the switch circuit SW5 and a second end connected to the signal port 850 / 900-Tx via a DC cut capacitor.
  • Capacitor GCc1 is connected in parallel to inductor GLt1.
  • the first end of the inductor GLt1 is connected to the ground via the capacitor GCu1.
  • the second end of the inductor GLt1 is connected to the ground via the capacitor GCu2.
  • the branch section 11A includes switch circuits SW1 and SW2, and is connected to the high-pass filter HPF at a connection point between the switch circuit SW1 and the switch circuit SW2.
  • the branching unit 11A switches between a transmission state and a reception state based on a voltage input to the control port Vc2 from the outside.
  • the switch circuit SW1 is connected between the high pass filter HPF and the low pass filter LPF1.
  • the switch circuit SW1 includes a diode DD1, an inductor DPSLt, a capacitor DPCt1, and an inductor DPSL1.
  • the diode DD1 has an anode connected to the high pass filter HPF and a cathode connected to the low pass filter LPF1.
  • the first end of the inductor DPSLt is connected to the anode of the diode DD1, and the second end is connected to the first end of the capacitor DPCt1.
  • the first end of the capacitor DPCt1 is connected to the first end of the inductor DPSLt, and the second end is connected to the cathode of the diode DD1.
  • the cathode of the diode DD1 is connected to the ground via the inductor DPSL1.
  • the switch circuit SW2 is connected between the high pass filter HPF and the branch part 11B.
  • the switch circuit SW2 includes an inductor DSL2, a capacitor CDPr, a capacitor DCu4, a diode DD2, a capacitor DC5, and a resistor Rd.
  • the inductor DSL2 has a first end connected to the high pass filter HPF and a second end connected to the first end of the capacitor CDPr and the cathode of the diode DD2.
  • the second end of the capacitor CDPr is connected to the ground via the capacitor DCu4 and is also connected to the branch portion 11B.
  • the anode of the diode DD2 is connected to the control port Vc2 through the resistor Rd, is connected to the ground through the capacitor DC5 corresponding to the series resonant capacitor of the present invention, and the second end of the filter adjustment capacitor CCC described in detail later. Is connected.
  • the switch circuit SW2 suppresses the transmission of PCS and DCS transmission signals, and the switch circuit SW1 propagates the PCS and DCS transmission signals.
  • a voltage higher than the switching voltage is applied to the anode of the diode DD2 by applying a voltage from the control port Vc2.
  • the diode DD2 is turned on, the second end of the inductor DSL2 is connected to the ground via the capacitor DC5, and the inductance component of the diode DD2 and the capacitor DC5 resonate in series.
  • the line length of the inductor DSL2 is set to approximately 1 ⁇ 4 of the wavelength in the transmission signal frequency band of the PCS and DCS, and the diode DD2 side of the inductor DSL2 is grounded by series resonance.
  • the impedance is set to an infinite open state. Therefore, propagation of PCS and DCS transmission signals in the switch circuit SW2 is suppressed.
  • the switch circuit SW1 a voltage higher than the switching voltage is applied to the anode of the diode DD1. For this reason, the diode DD1 is turned ON, and PCS and DCS transmission signals propagate through the switch circuit SW1.
  • the switch circuit SW2 propagates the PCS and DCS received signals, and the switch circuit SW1 suppresses the propagation of the PCS and DCS received signals.
  • a voltage lower than the switching voltage is applied to the anode of the diode DD2 by applying a voltage from the control port Vc2.
  • the diode DD2 is turned OFF.
  • PCS and DCS received signals propagate through the switch circuit SW2.
  • the switch circuit SW1 a voltage lower than the switching voltage is applied to the anode of the diode DD1. For this reason, the diode DD1 is turned OFF, and the propagation of PCS and DCS received signals in the switch circuit SW1 is suppressed.
  • the low pass filter LPF1 is connected between the switch circuit SW1 and the signal port 1800 / 1900-Tx.
  • the low-pass filter LPF1 includes inductors DLt1 and DLt2, a capacitor DCc1, and capacitors DCu1 and DCu2, and constitutes a low-pass filter that removes second-order harmonics and third-order harmonic components of PCS and DCS transmission signals.
  • the inductor DLt1 corresponds to the parallel resonant inductor of the present invention, and has a first end connected to the switch circuit SW1 and a second end connected to the first end of the inductor DLt2.
  • the first end of the inductor DLt2 is connected to the first end of the inductor DLt1, and the second end of the inductor DLt2 is connected to the signal port 1800 / 1900-Tx via a DC cut capacitor.
  • the capacitor DCc1 corresponds to the parallel resonant capacitor of the present invention, and is connected in parallel to the inductor DLt1.
  • the first end of the inductor DLt1 is connected to the ground via the capacitor DCu1.
  • a second end of the inductor DLt1 is connected to the ground via the capacitor DCu2, and a first end of a filter adjustment capacitor CCC described later is connected.
  • the branch section 11B includes switch circuits SW3 and SW4, and is connected to the switch circuit SW2 at a connection point between the switch circuit SW3 and the switch circuit SW4.
  • the branching unit 11B switches between the PCS reception state and the DCS reception state based on the voltage input to the control port Vc3 from the outside.
  • Switch circuit SW3 is connected between switch circuit SW2 and signal port 1900-Rx.
  • the switch circuit SW3 includes a diode PD1, an inductor PSL1, and a capacitor PCu3.
  • the diode PD1 has an anode connected to the switch circuit SW2 and a cathode connected to the signal port 1900-Rx via a DC cut capacitor.
  • the cathode of the diode PD1 is connected to the ground via the inductor PSL1, and is connected to the ground via the capacitor PCu3.
  • Switch circuit SW4 is connected between switch circuit SW2 and signal port 1800-Rx.
  • the switch circuit SW4 includes an inductor PSL2, a capacitor DCu3, a diode PD2, a capacitor PC5, and a resistor Rp.
  • the inductor PSL2 has a first end connected to the switch circuit SW2, and a second end connected to the signal port 1800-Rx via a DC cut capacitor.
  • the second end of the inductor PSL2 is connected to the ground via the capacitor DCu3, and the cathode of the diode PD2 is connected.
  • the anode of the diode PD2 is connected to the control port Vc3 through the resistor Rp, and is connected to the ground through the capacitor PC5.
  • the switch circuit SW4 suppresses the propagation of the PCS reception signal, and the switch circuit SW3 propagates the PCS reception signal.
  • a voltage higher than the switching voltage is applied to the anode of the diode PD2 by applying a voltage from the control port Vc3.
  • the diode PD2 is turned on, the second end of the inductor PSL2 is connected to the ground via the capacitor PC5, and the inductance component of the diode PD2 and the capacitor PC5 resonate in series.
  • the line length of the inductor PSL2 is set to approximately 1 ⁇ 4 of the wavelength in the reception signal frequency band of the PCS, and the diode PD2 side of the inductor PSL2 is grounded by series resonance, so that the inductor PSL2 is connected from the switch circuit SW3 side. It is set so that the impedance becomes infinite when viewed from the side. Therefore, propagation of the PCS received signal in the switch circuit SW4 is suppressed.
  • the switch circuit SW3 a voltage higher than the switching voltage is applied to the anode of the diode PD1. For this reason, the diode PD1 is turned ON, and the PCS received signal propagates through the switch circuit SW3.
  • the switch circuit SW4 propagates the DCS reception signal, and the switch circuit SW3 suppresses the propagation of the DCS reception signal.
  • a voltage lower than the switching voltage is applied to the anode of the diode PD2 by voltage application from the control port Vc3.
  • the diode PD2 is turned OFF.
  • the DCS received signal propagates through the switch circuit SW4.
  • the switch circuit SW3 a voltage lower than the switching voltage is applied to the anode of the diode PD1. For this reason, the diode PD1 is turned OFF, and the propagation of the DCS received signal in the switch circuit SW3 is suppressed.
  • the filter adjustment capacitor CCC has a capacitance of about 0.2 pF.
  • the first end of the filter adjustment capacitor CCC is connected to the signal port 1800 / 1900-Tx side of the low-pass filter LPF1 from the LC parallel resonance circuit formed by the inductor DLt1 and the capacitor DCc1. Further, the second end thereof is connected to the anode of the diode DD2 provided in the switch circuit SW2.
  • the diode DD2 is turned ON and the filter adjustment capacitor CCC is connected to the second end of the inductor DSL2, during the transmission state, the inductor DLt1 of the low-pass filter LPF1 and the filter adjustment capacitor CCC. Resonance in a parallel circuit occurs. Therefore, a desired change can be given to the frequency characteristics of the high-frequency module using this resonance.
  • the capacitance of the filter adjustment capacitor CCC is sufficiently small, for example, preferably 0.1 pF to 0.6 pF. Even if the capacitance of the filter adjustment capacitor CCC is small, the circuit constant of the low-pass filter LPF1 is properly set. By calibrating, it is possible to give a desired change to the frequency characteristics of the high-frequency module.
  • the low pass filter LPF1 corresponds to the filter of the present invention connected in series to the signal port 1800 / 1900-Tx side of the switch circuit SW1.
  • a signal line connecting the antenna port ANT and the signal port 1800 / 1900-Tx corresponds to the first signal line of the present invention.
  • a signal line connecting the antenna port ANT and the signal port 1900-Rx and a signal line connecting the antenna port ANT and the signal port 1800-Rx correspond to the second signal line of the present invention.
  • FIG. 2 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment.
  • the data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
  • FIG. 2A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 1800 / 1900-Tx.
  • the attenuation pole on the high frequency side of the pass band is located at about 3.37 GHz.
  • the attenuation pole on the high frequency side of the pass band is located at about 3.57 GHz.
  • the attenuation pole on the high frequency side of these passbands is a frequency at which high-order harmonics of the PCS signal and the DCS signal are blocked by the main action of the low-pass filter LPF1.
  • the frequency of the attenuation pole on the high frequency side of the passband does not change much from the comparative configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 1800 / 1900-Tx It was confirmed that it could be sufficiently blocked.
  • the pass characteristic in the signal line provided with the low-pass filter LPF1 is affected by the resonance of the low-pass filter LPF1 alone and the filter adjusting capacitor CCC.
  • the influence of the filter adjustment capacitor CCC is smaller than the influence of the resonance of the low-pass filter LPF1 alone, and it can be said that the pass characteristic in this signal line is not significantly impaired even if the filter adjustment capacitor CCC is provided.
  • the isolation between the signal propagating through the first signal line and the signal propagating through the second signal line is improved without impairing the pass characteristic in the first signal line. It can be said that it is possible.
  • FIG. 2B and FIG. 2C are characteristic diagrams illustrating the isolation characteristics between the signal port 1800 / 1900-Tx and the signal port 1900-Rx.
  • the attenuation pole due to the low-pass filter LPF1 alone is located at about 3.57 GHz having a frequency substantially equal to the attenuation pole in the frequency characteristics indicated by the broken line in FIG.
  • the attenuation pole due to the low-pass filter LPF1 alone is located at about 3.00 GHz, which is about 370 MHz lower than the attenuation pole in the frequency characteristic shown by the solid line in FIG. 2A (see the solid line in FIG. 2B). .
  • the inductor DLt1 constituting the low-pass filter LPF and another parallel resonance circuit can be configured.
  • the signal port 1800 / 1900-Tx and the signal port 1900-Rx It was confirmed that the frequency characteristic between the two can be lower than that of the comparative configuration example in the frequency of the attenuation pole on the high frequency side of the pass band. Furthermore, in this configuration example, it was confirmed that attenuation in the vicinity of about 1.71 GHz, which is not much attenuated in the comparative configuration example, can be increased.
  • the attenuation secured over the band of about 1.71 GHz to about 1.91 GHz was about 23.9 dB, but in this configuration example, about 31.1 dB over the band of about 1.71 GHz to about 1.91 GHz. It was possible to secure the amount of attenuation. In other words, the attenuation of the PCS transmission signal in the frequency band (1850 to 1910 MHz) was secured about 31.1 dB, and the isolation between the signal port 1800 / 1900-Tx and the signal port 1900-Rx could be improved.
  • FIGS. 3A to 3O and FIGS. 4P to 4Y are plan views of the substrates (A) to (Y) viewed from the bottom in order from the bottom layer to the top layer.
  • FIG. 4 (Z) is a plan view of the uppermost substrate (Y) of the multilayer substrate as viewed from above.
  • the via electrodes in the substrates (A) to (Y) are indicated by circles in the drawing.
  • the substrate (A) is laminated on the lowermost layer of the multilayer substrate, the lower surface is the mounting surface of the high-frequency module, and a plurality of mounting electrodes are formed.
  • the arrows shown in the figure indicate the port names of the mounting electrodes.
  • the substrate (B) is laminated in the second layer from the lowest layer of the multilayer substrate, an interior ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate.
  • the substrate (C) is stacked as the third layer from the bottom layer of the multilayer substrate, and a pattern electrode constituting the capacitor GCu3 and a pattern electrode constituting the capacitor GC5 are provided on the lower surface of the substrate, and a via electrode is provided inside the substrate. .
  • the substrate (D) is laminated in the fourth layer from the lowest layer of the multilayer substrate, an interior ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate.
  • Capacitors GCu3 and GC5 are formed between the ground electrode of the substrate (D) and the ground electrode of the substrate (B) and the substrate (C) pattern electrode sandwiched between the ground electrodes.
  • the substrate (E) is laminated in the fifth layer from the lowest layer of the multilayer substrate, and the pattern electrode constituting the capacitor PC5, the pattern electrode constituting the capacitor GC5, the pattern electrode constituting the capacitor DC5, and the capacitor GCu2 are formed on the lower surface of the substrate. And a via electrode is provided inside the substrate.
  • the substrate (F) is laminated in the sixth layer from the bottom layer of the multilayer substrate, the pattern electrode constituting the capacitor DCu2 and the interior ground electrode are provided on the lower surface of the substrate, and the via electrode is provided inside the substrate.
  • Capacitors PC5, GC5, DC5, and GCu2 are formed between the ground electrode of the substrate (F), the ground electrode of the substrate (D), and the pattern electrode of the substrate (E) sandwiched between the ground electrodes.
  • the pattern electrode constituting the capacitor DC5 of the substrate (E) and the pattern electrode constituting the capacitor DCu2 of the substrate (F) are opposed to each other through the substrate (E), and these pattern electrodes are overlapped. It functions as a filter adjustment capacitor CCC.
  • the substrate (G) is laminated to the seventh layer from the bottom layer of the multilayer substrate, and the pattern electrode constituting the capacitor Ct2, the pattern electrode constituting the capacitor Cu1, the pattern electrode constituting the capacitor DCu2, and the capacitor GCu1 are formed on the lower surface of the substrate. And a via electrode is provided inside the substrate.
  • the substrate (H) is laminated in the eighth layer from the bottom layer of the multilayer substrate, an inner layer ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate.
  • This ground electrode constitutes capacitors Ct2, Cu1, DCu2, and GCu1 with the pattern electrode formed on the substrate (G).
  • the substrate (I) is laminated in the ninth layer from the bottom layer of the multilayer substrate, and a ground electrode formed on the substrate (H) is provided with a pattern electrode constituting the capacitor DCu4 and a pattern electrode constituting the capacitor DCu1 on the lower surface of the substrate. Capacitors DCu4 and DCu1 are formed between the electrodes. Via electrodes are provided inside the substrate.
  • the substrate (J) is laminated to the tenth layer from the bottom layer of the multilayer substrate, and a via electrode is provided inside the substrate.
  • the substrates (K) to (Y) are stacked in the 11th to 25th layers from the bottom layer of the multilayer substrate, a plurality of pattern electrodes constituting a plurality of inductors are provided on the lower surface of the substrate, and via electrodes are provided inside the substrate. On the upper surface of the substrate (Y), a plurality of surface electrodes for connecting circuit elements of discrete components are provided.
  • the pattern adjustment capacitor CCC of the substrate (F) and the pattern electrode of the substrate (F) capacitor DCu2 are made to function as the filter adjustment capacitor CCC. It is not necessary to separately provide a pattern electrode for constituting the CCC, and an increase in module size can be suppressed. In addition, since the line electrode for connecting the filter adjustment capacitor CCC to other circuit elements is not necessary, generation of unnecessary parasitic capacitance can be suppressed, and the series resonance between the capacitor DC5 and the diode DD2 is stabilized, and the first It is possible to suppress fluctuations in pass characteristics in the two signal lines.
  • the filter adjustment capacitor CCC can be configured by making the wiring electrode connected to the capacitor DC5 and the wiring electrode connected to the capacitor DCu2 face each other.
  • the occurrence of parasitic inductance in the ground electrode portion can be suppressed by arranging the ground electrode in the lowermost layer of the multilayer substrate or a layer in the vicinity thereof as in the present embodiment. For this reason, by disposing the capacitor electrode in the vicinity of the ground electrode, the parasitic inductance generated in the capacitor grounded at one end can be reduced, the Q of the series resonance is improved, and the first signal line and the second signal are improved.
  • the isolation between the lines can be improved.
  • FIG. 5 is a schematic circuit diagram of the high-frequency module according to the present embodiment.
  • the first end of the filter adjustment capacitor CCC is connected to the second end of the inductor DLt2 in the low-pass filter LPF1. Even if such a circuit configuration is employed, the present invention can be suitably implemented.
  • FIG. 6 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment.
  • the data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
  • FIG. 6A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 1800 / 1900-Tx.
  • the attenuation pole on the high frequency side of the pass band is located at about 3.03 GHz in both this configuration example and the comparative configuration example.
  • the frequency of the attenuation pole on the high frequency side of the passband hardly changes from the comparative configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 1800 / 1900-Tx It was confirmed that it could be sufficiently blocked.
  • FIG. 6B is a characteristic diagram illustrating an isolation characteristic between the signal port 1800 / 1900-Tx and the signal port 1900-Rx.
  • the attenuation secured over the band of about 1.71 GHz to about 1.91 GHz was about 22.5 dB, but in this configuration example, the frequency band of the PCS transmission signal An attenuation of about 31.1 dB could be secured over a band from about 1.71 GHz to about 1.91 GHz.
  • FIG. 7 is a schematic circuit diagram of the high-frequency module according to the present embodiment.
  • the first end of the filter adjustment capacitor CCC is connected to the second end of the inductor GLt1 in the low-pass filter LPF2.
  • the second end of the filter adjustment capacitor CCC is connected to the anode of the diode GD2 in the switch circuit SW6.
  • the capacitance of the filter adjustment capacitor CCC is about 0.5 pF. Even if such a circuit configuration is employed, the present invention can be suitably implemented.
  • FIG. 8 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment.
  • the data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
  • FIG. 8A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 850 / 900-Tx.
  • the attenuation pole on the high frequency side of the passband is located at about 1.83 GHz in both this configuration example and the comparative configuration example.
  • the attenuation pole on the high frequency side of these passbands is a frequency at which high-order harmonics of the EGSM signal are blocked by the main action of the low-pass filter LPF2.
  • the frequency of the attenuation pole on the high frequency side of the passband hardly changes from the comparison configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 850 / 900-Tx It was confirmed that it could be sufficiently blocked.
  • FIG. 8B is a characteristic diagram illustrating isolation characteristics between the signal port 850 / 900-Tx and the signal port 900-Rx.
  • the attenuation secured over the band of about 820 MHz to 920 MHz was about 26.4 dB, but in this configuration example, 820 MHz including the frequency band of the EGSM transmission signal Attenuation of about 29.6dB could be secured over the band of ⁇ 920MHz.
  • the present invention can be suitably implemented by changing the connection location of the filter adjustment capacitor CCC with the above-described circuit configuration.
  • the first end of the filter adjustment capacitor CCC can be connected to the subsequent stage of the low-pass filter LPF1, and the second end can be connected to the anode of the diode PD2 or the like.
  • the present invention can be suitably implemented even with other circuit configurations.
  • a filter configuration is added to the signal port 1900-Rx having the circuit configuration described above, the first end of the filter adjustment capacitor CCC is connected to the signal port side of the filter, and the second end of the filter adjustment capacitor CCC is connected.
  • High frequency module DPX Diplexer HPF ... High pass filter LPF, LPF1, LPF2 ... Low pass filter 11A to 11C ... Branch SW1 to SW6 ... Switch circuit DD1, DD2, GD1, GD2, PD1, PD2 ... Diode CCC ... Capacitor for filter adjustment

Abstract

A high frequency module which is able to secure isolation between desired signals without the addition of a new switch circuit and filter. The high frequency module (1) is provided with a low pass filter (LPF1) and a filter adjusting capacitor (CCC). The signal line that connects an antenna port (ANT) to a signal port (1800/1900-Tx) is connected to a switch circuit (SW1) which controls the propagation of signals to the signal port, is connected to a low pass filter (LPF1) at the signal port side of the switch circuit (SW1), and is connected to a first end of a filter adjusting capacitor (CCC) at the signal port side of the low pass filter (LPF1). The signal line that connects the antenna port (ANT) to a signal port (1900-Rx) is connected to switch circuits (SW2, SW4) which control the propagation of signals to the signal port. The second end of the filter adjusting capacitor (CCC) is connected to an anode of a diode (DD2) of the switch circuit (SW2).

Description

高周波モジュールHigh frequency module
　この発明は、携帯電話機のフロントエンド部などに採用される高周波モジュールに関する。 This invention relates to a high frequency module employed in a front end portion of a mobile phone.
　携帯電話のフロントエンド部などでは、周波数帯域の異なる複数の通信システムでの携帯電話の利用を可能にするために、マルチバンド対応の高周波モジュールが採用されることがある（例えば特許文献１の図２参照。）。 In a mobile phone front-end unit or the like, a multi-band compatible high-frequency module may be employed in order to enable use of the mobile phone in a plurality of communication systems having different frequency bands (for example, see FIG. 1). 2).
　上記文献に開示された高周波モジュールは、PCSとDCSとEGSMとの３つの通信システムを利用するトリプルバンド対応のものである。この高周波モジュールは、個別信号入出力ポートと共用アンテナポートとを接続する複数の信号ラインを備える。共用アンテナポートにはダイプレクサが接続される。ダイプレクサはPCSおよびDCSの信号とEGSMの信号とを分離する。また、信号ラインにおけるダイプレクサよりも後段の分岐部は第１および第２のダイオードを備える。第１のダイオードは分岐する一方の信号ラインにシリーズに接続される。第２のダイオードは分岐する他方の信号ラインにシャントに接続される。また、送信信号が伝搬する信号ライン中にはローパスフィルタを備える。ローパスフィルタは送信信号の高調波を除く。 The high-frequency module disclosed in the above document is a triple band compatible one that uses three communication systems of PCS, DCS, and EGSM. The high-frequency module includes a plurality of signal lines that connect the individual signal input / output ports and the common antenna port. A diplexer is connected to the shared antenna port. The diplexer separates PCS and DCS signals from EGSM signals. In addition, the branch portion at a stage subsequent to the diplexer in the signal line includes first and second diodes. The first diode is connected in series to one of the branched signal lines. The second diode is connected to the shunt to the other branched signal line. Further, a low-pass filter is provided in the signal line through which the transmission signal propagates. The low-pass filter excludes harmonics of the transmission signal.
　各分岐部の第１および第２のダイオードは、ON／OFFの切り替えが同期する。第１のダイオードと第２のダイオードとをONにする時に、第２のダイオードのインダクタンス成分とキャパシタとが直列共振回路を構成する。第２のダイオードが設けられる信号ラインを分岐部から見たインピーダンスは、一方の信号ラインを通過する信号の周波数において直列共振時に無限大になるように設定される。これにより、第２のダイオードが設けられる信号ラインへの不要な信号の伝搬が抑えられる。また第１および第２のダイオードのOFF時には、第１のダイオードが遮断される。これにより第１のダイオードが設けられる信号ラインへの不要な信号の伝搬が抑えられる。 The ON / OFF switching of the first and second diodes of each branching unit is synchronized. When the first diode and the second diode are turned on, the inductance component of the second diode and the capacitor constitute a series resonance circuit. The impedance of the signal line provided with the second diode as viewed from the branch is set to be infinite at the time of series resonance at the frequency of the signal passing through one signal line. This suppresses unnecessary signal propagation to the signal line in which the second diode is provided. Further, when the first and second diodes are OFF, the first diode is cut off. This suppresses unnecessary signal propagation to the signal line provided with the first diode.
　この高周波モジュールの、ダイプレクサよりも後段のPCSおよびDCSの信号を伝搬する信号ライン側では、1段目の分岐部でPCSおよびDCSの受信信号と送信信号とを分離する。そして、PCSおよびDCSの受信信号が伝搬する信号ライン中に２段目の分岐部を設けている。これにより、各分岐部でのスイッチを適切なタイミングとすることで、周波数帯域の一部が重なるPCSの送信信号（1850～1910MHz）とDCSの受信信号（1805～1880MHz）との間でのアイソレーションを確保している。 ∙ On the signal line side that propagates the PCS and DCS signals downstream from the diplexer of this high-frequency module, the PCS and DCS received and transmitted signals are separated at the first branch. A second branch is provided in the signal line through which the PCS and DCS received signals propagate. As a result, by setting the switch at each branch to an appropriate timing, isolating between the PCS transmission signal (1850 to 1910MHz) and the DCS reception signal (1805 to 1880MHz) that overlap part of the frequency band. Is secured.
特開２００４－１２８７９９号公報JP 2004-128799 A
　携帯電話通信システムではGPRS方式からEDGE方式への移行が進展している。このため、帯域の重なるPCSの送信信号とDCSの受信信号との間でのアイソレーションに加え、帯域の重ならないPCSの送信信号（1850～1910MHz）と受信信号（1930～1990MHz）との間でのアイソレーションを高める必要が生じている。 In mobile phone communication systems, the transition from GPRS to EDGE is progressing. For this reason, in addition to the isolation between the PCS transmission signal and the DCS reception signal with overlapping bands, the PCS transmission signal (1850 to 1910 MHz) and the reception signal (1930 to 1990 MHz) without overlapping bands There is a need to increase the isolation.
　しかしながら従来の回路構成では、PCSの送信信号とDCSの受信信号との間でのアイソレーションを確保しながら、さらにPCSの送信信号と受信信号との間でのアイソレーションまでもGPRS方式の場合より高めることは困難であった。 However, with the conventional circuit configuration, isolation between the PCS transmission signal and the DCS reception signal is ensured, and even the isolation between the PCS transmission signal and the reception signal is more than that of the GPRS system. It was difficult to increase.
　仮に、従来の回路構成にスイッチ回路やフィルタを追加すれば、PCSの送信信号と受信信号との間でのアイソレーションを高めることは可能になる。しかしながらその場合、スイッチ回路やフィルタを追加することによる各信号ラインの通過特性の劣化や、モジュールサイズの大型化を招来する虞がある。この問題は、PCSの送信信号と受信信号との間でのアイソレーションに限らず、任意の信号間でのアイソレーションを高める場合であってもスイッチ回路やフィルタの追加により生じてしまう。 If a switch circuit and a filter are added to the conventional circuit configuration, it is possible to increase the isolation between the PCS transmission signal and the reception signal. However, in that case, there is a risk that the addition of a switch circuit or a filter may cause deterioration of the pass characteristics of each signal line and increase of the module size. This problem is caused not only by the isolation between the PCS transmission signal and the reception signal but also by the addition of a switch circuit and a filter even when the isolation between arbitrary signals is increased.
　そこで本発明は、所望する信号間のアイソレーションを改善するための新たなスイッチ回路やフィルタを回路構成に追加することなく、所望する信号間のアイソレーションを確保することが可能な高周波モジュールの提供を目的とする。 Therefore, the present invention provides a high-frequency module capable of ensuring isolation between desired signals without adding a new switch circuit or filter for improving isolation between desired signals to the circuit configuration. With the goal.
　この発明は、複数の個別信号入出力ポート、共用アンテナポート、スイッチ回路、第１の信号ライン、および、第２の信号ラインを備える高周波モジュールであって、フィルタとフィルタ調整用キャパシタとを備える。スイッチ回路は、共用アンテナポートと複数の個別信号入出力ポートとの接続を切り替える。第１および第２の信号ラインは個別信号入出力ポートと共用アンテナポートとを接続する。スイッチ回路は、第１および第２の信号ラインそれぞれに接続したスイッチ素子を含んで構成している。フィルタは、第１の信号ラインにおけるスイッチ回路の接続位置よりも個別信号入出力ポート側にシリーズに接続されている。フィルタ調整用キャパシタは、第１の信号ラインにおけるフィルタの接続位置よりも個別信号入出力ポート側に第一端が接続されている。また、第２の信号ラインに接続したスイッチ素子に第二端が接続されている。 The present invention is a high-frequency module including a plurality of individual signal input / output ports, a shared antenna port, a switch circuit, a first signal line, and a second signal line, and includes a filter and a filter adjusting capacitor. The switch circuit switches the connection between the shared antenna port and the plurality of individual signal input / output ports. The first and second signal lines connect the individual signal input / output port and the shared antenna port. The switch circuit includes a switch element connected to each of the first and second signal lines. The filter is connected in series to the individual signal input / output port side from the connection position of the switch circuit in the first signal line. The filter adjustment capacitor has a first end connected to the individual signal input / output port side of the filter connection position in the first signal line. The second end is connected to the switch element connected to the second signal line.
　この構成では、フィルタ調整用キャパシタと第２の信号ラインとが接続される際に、フィルタを構成するインダクタとフィルタ調整用キャパシタとによる並列回路での共振が生じる。そのため、この共振とフィルタ単体での共振との２つの共振を利用して、高周波モジュールの周波数特性に所望の変化を与えることが可能になる。具体的には、フィルタ調整用キャパシタのキャパシタンスを設定することで、第１の信号ラインを伝搬する信号の周波数帯域や第２の信号ラインを伝搬する信号の周波数帯域での減衰量を確保する。これにより、第１の信号ラインを伝搬する信号と第２の信号ラインを伝搬する信号との間のアイソレーションを改善できる。 In this configuration, when the filter adjustment capacitor and the second signal line are connected, resonance occurs in a parallel circuit due to the inductor and the filter adjustment capacitor constituting the filter. Therefore, it is possible to give a desired change to the frequency characteristics of the high-frequency module by using two resonances, that is, the resonance of the filter alone. Specifically, by setting the capacitance of the filter adjustment capacitor, the amount of attenuation in the frequency band of the signal propagating through the first signal line and the frequency band of the signal propagating through the second signal line are secured. Thereby, the isolation between the signal propagating through the first signal line and the signal propagating through the second signal line can be improved.
　この発明のフィルタは、並列に接続される並列共振キャパシタと並列共振インダクタとを備え、並列共振キャパシタと並列共振インダクタとによる並列共振の共振周波数が、第１の信号ラインを伝搬する信号の高次高調波の周波数に設定されてもよい。この構成により、第１の信号ラインにおける高次高調波を除去できる。また、フィルタ調整用キャパシタと並列共振インダクタとによる共振回路の共振周波数が、第１の信号ラインを伝搬する信号の基本波あるいは高次高調波の周波数に設定されてもよい。この構成により、第１の信号ラインを伝搬する信号と第２の信号ラインを伝搬する信号との間のアイソレーションを改善できる。 The filter of the present invention includes a parallel resonant capacitor and a parallel resonant inductor connected in parallel, and the resonance frequency of the parallel resonance caused by the parallel resonant capacitor and the parallel resonant inductor is higher order of the signal propagating through the first signal line. It may be set to a harmonic frequency. With this configuration, high-order harmonics in the first signal line can be removed. In addition, the resonance frequency of the resonance circuit including the filter adjustment capacitor and the parallel resonance inductor may be set to the fundamental wave or higher harmonic frequency of the signal propagating through the first signal line. With this configuration, the isolation between the signal propagating through the first signal line and the signal propagating through the second signal line can be improved.
　この発明の第１の信号ラインに接続したスイッチ素子は第１のダイオードであり、第２の信号ラインに接続したスイッチ素子は第２のダイオードであってもよい。第１のダイオードは、第１の信号ラインにおける共用アンテナポート側にアノードが接続され、個別信号入出力ポート側にカソードが接続される。第２のダイオードは、第２の信号ラインにカソードが接続され、制御端子にアノードが接続される。この第２のダイオードのアノードは直列共振キャパシタを介してグランドに接続される。また、フィルタ調整用キャパシタは、第２のダイオードと直列共振キャパシタとの接続位置に第二端が接続される。 The switch element connected to the first signal line of the present invention may be a first diode, and the switch element connected to the second signal line may be a second diode. The first diode has an anode connected to the shared antenna port side in the first signal line and a cathode connected to the individual signal input / output port side. The second diode has a cathode connected to the second signal line and an anode connected to the control terminal. The anode of this second diode is connected to ground through a series resonant capacitor. The filter adjustment capacitor has a second end connected to a connection position between the second diode and the series resonance capacitor.
　この構成によれば、制御端子からバイアス電圧を加えて第２の信号ラインに接続するダイオードをONにすることで、第１の信号ラインに接続するダイオードもONになる。このとき、第２の信号ラインに接続されるスイッチ回路で直列共振が生じ、その直列共振を利用して、第２の信号ラインに流入しようとする信号の伝搬を抑えることが可能になる。また、第２の信号ラインに接続するダイオードをOFFにすることで、第１の信号ラインに接続するダイオードもOFFになり、第２の信号ラインとフィルタ調整用キャパシタとの接続を切った状態で、第２の信号ラインに信号を伝搬させることが可能になる。したがって、第２の信号ラインにおける信号伝搬時にフィルタ調整用キャパシタの接続を切り、フィルタ調整用キャパシタによって第２の信号ラインの通過特性に及ぶ影響を除くことが可能になる。 According to this configuration, by applying a bias voltage from the control terminal and turning on the diode connected to the second signal line, the diode connected to the first signal line is also turned on. At this time, a series resonance occurs in the switch circuit connected to the second signal line, and it is possible to suppress the propagation of a signal to flow into the second signal line using the series resonance. Also, by turning off the diode connected to the second signal line, the diode connected to the first signal line is also turned off, and the connection between the second signal line and the filter adjustment capacitor is disconnected. The signal can be propagated to the second signal line. Therefore, it is possible to disconnect the filter adjustment capacitor at the time of signal propagation in the second signal line, and remove the influence on the pass characteristic of the second signal line by the filter adjustment capacitor.
　この発明の高周波モジュールは、並列共振キャパシタの少なくとも一部を構成するパターン電極と、直列共振キャパシタの少なくとも一部を構成するパターン電極と、を多層基板の主面法線方向に対向させてフィルタ調整用キャパシタを構成すると好適である。または、並列共振キャパシタに接続される配線電極と、直列共振キャパシタに接続される配線電極と、を多層基板の主面法線方向に対向させてフィルタ調整用キャパシタを構成すると好適である。 The high-frequency module according to the present invention adjusts a filter by making a pattern electrode constituting at least a part of a parallel resonant capacitor and a pattern electrode constituting at least a part of a series resonant capacitor face each other in the normal direction of the main surface of the multilayer substrate It is preferable to construct a capacitor for use. Alternatively, it is preferable that the filter adjustment capacitor is configured such that the wiring electrode connected to the parallel resonance capacitor and the wiring electrode connected to the series resonance capacitor face each other in the normal direction of the main surface of the multilayer substrate.
　このようにしてフィルタ調整用キャパシタを構成することで、モジュールサイズの増大を抑えながら、フィルタ調整用キャパシタを設けることができる。また、フィルタ調整用キャパシタの接続配線による寄生容量の発生を抑えることができ、直列共振キャパシタとダイオードとの直列共振を安定させ、第２の信号ラインにおける通過特性の変動を抑制できる。 By configuring the filter adjustment capacitor in this manner, it is possible to provide the filter adjustment capacitor while suppressing an increase in module size. In addition, the generation of parasitic capacitance due to the connection wiring of the filter adjustment capacitor can be suppressed, the series resonance between the series resonance capacitor and the diode can be stabilized, and the fluctuation of the pass characteristic in the second signal line can be suppressed.
　この発明によれば、フィルタ調整用キャパシタを設けてキャパシタンス調整することで、高周波モジュールの周波数特性に所望の変化を与えることができる。具体的には、フィルタ調整用キャパシタを接続する第１の信号ラインと第２の信号ラインとの間でのアイソレーションを確保することが可能になる。 According to the present invention, a desired change can be given to the frequency characteristics of the high-frequency module by providing the filter adjusting capacitor and adjusting the capacitance. Specifically, it is possible to ensure isolation between the first signal line and the second signal line connecting the filter adjustment capacitors.
本発明の第１の実施形態に係る高周波モジュールの概略の回路図である。1 is a schematic circuit diagram of a high-frequency module according to a first embodiment of the present invention. 図１に示す高周波モジュールの特性図である。It is a characteristic view of the high frequency module shown in FIG. 図１に示す高周波モジュールの積み図である。FIG. 2 is a stacking diagram of the high-frequency module shown in FIG. 1. 図１に示す高周波モジュールの積み図である。FIG. 2 is a stacking diagram of the high-frequency module shown in FIG. 1. 本発明の第２の実施形態に係る高周波モジュールの概略の回路図である。It is a schematic circuit diagram of the high frequency module which concerns on the 2nd Embodiment of this invention. 図５に示す高周波モジュールの特性図である。It is a characteristic view of the high frequency module shown in FIG. 本発明の第３の実施形態に係る高周波モジュールの概略の回路図である。It is a schematic circuit diagram of the high frequency module which concerns on the 3rd Embodiment of this invention. 図７に示す高周波モジュールの特性図である。It is a characteristic view of the high frequency module shown in FIG.
　以下、本発明の第１の実施形態に係る高周波モジュールの構成例を説明する。 Hereinafter, a configuration example of the high-frequency module according to the first embodiment of the present invention will be described.
　本実施形態の高周波モジュールは、EDGE方式の携帯電話機のフロントエンド部に採用され、PCSとDCSとEGSMとの３つの通信システムを利用するトリプルバンド対応のものである。 The high-frequency module of this embodiment is adopted for the front-end part of an EDGE type mobile phone, and is compatible with a triple band using three communication systems of PCS, DCS, and EGSM.
　図１は、本実施形態に係る高周波モジュールの概略の回路図である。 FIG. 1 is a schematic circuit diagram of the high-frequency module according to the present embodiment.
　高周波モジュール１は、ダイプレクサDPX、分岐部１１Ａ～１１Ｃ、ローパスフィルタLPF1，LPF2、および、フィルタ調整用キャパシタCCCを備える。また、外部接続ポートとして、本発明の共用アンテナポートに相当するアンテナポートANTと、本発明の個別信号入出力ポートに相当する信号ポート1800/1900-Tx，1900-Rx，1800-Rx，850/900-Tx，850/900-Rxと、本発明の制御端子に相当する制御ポートVc1～Vc3と、を備える。 The high-frequency module 1 includes a diplexer DPX, branch portions 11A to 11C, low-pass filters LPF1 and LPF2, and a filter adjustment capacitor CCC. Further, as external connection ports, an antenna port ANT corresponding to the shared antenna port of the present invention, and a signal port 1800 / 1900-Tx, 1900-Rx, 1800-Rx, 850 / 900-Tx, 850 / 900-Rx, and control ports Vc1 to Vc3 corresponding to the control terminals of the present invention.
　ダイプレクサDPXは、ローパスフィルタLPFとハイパスフィルタHPFとを備え、ローパスフィルタLPFとハイパスフィルタHPFとの接続点に直流カット用のキャパシタを介してアンテナポートANTが接続される。ダイプレクサDPXは、ローパスフィルタLPFにEGSMの信号を通過させ、PCSおよびDCSの信号を減衰させる。また、ハイパスフィルタHPFにPCSおよびDCSの信号を通過させ、EGSMの信号を減衰させる。 The diplexer DPX includes a low-pass filter LPF and a high-pass filter HPF, and an antenna port ANT is connected to a connection point between the low-pass filter LPF and the high-pass filter HPF via a DC cut capacitor. The diplexer DPX passes the EGSM signal through the low-pass filter LPF and attenuates the PCS and DCS signals. Further, the PCS and DCS signals are passed through the high-pass filter HPF, and the EGSM signals are attenuated.
　ローパスフィルタLPFはアンテナポートANTと分岐部１１Ｃとの間に接続される。このローパスフィルタLPFは、キャパシタCt1とインダクタLt1とキャパシタCu1とを備え、EGSMの信号帯域を通過帯域とする低域通過フィルタを構成する。インダクタLt1は第一端がアンテナポートANTに接続され、第二端が分岐部１１Ｃに接続される。キャパシタCt1はインダクタLt1に対して並列に接続される。インダクタLt1の第二端はキャパシタCu1を介してグランドに接続される。 The low pass filter LPF is connected between the antenna port ANT and the branch part 11C. This low-pass filter LPF includes a capacitor Ct1, an inductor Lt1, and a capacitor Cu1, and constitutes a low-pass filter that uses the signal band of EGSM as a pass band. The inductor Lt1 has a first end connected to the antenna port ANT and a second end connected to the branch portion 11C. Capacitor Ct1 is connected in parallel to inductor Lt1. The second end of the inductor Lt1 is connected to the ground via the capacitor Cu1.
　ハイパスフィルタHPFはアンテナポートANTと分岐部１１Ａとの間に接続される。このハイパスフィルタHPFはキャパシタCc1，Cc2とインダクタLt2とキャパシタCt2とを備え、PCSおよびDCSの信号帯域を通過帯域とする高域通過フィルタを構成する。キャパシタCc1は、第一端がアンテナポートANTに接続され、第二端がキャパシタCc2に接続される。キャパシタCc2は、第一端がキャパシタCc1に接続され、第二端が分岐部１１Ａに接続される。インダクタLt2の第一端は、キャパシタCc1の第二端とキャパシタCc2の第一端とに接続される。インダクタLt2の第二端は、キャパシタCt2を介してグランドに接続される。 The high pass filter HPF is connected between the antenna port ANT and the branch part 11A. The high-pass filter HPF includes capacitors Cc1 and Cc2, an inductor Lt2, and a capacitor Ct2, and constitutes a high-pass filter having the PCS and DCS signal bands as pass bands. The capacitor Cc1 has a first end connected to the antenna port ANT and a second end connected to the capacitor Cc2. Capacitor Cc2 has a first end connected to capacitor Cc1 and a second end connected to branch portion 11A. The first end of the inductor Lt2 is connected to the second end of the capacitor Cc1 and the first end of the capacitor Cc2. The second end of the inductor Lt2 is connected to the ground via the capacitor Ct2.
　分岐部１１Ｃは、スイッチ回路SW5，SW6を備え、スイッチ回路SW5とスイッチ回路SW6との接続点でローパスフィルタLPFに接続される。分岐部１１Ｃは、外部から制御ポートVc1に入力される電圧に基づいてEGSM送信状態とEGSM受信状態とが切り替わる。 The branch section 11C includes switch circuits SW5 and SW6, and is connected to the low-pass filter LPF at a connection point between the switch circuit SW5 and the switch circuit SW6. The branching unit 11C switches between an EGSM transmission state and an EGSM reception state based on a voltage input to the control port Vc1 from the outside.
　スイッチ回路SW5は、ローパスフィルタLPFとローパスフィルタLPF2との間に接続される。このスイッチ回路SW5は、ダイオードGD1とインダクタGSL1とを備える。ダイオードGD1は、アノードがローパスフィルタLPFに、カソードがローパスフィルタLPF2に接続される。ダイオードGD1のカソードは、インダクタGSL1を介してグランドに接続される。 The switch circuit SW5 is connected between the low pass filter LPF and the low pass filter LPF2. The switch circuit SW5 includes a diode GD1 and an inductor GSL1. The diode GD1 has an anode connected to the low-pass filter LPF and a cathode connected to the low-pass filter LPF2. The cathode of the diode GD1 is connected to the ground via the inductor GSL1.
　スイッチ回路SW6はローパスフィルタLPFと信号ポート850/900-Rxとの間に接続される。このスイッチ回路SW6は、インダクタGSL2とキャパシタGCu3とダイオードGD2とキャパシタGC5と抵抗Rgとを備える。インダクタGSL2は、第一端がローパスフィルタLPFに接続され、第二端が直流カット用キャパシタを介して信号ポート850/900-Rxに接続される。インダクタGSL2の第二端は、キャパシタGCu3を介してグランドに接続されるとともに、ダイオードGD2のカソードが接続される。ダイオードGD2のアノードは、抵抗Rgを介して制御ポートVc1に接続され、キャパシタGC5を介してグランドに接続される。 Switch circuit SW6 is connected between low pass filter LPF and signal port 850 / 900-Rx. The switch circuit SW6 includes an inductor GSL2, a capacitor GCu3, a diode GD2, a capacitor GC5, and a resistor Rg. The inductor GSL2 has a first end connected to the low pass filter LPF and a second end connected to the signal port 850 / 900-Rx via a DC cut capacitor. The second end of the inductor GSL2 is connected to the ground via the capacitor GCu3 and the cathode of the diode GD2 is connected. The anode of the diode GD2 is connected to the control port Vc1 through the resistor Rg, and is connected to the ground through the capacitor GC5.
　分岐部１１ＣがEGSM送信状態のとき、スイッチ回路SW6はEGSMの送信信号の伝搬を抑制し、スイッチ回路SW5はEGSMの送信信号を伝搬する。その際には制御ポートVc1からの電圧印加により、ダイオードGD2のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードGD2がONになってインダクタGSL2の第二端がキャパシタGC5を介してグランドに接続され、ダイオードGD2のインダクタンス成分とキャパシタGC5とが直列共振する。インダクタGSL2の線路長は、EGSMの送信信号周波数帯における波長のほぼ１／４の長さに設定されており、インダクタGSL2のダイオードGD2側が直列共振により接地されるため、スイッチ回路SW5側からインダクタGSL2側を見るとインピーダンスが無限大のオープン状態になるように設定されている。したがって、スイッチ回路SW6におけるEGSMの送信信号の伝搬が抑えられる。一方、スイッチ回路SW5では、ダイオードGD1のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードGD1がONになって、スイッチ回路SW5をEGSMの送信信号が伝搬する。 When the branch unit 11C is in the EGSM transmission state, the switch circuit SW6 suppresses the propagation of the EGSM transmission signal, and the switch circuit SW5 propagates the EGSM transmission signal. At that time, a voltage higher than the switching voltage is applied to the anode of the diode GD2 by applying a voltage from the control port Vc1. For this reason, the diode GD2 is turned on, the second end of the inductor GSL2 is connected to the ground via the capacitor GC5, and the inductance component of the diode GD2 and the capacitor GC5 resonate in series. The line length of the inductor GSL2 is set to approximately ¼ of the wavelength in the transmission signal frequency band of EGSM, and the diode GD2 side of the inductor GSL2 is grounded by series resonance, so that the inductor GSL2 is connected from the switch circuit SW5 side. It is set so that the impedance becomes infinite when viewed from the side. Therefore, propagation of the EGSM transmission signal in the switch circuit SW6 is suppressed. On the other hand, in the switch circuit SW5, a voltage higher than the switching voltage is applied to the anode of the diode GD1. For this reason, the diode GD1 is turned ON, and the transmission signal of EGSM propagates through the switch circuit SW5.
　分岐部１１ＣがEGSM受信状態のとき、スイッチ回路SW6はEGSMの受信信号を伝搬し、スイッチ回路SW5はEGSMの受信信号の伝搬を抑制する。その際には制御ポートVc1からの電圧印加により、ダイオードGD2のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードGD2がOFFになる。これにより、スイッチ回路SW6をEGSMの受信信号が伝搬する。一方、スイッチ回路SW5では、ダイオードGD1のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードGD1がOFFになって、スイッチ回路SW5におけるEGSMの受信信号の伝搬が抑制される。 When the branch unit 11C is in the EGSM reception state, the switch circuit SW6 propagates the EGSM reception signal, and the switch circuit SW5 suppresses the propagation of the EGSM reception signal. At that time, a voltage lower than the switching voltage is applied to the anode of the diode GD2 by applying a voltage from the control port Vc1. For this reason, the diode GD2 is turned OFF. As a result, the received signal of EGSM propagates through the switch circuit SW6. On the other hand, in the switch circuit SW5, a voltage lower than the switching voltage is applied to the anode of the diode GD1. For this reason, the diode GD1 is turned OFF, and the propagation of the reception signal of the EGSM in the switch circuit SW5 is suppressed.
　ローパスフィルタLPF2は、スイッチ回路SW5と信号ポート850/900-Txとの間に接続される。このローパスフィルタLPF2は、インダクタGLt1とキャパシタGCc1とキャパシタGCu1，GCu2とを備え、EGSMの送信信号の２次高調波および３次高調波成分を除去する低域通過フィルタを構成する。インダクタGLt1は、第一端がスイッチ回路SW5に接続され、第二端が直流カット用キャパシタを介して信号ポート850/900-Txに接続される。キャパシタGCc1はインダクタGLt1に対して並列に接続される。インダクタGLt1の第一端はキャパシタGCu1を介してグランドに接続される。インダクタGLt1の第二端は、キャパシタGCu2を介してグランドに接続される。 The low pass filter LPF2 is connected between the switch circuit SW5 and the signal port 850 / 900-Tx. The low-pass filter LPF2 includes an inductor GLt1, a capacitor GCc1, and capacitors GCu1 and GCu2, and constitutes a low-pass filter that removes second and third harmonic components of the EGSM transmission signal. The inductor GLt1 has a first end connected to the switch circuit SW5 and a second end connected to the signal port 850 / 900-Tx via a DC cut capacitor. Capacitor GCc1 is connected in parallel to inductor GLt1. The first end of the inductor GLt1 is connected to the ground via the capacitor GCu1. The second end of the inductor GLt1 is connected to the ground via the capacitor GCu2.
　分岐部１１Ａは、スイッチ回路SW1，SW2を備え、スイッチ回路SW1とスイッチ回路SW2との接続点でハイパスフィルタHPFに接続される。分岐部１１Ａは、外部から制御ポートVc2に入力される電圧に基づいて、送信状態と受信状態とが切り替わる。 The branch section 11A includes switch circuits SW1 and SW2, and is connected to the high-pass filter HPF at a connection point between the switch circuit SW1 and the switch circuit SW2. The branching unit 11A switches between a transmission state and a reception state based on a voltage input to the control port Vc2 from the outside.
　スイッチ回路SW1はハイパスフィルタHPFとローパスフィルタLPF1との間に接続される。このスイッチ回路SW1は、ダイオードDD1とインダクタDPSLtとキャパシタDPCt1とインダクタDPSL1とを備える。ダイオードDD1は、アノードがハイパスフィルタHPFに、カソードがローパスフィルタLPF1に接続される。インダクタDPSLtの第一端はダイオードDD1のアノードに接続され、第二端はキャパシタDPCt1の第一端に接続される。キャパシタDPCt1の第一端は、インダクタDPSLtの第一端に接続され、第二端はダイオードDD1のカソードに接続される。ダイオードDD1のカソードは、インダクタDPSL1を介してグランドに接続される。 The switch circuit SW1 is connected between the high pass filter HPF and the low pass filter LPF1. The switch circuit SW1 includes a diode DD1, an inductor DPSLt, a capacitor DPCt1, and an inductor DPSL1. The diode DD1 has an anode connected to the high pass filter HPF and a cathode connected to the low pass filter LPF1. The first end of the inductor DPSLt is connected to the anode of the diode DD1, and the second end is connected to the first end of the capacitor DPCt1. The first end of the capacitor DPCt1 is connected to the first end of the inductor DPSLt, and the second end is connected to the cathode of the diode DD1. The cathode of the diode DD1 is connected to the ground via the inductor DPSL1.
　スイッチ回路SW2はハイパスフィルタHPFと分岐部１１Ｂとの間に接続される。このスイッチ回路SW2は、インダクタDSL2とキャパシタCDPrとキャパシタDCu4とダイオードDD2とキャパシタDC5と抵抗Rdとを備える。インダクタDSL2は、第一端がハイパスフィルタHPFに接続され、第二端がキャパシタCDPrの第一端とダイオードDD2のカソードとに接続される。キャパシタCDPrの第二端はキャパシタDCu4を介してグランドに接続されるとともに、分岐部１１Ｂに接続される。ダイオードDD2のアノードは、抵抗Rdを介して制御ポートVc2に接続され、本発明の直列共振キャパシタに相当するキャパシタDC5を介してグランドに接続され、詳細を後述するフィルタ調整用キャパシタCCCの第二端が接続される。 The switch circuit SW2 is connected between the high pass filter HPF and the branch part 11B. The switch circuit SW2 includes an inductor DSL2, a capacitor CDPr, a capacitor DCu4, a diode DD2, a capacitor DC5, and a resistor Rd. The inductor DSL2 has a first end connected to the high pass filter HPF and a second end connected to the first end of the capacitor CDPr and the cathode of the diode DD2. The second end of the capacitor CDPr is connected to the ground via the capacitor DCu4 and is also connected to the branch portion 11B. The anode of the diode DD2 is connected to the control port Vc2 through the resistor Rd, is connected to the ground through the capacitor DC5 corresponding to the series resonant capacitor of the present invention, and the second end of the filter adjustment capacitor CCC described in detail later. Is connected.
　分岐部１１Ａが送信状態のとき、スイッチ回路SW2はPCSおよびDCSの送信信号の伝搬を抑制し、スイッチ回路SW1はPCSおよびDCSの送信信号を伝搬する。その際には制御ポートVc2からの電圧印加により、ダイオードDD2のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードDD2がONになってインダクタDSL2の第二端がキャパシタDC5を介してグランドに接続され、ダイオードDD2のインダクタンス成分とキャパシタDC5とが直列共振する。インダクタDSL2の線路長は、PCSおよびDCSの送信信号周波数帯における波長のほぼ１／４の長さに設定されており、インダクタDSL2のダイオードDD2側が直列共振により接地されるため、スイッチ回路SW1側からインダクタDSL2側を見るとインピーダンスが無限大のオープン状態になるように設定されている。したがって、スイッチ回路SW2におけるPCSおよびDCSの送信信号の伝搬が抑えられる。一方、スイッチ回路SW1ではダイオードDD1のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードDD1がONになって、スイッチ回路SW1をPCSおよびDCSの送信信号が伝搬する。 When the branching unit 11A is in a transmission state, the switch circuit SW2 suppresses the transmission of PCS and DCS transmission signals, and the switch circuit SW1 propagates the PCS and DCS transmission signals. At that time, a voltage higher than the switching voltage is applied to the anode of the diode DD2 by applying a voltage from the control port Vc2. For this reason, the diode DD2 is turned on, the second end of the inductor DSL2 is connected to the ground via the capacitor DC5, and the inductance component of the diode DD2 and the capacitor DC5 resonate in series. The line length of the inductor DSL2 is set to approximately ¼ of the wavelength in the transmission signal frequency band of the PCS and DCS, and the diode DD2 side of the inductor DSL2 is grounded by series resonance. When looking at the inductor DSL2 side, the impedance is set to an infinite open state. Therefore, propagation of PCS and DCS transmission signals in the switch circuit SW2 is suppressed. On the other hand, in the switch circuit SW1, a voltage higher than the switching voltage is applied to the anode of the diode DD1. For this reason, the diode DD1 is turned ON, and PCS and DCS transmission signals propagate through the switch circuit SW1.
　分岐部１１Ａが受信状態のとき、スイッチ回路SW2はPCSおよびDCSの受信信号を伝搬し、スイッチ回路SW1はPCSおよびDCSの受信信号の伝搬を抑制する。その際には制御ポートVc2からの電圧印加により、ダイオードDD2のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードDD2がOFFになる。これにより、スイッチ回路SW2をPCSおよびDCSの受信信号が伝搬する。一方、スイッチ回路SW1では、ダイオードDD1のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードDD1がOFFになって、スイッチ回路SW1におけるPCSおよびDCSの受信信号の伝搬が抑制される。 When the branching unit 11A is in a receiving state, the switch circuit SW2 propagates the PCS and DCS received signals, and the switch circuit SW1 suppresses the propagation of the PCS and DCS received signals. At that time, a voltage lower than the switching voltage is applied to the anode of the diode DD2 by applying a voltage from the control port Vc2. For this reason, the diode DD2 is turned OFF. As a result, PCS and DCS received signals propagate through the switch circuit SW2. On the other hand, in the switch circuit SW1, a voltage lower than the switching voltage is applied to the anode of the diode DD1. For this reason, the diode DD1 is turned OFF, and the propagation of PCS and DCS received signals in the switch circuit SW1 is suppressed.
　ローパスフィルタLPF1は、スイッチ回路SW1と信号ポート1800/1900-Txとの間に接続される。このローパスフィルタLPF1は、インダクタDLt1，DLt2とキャパシタDCc1とキャパシタDCu1，DCu2とを備え、PCSおよびDCSの送信信号の２次高調波および３次高調波成分を除去する低域通過フィルタを構成する。インダクタDLt1は本発明の並列共振インダクタに相当し、第一端がスイッチ回路SW1に接続され、第二端がインダクタDLt2の第一端に接続される。インダクタDLt2の第一端はインダクタDLt1の第一端に接続され、インダクタDLt2の第二端は直流カット用キャパシタを介して信号ポート1800/1900-Txに接続される。キャパシタDCc1は本発明の並列共振キャパシタに相当し、インダクタDLt1に並列に接続される。インダクタDLt1の第一端はキャパシタDCu1を介してグランドに接続される。インダクタDLt1の第二端は、キャパシタDCu2を介してグランドに接続されるとともに、後述するフィルタ調整用キャパシタCCCの第一端が接続される。 The low pass filter LPF1 is connected between the switch circuit SW1 and the signal port 1800 / 1900-Tx. The low-pass filter LPF1 includes inductors DLt1 and DLt2, a capacitor DCc1, and capacitors DCu1 and DCu2, and constitutes a low-pass filter that removes second-order harmonics and third-order harmonic components of PCS and DCS transmission signals. The inductor DLt1 corresponds to the parallel resonant inductor of the present invention, and has a first end connected to the switch circuit SW1 and a second end connected to the first end of the inductor DLt2. The first end of the inductor DLt2 is connected to the first end of the inductor DLt1, and the second end of the inductor DLt2 is connected to the signal port 1800 / 1900-Tx via a DC cut capacitor. The capacitor DCc1 corresponds to the parallel resonant capacitor of the present invention, and is connected in parallel to the inductor DLt1. The first end of the inductor DLt1 is connected to the ground via the capacitor DCu1. A second end of the inductor DLt1 is connected to the ground via the capacitor DCu2, and a first end of a filter adjustment capacitor CCC described later is connected.
　分岐部１１Ｂは、スイッチ回路SW3，SW4を備え、スイッチ回路SW3とスイッチ回路SW4との接続点でスイッチ回路SW2に接続される。分岐部１１Bは、外部から制御ポートVc3に入力される電圧に基づいて、PCS受信状態とDCS受信状態とが切り替わる。 The branch section 11B includes switch circuits SW3 and SW4, and is connected to the switch circuit SW2 at a connection point between the switch circuit SW3 and the switch circuit SW4. The branching unit 11B switches between the PCS reception state and the DCS reception state based on the voltage input to the control port Vc3 from the outside.
　スイッチ回路SW3は、スイッチ回路SW2と信号ポート1900-Rxとの間に接続される。このスイッチ回路SW3は、ダイオードPD1とインダクタPSL1とキャパシタPCu3とを備える。ダイオードPD1は、アノードがスイッチ回路SW2に、カソードが直流カット用キャパシタを介して信号ポート1900-Rxに接続される。ダイオードPD1のカソードは、インダクタPSL1を介してグランドに接続され、キャパシタPCu3を介してグランドに接続される。 Switch circuit SW3 is connected between switch circuit SW2 and signal port 1900-Rx. The switch circuit SW3 includes a diode PD1, an inductor PSL1, and a capacitor PCu3. The diode PD1 has an anode connected to the switch circuit SW2 and a cathode connected to the signal port 1900-Rx via a DC cut capacitor. The cathode of the diode PD1 is connected to the ground via the inductor PSL1, and is connected to the ground via the capacitor PCu3.
　スイッチ回路SW4はスイッチ回路SW2と信号ポート1800-Rxとの間に接続される。このスイッチ回路SW4は、インダクタPSL2とキャパシタDCu3とダイオードPD2とキャパシタPC5と抵抗Rpとを備える。インダクタPSL2は、第一端がスイッチ回路SW2に接続され、第二端が直流カット用キャパシタを介して信号ポート1800-Rxに接続される。インダクタPSL2の第二端は、キャパシタDCu3を介してグランドに接続され、ダイオードPD2のカソードが接続される。ダイオードPD2のアノードは、抵抗Rpを介して制御ポートVc3に接続され、キャパシタPC5を介してグランドに接続される。 Switch circuit SW4 is connected between switch circuit SW2 and signal port 1800-Rx. The switch circuit SW4 includes an inductor PSL2, a capacitor DCu3, a diode PD2, a capacitor PC5, and a resistor Rp. The inductor PSL2 has a first end connected to the switch circuit SW2, and a second end connected to the signal port 1800-Rx via a DC cut capacitor. The second end of the inductor PSL2 is connected to the ground via the capacitor DCu3, and the cathode of the diode PD2 is connected. The anode of the diode PD2 is connected to the control port Vc3 through the resistor Rp, and is connected to the ground through the capacitor PC5.
　分岐部１１BがPCS受信状態のとき、スイッチ回路SW4はPCSの受信信号の伝搬を抑制し、スイッチ回路SW3はPCSの受信信号を伝搬する。その際には制御ポートVc3からの電圧印加により、ダイオードPD2のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードPD2がONになってインダクタPSL2の第二端がキャパシタPC5を介してグランドに接続され、ダイオードPD2のインダクタンス成分とキャパシタPC5とが直列共振する。インダクタPSL2の線路長は、PCSの受信信号周波数帯における波長のほぼ１／４の長さに設定されており、インダクタPSL2のダイオードPD2側が直列共振により接地されるため、スイッチ回路SW3側からインダクタPSL2側を見るとインピーダンスが無限大のオープン状態になるように設定されている。したがって、スイッチ回路SW4におけるPCSの受信信号の伝搬が抑えられる。一方、スイッチ回路SW3では、ダイオードPD1のアノードにスイッチング電圧より高い電圧が印加される。このため、ダイオードPD1がONになってスイッチ回路SW3をPCSの受信信号が伝搬する。 When the branch unit 11B is in the PCS reception state, the switch circuit SW4 suppresses the propagation of the PCS reception signal, and the switch circuit SW3 propagates the PCS reception signal. At that time, a voltage higher than the switching voltage is applied to the anode of the diode PD2 by applying a voltage from the control port Vc3. For this reason, the diode PD2 is turned on, the second end of the inductor PSL2 is connected to the ground via the capacitor PC5, and the inductance component of the diode PD2 and the capacitor PC5 resonate in series. The line length of the inductor PSL2 is set to approximately ¼ of the wavelength in the reception signal frequency band of the PCS, and the diode PD2 side of the inductor PSL2 is grounded by series resonance, so that the inductor PSL2 is connected from the switch circuit SW3 side. It is set so that the impedance becomes infinite when viewed from the side. Therefore, propagation of the PCS received signal in the switch circuit SW4 is suppressed. On the other hand, in the switch circuit SW3, a voltage higher than the switching voltage is applied to the anode of the diode PD1. For this reason, the diode PD1 is turned ON, and the PCS received signal propagates through the switch circuit SW3.
　分岐部１１BがDCS受信状態のとき、スイッチ回路SW4はDCSの受信信号を伝搬し、スイッチ回路SW3はDCSの受信信号の伝搬を抑制する。その際には制御ポートVc3からの電圧印加により、ダイオードPD2のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードPD2がOFFになる。これにより、スイッチ回路SW4をDCSの受信信号が伝搬する。一方、スイッチ回路SW3では、ダイオードPD1のアノードにスイッチング電圧より低い電圧が印加される。このため、ダイオードPD1がOFFになって、スイッチ回路SW3におけるDCSの受信信号の伝搬が抑制される。 When the branch unit 11B is in the DCS reception state, the switch circuit SW4 propagates the DCS reception signal, and the switch circuit SW3 suppresses the propagation of the DCS reception signal. At that time, a voltage lower than the switching voltage is applied to the anode of the diode PD2 by voltage application from the control port Vc3. For this reason, the diode PD2 is turned OFF. As a result, the DCS received signal propagates through the switch circuit SW4. On the other hand, in the switch circuit SW3, a voltage lower than the switching voltage is applied to the anode of the diode PD1. For this reason, the diode PD1 is turned OFF, and the propagation of the DCS received signal in the switch circuit SW3 is suppressed.
　ここで、フィルタ調整用キャパシタCCCとしては、約0.2pFのキャパシタンスのものを採用している。フィルタ調整用キャパシタCCCの第一端はローパスフィルタLPF1の、インダクタDLt1とキャパシタDCc1とが構成するLC並列共振回路よりも信号ポート1800/1900-Tx側に接続している。また、その第二端はスイッチ回路SW2に設けたダイオードDD2のアノードに接続している。これにより、分岐部１１Ａでは、ダイオードDD2がONになり、フィルタ調整用キャパシタCCCがインダクタDSL2の第二端に接続されている送信状態の間に、ローパスフィルタLPF1のインダクタDLt1とフィルタ調整用キャパシタCCCとによる並列回路での共振が生じることになる。そのため、この共振を利用して、高周波モジュールの周波数特性に所望の変更を与えることができる。 Here, the filter adjustment capacitor CCC has a capacitance of about 0.2 pF. The first end of the filter adjustment capacitor CCC is connected to the signal port 1800 / 1900-Tx side of the low-pass filter LPF1 from the LC parallel resonance circuit formed by the inductor DLt1 and the capacitor DCc1. Further, the second end thereof is connected to the anode of the diode DD2 provided in the switch circuit SW2. As a result, in the branching section 11A, the diode DD2 is turned ON and the filter adjustment capacitor CCC is connected to the second end of the inductor DSL2, during the transmission state, the inductor DLt1 of the low-pass filter LPF1 and the filter adjustment capacitor CCC. Resonance in a parallel circuit occurs. Therefore, a desired change can be given to the frequency characteristics of the high-frequency module using this resonance.
　なお、フィルタ調整用キャパシタCCCのキャパシタンス値が大きすぎると、フィルタ調整用キャパシタCCCにより接続される信号ライン間のアイソレーションや、各信号ラインの通過特性が劣化する虞がある。そのため、フィルタ調整用キャパシタCCCのキャパシタンスは十分小さく、例えば0.1pF～0.6pFに設定すると好適であり、そのようにフィルタ調整用キャパシタCCCのキャパシタンスが小さくてもローパスフィルタLPF1の回路定数などを適正にキャリブレーションすることで、高周波モジュールの周波数特性に所望の変更を与えることが可能である。 If the capacitance value of the filter adjustment capacitor CCC is too large, the isolation between signal lines connected by the filter adjustment capacitor CCC and the pass characteristics of each signal line may be deteriorated. For this reason, the capacitance of the filter adjustment capacitor CCC is sufficiently small, for example, preferably 0.1 pF to 0.6 pF. Even if the capacitance of the filter adjustment capacitor CCC is small, the circuit constant of the low-pass filter LPF1 is properly set. By calibrating, it is possible to give a desired change to the frequency characteristics of the high-frequency module.
　以上の構成では、ローパスフィルタLPF1がスイッチ回路SW1よりも信号ポート1800/1900-Tx側にシリーズに接続された本発明のフィルタに相当する。そして、アンテナポートANTと信号ポート1800/1900-Txとを接続する信号ラインが、本発明の第1の信号ラインに相当する。また、アンテナポートANTと信号ポート1900-Rxとを接続する信号ラインと、アンテナポートANTと信号ポート1800-Rxとを接続する信号ラインと、がそれぞれ本発明の第２の信号ラインに相当する。 In the above configuration, the low pass filter LPF1 corresponds to the filter of the present invention connected in series to the signal port 1800 / 1900-Tx side of the switch circuit SW1. A signal line connecting the antenna port ANT and the signal port 1800 / 1900-Tx corresponds to the first signal line of the present invention. Further, a signal line connecting the antenna port ANT and the signal port 1900-Rx and a signal line connecting the antenna port ANT and the signal port 1800-Rx correspond to the second signal line of the present invention.
　図２は、本実施形態に係る高周波モジュールの周波数特性を例示する特性図である。なお、本構成例でのデータを図中に実線で、フィルタ調整用キャパシタCCCを設けない比較構成例でのデータを図中に破線で示す。 FIG. 2 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment. The data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
　図２（Ａ）は、アンテナポートANTと信号ポート1800/1900-Txとの間での通過特性を例示する特性図である。これらのポート間の通過特性において、本構成例では約3.37GHzに通過帯域の高周波側の減衰極が位置した。一方、比較構成例では約3.57GHzに通過帯域の高周波側の減衰極が位置した。これらの通過帯域の高周波側の減衰極は、ローパスフィルタLPF1の主作用によってPCS信号およびDCS信号の高次高調波が遮断される周波数である。本構成例では通過帯域の高周波側の減衰極の周波数は比較構成例からあまり遷移せず、フィルタ調整用キャパシタCCCを設けても信号ポート1800/1900-Txを伝搬する信号の高次高調波を十分に遮断できることが確認された。 FIG. 2A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 1800 / 1900-Tx. In the pass characteristics between these ports, in this configuration example, the attenuation pole on the high frequency side of the pass band is located at about 3.37 GHz. On the other hand, in the comparative configuration example, the attenuation pole on the high frequency side of the pass band is located at about 3.57 GHz. The attenuation pole on the high frequency side of these passbands is a frequency at which high-order harmonics of the PCS signal and the DCS signal are blocked by the main action of the low-pass filter LPF1. In this configuration example, the frequency of the attenuation pole on the high frequency side of the passband does not change much from the comparative configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 1800 / 1900-Tx It was confirmed that it could be sufficiently blocked.
　このことから、ローパスフィルタLPF1が設けられる信号ラインにおける通過特性は、ローパスフィルタLPF1単体の共振と、フィルタ調整用キャパシタCCCとによる影響を受けることがわかる。しかしながら、フィルタ調整用キャパシタCCCによる影響はローパスフィルタLPF1単体の共振による影響よりも小さく、この信号ラインにおける通過特性は、フィルタ調整用キャパシタCCCを設けても、あまり損なわれないといえる。このため、本発明によれば、第１の信号ラインにおける通過特性を損なわずに、第１の信号ラインを伝搬する信号と第２の信号ラインを伝搬する信号との間のアイソレーションを改善することが可能であるといえる。 From this, it can be seen that the pass characteristic in the signal line provided with the low-pass filter LPF1 is affected by the resonance of the low-pass filter LPF1 alone and the filter adjusting capacitor CCC. However, the influence of the filter adjustment capacitor CCC is smaller than the influence of the resonance of the low-pass filter LPF1 alone, and it can be said that the pass characteristic in this signal line is not significantly impaired even if the filter adjustment capacitor CCC is provided. For this reason, according to the present invention, the isolation between the signal propagating through the first signal line and the signal propagating through the second signal line is improved without impairing the pass characteristic in the first signal line. It can be said that it is possible.
　図２（Ｂ）および図２（Ｃ）は、信号ポート1800/1900-Txと信号ポート1900-Rxとの間でのアイソレーション特性を例示する特性図である。これらのポート間での周波数特性において、比較構成例では、ローパスフィルタLPF1単体による減衰極が図２（Ａ）の破線に示す周波数特性における減衰極とほぼ等しい周波数の約3.57GHzに位置した。一方、本構成例ではローパスフィルタLPF1単体による減衰極が図２（Ａ）の実線に示す周波数特性における減衰極よりも約370MHz 低い約3.00GHzに位置した（図２（Ｂ）の実線を参照）。本構成例ではフィルタ調整用キャパシタCCCを設けることで、ローパスフィルタLPFを構成するインダクタDLt1ともう１つの並列共振回路を構成することができ、信号ポート1800/1900-Txと信号ポート1900-Rxとの間での周波数特性において、通過帯域の高周波側の減衰極の周波数を比較構成例より低くできることが確認された。さらに本構成例では、比較構成例ではあまり減衰のない約1.71GHz付近での減衰を大きくできることが確認された。これらのことにより、比較構成例では約1.71GHz～約1.91GHzの帯域にわたって確保された減衰量は約23.9dBであったが、本構成例では約1.71GHz～約1.91GHzの帯域にわたって約31.1dBの減衰量を確保することができた。すなわち、PCSの送信信号の周波数帯域（1850～1910MHz）での減衰量を約31.1dB確保し、信号ポート1800/1900-Txと信号ポート1900-Rxとの間のアイソレーションを改善できた。 FIG. 2B and FIG. 2C are characteristic diagrams illustrating the isolation characteristics between the signal port 1800 / 1900-Tx and the signal port 1900-Rx. In the frequency characteristics between these ports, in the comparative configuration example, the attenuation pole due to the low-pass filter LPF1 alone is located at about 3.57 GHz having a frequency substantially equal to the attenuation pole in the frequency characteristics indicated by the broken line in FIG. On the other hand, in this configuration example, the attenuation pole due to the low-pass filter LPF1 alone is located at about 3.00 GHz, which is about 370 MHz lower than the attenuation pole in the frequency characteristic shown by the solid line in FIG. 2A (see the solid line in FIG. 2B). . In this configuration example, by providing the filter adjustment capacitor CCC, the inductor DLt1 constituting the low-pass filter LPF and another parallel resonance circuit can be configured. The signal port 1800 / 1900-Tx and the signal port 1900-Rx It was confirmed that the frequency characteristic between the two can be lower than that of the comparative configuration example in the frequency of the attenuation pole on the high frequency side of the pass band. Furthermore, in this configuration example, it was confirmed that attenuation in the vicinity of about 1.71 GHz, which is not much attenuated in the comparative configuration example, can be increased. As a result, in the comparative configuration example, the attenuation secured over the band of about 1.71 GHz to about 1.91 GHz was about 23.9 dB, but in this configuration example, about 31.1 dB over the band of about 1.71 GHz to about 1.91 GHz. It was possible to secure the amount of attenuation. In other words, the attenuation of the PCS transmission signal in the frequency band (1850 to 1910 MHz) was secured about 31.1 dB, and the isolation between the signal port 1800 / 1900-Tx and the signal port 1900-Rx could be improved.
　図３，４は、本実施形態に係る高周波モジュールの積み図である。図３（Ａ）～（Ｏ），図４（Ｐ）～（Ｙ）は最下層から最上層まで順に基板（Ａ）～（Ｙ）を下面視した平面図である。また図４（Ｚ）は多層基板の最上層の基板（Ｙ）を上面視した平面図である。なお、基板（Ａ）～（Ｙ）におけるビア電極は図中に丸印で示す。 3 and 4 are stacked diagrams of the high-frequency module according to the present embodiment. FIGS. 3A to 3O and FIGS. 4P to 4Y are plan views of the substrates (A) to (Y) viewed from the bottom in order from the bottom layer to the top layer. FIG. 4 (Z) is a plan view of the uppermost substrate (Y) of the multilayer substrate as viewed from above. The via electrodes in the substrates (A) to (Y) are indicated by circles in the drawing.
　基板（Ａ）は多層基板の最下層に積層され、下面が高周波モジュールの実装面になっていて、複数の実装電極が形成されている。図中に示す矢印は、実装電極のポート名を示す。 The substrate (A) is laminated on the lowermost layer of the multilayer substrate, the lower surface is the mounting surface of the high-frequency module, and a plurality of mounting electrodes are formed. The arrows shown in the figure indicate the port names of the mounting electrodes.
　基板（Ｂ）は多層基板の最下層から２層目に積層され、基板下面に内装グランド電極が設けられ、基板内部にビア電極が設けられる。 The substrate (B) is laminated in the second layer from the lowest layer of the multilayer substrate, an interior ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate.
　基板（Ｃ）は多層基板の最下層から３層目に積層され、基板下面にキャパシタGCu3を構成するパターン電極と、キャパシタGC5を構成するパターン電極とが設けられ、基板内部にビア電極が設けられる。 The substrate (C) is stacked as the third layer from the bottom layer of the multilayer substrate, and a pattern electrode constituting the capacitor GCu3 and a pattern electrode constituting the capacitor GC5 are provided on the lower surface of the substrate, and a via electrode is provided inside the substrate. .
　基板（Ｄ）は多層基板の最下層から４層目に積層され、基板下面に内装グランド電極が設けられ、基板内部にビア電極が設けられる。基板（Ｄ）のグランド電極および基板（Ｂ）のグランド電極と、両グランド電極にはさみこまれる基板（Ｃ）パターン電極との間でキャパシタGCu3，GC5を構成している。 The substrate (D) is laminated in the fourth layer from the lowest layer of the multilayer substrate, an interior ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate. Capacitors GCu3 and GC5 are formed between the ground electrode of the substrate (D) and the ground electrode of the substrate (B) and the substrate (C) pattern electrode sandwiched between the ground electrodes.
　基板（Ｅ）は多層基板の最下層から５層目に積層され、基板下面にキャパシタPC5を構成するパターン電極と、キャパシタGC5を構成するパターン電極と、キャパシタDC5を構成するパターン電極と、キャパシタGCu2を構成するパターン電極とが設けられ、基板内部にビア電極が設けられる。 The substrate (E) is laminated in the fifth layer from the lowest layer of the multilayer substrate, and the pattern electrode constituting the capacitor PC5, the pattern electrode constituting the capacitor GC5, the pattern electrode constituting the capacitor DC5, and the capacitor GCu2 are formed on the lower surface of the substrate. And a via electrode is provided inside the substrate.
　基板（Ｆ）は多層基板の最下層から６層目に積層され、基板下面にキャパシタDCu2を構成するパターン電極と、内装グランド電極とが設けられ、基板内部にビア電極が設けられる。基板（Ｆ）のグランド電極および基板（Ｄ）のグランド電極と、両グランド電極にはさみこまれる基板（Ｅ）のパターン電極との間でキャパシタPC5，GC5，DC5，GCu2を構成している。 The substrate (F) is laminated in the sixth layer from the bottom layer of the multilayer substrate, the pattern electrode constituting the capacitor DCu2 and the interior ground electrode are provided on the lower surface of the substrate, and the via electrode is provided inside the substrate. Capacitors PC5, GC5, DC5, and GCu2 are formed between the ground electrode of the substrate (F), the ground electrode of the substrate (D), and the pattern electrode of the substrate (E) sandwiched between the ground electrodes.
　ここで、基板（Ｅ）のキャパシタDC5を構成するパターン電極と、基板（Ｆ）のキャパシタDCu2を構成するパターン電極とは基板（Ｅ）を介して対向させていて、これらのパターン電極の重なりによりフィルタ調整用キャパシタCCCとして機能させている。 Here, the pattern electrode constituting the capacitor DC5 of the substrate (E) and the pattern electrode constituting the capacitor DCu2 of the substrate (F) are opposed to each other through the substrate (E), and these pattern electrodes are overlapped. It functions as a filter adjustment capacitor CCC.
　基板（Ｇ）は多層基板の最下層から７層目に積層され、基板下面にキャパシタCt2を構成するパターン電極と、キャパシタCu1を構成するパターン電極と、キャパシタDCu2を構成するパターン電極と、キャパシタGCu1を構成するパターン電極とが設けられ、基板内部にビア電極が設けられる。 The substrate (G) is laminated to the seventh layer from the bottom layer of the multilayer substrate, and the pattern electrode constituting the capacitor Ct2, the pattern electrode constituting the capacitor Cu1, the pattern electrode constituting the capacitor DCu2, and the capacitor GCu1 are formed on the lower surface of the substrate. And a via electrode is provided inside the substrate.
　基板（Ｈ）は多層基板の最下層から８層目に積層され、基板下面に内層グランド電極が設けられ、基板内部にビア電極が設けられる。このグランド電極は、基板（Ｇ）に形成したパターン電極との間でキャパシタCt2，Cu1，DCu2，GCu1を構成している。 The substrate (H) is laminated in the eighth layer from the bottom layer of the multilayer substrate, an inner layer ground electrode is provided on the lower surface of the substrate, and a via electrode is provided inside the substrate. This ground electrode constitutes capacitors Ct2, Cu1, DCu2, and GCu1 with the pattern electrode formed on the substrate (G).
　基板（Ｉ）は多層基板の最下層から９層目に積層され、基板下面にキャパシタDCu4を構成するパターン電極と、キャパシタDCu1を構成するパターン電極とが設けられ、基板（Ｈ）に形成したグランド電極との間でキャパシタDCu4，DCu1を構成している。基板内部にはビア電極が設けられている。 The substrate (I) is laminated in the ninth layer from the bottom layer of the multilayer substrate, and a ground electrode formed on the substrate (H) is provided with a pattern electrode constituting the capacitor DCu4 and a pattern electrode constituting the capacitor DCu1 on the lower surface of the substrate. Capacitors DCu4 and DCu1 are formed between the electrodes. Via electrodes are provided inside the substrate.
　基板（Ｊ）は多層基板の最下層から１０層目に積層され、基板内部にビア電極が設けられる。 The substrate (J) is laminated to the tenth layer from the bottom layer of the multilayer substrate, and a via electrode is provided inside the substrate.
　基板（Ｋ）～（Ｙ）は多層基板の最下層から１１～２５層目に積層され、基板下面に複数のインダクタを構成する複数のパターン電極が設けられ、基板内部にビア電極が設けられる。基板（Ｙ）の上面には、ディスクリート部品の回路素子を接続する複数の表面電極が設けられる。 The substrates (K) to (Y) are stacked in the 11th to 25th layers from the bottom layer of the multilayer substrate, a plurality of pattern electrodes constituting a plurality of inductors are provided on the lower surface of the substrate, and via electrodes are provided inside the substrate. On the upper surface of the substrate (Y), a plurality of surface electrodes for connecting circuit elements of discrete components are provided.
　本実施形態のように、基板（Ｅ）のキャパシタDC5を構成するパターン電極と、基板（Ｆ）のキャパシタDCu2を構成するパターン電極とをフィルタ調整用キャパシタCCCとして機能させることにより、フィルタ調整用キャパシタCCCを構成するためのパターン電極を別途設ける必要がなくなりモジュールサイズの増大を抑えることができる。また、フィルタ調整用キャパシタCCCを他の回路素子と接続するための線路電極が必要なくなるので、不要な寄生容量の発生を抑えることができ、キャパシタDC5とダイオードDD2との直列共振を安定させ、第２の信号ラインにおける通過特性の変動を抑制できる。 As in this embodiment, the pattern adjustment capacitor CCC of the substrate (F) and the pattern electrode of the substrate (F) capacitor DCu2 are made to function as the filter adjustment capacitor CCC. It is not necessary to separately provide a pattern electrode for constituting the CCC, and an increase in module size can be suppressed. In addition, since the line electrode for connecting the filter adjustment capacitor CCC to other circuit elements is not necessary, generation of unnecessary parasitic capacitance can be suppressed, and the series resonance between the capacitor DC5 and the diode DD2 is stabilized, and the first It is possible to suppress fluctuations in pass characteristics in the two signal lines.
　なお、他にも、キャパシタDC5に接続する配線電極と、キャパシタDCu2に接続する配線電極とを対向させることで、フィルタ調整用キャパシタCCCを構成することも可能である。なお、本実施形態のように多層基板の最下層あるいはその近傍の層にグランド電極を配置することでグランド電極部での寄生インダクタンスの発生が抑えられる。このため、グランド電極の近傍にキャパシタ電極を配置することにより、片端を接地するキャパシタで発生する寄生インダクタンスを低減でき、前記の直列共振のＱが向上し、第１の信号ラインと第２の信号ラインとの間のアイソレーションを改善することができる。 In addition, the filter adjustment capacitor CCC can be configured by making the wiring electrode connected to the capacitor DC5 and the wiring electrode connected to the capacitor DCu2 face each other. In addition, the occurrence of parasitic inductance in the ground electrode portion can be suppressed by arranging the ground electrode in the lowermost layer of the multilayer substrate or a layer in the vicinity thereof as in the present embodiment. For this reason, by disposing the capacitor electrode in the vicinity of the ground electrode, the parasitic inductance generated in the capacitor grounded at one end can be reduced, the Q of the series resonance is improved, and the first signal line and the second signal are improved. The isolation between the lines can be improved.
　次に、本発明の第２の実施形態に係る高周波モジュールの構成例を説明する。以下の説明では、第１の実施形態に係る高周波モジュールと同じ構成には同じ記号を付し、説明を省く。 Next, a configuration example of the high-frequency module according to the second embodiment of the present invention will be described. In the following description, the same symbols are assigned to the same components as those of the high-frequency module according to the first embodiment, and the description is omitted.
　図５は、本実施形態に係る高周波モジュールの概略の回路図である。本実施形態は、フィルタ調整用キャパシタCCCの第一端を、ローパスフィルタLPF1におけるインダクタDLt2の第二端に接続している。このような回路構成を採用しても、本発明は好適に実施できる。 FIG. 5 is a schematic circuit diagram of the high-frequency module according to the present embodiment. In the present embodiment, the first end of the filter adjustment capacitor CCC is connected to the second end of the inductor DLt2 in the low-pass filter LPF1. Even if such a circuit configuration is employed, the present invention can be suitably implemented.
　図６は、本実施形態に係る高周波モジュールの周波数特性を例示する特性図である。なお、本構成例でのデータを図中に実線で、フィルタ調整用キャパシタCCCを設けない比較構成例でのデータを図中に破線で示す。 FIG. 6 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment. The data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
　図６（Ａ）は、アンテナポートANTと信号ポート1800/1900-Txとの間での通過特性を例示する特性図である。これらのポート間の通過特性において、本構成例も比較構成例も約3.03GHzに通過帯域の高周波側の減衰極が位置した。本構成例では通過帯域の高周波側の減衰極の周波数は比較構成例からほとんど遷移せず、フィルタ調整用キャパシタCCCを設けても信号ポート1800/1900-Txを伝搬する信号の高次高調波を十分に遮断できることが確認された。 FIG. 6A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 1800 / 1900-Tx. In the pass characteristics between these ports, the attenuation pole on the high frequency side of the pass band is located at about 3.03 GHz in both this configuration example and the comparative configuration example. In this configuration example, the frequency of the attenuation pole on the high frequency side of the passband hardly changes from the comparative configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 1800 / 1900-Tx It was confirmed that it could be sufficiently blocked.
　図６（Ｂ）は、信号ポート1800/1900-Txと信号ポート1900-Rxとの間でのアイソレーション特性を例示する特性図である。これらのポート間でのアイソレーション特性において、比較構成例では約1.71GHz～約1.91GHzの帯域にわたって確保された減衰量は約22.5dBであったが、本構成例ではPCSの送信信号の周波数帯域を含む約1.71GHz～約1.91GHzの帯域にわたって約31.1dBの減衰量を確保することができた。 FIG. 6B is a characteristic diagram illustrating an isolation characteristic between the signal port 1800 / 1900-Tx and the signal port 1900-Rx. With regard to the isolation characteristics between these ports, in the comparative configuration example, the attenuation secured over the band of about 1.71 GHz to about 1.91 GHz was about 22.5 dB, but in this configuration example, the frequency band of the PCS transmission signal An attenuation of about 31.1 dB could be secured over a band from about 1.71 GHz to about 1.91 GHz.
　次に、本発明の第３の実施形態に係る高周波モジュールの構成例を説明する。以下の説明では、第１の実施形態に係る高周波モジュールと同じ構成には同じ記号を付し、説明を省く。 Next, a configuration example of the high-frequency module according to the third embodiment of the present invention will be described. In the following description, the same symbols are assigned to the same components as those of the high-frequency module according to the first embodiment, and the description is omitted.
　図７は、本実施形態に係る高周波モジュールの概略の回路図である。本実施形態は、フィルタ調整用キャパシタCCCの第一端を、ローパスフィルタLPF2におけるインダクタGLt1の第二端に接続している。そして、フィルタ調整用キャパシタCCCの第二端を、スイッチ回路SW6におけるダイオードGD2のアノードに接続している。なお、ここではフィルタ調整用キャパシタCCCのキャパシタンスを約0.5pFとしている。このような回路構成を採用しても、本発明は好適に実施できる。 FIG. 7 is a schematic circuit diagram of the high-frequency module according to the present embodiment. In the present embodiment, the first end of the filter adjustment capacitor CCC is connected to the second end of the inductor GLt1 in the low-pass filter LPF2. The second end of the filter adjustment capacitor CCC is connected to the anode of the diode GD2 in the switch circuit SW6. Here, the capacitance of the filter adjustment capacitor CCC is about 0.5 pF. Even if such a circuit configuration is employed, the present invention can be suitably implemented.
　図８は、本実施形態に係る高周波モジュールの周波数特性を例示する特性図である。なお、本構成例でのデータを図中に実線で、フィルタ調整用キャパシタCCCを設けない比較構成例でのデータを図中に破線で示す。 FIG. 8 is a characteristic diagram illustrating the frequency characteristics of the high-frequency module according to this embodiment. The data in this configuration example is indicated by a solid line in the drawing, and the data in a comparative configuration example in which the filter adjustment capacitor CCC is not provided is indicated by a broken line in the drawing.
　図８（Ａ）は、アンテナポートANTと信号ポート850/900-Txとの間での通過特性を例示する特性図である。これらのポート間の通過特性において、本構成例も比較構成例も約1.83GHzに通過帯域の高周波側の減衰極が位置した。これらの通過帯域の高周波側の減衰極は、ローパスフィルタLPF2の主作用によってEGSM信号の高次高調波が遮断される周波数である。本構成例では通過帯域の高周波側の減衰極の周波数は比較構成例からほとんど遷移せず、フィルタ調整用キャパシタCCCを設けても信号ポート850/900-Txを伝搬する信号の高次高調波を十分に遮断できることが確認された。 FIG. 8A is a characteristic diagram illustrating the pass characteristic between the antenna port ANT and the signal port 850 / 900-Tx. In the pass characteristics between these ports, the attenuation pole on the high frequency side of the passband is located at about 1.83 GHz in both this configuration example and the comparative configuration example. The attenuation pole on the high frequency side of these passbands is a frequency at which high-order harmonics of the EGSM signal are blocked by the main action of the low-pass filter LPF2. In this configuration example, the frequency of the attenuation pole on the high frequency side of the passband hardly changes from the comparison configuration example, and even if the filter adjustment capacitor CCC is provided, the higher-order harmonics of the signal propagating through the signal port 850 / 900-Tx It was confirmed that it could be sufficiently blocked.
　図８（Ｂ）は、信号ポート850/900-Txと信号ポート900-Rxとの間でのアイソレーション特性を例示する特性図である。これらのポート間でのアイソレーション特性において、比較構成例では約820MHz～920MHzの帯域にわたって確保された減衰量は約26.4dBであったが、本構成例ではEGSMの送信信号の周波数帯域を含む820MHz～920MHzの帯域にわたって約29.6dBの減衰量を確保することができた。 FIG. 8B is a characteristic diagram illustrating isolation characteristics between the signal port 850 / 900-Tx and the signal port 900-Rx. With regard to the isolation characteristics between these ports, in the comparative configuration example, the attenuation secured over the band of about 820 MHz to 920 MHz was about 26.4 dB, but in this configuration example, 820 MHz including the frequency band of the EGSM transmission signal Attenuation of about 29.6dB could be secured over the band of ~ 920MHz.
　上述の各実施形態に示す他にも、本発明は上述の回路構成でフィルタ調整用キャパシタCCCの接続箇所を変更するようにしても好適に実施できる。例えば、フィルタ調整用キャパシタCCCの第一端をローパスフィルタLPF1の後段に接続し、第二端をダイオードPD2のアノードなどに接続して構成することも可能である。 Besides the above-described embodiments, the present invention can be suitably implemented by changing the connection location of the filter adjustment capacitor CCC with the above-described circuit configuration. For example, the first end of the filter adjustment capacitor CCC can be connected to the subsequent stage of the low-pass filter LPF1, and the second end can be connected to the anode of the diode PD2 or the like.
　また、本発明は他の回路構成であっても好適に実施できる。例えば、上述の回路構成の信号ポート1900-Rxなどにフィルタの構成を追加し、そのフィルタの信号ポート側にフィルタ調整用キャパシタCCCの第一端を接続し、フィルタ調整用キャパシタCCCの第二端をダイオードPD2のアノードに接続するように構成することも可能である。 In addition, the present invention can be suitably implemented even with other circuit configurations. For example, a filter configuration is added to the signal port 1900-Rx having the circuit configuration described above, the first end of the filter adjustment capacitor CCC is connected to the signal port side of the filter, and the second end of the filter adjustment capacitor CCC is connected. Can be connected to the anode of the diode PD2.
　１…高周波モジュール
　DPX…ダイプレクサ
　HPF…ハイパスフィルタ
　LPF，LPF1，LPF2…ローパスフィルタ
　１１Ａ～１１Ｃ…分岐部
　SW1～SW6…スイッチ回路
　DD1，DD2，GD1，GD2，PD1，PD2…ダイオード
　CCC…フィルタ調整用キャパシタ 1 ... High frequency module DPX ... Diplexer HPF ... High pass filter LPF, LPF1, LPF2 ... Low pass filter 11A to 11C ... Branch SW1 to SW6 ... Switch circuit DD1, DD2, GD1, GD2, PD1, PD2 ... Diode CCC ... Capacitor for filter adjustment

Claims (7)

  1. 　複数の個別信号入出力ポートと、共用アンテナポートと、前記共用アンテナポートと前記複数の個別信号入出力ポートとの接続を切り替えるスイッチ回路と、前記共用アンテナポートと前記個別信号入出力ポートとを接続する第１および第２の信号ラインと、を備える高周波モジュールであって、
    　前記スイッチ回路を、前記第１および第２の信号ラインそれぞれに接続したスイッチ素子を含んで構成し、
    　前記第１の信号ラインにおける前記スイッチ回路の接続位置よりも前記個別信号入出力ポート側にシリーズに接続されたフィルタと、
    　前記第１の信号ラインにおける前記フィルタの接続位置よりも前記個別信号入出力ポート側に第一端が接続され、前記第２の信号ラインに接続した前記スイッチ素子に第二端が接続されたフィルタ調整用キャパシタと、を備える、
    高周波モジュール。     A plurality of individual signal input / output ports, a shared antenna port, a switch circuit for switching connection between the shared antenna port and the plurality of individual signal input / output ports, and a connection between the shared antenna port and the individual signal input / output port A high frequency module comprising: a first signal line and a second signal line;
    The switch circuit includes a switch element connected to each of the first and second signal lines;
    A filter connected in series to the individual signal input / output port side from the connection position of the switch circuit in the first signal line;
    A filter having a first end connected to the individual signal input / output port side of a connection position of the filter in the first signal line, and a second end connected to the switch element connected to the second signal line. An adjustment capacitor,
    High frequency module.
  2. 　前記フィルタは、並列に接続される並列共振キャパシタと並列共振インダクタとを備え、前記並列共振キャパシタと前記並列共振インダクタとによる並列共振の共振周波数が、前記第１の信号ラインを伝搬する信号の高次高調波の周波数に設定される、請求項１に記載の高周波モジュール。 The filter includes a parallel resonant capacitor and a parallel resonant inductor connected in parallel, and a resonance frequency of parallel resonance caused by the parallel resonant capacitor and the parallel resonant inductor is high in a signal propagating through the first signal line. The high frequency module according to claim 1, wherein the high frequency module is set to a frequency of a second harmonic.
  3. 　前記フィルタ調整用キャパシタと前記並列共振インダクタとによる共振回路の共振周波数が、前記第１の信号ラインを伝搬する信号の基本波あるいは高次高調波の周波数に設定される、請求項２に記載の高周波モジュール。 The resonance frequency of a resonance circuit including the filter adjustment capacitor and the parallel resonance inductor is set to a frequency of a fundamental wave or a high-order harmonic of a signal propagating through the first signal line. High frequency module.
  4. 　前記第１の信号ラインに接続した前記スイッチ素子は、前記第１の信号ラインにおける前記共用アンテナポート側にアノードが接続され、前記個別信号入出力ポート側にカソードが接続された第１のダイオードであり、
    　前記第２の信号ラインに接続した前記スイッチ素子は、前記第２の信号ラインにカソードが接続され、制御端子にアノードが接続される第２のダイオードであって、前記アノードが直列共振キャパシタを介してグランドに接続され、
    　前記フィルタ調整用キャパシタは、前記第２のダイオードと前記直列共振キャパシタとの接続位置に前記第二端が接続される、請求項１～３のいずれかに記載の高周波モジュール。     The switch element connected to the first signal line is a first diode having an anode connected to the shared antenna port side in the first signal line and a cathode connected to the individual signal input / output port side. Yes,
    The switch element connected to the second signal line is a second diode having a cathode connected to the second signal line and an anode connected to a control terminal, the anode being connected via a series resonant capacitor. Connected to ground,
    The high-frequency module according to claim 1, wherein the second end of the filter adjustment capacitor is connected to a connection position between the second diode and the series resonance capacitor.
  5. 　前記並列共振キャパシタの少なくとも一部を構成するパターン電極と、前記直列共振キャパシタの少なくとも一部を構成するパターン電極と、を多層基板の主面法線方向に対向させて前記フィルタ調整用キャパシタを構成した、請求項４に記載の高周波モジュール。 The filter adjustment capacitor is configured such that a pattern electrode constituting at least part of the parallel resonant capacitor and a pattern electrode constituting at least part of the series resonant capacitor are opposed to each other in the normal direction of the main surface of the multilayer substrate. The high frequency module according to claim 4.
  6. 　前記並列共振キャパシタに接続される配線電極と、前記直列共振キャパシタに接続される配線電極と、を多層基板の主面法線方向に対向させて前記フィルタ調整用キャパシタを構成した、請求項４に記載の高周波モジュール。 5. The filter adjustment capacitor is configured by configuring a wiring electrode connected to the parallel resonant capacitor and a wiring electrode connected to the series resonant capacitor to face each other in a normal direction of a main surface of the multilayer substrate. The high-frequency module described.
  7. 　前記フィルタ調整用キャパシタのキャパシタンスを約0.1pF～約0.6pFとした、請求項１～６のいずれかに記載の高周波モジュール。 The high frequency module according to any one of claims 1 to 6, wherein a capacitance of the filter adjusting capacitor is set to about 0.1 pF to about 0.6 pF.
PCT/JP2010/053284 2009-03-03 2010-03-02 High frequency module WO2010101130A1 (en)

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