WO2010098486A1 - Dc-dc converter - Google Patents

Dc-dc converter Download PDF

Info

Publication number
WO2010098486A1
WO2010098486A1 PCT/JP2010/053269 JP2010053269W WO2010098486A1 WO 2010098486 A1 WO2010098486 A1 WO 2010098486A1 JP 2010053269 W JP2010053269 W JP 2010053269W WO 2010098486 A1 WO2010098486 A1 WO 2010098486A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
circuit
switching
switching elements
timing
Prior art date
Application number
PCT/JP2010/053269
Other languages
French (fr)
Japanese (ja)
Inventor
希 丹
彰二 堀内
Original Assignee
株式会社ウインズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ウインズ filed Critical 株式会社ウインズ
Publication of WO2010098486A1 publication Critical patent/WO2010098486A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a DC-DC converter, and more particularly to an isolated DC-DC converter premised on the use of a power factor correction circuit.
  • a distributed power supply system that converts electric power from a distributed direct current power source, for example, a household fuel cell, a solar power generation system or a wind power generation system into a medium power capacity (0.3 kW to 10 kW) is a power conversion device such as an inverter.
  • a power conversion device such as an inverter.
  • insulation between the input (primary side) and the system (secondary side) is desired. Even if a high-frequency insulation type converter is used in such a power conversion device, there is a problem that efficiency is deteriorated as compared with a non-insulation type converter.
  • Patent Document 1 proposes a highly efficient DC-DC converter.
  • Patent Document 2 discloses a resonant switching power supply that can reduce switching loss by switching a switching element (FET) with zero voltage or zero current (ZVS or ZCS).
  • Patent Document 3 discloses a DC-DC converter that switches a switch of a switching power supply at zero voltage and zero current. Patent Document 3 describes that a current resonance circuit is provided between the switching power supply circuit and the transformer, and the switch of the switching power supply circuit is operated at a frequency near the resonance frequency fr.
  • Patent Documents 4 and 5 describe that not only the switching power supply is provided on the primary side of the transformer, but also the booster circuit provided on the secondary side is formed of switching elements.
  • Japanese Patent No. 3934654 Japanese Patent Application Laid-Open No. 07-274498 Japanese Patent Application Laid-Open No. 07-222444 JP 2005-318757 A Japanese Patent Laid-Open No. 06-311743
  • the DC-DC converters disclosed in Patent Documents 1 to 5 can achieve high efficiency. However, from the viewpoint of small energy, there is a demand for further improvement in the efficiency of an isolated DC-DC converter that can realize a DC-DC conversion with a higher switching efficiency and a higher efficiency. In particular, in a DC-DC converter in which a resonance current circuit is provided on the primary side of a high-frequency transformer and the primary side voltage can be boosted, it is desired that target power can be efficiently supplied according to output side load fluctuations. Yes. In particular, there is a demand for the appearance of a DC-DC converter circuit that is stable and has little loss even when a load change from small power to steady power occurs.
  • an isolated DC-DC converter it is important to improve efficiency in the entire operation range, and a fail-safe function for safety and a communication function as a network power source are becoming more important. Furthermore, in an isolated DC-DC converter, it is required to realize a low-cost digital power source on the premise of using an MPU or the like.
  • the present invention has been made to solve the above problems, and an object thereof is to provide a highly efficient DC-DC converter.
  • DC power is input from a low voltage DC power source including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies.
  • a voltage resonant circuit that converts and outputs, and An insulated high-frequency transformer having a primary side and a secondary side;
  • a series resonance circuit comprising an inductance connected between the voltage resonance circuit and a first terminal on the primary side of the first transformer, and a capacitor connected in series with the inductance, via the series circuit
  • a rectifier circuit connected to the secondary side of the insulated high-frequency transformer;
  • a smoothing circuit connected to the rectifier circuit;
  • a first driver circuit that maintains voltage resonance in the voltage resonance circuit with a first switching signal that turns on and off the first switching element at a timing when the conduction current is zero and the applied voltage is substantially zero;
  • a control circuit that sets a frequency of the first switching signal depending on an output
  • the primary and secondary switching circuits perform soft switching in the entire operation region, the efficiency becomes high. Further, according to the DC-DC converter of the present invention, since the number of circuit components is small, the size and weight can be reduced, and not only the cost is reduced, but also the reliability against the component failure is improved.
  • a highly efficient DC-DC converter is provided.
  • FIG. 1 is a block diagram schematically showing a DC-DC converter according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing in detail the DC-DC converter shown in FIG.
  • FIG. 3 is a circuit diagram showing a half-bridge circuit according to a modification of the voltage resonance circuit shown in FIG.
  • FIG. 4 is a graph showing the relationship between the frequency of the pulse signal and the input voltage Vin for making the output power output constant in the circuit shown in FIG.
  • FIG. 5A is a graph showing the relationship between the output power and the frequency of a pulse signal that varies the output power output after the input voltage reaches a certain steady state in the circuit shown in FIG.
  • FIG. 5B is a graph showing the relationship between the duty ratio of the pulse signal and the output power in the circuit shown in FIG. FIG.
  • FIG. 6 is a circuit diagram showing a modification of the rectifier circuit shown in FIG.
  • FIG. 7 is a control block diagram for controlling the voltage resonance circuit shown in FIG.
  • FIG. 8 is a flowchart showing a control flow for controlling the voltage resonance circuit shown in FIG.
  • FIG. 9 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode.
  • FIG. 10 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode.
  • FIG. 11 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode.
  • FIG. 12 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode.
  • FIG. 10 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode.
  • FIG. 13 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the low power mode.
  • FIG. 14 shows the operation of each part in the DC-DC converter shown in FIG. 1 set in the low power mode.
  • FIG. 15 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the low power mode.
  • FIG. 16 shows the operation of each part in the DC-DC converter shown in FIG. 1 set in the low power mode.
  • FIG. 17 is a circuit diagram showing another modification of the rectifier circuit shown in FIG.
  • FIG. 18 is a circuit diagram showing still another modification of the rectifier circuit shown in FIG.
  • FIG. 1 is a block diagram of an isolated DC-DC converter according to an embodiment of the present invention. If the power factor correction circuit for performing the DC-DC converter and AC-DC conversion shown in FIG. 1 is connected to the input of the DC-DC converter, it can be applied to an AC-DC converter with high power factor and high efficiency. When the output voltage of the power factor correction circuit is about 370 V, the AC input voltage can be globally supported.
  • the DC-DC converter Since the output voltage of this power factor correction circuit becomes the input voltage, the DC-DC converter operates in a range where the input voltage fluctuation is relatively small, and there is no need to control a wide range of input fluctuation, which is different from a normal PWM circuit. Different operating principles can be applied.
  • this converter is a high-frequency insulation type DC-DC converter, and includes a high-frequency transformer T1, input terminals 10A and 10B connected to a DC power source, and a primary side of the high-frequency transformer T1.
  • a voltage resonance circuit 11 that outputs a high-frequency voltage, a leakage inductor L1 included in the high-frequency transformer T1, and a resonance capacitor C8, and generates a current resonance at a certain resonance frequency fr.
  • the synchronous rectifier circuit 13 disposed on the secondary side of the transformer T1 and the smoothing circuit 16 that smoothes the output current from the synchronous rectifier circuit 13 are configured. Output voltages are output from the output terminals 20A and 20B of the smoothing circuit 16. .
  • the resonance frequency fr of the current resonance circuit 14 mainly depends on the inductance of the leakage inductor L1 and the capacitance of the resonance capacitor C8.
  • the leakage inductor L1 in the current resonance circuit 14 the leakage inductor L1 included in the high-frequency transformer T1 may be used, or the inductor L1 may be separately connected to the primary side of the high-frequency transformer T1.
  • the converter shown in FIGS. 1 and 2 includes a drive buffer 17 that controls the voltage resonance circuit 11, a drive buffer 18 that controls the synchronous rectification circuit 13, a reference table 36 that stores a pulse signal corresponding to an operation mode, and a reference.
  • a switching control unit 12 comprising a CPU 30 that outputs a pulse width modulation signal PWM to the drive buffers 17 and 18 with reference to the table 36 is further provided.
  • the voltage resonance circuit 11 arranged on the primary side can be constituted by a full bridge voltage resonance circuit as shown in FIG.
  • the switching element Q1 and the switching element Q3 are connected in series, and the switching element Q2 and the switching element Q4 are connected in series.
  • a series circuit of the switching elements Q1 and Q2 and a series circuit of the switching elements Q3 and Q4 are connected in parallel to the input capacitor C7 and are connected in parallel to the DC power sources on the input sides 10A and 10B so as to form a full bridge circuit. .
  • the input capacitor C7 is connected between the positive side 10A and the negative side 10B of the power source, the drains of the switching elements Q1, Q2 are connected to the positive side 10A of the power source, and the sources of the switching elements Q3, Q4 are the negative side 10B of the power source. It is connected to the. Further, the connection between the switching element Q1 and the switching element Q3 is connected to one end of the output-side transformer T1, and the connection between the switching element Q2 and the switching element Q4 is a leakage inductor or inductor L1 included in the resonance capacitor C8 and the transformer T1. To the other end of the transformer T1.
  • Each of these switching elements Q1 to Q4 is composed of a switching element such as an FET (field effect transistor) or an IGBT (insulated gate / bipolar transistor), and is parasitic between a drain and a source (between an emitter and a collector in the case of IGBT). Capacitors C1 to C4 and parasitic diodes D1 to D4 are provided.
  • the gates of the switching elements Q1 to Q4 are connected to a drive buffer 17 that turns on and off the switching elements Q1 to Q4 at the timing of substantially zero voltage and zero supply current.
  • the voltage at the output terminal 20A is detected as an output voltage signal and input to the CPU 30 via an interface (not shown).
  • the output voltage signal is referred to the reference output voltage stored in the reference table 36 by the CPU 30, and a pulse signal having a switching period and a pulse width corresponding to the reference output voltage is selected.
  • This pulse signal is supplied from the CPU 30 to the drive buffer 17, and a switching signal is output from the drive buffer 17 to the switching elements Q1 to Q4. That is, the switching pulse output from the drive buffer 17 has its frequency and duty ratio (ratio of the on period with respect to the duty cycle) selected according to the output voltage signal, so that each of the switching elements Q1 to Q4 is substantially effective. ON and OFF at the timing of a zero voltage and a zero supply current.
  • the voltage resonance circuit 11 shown in FIGS. 1 and 2 may be a half-bridge voltage resonance circuit (not shown) as shown in FIG.
  • the switching elements Q1 and Q3 in the full-bridge voltage resonance circuit shown in FIG. 2 are removed, a series circuit of the switching elements Q2 and Q4 is connected in parallel to the capacitor C7, and the switching elements Q2 and Q4
  • the connection point is connected to one end of the output-side transformer T1 via the resonant capacitor C8 and the leakage inductor or inductor L1 of the transformer T1, and the input terminal 10B is connected to the other end of the transformer T1.
  • a synchronous rectifier circuit 13 is connected to the secondary side of the transformer T1.
  • a switching element Q6 constituting the synchronous rectifier circuit 13 is connected between the secondary high voltage terminal of the transformer T1 and the ground terminal 20B, and the transformer T1 2
  • a switching element Q5 constituting the synchronous rectifier circuit 13 is connected between the low voltage terminal on the next side and the ground terminal 20B.
  • An output terminal 20A is connected to the intermediate terminal of the transformer T1, and a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
  • the switching elements Q5 and Q6 include parasitic capacitors C5 and C6 and parasitic diodes D5 and D6 connected in parallel between the drain (emitter in the case of IGBT) and the source (collector in the case of IGBT), respectively. ing.
  • a driver buffer 18 is connected to the switching elements Q5 and Q6. That is, the drain (emitter in the case of IGBT) of the switching element Q6 is connected to the secondary high-voltage side terminal of the transformer T1, and the source (collector in the case of IGBT) of the switching element Q6 is connected to the ground-side output terminal 20B. Has been.
  • the drain (emitter in the case of IGBT) of the switching element Q5 is connected to the secondary low voltage side terminal of the transformer T1, and the source (collector in the case of IGBT) of the switching element Q5 is connected to the ground side output terminal 20B. It is connected to the.
  • the gates of the switching element Q5 and the switching element Q6 are connected to the drive buffer 18 to turn on and off the switching element Q5 and the switching element Q6 at a predetermined timing, and the output voltage signal Vout is output from the output terminals 20A and 20B.
  • the output voltage detected at the output terminal 20A is input to the CPU 30 as an output voltage signal through an electrically insulating circuit element 32, for example, a photocoupler and an interface (not shown).
  • the CPU 30 refers to the reference table 36 with the input voltage signal input from the input terminal 10A and the output voltage signal output between the output terminals 20A and 20B, and switches the switching element Q5 and the switching element according to each mode described below.
  • the reference table 36 stores the optimum frequency of the pulse signal and the duty ratio of the pulse signal from the relationship shown in FIG. 4 and FIGS. 5A and 5B.
  • a pulse signal selected from the stored table is applied to the switching elements Q5 and Q6, and the synchronous rectification circuit 13 is optimally controlled.
  • FIG. 4 is a graph showing the relationship between the frequency of the pulse signal and the output voltage Vout for making the output power Vout output from the output terminals 20A and 20B constant, and the duty ratio of the pulse signal (the ON period with respect to the duty cycle). It is a graph which shows the relationship between an input voltage and an input voltage. As apparent from FIG.
  • the primary side input voltage of the transformer T1 decreases. Accordingly, the frequency of the pulse signal is lowered to increase the ON time in the voltage resonance circuit 11 functioning as a booster circuit on the secondary side of the transformer T1, and the duty ratio is selected to be large so that the switching elements Q1, Q2, Q3 are selected. , Q4 are set to be long and the OFF period is set to be short so that the boosting ratio in the switching elements Q1, Q2, Q3, and Q4 is increased.
  • the input voltage Vin is high, the primary side input voltage of the transformer T1 is increased.
  • the frequency of the pulse signal is increased in order to shorten the ON time in the voltage resonance circuit 11 functioning as a booster circuit on the secondary side of the transformer T1, and the duty ratio is selected to be small so that the switching elements Q1, Q2, Q3 are selected.
  • Q4 are set to be short and the off period is set to be long so that the step-up ratio in the switching elements Q1, Q2, Q3, Q4 is lowered.
  • 5A and 5B show the frequency of the pulse signal that makes the output power Vout output from between the output terminals 20A and 20B variable after the input voltage reaches a constant steady state and the output power (correlation with the output voltage Vout). And a graph showing a relationship between the duty ratio of the pulse signal (the ratio of the on period to the duty cycle) and the output power (correlated to the output voltage Vout).
  • the duty ratio of the pulse signal the ratio of the on period to the duty cycle
  • the output power correlated to the output voltage Vout
  • the input voltage Vin is constant without depending on the setting of the pulse signal, so that the output voltage Vout is also kept constant. Accordingly, when the frequency of the pulse signal is varied, the output voltage signal Vout output from between the output terminals 20A and 20B is varied. Therefore, the frequency of the pulse signal is varied according to the load connected to the output terminals 20A and 20B, and the output voltage is output from the output terminals 20A and 20B.
  • the frequency of the switching pulse for switching the switching elements Q1 to Q4 of the voltage resonance circuit 11 is variably set within a frequency range lower than the resonance frequency f0 of the current resonance circuit 14, and is from the DC-DC converter. The power supplied to the load is controlled.
  • the emitted current emitted can be controlled.
  • the power (voltage) output from the DC-DC converter can be controlled to reach the target power (target voltage).
  • the switching pulse is turned on / off with a switching pulse having a switching frequency fs higher than the resonance frequency fr.
  • a secondary side resonance current is generated by the primary side resonance current supplied from the resonance current circuit 14 to the primary side of the transformer T1.
  • the switching elements Q5 and Q6 of the synchronous rectifier circuit 13 are turned on / off by a switching pulse in synchronization with the secondary side resonance current. Therefore, the switching pulse for turning on / off the switching elements Q5 and Q6 has an on-time corresponding to a half cycle (half cycle) of the resonance current.
  • the switching elements Q5 and Q6 are driven by switching pulses so as to be switched in synchronization with the switching elements Q1 and Q4 and the switching elements Q2 and Q3, respectively.
  • the synchronous rectifier circuit 13 is not limited to the synchronous rectifier circuit 13 using the intermediate terminal shown in FIG. 1, but may be configured by a bridge synchronous rectifier circuit 13 as shown in FIG. As shown in FIG. 5, in the bridge synchronous rectifier circuit 13, the series circuit of the switching elements Q5 and Q7 and the series circuit of the switching elements Q6 and Q8 are connected in parallel to the capacitor C9, and the connection part of the switching elements Q5 and Q7 Is connected to the secondary high voltage terminal of the transformer T1, and the connection of the switching elements Q6 and Q8 is connected to the secondary low voltage terminal of the transformer T1.
  • a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
  • the switching elements Q5, Q6, Q7, Q8 are parasitic capacitors C5, C6, C7, C8 and a parasitic diode connected in parallel between the drain (emitter in the case of IGBT) and the source (collector in the case of IGBT), respectively. D5, D6, D7, and D8 are included.
  • a driver buffer 18 is connected to the switching elements Q5, Q6, Q7, and Q8. More specifically, the drains (collector in the case of IGBT) of switching elements Q5 and Q6 are connected to output terminal 20A, and the sources (emitters in the case of IGBT) of switching elements Q6 and Q8 are connected to ground side output terminal 20B. It is connected.
  • the source of the switching element Q5 (emitter in the case of IGBT) and the drain of the switching element Q7 (collector in the case of IGBT) are connected to the secondary high-voltage side terminal of the transformer T1
  • the source of the switching element Q6 in the case of IGBT
  • the drain in the case of IGBT
  • the drain are connected to the secondary low-voltage side terminal of the transformer T1.
  • the gates of the switching elements Q5, Q6, Q7 and Q8 are connected to the drive buffer 18 to turn on and off the switching elements Q5, Q6, Q7 and Q8 at a predetermined timing, and the output voltage signal Vout is output to the output terminals 20A, 20A, 20B.
  • the output voltage detected at the output terminal 20A is input to the CPU 30 as an output voltage signal through an electrically insulating circuit element 32, for example, a photocoupler and an interface (not shown).
  • the switching elements Q5, Q6, Q7, and Q8 are turned on / off according to each mode by referring to the reference table 36 with the output voltage signal output from between the output terminals 20A, 20B.
  • the duty ratio of the pulse signal (ratio of the on period to the duty cycle) and the frequency are set and the switching elements Q5, Q6, Q7 and Q8 are turned on at the timing of substantially zero current and zero voltage under the optimum conditions.
  • the switching elements Q5 and Q8 and the switching elements Q6 and Q7 are alternately turned on by the switching pulse in synchronization with the secondary side resonance current flowing on the secondary side of the transformer T1.
  • the switching pulses for turning on / off the switching elements Q5, Q6, Q7, and Q8 have an on-time that matches the half cycle (half cycle) of the resonance current.
  • Switching elements Q5 and Q8 and switching elements Q6 and Q7 are driven by switching pulses so as to be switched in synchronization with switching elements Q1 and Q4 and switching elements Q2 and Q3, respectively.
  • the target voltage Vref is input to the CPU 30 by an input device (not shown) as shown in FIG. 7 and output from the rectifier circuit 13 as shown in FIG.
  • the voltage Vout is input through the electrically insulating circuit element 32 as shown in step S2.
  • the target voltage Vref and the output voltage Vout are compared by the CPU 30 as shown in step S3, the reference table 36 is referred to by the difference voltage, and the primary of the transformer T1 is shown in the frequency table in the reference table 36 as shown in step S4.
  • the switching frequencies of the switching elements Q1 to Q4 on the side and the switching elements Q5 to Q6 on the secondary side of the transformer T1 are determined.
  • the CPU 30 determines the ON period (time) of the pulse width modulation signal PWM. Based on the determined frequency and on-period, the CPU 30 operates as a pulse generator as shown in step S7, and a pulse signal (pulse width modulation signal) PWM is supplied to the driver buffer 17 and stored therein. Based on the determined frequency and on-period, the CPU 30 operates as a pulse generator as shown in step S7, and the pulse signal (pulse width modulation signal) PWM is supplied to the driver buffer 18 via the electrical insulation circuit element 34. Is given and stored.
  • the driver buffers 17 and 18 switch the switching elements Q1 to Q4 by applying the first to fourth gate pulses to the primary side switching elements Q1 to Q4 as shown in steps S8 to S11. Similarly, the driver buffers 17 and 18 switch the switching elements Q5 to Q6 by applying fifth and sixth gate pulses to the secondary side switching elements Q5 and Q6 as shown in steps S12 and S13. As a result, as will be described later, a target voltage is output from the smoothing circuit 16.
  • the switching pulse for turning on / off the switching elements Q5, Q6 or the switching elements Q1-Q4 is selected so that the on-time is matched with the half cycle (half cycle) of the resonance current.
  • the target output voltage is first set as shown in FIG. (Step S21)
  • a switching frequency fs serving as a reference corresponding to the target output voltage is set in advance.
  • the primary side switching elements Q1 to Q5 are switched at this switching frequency.
  • the output voltage Vout from the rectifier circuit 13 is detected and compared with the target voltage in step S22.
  • switching is continued at the switching frequency fs.
  • step S24 it is determined whether the output voltage Vout is larger than the target voltage.
  • step S25 When the output voltage Vout is higher than the target voltage, a frequency (fs + ⁇ f ⁇ fr) higher than the set frequency fs is set as shown in step S25, and step S22 is executed again.
  • the frequency (fs + ⁇ f) is set high, the period during which the excitation current flows is reduced, the excitation energy of the reactance L1 is reduced, the primary terminal voltage of the transformer T1 is reduced, and the boosting effect is reduced. As a result, the output voltage Vout is reduced.
  • a frequency (fs ⁇ f ⁇ fr) lower than the set frequency fs is set as shown in step S26, and step S22 is executed again.
  • the secondary side current is rectified (synchronous rectification) in synchronization with the primary side switching, and the secondary side switching elements Q5, Q6 are only in the period when the resonance current is flowing in the resonance circuit 14. Is turned on.
  • the switching frequency fs is determined such that the ON period of the primary side switching elements Q1 to Q4 is larger than the period Tr in which the resonance current flows (Ts> 2Tr). Therefore, in the rated input voltage mode, the excitation energy of the inductance of the transformer T1 is actively used, and the terminal voltage on the primary side of the transformer T1 is boosted.
  • the switching elements Q1 to Q6 are switched by setting the frequency (fs + ⁇ f) higher than that in the rated input voltage mode (fs).
  • the switching frequency is set high until it becomes equal to the period during which the resonance current flows. Therefore, in the resonance circuit 14, the period during which the excitation current flows through the transformer T1 is reduced and the excitation energy is reduced. As a result, the boost of the primary terminal voltage of the transformer T1 is reduced, and the output voltage can be controlled. It becomes possible.
  • the cycle (Ts) is variable, and this variable range can set a maximum cycle longer than 50% with respect to the minimum cycle.
  • the maximum period (Tsmax) with respect to the minimum period (Tsmin) is set too large, the ratio of the current resonance time during which the resonance circuit 14 supplies the output current to the transformer T1 is decreased. Therefore, the resonance current increases and the communication loss increases, and as a result, improvement in efficiency cannot be expected.
  • the maximum period (Tsmax) with respect to the minimum period (Tsmin) is set to a range of 30% or less, and it is desirable to perform frequency control within this range.
  • the excitation energy of the transformer T1 is charged in the resonance capacitor C8, and the voltage appearing at the primary side terminal of the transformer T1 when the charged energy is discharged.
  • the voltage can be boosted by the transformer T1, and the output can be made variable by using discharge energy. Accordingly, the ripple voltage or the fluctuation of the input voltage appearing at the input terminals 10A and 10B is absorbed by the current resonance circuit. As a result, fluctuations in output voltage can be improved.
  • the output voltage of the power factor correction circuit is basically constant, but slightly fluctuates due to ripple voltage or input fluctuation.
  • the DC-DC converter shown in FIGS. 1 and 2 operates with high efficiency because the primary and secondary switching elements Q1 to Q6 are soft-switched in the entire operation region.
  • the size and weight can be reduced, and not only the cost is reduced, but also the reliability against component failure is improved.
  • the drain voltages of the switching elements Q1 and Q4 are gently increased from time t2 to time t3 as shown in FIG. 9B.
  • the drain voltages of the switching elements Q1 and Q4 are zero at the time point t2, the switching elements Q1 and Q4 are switched at zero voltage.
  • the exciting current flowing from the exciting inductance L1 of the transformer T1 corresponds to a reactive current, and the current supplied from the input side (Vin) at time t2 is zero. From this viewpoint, the switching elements Q1 and Q4 are At t2, switching is performed with zero supply current.
  • the other switching elements Q2 and Q3 constituting the bridge circuit are in the OFF state from time t2 to time t3 as shown in FIG. 9D, and the transformers are turned off as the switching elements Q1 and Q4 are turned off.
  • the exciting current flows from the exciting inductance L1 of T1
  • the capacitors C2 and C3 between the drain and source of the switching elements Q2 and Q3 are discharged as shown in FIG. Therefore, the drain voltages of the switching elements Q2 and Q3 are gently lowered from the time point t2 to the time point t3 as shown in FIG.
  • the drain voltages of the switching elements Q2 and Q3 are similarly zero, so that the switching elements Q2 and Q3 are switched at zero voltage.
  • a secondary side voltage boosted with a change in the primary side excitation voltage VT1 appears on the secondary side of the transformer T1.
  • the switching elements Q5 and Q6 are turned off between time t2 and time t3 as shown in FIGS. 11A and 11D, the switching element Q6 is based on the intermediate terminal of the transformer T1.
  • a drain voltage that rises gently as shown in FIG. 11B is applied to the drain of FIG. 11, and a drain voltage that gently decreases as shown in FIG. 11E is applied to the drain of the switching element Q5. Applied.
  • the exciting current iT1 is supplied to the primary side of the transformer T1.
  • the current flowing through the drain between time t3 and time t6 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q2 and Q3 being turned on. Yes.
  • the period of the resonance current that flows between time t3 and time t6 is set to a half cycle of the ON period of switching elements Q2 and Q3. Further, since the exciting current is used to charge the resonance capacitor C8 between the time point t6 and the time point t9, the voltage of the transformer T1 is gradually decreased.
  • the switching frequency (fs ⁇ fr) is set so that the ON period of the primary side switching elements Q1 to Q4 is larger than the period during which the resonance current flows. Is set. Therefore, in the rated input voltage mode, the excitation energy of the excitation inductor of the transformer T1 is positively used, and the terminal voltage on the primary side of the transformer T1 is boosted.
  • the exciting current iT1 is supplied to the primary side of the transformer T1
  • a boosted voltage is generated on the secondary side of the transformer T1
  • the drain of the switching element Q6 is connected to the drain of the switching element Q6 with reference to the intermediate terminal of the transformer T1.
  • a substantially constant drain voltage is applied.
  • an ON signal is applied to the gate of the applied switching element Q5 to turn on the switching element Q5. Therefore, as shown in FIG. 11 (e).
  • the drain voltage of the switching element Q5 is reduced to substantially zero and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with this resonance current as shown in FIG.
  • a drain current (diode current) flows through the switching element Q5 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
  • the gate signal applied to the gate of the applied switching element Q5 is turned off, and the excitation current charges the resonance capacitor C8 between time t6 and time t9.
  • the voltage of the transformer T1 is decreased.
  • the drain voltage of the switching element Q5 is slightly increased from the time point t6 to the time point t9.
  • the voltage charged in the resonance capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q1 and Q4 are turned on at the timing of the time point t10. That is, since the voltage of the resonance capacitor C8 is generated in the addition direction with respect to the input voltage, it is applied to the transformer T1 with the input voltage boosted.
  • the switching frequency (fs ⁇ fr) is set so that the ON period of the primary side switching elements Q1 to Q4 is larger than the period during which the resonance current flows. Is set. Therefore, in the rated input voltage mode, the excitation energy of the excitation inductor of the transformer T1 is positively used, and the terminal voltage on the primary side of the transformer T1 is boosted.
  • a boosted voltage is generated on the secondary side of the transformer T1
  • the drain of the switching element Q5 is connected to the drain of the switching element Q5 with reference to the intermediate terminal of the transformer T1.
  • a substantially constant drain voltage is applied.
  • an ON signal is applied to the gate of the applied switching element Q6 to turn on the switching element Q6.
  • the drain voltage of the switching element Q6 is reduced to substantially zero, and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with this resonance current as shown in FIG.
  • a drain current (diode current) flows through the switching element Q6 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
  • the gate signal applied to the gate of the applied switching element Q6 is turned off, and the excitation current charges the resonance capacitor C8 between time t13 and time t16.
  • the voltage of the transformer T1 is decreased.
  • the drain voltage of the switching element Q6 is slightly increased from the time point t13 to the time point t16.
  • one cycle of operation is completed from time t2 to time t16.
  • FIG. 13 (a) to FIG. 16 (g) show the operation of each part in the low power mode with constant input power in the DC-DC converter shown in FIG. The operation of the DC-DC converter shown in FIG. 1 will be described with reference to FIGS. 13 (a) to 16 (g).
  • the drain voltages of the switching elements Q1 and Q4 are gently increased from the time point t2 to the time point t3 as shown in FIG. 13B.
  • the switching elements Q1 and Q4 are switched at zero voltage.
  • the exciting current flowing from the exciting inductance L1 of the transformer T1 corresponds to a reactive current, and the current supplied from the input side (Vin) at time t2 is zero. From this viewpoint, the switching elements Q1 and Q4 are At t2, switching is performed with zero supply current.
  • the other switching elements Q2 and Q3 constituting the bridge circuit are in the OFF state from the time point t2 to the time point t3 as shown in FIG. 13D, and the transformers are turned off as the switching elements Q1 and Q4 are turned off.
  • the exciting current flows from the exciting inductance L1 of T1
  • the capacitors C2 and C3 between the drains and sources of the switching elements Q2 and Q3 are discharged as shown in FIG. Therefore, the drain voltages of the switching elements Q2 and Q3 are gently lowered from the time point t2 to the time point t3 as shown in FIG.
  • the drain voltages of the switching elements Q2 and Q3 are similarly zero, so that the switching elements Q2 and Q3 are switched at zero voltage.
  • a secondary side voltage boosted with a change in the primary side excitation voltage VT1 appears on the secondary side of the transformer T1.
  • the switching elements Q5 and Q6 are turned off between the time point t2 and the time point t3 as shown in FIGS. 15A and 15D, the switching element Q6 is based on the intermediate terminal of the transformer T1.
  • a drain voltage that rises gently as shown in FIG. 15B is applied to the drain of FIG. 15, and a drain voltage that gently decreases as shown in FIG. 15E is applied to the drain of the switching element Q5. Applied.
  • the period of the resonance current that flows between the time point t3 and the time point after the time point t5 is set to a period longer than the half cycle of the ON period of the switching elements Q2 and Q3.
  • the exciting current is used to charge the resonance capacitor C8 from the time point after the time point t5 to the time point t6, the voltage of the transformer T1 is gradually decreased.
  • the voltage charged in the resonant capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q1 and Q4 are turned on at the timing of the time point t7. That is, since the voltage of the resonance capacitor C8 is generated in the addition direction with respect to the input voltage, it is applied to the transformer T1 with the input voltage boosted.
  • the exciting current iT1 is supplied to the primary side of the transformer T1.
  • the current flowing through the drain between time t7 and time t9 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q1 and Q4 being turned on.
  • the period of the resonance current flowing between the time point t7 and the time point after the time point t9 is set to a period longer than the half cycle of the ON period of the switching elements Q1 and Q4.
  • the exciting current is used to charge the resonant capacitor C8 from the time point after the time point t9 to the time point t10, the voltage of the transformer T1 is gradually reduced.
  • the frequency (fs + ⁇ f) is set higher than the rated input voltage mode fs, and the switching elements Q1 to Q6 are switched.
  • the switching frequency (fs ⁇ fr) is set high until it becomes equal to the period during which the resonance current flows. Therefore, in the resonance circuit 14, the period during which the exciting current flows through the leakage inductor L1 is reduced and the excitation energy is reduced. As a result, the boosting of the primary side terminal voltage of the transformer T1 is reduced, and the output voltage is controlled. Is possible.
  • a boosted voltage is generated on the secondary side of the transformer T1
  • the drain of the switching element Q5 is connected to the drain of the switching element Q5 with reference to the intermediate terminal of the transformer T1.
  • a substantially constant drain voltage is applied.
  • an ON signal is applied to the gate of the applied switching element Q6 to turn on the switching element Q6.
  • the drain voltage of the switching element Q6 is reduced to substantially zero and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with the resonance current as shown in FIG.
  • a drain current (diode current) flows through the switching element Q6 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
  • the gate signal applied to the gate of the applied switching element Q6 is turned off, and the excitation current charges the resonance capacitor C8 between time t10 and time t11.
  • the voltage of the transformer T1 is decreased.
  • the drain voltage of the switching element Q6 is slightly increased from the time point t10 to the time point t11.
  • the voltage charged in the resonant capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q2 and Q3 are turned on at the time t11. That is, since it is in the addition direction with respect to the input voltage, it can be applied to the transformer T1 in a state where the input voltage is boosted.
  • one cycle of operation is completed from time t2 to time t11.
  • the switching elements used on the input / output sides (primary and secondary sides) of the isolation transformer are all controlled by soft switching, a highly efficient DC -It can be a DC converter.
  • the leakage inductance of the transformer is used as the resonance reactor. Therefore, although it is a high-efficiency DC-DC converter, it is possible to realize low cost without requiring individual components.
  • leakage inductance has a large individual difference and variation in the value of the resonance frequency, but since switching control is performed by software, individual adjustment values can be recorded, and ideal resonance and control can be realized. . Further, since the switching element is controlled by lowering the switching frequency, the loss in switching or the core loss of the transformer can be reduced, and higher efficiency can be realized.
  • 1 employs a center tap rectification method, but a bridge rectification circuit method may be employed as will be described later. 1 uses the rectification action of the diodes D5 and D6 of the switching elements Q5 and Q6, the switching elements Q5 and Q6 may be replaced with the rectification diodes D5 and D6.
  • the synchronous rectifier circuit 13 may be configured as the intermediate tap rectifier circuit 13 with diodes D5 and D6 as shown in FIG. 17 instead of the switching elements Q5 and Q6 shown in FIG.
  • the bridge rectifier circuit 13 may be constituted by diodes D5 to D8 as shown in FIG.
  • the rectifier circuit 13 constituted by diodes D5 and D6 instead of the switching elements Q5 and Q6 shown in FIG. 17
  • the rectifier circuit 13 constituted by diodes D5 to D8 instead of the switching elements Q5 to Q8 shown in FIG.
  • the circuit Since D5, D6 or the diodes D5 to D8 are automatically turned off as the voltage decreases, the circuit operates in the same manner as the circuit employing the switching elements Q5, Q6 or the switching elements Q5 to Q8. However, since the power consumed in the synchronous rectifier circuit 13 is generated as compared with the case where the switching elements Q5, Q6 or the switching elements Q5 to Q8 are forcibly turned off, the synchronous rectifier circuit 13 includes the switching elements Q5, Q6 or It is preferable to configure with switching elements Q5 to Q8.
  • a rectifier diode D6 constituting the synchronous rectifier circuit 13 is connected between the secondary high voltage terminal of the transformer T1 and the ground terminal 20B, and the secondary side of the transformer T1
  • a rectifier diode D5 constituting the synchronous rectifier circuit 13 is connected between the low voltage terminal and the ground terminal 20B.
  • An output terminal 20A is connected to the intermediate terminal of the transformer T1
  • a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
  • the cathode of the rectifier diode D6 is connected to the secondary high-voltage side terminal of the transformer T1, and the anode of the rectifier diode D6 is connected to the ground-side output terminal 20B.
  • the cathode of the rectifier diode D5 is connected to the secondary low-voltage side terminal of the transformer T1, and the anode of the rectifier diode D5 is connected to the ground-side output terminal 20B.
  • a series circuit of rectifier diodes D5 and D7 and a series circuit of rectifier diodes D6 and D8 are connected in parallel to the capacitor C9, and the rectifier diodes D5 and D7 are connected.
  • the connecting portion is connected to the secondary high voltage terminal of the transformer T1
  • the connecting portion of the rectifier diodes D6 and D8 is connected to the secondary low voltage terminal of the transformer T1.
  • a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
  • a highly efficient DC-DC converter is provided.

Abstract

A DC-DC converter is provided with an insulating high-frequency transformer, and a serial resonant circuit composed of an inductor and a capacitor is connected between a voltage resonant circuit, which is composed of a switching circuit, and the terminal on the primary side of a first transformer. On the secondary side of the insulating high-frequency transformer, a rectifying circuit and a smoothing circuit are connected. The voltage resonance circuit is switched by means of first switching signals, and the frequency of the first switching signals is set higher than the reference frequency when the output voltage is higher than a target voltage, and is set lower than the reference frequency when the output voltage is lower than the target voltage.

Description

ＤＣ－ＤＣコンバータDC-DC converter
　この発明は、ＤＣ－ＤＣコンバータに係り、特に、力率改善回路の使用を前提とした絶縁型ＤＣ－ＤＣコンバータに関する。 The present invention relates to a DC-DC converter, and more particularly to an isolated DC-DC converter premised on the use of a power factor correction circuit.
　分散型直流電源、例えば、家庭用燃料電池、太陽光発電或いは風力発電システムから電力を中電力容量（０．３ｋW～１０ｋW）の電力に変換する分散型電源システムは、インバータなどの電力変換装置を備え、この電力変換装置では、入力（１次側）と系統（２次側）との絶縁が望まれている。このような電力変換装置に、高周波絶縁型のコンバータが使用されても、非絶縁型のコンバータに比較して、効率が悪化する問題がある。 A distributed power supply system that converts electric power from a distributed direct current power source, for example, a household fuel cell, a solar power generation system or a wind power generation system into a medium power capacity (0.3 kW to 10 kW) is a power conversion device such as an inverter. In this power converter, insulation between the input (primary side) and the system (secondary side) is desired. Even if a high-frequency insulation type converter is used in such a power conversion device, there is a problem that efficiency is deteriorated as compared with a non-insulation type converter.
　また、燃料電池などの電源では、定格未満の出力で運転する頻度が必然的に多くなることから、上記のような定格出力時における効率向上はもとより、定格出力の５０％以下の省電力の小出力運転時の効率を向上することが重要な課題となっている。このような背景から、特許文献１において、高効率のＤＣ－ＤＣコンバータが提案されている。 In addition, since a power source such as a fuel cell inevitably increases the frequency of operation at an output less than the rated value, not only is the efficiency improved at the rated output as described above, but the power saving is less than 50% of the rated output. Improving efficiency during output operation is an important issue. Against this background, Patent Document 1 proposes a highly efficient DC-DC converter.
　また、特許文献２には、スイッチング素子（ＦＥＴ）をゼロ電圧又はゼロ電流でスイッチング（ＺＶＳ或いはＺＣＳ）してスイッチング損失を低減することができる共振型スイッチング電源が開示されている。同様に、特許文献３にもスイッチング電源のスイッチをゼロ電圧・ゼロ電流でスイッチングするＤＣ―ＤＣコンバータが開示されている。また、この特許文献３には、スイッチング電源回路とトランスの間に電流共振回路が設けられ、スイッチング電源回路のスイッチが共振周波数付近ｆｒで動作される旨が記述されている。 Patent Document 2 discloses a resonant switching power supply that can reduce switching loss by switching a switching element (FET) with zero voltage or zero current (ZVS or ZCS). Similarly, Patent Document 3 discloses a DC-DC converter that switches a switch of a switching power supply at zero voltage and zero current. Patent Document 3 describes that a current resonance circuit is provided between the switching power supply circuit and the transformer, and the switch of the switching power supply circuit is operated at a frequency near the resonance frequency fr.
　更に、特許文献４及び５には、トランスの一次側にスイッチング電源を設けるのみならず、その２次側に設けた昇圧回路がスイッチング素子で構成される旨が記述されている。 Furthermore, Patent Documents 4 and 5 describe that not only the switching power supply is provided on the primary side of the transformer, but also the booster circuit provided on the secondary side is formed of switching elements.
特許第３９３４６５４号公報Japanese Patent No. 3934654 特開平０７－２７４４９８号公報Japanese Patent Application Laid-Open No. 07-274498 特開平０７－２２２４４４号公報Japanese Patent Application Laid-Open No. 07-222444 特開２００５－３１８７５７号公報JP 2005-318757 A 特開平０６－３１１７４３号公報Japanese Patent Laid-Open No. 06-311743
　特許文献１～５に開示されたＤＣ－ＤＣコンバータは、高効率を実現することができる。しかし、小エネルギーの観点から、よりスイッチング・ロスが減少され、より高効率でＤＣ－ＤＣ変換を実現することができる絶縁型ＤＣ－ＤＣコンバータの更なる効率向上が要請されている。特に、高周波トランスの一次側に共振電流回路を設けて、一次側電圧を昇圧可能なＤＣ－ＤＣコンバータにおいて、出力側負荷変動に応じて効率的に目標電力を供給することができることが望まれている。特に、小電力から定常電力に亘る負荷変動が生じても安定して損出の少ないＤＣ－ＤＣコンバータ回路の出現が望まれている。 The DC-DC converters disclosed in Patent Documents 1 to 5 can achieve high efficiency. However, from the viewpoint of small energy, there is a demand for further improvement in the efficiency of an isolated DC-DC converter that can realize a DC-DC conversion with a higher switching efficiency and a higher efficiency. In particular, in a DC-DC converter in which a resonance current circuit is provided on the primary side of a high-frequency transformer and the primary side voltage can be boosted, it is desired that target power can be efficiently supplied according to output side load fluctuations. Yes. In particular, there is a demand for the appearance of a DC-DC converter circuit that is stable and has little loss even when a load change from small power to steady power occurs.
　このように絶縁型ＤＣ－ＤＣコンバータにおいては、全動作範囲において、効率向上することが重要され、安全性に対するフェールセーフ機能及びネットワーク電源としての通信機能が重要性を増している。更に、絶縁型ＤＣ－ＤＣコンバータでは、ＭＰＵ等の使用を前提としたローコストのデジタル電源の実現が要請されている。 As described above, in an isolated DC-DC converter, it is important to improve efficiency in the entire operation range, and a fail-safe function for safety and a communication function as a network power source are becoming more important. Furthermore, in an isolated DC-DC converter, it is required to realize a low-cost digital power source on the premise of using an MPU or the like.
　本発明は、上記問題点を解決するためになされているものであり、その目的は、高効率のＤＣ－ＤＣコンバータを提供することになる。特に、ＤＣ－ＤＣコンバータに組み込まれる高周波トランスが有するインダクタで生ずる励磁エネルギーを積極的に利用して高効率での変換を可能とするＤＣ－ＤＣコンバータを提供することにある。 The present invention has been made to solve the above problems, and an object thereof is to provide a highly efficient DC-DC converter. In particular, it is an object of the present invention to provide a DC-DC converter that enables high-efficiency conversion by actively utilizing excitation energy generated by an inductor included in a high-frequency transformer incorporated in the DC-DC converter.
　この発明によれば、
　交互にスイッチングされるように接続された第１のスイッチング素子から構成される第１のスイッチング回路を含み、出力電圧が変動する低電圧直流電源から直流電力が入力され、この直流電力をＤＣ－ＡＣ変換して出力する電圧共振回路と、
　１次側及び２次側を有する絶縁型高周波トランスと、
　前記電圧共振回路と前記第１のトランスの１次側の第１端子との間に接続されるインダクタンス及びこのインダクタンスに直列に接続されるキャパシタから成る直列共振回路であって、この直列回路を介して前記電圧共振回路からの出力電圧が前記絶縁型高周波トランスの一次側に印加されている直列回路と、
　前記絶縁型高周波トランスの２次側に接続されている整流回路と、
　この整流回路に接続されている平滑回路と、
　導通電流が零並びに印加電圧が略零のタイミングで前記第１のスイッチング素子をターンオン及びターンオフする第１のスイッチング信号で前記電圧共振回路における電圧共振を維持する第１のドライバ回路と、
　前記整流回路から出力された出力電圧に依存して前記第１のスイッチング信号の周波数を設定する制御回路であって、目標電圧に比べて前記出力電圧が大きい際に基準周波数よりも高い周波数を設定し、目標電圧に比べて前記出力電圧が小さい際に基準周波数よりも低い周波数を設定する制御回路と、
　を具備することを特徴とするＤＣ―ＤＣコンバータが提供される。 According to this invention,
DC power is input from a low voltage DC power source including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A voltage resonant circuit that converts and outputs, and
An insulated high-frequency transformer having a primary side and a secondary side;
A series resonance circuit comprising an inductance connected between the voltage resonance circuit and a first terminal on the primary side of the first transformer, and a capacitor connected in series with the inductance, via the series circuit A series circuit in which an output voltage from the voltage resonance circuit is applied to a primary side of the insulating high-frequency transformer;
A rectifier circuit connected to the secondary side of the insulated high-frequency transformer;
A smoothing circuit connected to the rectifier circuit;
A first driver circuit that maintains voltage resonance in the voltage resonance circuit with a first switching signal that turns on and off the first switching element at a timing when the conduction current is zero and the applied voltage is substantially zero;
A control circuit that sets a frequency of the first switching signal depending on an output voltage output from the rectifier circuit, and sets a frequency higher than a reference frequency when the output voltage is larger than a target voltage. A control circuit that sets a frequency lower than a reference frequency when the output voltage is smaller than a target voltage;
A DC-DC converter is provided.
　この発明のＤＣ－ＤＣコンバータによれば、スイッチング・ロスの無い高効率の変換を実現することが出来る。 According to the DC-DC converter of the present invention, high-efficiency conversion without switching loss can be realized.
　この発明のＤＣ－ＤＣコンバータによれば、全動作領域領において、１次及び２次のスイッチング回路がソフトスイッチングを行っているため高効率となる。また、この発明のＤＣ－ＤＣコンバータによれば、回路部品点数が少ないため、小型軽量化が図れ、コストダウンだけでなく、部品故障に対する信頼性が向上される。 According to the DC-DC converter of the present invention, since the primary and secondary switching circuits perform soft switching in the entire operation region, the efficiency becomes high. Further, according to the DC-DC converter of the present invention, since the number of circuit components is small, the size and weight can be reduced, and not only the cost is reduced, but also the reliability against the component failure is improved.
　全動作領域において、１次及び２次のスイッチング回路がソフトスイッチングを行っているため高効率となる。更に回路部品点数が少ないため、小型軽量化が図れ、コストダウンだけでなく、部品故障に対する信頼性が向上する。 ∙ High efficiency is achieved because the primary and secondary switching circuits perform soft switching in the entire operating range. Furthermore, since the number of circuit components is small, the size and weight can be reduced, and not only the cost is reduced, but also the reliability against component failure is improved.
この発明によれば、高効率のＤＣ－ＤＣコンバータが提供される。 According to the present invention, a highly efficient DC-DC converter is provided.
図１は、本発明の実施の形態に係るＤＣ－ＤＣコンバータを概略的に示すブロック図である。FIG. 1 is a block diagram schematically showing a DC-DC converter according to an embodiment of the present invention. 図２は、図１に示すＤＣ－ＤＣコンバータを詳細に示す回路図である。FIG. 2 is a circuit diagram showing in detail the DC-DC converter shown in FIG. 図３は、図２に示す電圧共振回路の変形例に係るハーフブリッジ回路を示す回路図である。FIG. 3 is a circuit diagram showing a half-bridge circuit according to a modification of the voltage resonance circuit shown in FIG. 図４は、図１２に示される回路において、出力される出力電力を一定にする為のパルス信号の周波数と入力電圧Ｖinとの関係を示すグラフである。FIG. 4 is a graph showing the relationship between the frequency of the pulse signal and the input voltage Vin for making the output power output constant in the circuit shown in FIG. 図５Ａは、図１に示される回路において、入力電圧が一定の定常状態に達した後に出力される出力電力を可変とするパルス信号の周波数と出力電力との関係を示すグラフである。FIG. 5A is a graph showing the relationship between the output power and the frequency of a pulse signal that varies the output power output after the input voltage reaches a certain steady state in the circuit shown in FIG. 図５Ｂは、図１に示される回路において、パルス信号のデューティー比と出力電力との関係を示すグラフである。FIG. 5B is a graph showing the relationship between the duty ratio of the pulse signal and the output power in the circuit shown in FIG. 図６は、図２に示す整流回路の変形例を示す回路図である。FIG. 6 is a circuit diagram showing a modification of the rectifier circuit shown in FIG. 図７は、図２に示す電圧共振回路を制御する制御ブロック図である。FIG. 7 is a control block diagram for controlling the voltage resonance circuit shown in FIG. 図８は、図２に示す電圧共振回路を制御する制御フローを示すフローチャートである。FIG. 8 is a flowchart showing a control flow for controlling the voltage resonance circuit shown in FIG. 図９は、定格入力電圧モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 9 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode. 図１０は、定格入力電圧モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 10 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode. 図１１は、定格入力電圧モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 11 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode. 図１２は、定格入力電圧モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 12 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the rated input voltage mode. 図１３は、小電力モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 13 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the low power mode. 図１４は、小電力モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 14 shows the operation of each part in the DC-DC converter shown in FIG. 1 set in the low power mode. 図１５は、小電力モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 15 shows the operation of each part in the DC-DC converter shown in FIG. 1 set to the low power mode. 図１６は、小電力モードに設定されている図１に示されるＤＣ－ＤＣコンバータにおける各部の動作を示している。FIG. 16 shows the operation of each part in the DC-DC converter shown in FIG. 1 set in the low power mode. 図１７は、図２に示す整流回路の他の変形例を示す回路図である。FIG. 17 is a circuit diagram showing another modification of the rectifier circuit shown in FIG. 図１８は、図２に示す整流回路の更に他の変形例を示す回路図である。FIG. 18 is a circuit diagram showing still another modification of the rectifier circuit shown in FIG.
　以下、必要に応じて図面を参照しながら、この発明の一実施の形態に係る絶縁型ＤＣ－ＤＣコンバータを説明する。 Hereinafter, an insulated DC-DC converter according to an embodiment of the present invention will be described with reference to the drawings as necessary.
　図１は、この発明の実施の形態に係る絶縁型ＤＣ－ＤＣコンバータのブロック図を示している。この図１に示されるＤＣ－ＤＣコンバータとＡＣ－ＤＣ変換と行う力率改善回路をＤＣ－ＤＣコンバータの入力に接続すると高力率、高効率のＡＣ－ＤＣコンバータに適用することが出来る。この力率改善回路の出力電圧を３７０Ｖ程度とするとＡＣ入力電圧はグローバル対応とすることが出来る。 FIG. 1 is a block diagram of an isolated DC-DC converter according to an embodiment of the present invention. If the power factor correction circuit for performing the DC-DC converter and AC-DC conversion shown in FIG. 1 is connected to the input of the DC-DC converter, it can be applied to an AC-DC converter with high power factor and high efficiency. When the output voltage of the power factor correction circuit is about 370 V, the AC input voltage can be globally supported.
この力率改善回路の出力電圧はほぼ一定であるが、ＡＣ変動及び負荷変動の影響を受け、わずかに変動し、リップル電圧が発生する。 Although the output voltage of the power factor correction circuit is almost constant, it is slightly affected by the influence of AC fluctuation and load fluctuation, and a ripple voltage is generated.
　ＤＣ－ＤＣコンバータはこの力率改善回路の出力電圧が入力電圧となるので比較的入力電圧変動の小さい範囲での動作となり、広範囲の入力変動を制御する必要が無く、通常のＰＷＭ回路とは異なった動作原理が適用できる。 Since the output voltage of this power factor correction circuit becomes the input voltage, the DC-DC converter operates in a range where the input voltage fluctuation is relatively small, and there is no need to control a wide range of input fluctuation, which is different from a normal PWM circuit. Different operating principles can be applied.
　このコンバータは、図１及び図２に示されるように、高周波絶縁型のＤＣ－ＤＣコンバータであって、高周波トランスＴ１、直流電源に接続された入力端子１０Ａ、１０Ｂと高周波トランスＴ１の１次側との間に配置され、高周波の電圧を出力する電圧共振回路１１、高周波トランスＴ１が有するリーケージインダクタＬ１及び共振キャパシタＣ８で構成され、ある共振周波数ｆｒで電流共振を生じさせる電流共振回路１４、高周波トランスＴ１の二次側に配置された同期整流回路１３、同期整流回路１３からの出力電流を平滑化する平滑回路１６から構成され、平滑回路１６の出力端子２０Ａ、２０Ｂから出力電圧が出力される。ここで、電流共振回路１４の共振周波数ｆｒは、主にリーケージインダクタＬ１のインダクタ及び共振キャパシタＣ８のキャパシタンスに依存している。ここで、電流共振回路１４におけるリーケージインダクタＬ１は、高周波トランスＴ１が有するリーケージインダクタＬ１が利用されても良く、或いは、別途高周波トランスＴ１の一次側にインダクタＬ１が接続されても良い。 As shown in FIGS. 1 and 2, this converter is a high-frequency insulation type DC-DC converter, and includes a high-frequency transformer T1, input terminals 10A and 10B connected to a DC power source, and a primary side of the high-frequency transformer T1. A voltage resonance circuit 11 that outputs a high-frequency voltage, a leakage inductor L1 included in the high-frequency transformer T1, and a resonance capacitor C8, and generates a current resonance at a certain resonance frequency fr. The synchronous rectifier circuit 13 disposed on the secondary side of the transformer T1 and the smoothing circuit 16 that smoothes the output current from the synchronous rectifier circuit 13 are configured. Output voltages are output from the output terminals 20A and 20B of the smoothing circuit 16. . Here, the resonance frequency fr of the current resonance circuit 14 mainly depends on the inductance of the leakage inductor L1 and the capacitance of the resonance capacitor C8. Here, as the leakage inductor L1 in the current resonance circuit 14, the leakage inductor L1 included in the high-frequency transformer T1 may be used, or the inductor L1 may be separately connected to the primary side of the high-frequency transformer T1.
　図１及び図２に示されるコンバータは、電圧共振回路１１を制御するドライブ・バッファ１７及び同期整流回路１３を制御するドライブ・バッファ１８、動作モードに応じたパルス信号を格納した参照テーブル３６及び参照テーブル３６を参照してこれらドライブ・バッファ１７、１８にパルス幅変調信号ＰＷＭを出力するＣＰＵ３０から構成されるスイッチング制御部１２を更に備えている。 The converter shown in FIGS. 1 and 2 includes a drive buffer 17 that controls the voltage resonance circuit 11, a drive buffer 18 that controls the synchronous rectification circuit 13, a reference table 36 that stores a pulse signal corresponding to an operation mode, and a reference. A switching control unit 12 comprising a CPU 30 that outputs a pulse width modulation signal PWM to the drive buffers 17 and 18 with reference to the table 36 is further provided.
　１次側に配置された電圧共振回路１１は、図２に示すようにフルブリッジ電圧共振回路で構成することができる。フルブリッジ電圧共振回路１１においては、スイッチング素子Ｑ１及びスイッチング素子Ｑ３が直列接続され、スイッチング素子Ｑ２及びスイッチング素子Ｑ４が直列接続されている。スイッチング素子Ｑ１、Ｑ２の直列回路及びスイッチング素子Ｑ３，Ｑ４の直列回路が入力キャパシタＣ７に並列接続されるとともにフルブリッジ回路を構成するように夫々入力側１０Ａ、１０Ｂの直流電源に並列接続されている。即ち、入力キャパシタＣ７が電源のプラス側１０Ａ及びマイナス側１０Ｂ間に接続され、スイッチング素子Ｑ１、Ｑ２のドレインが電源のプラス側１０Ａに接続され、スイッチング素子Ｑ３、Ｑ４のソースが電源のマイナス側１０Ｂに接続されている。また、スイッチング素子Ｑ１及びスイッチング素子Ｑ３間の接続部が出力側のトランスＴ１の一端部に接続され、スイッチング素子Ｑ２及びスイッチング素子Ｑ４の接続部が共振キャパシタＣ８並びにトランスＴ１が有するリーケージインダクタ或いはインダクタＬ１を介してトランスＴ１の他端部に接続されている。これらスイッチング素子Ｑ１～Ｑ４の夫々は、ＦＥＴ（電界効果トランジスタ）或いはＩＧＢＴ（絶縁ゲート・バイポーラトランジスタ）等のスイッチング素子で構成され、ドレイン及びソース間（ＩＧＢＴの場合にはエミッタ・コレクタ間）に寄生キャパシタＣ１～Ｃ４及び寄生ダイオードＤ１～Ｄ４を有している。また、スイッチング素子Ｑ１～Ｑ４のゲートには、スイッチング素子Ｑ１～Ｑ４を実質的な零電圧並びに零供給電流のタイミングでオン・オフするドライブ・バッファ１７が接続されている。出力端子２０Ａの電圧は、出力電圧信号として検出されてインタフェース(図示せず）を介してＣＰＵ３０に入力されている。出力電圧信号は、ＣＰＵ３０によって参照テーブ３６に格納されている参照出力電圧に参照され、参照出力電圧に対応するスイッチング周期及びパルス幅を有するパルス信号が選定される。このパルス信号は、ＣＰＵ３０からドライブ・バッファ１７に与えられてこのドライブ・バッファ１７からスイッチング信号がスイッチング素子Ｑ１～Ｑ４に出力される。即ち、ドライブ・バッファ１７から出力されるスイッチング・パルスは、出力電圧信号に応じてその周波数並びにデューティー比（デューティー・サイクルに対するオン期間の比）が選定されてスイッチング素子Ｑ１～Ｑ４の夫々が実質的な零電圧並びに零供給電流のタイミングでオン及びオフされる。 The voltage resonance circuit 11 arranged on the primary side can be constituted by a full bridge voltage resonance circuit as shown in FIG. In the full bridge voltage resonance circuit 11, the switching element Q1 and the switching element Q3 are connected in series, and the switching element Q2 and the switching element Q4 are connected in series. A series circuit of the switching elements Q1 and Q2 and a series circuit of the switching elements Q3 and Q4 are connected in parallel to the input capacitor C7 and are connected in parallel to the DC power sources on the input sides 10A and 10B so as to form a full bridge circuit. . That is, the input capacitor C7 is connected between the positive side 10A and the negative side 10B of the power source, the drains of the switching elements Q1, Q2 are connected to the positive side 10A of the power source, and the sources of the switching elements Q3, Q4 are the negative side 10B of the power source. It is connected to the. Further, the connection between the switching element Q1 and the switching element Q3 is connected to one end of the output-side transformer T1, and the connection between the switching element Q2 and the switching element Q4 is a leakage inductor or inductor L1 included in the resonance capacitor C8 and the transformer T1. To the other end of the transformer T1. Each of these switching elements Q1 to Q4 is composed of a switching element such as an FET (field effect transistor) or an IGBT (insulated gate / bipolar transistor), and is parasitic between a drain and a source (between an emitter and a collector in the case of IGBT). Capacitors C1 to C4 and parasitic diodes D1 to D4 are provided. The gates of the switching elements Q1 to Q4 are connected to a drive buffer 17 that turns on and off the switching elements Q1 to Q4 at the timing of substantially zero voltage and zero supply current. The voltage at the output terminal 20A is detected as an output voltage signal and input to the CPU 30 via an interface (not shown). The output voltage signal is referred to the reference output voltage stored in the reference table 36 by the CPU 30, and a pulse signal having a switching period and a pulse width corresponding to the reference output voltage is selected. This pulse signal is supplied from the CPU 30 to the drive buffer 17, and a switching signal is output from the drive buffer 17 to the switching elements Q1 to Q4. That is, the switching pulse output from the drive buffer 17 has its frequency and duty ratio (ratio of the on period with respect to the duty cycle) selected according to the output voltage signal, so that each of the switching elements Q1 to Q4 is substantially effective. ON and OFF at the timing of a zero voltage and a zero supply current.
　図１及び図２に示される電圧共振回路１１は、図３に示されるようにハーフブリッジ電圧共振回路(図示せず）で構成しても良い。ハーフブリッジ電圧共振回路においては、図２に示すフルブリッジ電圧共振回路におけるスイッチング素子Ｑ１、Ｑ３が除去され、スイッチング素子Ｑ２、Ｑ４の直列回路がキャパシタＣ７に並列に接続され、スイッチング素子Ｑ２、Ｑ４の接続点が共振キャパシタＣ８並びにトランスＴ１のリーケージインダクタ或いはインダクタＬ１を介して出力側のトランスＴ１の一端部に接続され、入力端子１０ＢがトランスＴ１の他端部に接続されている。 The voltage resonance circuit 11 shown in FIGS. 1 and 2 may be a half-bridge voltage resonance circuit (not shown) as shown in FIG. In the half-bridge voltage resonance circuit, the switching elements Q1 and Q3 in the full-bridge voltage resonance circuit shown in FIG. 2 are removed, a series circuit of the switching elements Q2 and Q4 is connected in parallel to the capacitor C7, and the switching elements Q2 and Q4 The connection point is connected to one end of the output-side transformer T1 via the resonant capacitor C8 and the leakage inductor or inductor L1 of the transformer T1, and the input terminal 10B is connected to the other end of the transformer T1.
　図２に示されるようにトランスＴ１の二次側には、同期整流回路１３が接続されている。 As shown in FIG. 2, a synchronous rectifier circuit 13 is connected to the secondary side of the transformer T1.
　図２に示すセンタータップ同期整流回路１３では、トランスＴ１の二次側の高電圧端子と接地端子２０Ｂとの間には、同期整流回路１３を構成するスイッチング素子Ｑ６が接続され、トランスＴ１の２次側の低電圧端子と接地端子２０Ｂとの間には、同期整流回路１３を構成するスイッチング素子Ｑ５が接続されている。また、トランスＴ１の中間端子には、出力端子２０Ａが接続され、出力端子２０Ａ及び接地端子２０Ｂ間には、平滑回路１６のキャパシタＣ９が接続されている。 In the center tap synchronous rectifier circuit 13 shown in FIG. 2, a switching element Q6 constituting the synchronous rectifier circuit 13 is connected between the secondary high voltage terminal of the transformer T1 and the ground terminal 20B, and the transformer T1 2 A switching element Q5 constituting the synchronous rectifier circuit 13 is connected between the low voltage terminal on the next side and the ground terminal 20B. An output terminal 20A is connected to the intermediate terminal of the transformer T1, and a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
　スイッチング素子Ｑ５及びＱ６は、夫々そのドレイン（ＩＧＢＴの場合にはエミッタ）及びソース（ＩＧＢＴの場合にはコレクタ）間に並列接続された寄生キャパシタＣ５、Ｃ６並びに寄生ダイオードＤ５，Ｄ６を含んで構成されている。また、スイッチング素子Ｑ５及びＱ６には、ドライバ・バッファ１８が接続されている。即ち、スイッチング素子Ｑ６のドレイン（ＩＧＢＴの場合にはエミッタ）がトランスＴ１の二次側高圧側端子に接続され、スイッチング素子Ｑ６のソース（ＩＧＢＴの場合にはコレクタ）が接地側出力端子２０Ｂに接続されている。また、スイッチング素子Ｑ５のドレイン（ＩＧＢＴの場合にはエミッタ）は、トランスＴ１の二次側低電圧側端子に接続され、スイッチング素子Ｑ５のソース（ＩＧＢＴの場合にはコレクタ）が接地側出力端子２０Ｂに接続されている。 The switching elements Q5 and Q6 include parasitic capacitors C5 and C6 and parasitic diodes D5 and D6 connected in parallel between the drain (emitter in the case of IGBT) and the source (collector in the case of IGBT), respectively. ing. A driver buffer 18 is connected to the switching elements Q5 and Q6. That is, the drain (emitter in the case of IGBT) of the switching element Q6 is connected to the secondary high-voltage side terminal of the transformer T1, and the source (collector in the case of IGBT) of the switching element Q6 is connected to the ground-side output terminal 20B. Has been. The drain (emitter in the case of IGBT) of the switching element Q5 is connected to the secondary low voltage side terminal of the transformer T1, and the source (collector in the case of IGBT) of the switching element Q5 is connected to the ground side output terminal 20B. It is connected to the.
　スイッチング素子Ｑ５及びスイッチング素子Ｑ６のゲートは、スイッチング素子Ｑ５及びスイッチング素子Ｑ６を所定のタイミングでオン・オフするためにドライブ・バッファ１８に接続されて出力電圧信号Ｖoutが出力端子２０Ａ，２０Ｂから出力される。出力端子２０Ａで検出される出力電圧は、電気的絶縁回路素子３２、例えば、フォトカプラ及び図示しないインタフェースを介して出力電圧信号としてＣＰＵ３０に入力されている。ＣＰＵ３０は、入力端子１０Ａから入力される入力電圧信号及び出力端子２０Ａ，２０Ｂ間から出力される出力電圧信号で参照テーブル３６を参照して下記に説明する各モードに応じてスイッチング素子Ｑ５及びスイッチング素子Ｑ６をオン・オフするパルス信号のデューティー比（デューティー・サイクルに対するオン期間の比）及び周波数を設定して最適な条件下でスイッチング素子Ｑ５、Ｑ６を実質的な零電流並びに零電圧のタイミングでオン・オフされる。 The gates of the switching element Q5 and the switching element Q6 are connected to the drive buffer 18 to turn on and off the switching element Q5 and the switching element Q6 at a predetermined timing, and the output voltage signal Vout is output from the output terminals 20A and 20B. The The output voltage detected at the output terminal 20A is input to the CPU 30 as an output voltage signal through an electrically insulating circuit element 32, for example, a photocoupler and an interface (not shown). The CPU 30 refers to the reference table 36 with the input voltage signal input from the input terminal 10A and the output voltage signal output between the output terminals 20A and 20B, and switches the switching element Q5 and the switching element according to each mode described below. Set the duty ratio (ratio of the on period to the duty cycle) and frequency of the pulse signal that turns Q6 on and off, and set the frequency to turn on the switching elements Q5 and Q6 at a substantially zero current and zero voltage timing under optimum conditions.・ Turned off.
　ここで、各モードに応じた最適制御を実施する為に参照テーブル３６には、図４並びに図５Ａ及び図５Ｂに示される関係から最適なパルス信号の周波数及びパルス信号のデューティー比が格納され、この格納されたテーブルから選定されたパルス信号がスイッチング素子Ｑ５、Ｑ６に与えられて同期整流回路１３が最適制御される。図４は、出力端子２０Ａ，２０Ｂ間から出力される出力電力Ｖoutを一定にする為のパルス信号の周波数と出力電圧Ｖoutとの関係を示すグラフ及びパルス信号のデューティー比（デューティー・サイクルに対するオン期間の比）と入力電圧との関係を示すグラフである。図４から明らかなように出力電圧Ｖoutが低下されると、パルス信号の周波数が低く設定され、出力電圧Ｖoutが上昇されると、パルス信号の周波数が高く設定される。また、図４から明らかなように出力電圧Ｖoutが低下されると、パルス信号のデューティー比が高く設定され、出力電圧Ｖoutが上昇されると、パルス信号のデューティー比が低く設定される。パルス信号の周波数及びパルス信号のデューティー比が適切に設定された出力端子２０Ａ，２０Ｂ間から出力される出力電圧信号Ｖoutが一定に設定される。出力電圧信号Ｖoutは、既に説明されるようにモニタされ、出力電圧信号Ｖoutが一定となるようにパルス信号の周波数及びパルス信号のデューティー比が設定される。 Here, in order to perform the optimum control according to each mode, the reference table 36 stores the optimum frequency of the pulse signal and the duty ratio of the pulse signal from the relationship shown in FIG. 4 and FIGS. 5A and 5B. A pulse signal selected from the stored table is applied to the switching elements Q5 and Q6, and the synchronous rectification circuit 13 is optimally controlled. FIG. 4 is a graph showing the relationship between the frequency of the pulse signal and the output voltage Vout for making the output power Vout output from the output terminals 20A and 20B constant, and the duty ratio of the pulse signal (the ON period with respect to the duty cycle). It is a graph which shows the relationship between an input voltage and an input voltage. As apparent from FIG. 4, when the output voltage Vout is lowered, the frequency of the pulse signal is set low, and when the output voltage Vout is raised, the frequency of the pulse signal is set high. As is clear from FIG. 4, when the output voltage Vout is lowered, the duty ratio of the pulse signal is set high, and when the output voltage Vout is raised, the duty ratio of the pulse signal is set low. The output voltage signal Vout output from between the output terminals 20A and 20B in which the frequency of the pulse signal and the duty ratio of the pulse signal are appropriately set is set constant. The output voltage signal Vout is monitored as described above, and the frequency of the pulse signal and the duty ratio of the pulse signal are set so that the output voltage signal Vout is constant.
　より具体的には、出力電圧Ｖoutが低い場合には、トランスＴ１の１次側入力電圧が低下する。従って、トランスＴ１の二次側における昇圧回路として機能する電圧共振回路１１におけるオン時間を長くする為にパルス信号の周波数が低下され、また、デューティー比が大きく選定されてスイッチング素子Ｑ1，Ｑ２，Ｑ３，Ｑ４のオン期間が長く、オフ期間が短く設定されてこのスイッチング素子Ｑ1，Ｑ２，Ｑ３，Ｑ４での昇圧比が大きくなる。これに対して入力電圧Ｖinが高い場合には、トランスＴ１の１次側入力電圧が上昇される。従って、トランスＴ１の二次側における昇圧回路として機能する電圧共振回路１１におけるオン時間を短くする為にパルス信号の周波数が上昇され、また、デューティー比が小さく選定されてスイッチング素子Ｑ1，Ｑ２，Ｑ３，Ｑ４のオン期間が短く、オフ期間が長く設定されてこのスイッチング素子Ｑ1，Ｑ２，Ｑ３，Ｑ４での昇圧比が低下される。 More specifically, when the output voltage Vout is low, the primary side input voltage of the transformer T1 decreases. Accordingly, the frequency of the pulse signal is lowered to increase the ON time in the voltage resonance circuit 11 functioning as a booster circuit on the secondary side of the transformer T1, and the duty ratio is selected to be large so that the switching elements Q1, Q2, Q3 are selected. , Q4 are set to be long and the OFF period is set to be short so that the boosting ratio in the switching elements Q1, Q2, Q3, and Q4 is increased. On the other hand, when the input voltage Vin is high, the primary side input voltage of the transformer T1 is increased. Accordingly, the frequency of the pulse signal is increased in order to shorten the ON time in the voltage resonance circuit 11 functioning as a booster circuit on the secondary side of the transformer T1, and the duty ratio is selected to be small so that the switching elements Q1, Q2, Q3 are selected. , Q4 are set to be short and the off period is set to be long so that the step-up ratio in the switching elements Q1, Q2, Q3, Q4 is lowered.
　図５Ａ及び図５Ｂは、入力電圧が一定の定常状態に達した後における出力端子２０Ａ，２０Ｂ間から出力される出力電力Ｖoutを可変とするパルス信号の周波数と出力電力（出力電圧Ｖoutに相関する。）との関係を示すグラフ及びパルス信号のデューティー比（デューティー・サイクルに対するオン期間の比）と出力電力（出力電圧Ｖoutに相関する。）との関係を示すグラフである。図５Ａから明らかなように入力電圧Ｖinが一定の定常状態となっている場合には、パルス信号の周波数が低く設定されると、出力電圧Ｖoutが上昇され、パルス信号の周波数が高く設定されると、出力電圧Ｖoutが低下される。また、図４から明らかなようにパルス信号の設定に依存せず、入力電圧Ｖinが一定であることから、出力電圧Ｖoutも一定に維持される。従って、パルス信号の周波数が可変されると、出力端子２０Ａ，２０Ｂ間から出力される出力電圧信号Ｖoutが可変される。従って、出力端子２０Ａ、２０Ｂに接続された負荷に応じてパルス信号の周波数が可変されて出力電圧が出力端子２０Ａ、２０Ｂから出力される。ここで、電圧共振回路１１のスイッチング素子Ｑ１～Ｑ４をスイッチングするスイッチング・パルスの周波数は、電流共振回路１４の共振周波数ｆ０に比べて低い周波数の範囲内で可変に設定されてＤＣ―ＤＣコンバータから負荷に供給される電力が制御される。共振周波数ｆ０に比べて低い周波数でスイッチング・パルスが発生される場合には、このキャパシタＣ８を充電する充電電流並びに共振キャパシタＣ８から放出される放出電流及びインダクタＬ１に供給される供給電流或いはインダクタから放出される放出電流を制御することができる。その結果、ＤＣ－ＤＣコンバータから出力する電力（電圧）を目標電力（目標電圧）に達するように制御することができる。また、後に詳細に示されるように、この制御においては、共振電流回路１４の共振周期Ｔｒを基準とすると、スイッチング素子Ｑ１～Ｑ５は、最大で共振周期Ｔｒの２倍の周期２Ｔｒに相当するスイッチング周期Ｔｓ（Ｔｓ＝２Ｔｒ）を有するスイッチング・パルスでオン・オフされる。負荷に目標電力を供給する定格電圧モードにおいて、この最大で共振周期Ｔｒの２倍のスイッチング周期Ｔｓ（Ｔｓ＝２Ｔｒ）を有するスイッチング・パルスでオン・オフされ、負荷に目標電力比べて小さい小電力を供給する小電力モードにおいて、この最大の共振周期２Ｔｒに比べてより小さなスイッチング周期Ｔｓ（Ｔｓ＜２Ｔｒ）を有するスイッチング・パルスでオン・オフされる。周波数で言い換えると、スイッチング素子Ｑ１～Ｑ５は、定格電圧モードにおいて、この共振周波数ｆｒの１／２のスイッチング周波数ｆｓ（ｆｓ＝ｆｒ・１／２）を有するスイッチング・パルスでオン・オフされ、小電力モードにおいて、この共振周波数ｆｒに比べてより高いスイッチング周波数ｆｓを有するスイッチング・パルスでオン・オフされる。 5A and 5B show the frequency of the pulse signal that makes the output power Vout output from between the output terminals 20A and 20B variable after the input voltage reaches a constant steady state and the output power (correlation with the output voltage Vout). And a graph showing a relationship between the duty ratio of the pulse signal (the ratio of the on period to the duty cycle) and the output power (correlated to the output voltage Vout). As apparent from FIG. 5A, when the input voltage Vin is in a constant steady state, when the frequency of the pulse signal is set low, the output voltage Vout is increased and the frequency of the pulse signal is set high. As a result, the output voltage Vout is lowered. Further, as apparent from FIG. 4, the input voltage Vin is constant without depending on the setting of the pulse signal, so that the output voltage Vout is also kept constant. Accordingly, when the frequency of the pulse signal is varied, the output voltage signal Vout output from between the output terminals 20A and 20B is varied. Therefore, the frequency of the pulse signal is varied according to the load connected to the output terminals 20A and 20B, and the output voltage is output from the output terminals 20A and 20B. Here, the frequency of the switching pulse for switching the switching elements Q1 to Q4 of the voltage resonance circuit 11 is variably set within a frequency range lower than the resonance frequency f0 of the current resonance circuit 14, and is from the DC-DC converter. The power supplied to the load is controlled. When a switching pulse is generated at a frequency lower than the resonance frequency f0, a charging current for charging the capacitor C8, a discharge current discharged from the resonance capacitor C8, a supply current supplied to the inductor L1, or an inductor The emitted current emitted can be controlled. As a result, the power (voltage) output from the DC-DC converter can be controlled to reach the target power (target voltage). Further, as will be described later in detail, in this control, when the resonance period Tr of the resonance current circuit 14 is used as a reference, the switching elements Q1 to Q5 perform switching corresponding to a period 2Tr that is twice as large as the resonance period Tr. It is turned on / off by a switching pulse having a period Ts (Ts = 2Tr). In the rated voltage mode in which the target power is supplied to the load, the power is turned on / off by a switching pulse having a switching period Ts (Ts = 2Tr) that is twice as large as the resonance period Tr. Is switched on / off by a switching pulse having a switching period Ts (Ts <2Tr) smaller than the maximum resonance period 2Tr. In other words, the switching elements Q1 to Q5 are turned on / off by a switching pulse having a switching frequency fs (fs = fr · 1/2) of the resonance frequency fr in the rated voltage mode. In the power mode, the switching pulse is turned on / off with a switching pulse having a switching frequency fs higher than the resonance frequency fr.
　また、トランスＴ１の２次側においては、トランスＴ１の一次側に共振電流回路１４から供給される一次側共振電流によって２次側共振電流が生ずる。この２次側共振電流に同期して同期整流回路１３のスイッチング素子Ｑ５、Ｑ６がスイッチング・パルスでオン・オフされる。従って、スイッチング素子Ｑ５、Ｑ６をオン・オフするスイッチング・パルスは、オン時間が共振電流の半サイクル（半周期）に一致されている。そして、スイッチング素子Ｑ５、Ｑ６は、スイッチング素子Ｑ１、Ｑ４並びにスイッチング素子Ｑ２，Ｑ３に夫々同期してスイッチングされるようにスイッチング・パルスで駆動される。 Also, on the secondary side of the transformer T1, a secondary side resonance current is generated by the primary side resonance current supplied from the resonance current circuit 14 to the primary side of the transformer T1. The switching elements Q5 and Q6 of the synchronous rectifier circuit 13 are turned on / off by a switching pulse in synchronization with the secondary side resonance current. Therefore, the switching pulse for turning on / off the switching elements Q5 and Q6 has an on-time corresponding to a half cycle (half cycle) of the resonance current. The switching elements Q5 and Q6 are driven by switching pulses so as to be switched in synchronization with the switching elements Q1 and Q4 and the switching elements Q2 and Q3, respectively.
　同期整流回路１３は、図１に示す中間端子を利用した同期整流回路１３に限らず、図６に示すようにブリッジ同期整流回路１３で構成されても良い。図５に示すように、ブリッジ同期整流回路１３においては、スイッチング素子Ｑ５、Ｑ７の直列回路及びスイッチング素子Ｑ６、Ｑ８の直列回路がキャパシタＣ９に対して並列接続され、スイッチング素子Ｑ５、Ｑ７の接続部がトランスＴ１の二次側の高電圧端子に接続され、スイッチング素子Ｑ６、Ｑ８の接続部がトランスＴ１の二次側の低電圧端子に接続されている。また、出力端子２０Ａ及び接地端子２０Ｂ間には、平滑回路１６のキャパシタＣ９が接続されている。 The synchronous rectifier circuit 13 is not limited to the synchronous rectifier circuit 13 using the intermediate terminal shown in FIG. 1, but may be configured by a bridge synchronous rectifier circuit 13 as shown in FIG. As shown in FIG. 5, in the bridge synchronous rectifier circuit 13, the series circuit of the switching elements Q5 and Q7 and the series circuit of the switching elements Q6 and Q8 are connected in parallel to the capacitor C9, and the connection part of the switching elements Q5 and Q7 Is connected to the secondary high voltage terminal of the transformer T1, and the connection of the switching elements Q6 and Q8 is connected to the secondary low voltage terminal of the transformer T1. A capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
　スイッチング素子Ｑ５、Ｑ６、Ｑ７、Ｑ８は、夫々そのドレイン（ＩＧＢＴの場合にはエミッタ）及びソース（ＩＧＢＴの場合にはコレクタ）間に並列接続された寄生キャパシタＣ５、Ｃ６、Ｃ７、Ｃ８並びに寄生ダイオードＤ５、Ｄ６、Ｄ７，Ｄ８を含んで構成されている。また、スイッチング素子Ｑ５、Ｑ６、Ｑ７、Ｑ８には、ドライバ・バッファ１８が接続されている。より詳細には、スイッチング素子Ｑ５，Ｑ６のドレイン（ＩＧＢＴの場合にはコレクタ）が出力端子２０Ａに接続され、スイッチング素子Ｑ６、Ｑ８のソース（ＩＧＢＴの場合にはエミッタ）が接地側出力端子２０Ｂに接続されている。スイッチング素子Ｑ５のソース（ＩＧＢＴの場合にはエミッタ）及びスイッチング素子Ｑ７のドレイン（ＩＧＢＴの場合にはコレクタ）がトランスＴ１の二次側高圧側端子に接続され、スイッチング素子Ｑ６のソース（ＩＧＢＴの場合にはエミッタ）及びスイッチング素子Ｑ８のドレイン（ＩＧＢＴの場合にはコレクタ）は、トランスＴ１の二次側低電圧側端子に接続されている。 The switching elements Q5, Q6, Q7, Q8 are parasitic capacitors C5, C6, C7, C8 and a parasitic diode connected in parallel between the drain (emitter in the case of IGBT) and the source (collector in the case of IGBT), respectively. D5, D6, D7, and D8 are included. A driver buffer 18 is connected to the switching elements Q5, Q6, Q7, and Q8. More specifically, the drains (collector in the case of IGBT) of switching elements Q5 and Q6 are connected to output terminal 20A, and the sources (emitters in the case of IGBT) of switching elements Q6 and Q8 are connected to ground side output terminal 20B. It is connected. The source of the switching element Q5 (emitter in the case of IGBT) and the drain of the switching element Q7 (collector in the case of IGBT) are connected to the secondary high-voltage side terminal of the transformer T1, and the source of the switching element Q6 (in the case of IGBT) And the drain (collector in the case of IGBT) of the switching element Q8 are connected to the secondary low-voltage side terminal of the transformer T1.
　スイッチング素子Ｑ５、Ｑ６、Ｑ７及びＱ８のゲートは、スイッチング素子Ｑ５、Ｑ６、Ｑ７及びＱ８を所定のタイミングでオン・オフするためにドライブ・バッファ１８に接続されて出力電圧信号Ｖoutが出力端子２０Ａ，２０Ｂから出力される。出力端子２０Ａで検出される出力電圧は、電気的絶縁回路素子３２、例えば、フォトカプラ及び図示しないインタフェースを介して出力電圧信号としてＣＰＵ３０に入力されている。ＣＰＵ３０は、出力端子２０Ａ，２０Ｂ間から出力される出力電圧信号で参照テーブル３６を参照して各モードに応じてスイッチング素子Ｑ５、Ｑ６、Ｑ７及びＱ８がオン・オフされる。即ち、パルス信号のデューティー比（デューティー・サイクルに対するオン期間の比）及び周波数が設定されて最適な条件下でスイッチング素子Ｑ５、Ｑ６、Ｑ７及びＱ８が実質的な零電流並びに零電圧のタイミングでオン・オフされる。また、図６に示される同期整流回路１３においても、トランスＴ１の２次側に流れる２次側共振電流に同期してスイッチング素子Ｑ５、Ｑ８並びにスイッチング素子Ｑ６、Ｑ７が交互にスイッチング・パルスでオン・オフされる。従って、スイッチング素子Ｑ５、Ｑ６、Ｑ７、Ｑ８をオン・オフするスイッチング・パルスは、オン時間が共振電流の半サイクル（半周期）に一致されている。そして、スイッチング素子Ｑ５、Ｑ８並びにスイッチング素子Ｑ６、Ｑ７は、夫々スイッチング素子Ｑ１、Ｑ４並びにスイッチング素子Ｑ２，Ｑ３に同期してスイッチングされるようにスイッチング・パルスで駆動される。 The gates of the switching elements Q5, Q6, Q7 and Q8 are connected to the drive buffer 18 to turn on and off the switching elements Q5, Q6, Q7 and Q8 at a predetermined timing, and the output voltage signal Vout is output to the output terminals 20A, 20A, 20B. The output voltage detected at the output terminal 20A is input to the CPU 30 as an output voltage signal through an electrically insulating circuit element 32, for example, a photocoupler and an interface (not shown). In the CPU 30, the switching elements Q5, Q6, Q7, and Q8 are turned on / off according to each mode by referring to the reference table 36 with the output voltage signal output from between the output terminals 20A, 20B. That is, the duty ratio of the pulse signal (ratio of the on period to the duty cycle) and the frequency are set and the switching elements Q5, Q6, Q7 and Q8 are turned on at the timing of substantially zero current and zero voltage under the optimum conditions.・ Turned off. In the synchronous rectifier circuit 13 shown in FIG. 6, the switching elements Q5 and Q8 and the switching elements Q6 and Q7 are alternately turned on by the switching pulse in synchronization with the secondary side resonance current flowing on the secondary side of the transformer T1.・ Turned off. Therefore, the switching pulses for turning on / off the switching elements Q5, Q6, Q7, and Q8 have an on-time that matches the half cycle (half cycle) of the resonance current. Switching elements Q5 and Q8 and switching elements Q6 and Q7 are driven by switching pulses so as to be switched in synchronization with switching elements Q1 and Q4 and switching elements Q2 and Q3, respectively.
　上述した図１及び図２に示すＤＣ―ＤＣコンバータにおいては、図７に示すように目標電圧ＶrefがステップＳ１に示すように図示しない入力装置でＣＰＵ３０に入力され、また、整流回路１３からの出力電圧ＶoutがステップＳ２に示すように電気的絶縁回路素子３２を介して入力される。目標電圧Ｖref及び出力電圧Ｖoutは、ステップＳ３に示すようにＣＰＵ３０で比較され、その差電圧で参照テーブル３６が参照されてステップＳ４に示すように参照テーブル３６内の周波数テーブルでトランスＴ１の１次側のスイッチング素子Ｑ１～Ｑ４及びトランスＴ１の２次側のスイッチング素子Ｑ５～Ｑ６のスイッチング周波数が決定される。この周波数は、既に説明したように電流共振回路１４の共振周波数ｆ０に比べて低い周波数の範囲内で選定される。また、ステップＳ５及びＳ６に示すようにＣＰＵ３０においてパルス幅変調信号ＰＷＭのオン期間(時間）が決定される。この決定された周波数及びオン期間に基づいてステップＳ７に示すようにＣＰＵ３０がパルスジェネレータとして作動してパルス信号（パルス幅変調信号）ＰＷＭがドライバ・バッファ１７に与えられて格納される。また、この決定された周波数及びオン期間に基づいてステップＳ７に示すようにＣＰＵ３０がパルスジェネレータとして作動して電気的絶縁回路素子３４を介してパルス信号（パルス幅変調信号）ＰＷＭがドライバ・バッファ１８に与えられて格納される。従って、ドライバ・バッファ１７，１８は、ステップＳ８～Ｓ１１に示すように１次側のスイッチング素子Ｑ１～Ｑ４に第１～第４のゲートパルスを与えてスイッチング素子Ｑ１～Ｑ４をスイッチングする。同様に、ドライバ・バッファ１７，１８は、ステップＳ１２及びＳ１３に示すように２次側のスイッチング素子Ｑ５，Ｑ６に第５及び第６のゲートパルスを与えてスイッチング素子Ｑ５～Ｑ６をスイッチングする。その結果、後に説明されるように、目標とされる電圧が平滑回路１６から出力される。 In the DC-DC converter shown in FIGS. 1 and 2, the target voltage Vref is input to the CPU 30 by an input device (not shown) as shown in FIG. 7 and output from the rectifier circuit 13 as shown in FIG. The voltage Vout is input through the electrically insulating circuit element 32 as shown in step S2. The target voltage Vref and the output voltage Vout are compared by the CPU 30 as shown in step S3, the reference table 36 is referred to by the difference voltage, and the primary of the transformer T1 is shown in the frequency table in the reference table 36 as shown in step S4. The switching frequencies of the switching elements Q1 to Q4 on the side and the switching elements Q5 to Q6 on the secondary side of the transformer T1 are determined. This frequency is selected within a range of frequencies lower than the resonance frequency f0 of the current resonance circuit 14 as already described. Further, as shown in steps S5 and S6, the CPU 30 determines the ON period (time) of the pulse width modulation signal PWM. Based on the determined frequency and on-period, the CPU 30 operates as a pulse generator as shown in step S7, and a pulse signal (pulse width modulation signal) PWM is supplied to the driver buffer 17 and stored therein. Based on the determined frequency and on-period, the CPU 30 operates as a pulse generator as shown in step S7, and the pulse signal (pulse width modulation signal) PWM is supplied to the driver buffer 18 via the electrical insulation circuit element 34. Is given and stored. Accordingly, the driver buffers 17 and 18 switch the switching elements Q1 to Q4 by applying the first to fourth gate pulses to the primary side switching elements Q1 to Q4 as shown in steps S8 to S11. Similarly, the driver buffers 17 and 18 switch the switching elements Q5 to Q6 by applying fifth and sixth gate pulses to the secondary side switching elements Q5 and Q6 as shown in steps S12 and S13. As a result, as will be described later, a target voltage is output from the smoothing circuit 16.
　尚、スイッチング素子Ｑ５、Ｑ６或いはスイッチング素子Ｑ１～Ｑ４をオン・オフするスイッチング・パルスは、オン時間が共振電流の半サイクル（半周期）に一致されるように選定される。 Incidentally, the switching pulse for turning on / off the switching elements Q5, Q6 or the switching elements Q1-Q4 is selected so that the on-time is matched with the half cycle (half cycle) of the resonance current.
　より詳細には、図７に示されたスイッチング制御では、図８に示されるように始めに目標出力電圧が設定される。（ステップＳ２１）ここで、予め目標出力電圧に対応する基準となるスイッチング周波数ｆｓが設定される。このスイッチング周波数で１次側のスイッチング素子Ｑ１～Ｑ５がスイッチングされる。整流回路１３からの出力電圧Ｖoutが検出されてステップＳ２２で目標電圧と比較される。出力電圧Ｖoutが目標電圧に達している場合には、そのスイッチング周波数ｆｓでスイッチングが継続される。ステップＳ２４で目標電圧よりも出力電圧Ｖoutが大きいかが判別される。出力電圧Ｖoutが目標電圧よりも大きい場合には、ステップＳ２５に示すように設定した周波数ｆｓよりもより高い周波数（ｆｓ＋Δｆ＜ｆｒ）が設定されて再びステップＳ２２が実行される。周波数（ｆｓ＋Δｆ）が高く設定されると、励磁電流が流れる期間が小さくなり、リアクタンスＬ１の励磁エネルギーが減少し、トランスＴ１の一次側端子電圧が減少して昇圧効果が低下される。結果として、出力電圧Ｖoutが低下される。また、出力電圧Ｖoutが目標電圧よりも小さい場合には、ステップＳ２６に示すように設定した周波数ｆｓよりもより低い周波数（ｆｓ－Δｆ＜ｆｒ）が設定されて再びステップＳ２２が実行される。周波数（ｆｓ－Δｆ）が低く設定されると、励磁電流が流れる期間が大きくなり、リアクタンスＬ１の励磁エネルギーが増加し、トランスＴ１の一次側端子電圧が増加して昇圧効果が増加される。結果として、出力電圧Ｖoutが増加される。このようにしてゲートパルスの周波数が制御されて出力が一定に維持される。 More specifically, in the switching control shown in FIG. 7, the target output voltage is first set as shown in FIG. (Step S21) Here, a switching frequency fs serving as a reference corresponding to the target output voltage is set in advance. The primary side switching elements Q1 to Q5 are switched at this switching frequency. The output voltage Vout from the rectifier circuit 13 is detected and compared with the target voltage in step S22. When the output voltage Vout has reached the target voltage, switching is continued at the switching frequency fs. In step S24, it is determined whether the output voltage Vout is larger than the target voltage. When the output voltage Vout is higher than the target voltage, a frequency (fs + Δf <fr) higher than the set frequency fs is set as shown in step S25, and step S22 is executed again. When the frequency (fs + Δf) is set high, the period during which the excitation current flows is reduced, the excitation energy of the reactance L1 is reduced, the primary terminal voltage of the transformer T1 is reduced, and the boosting effect is reduced. As a result, the output voltage Vout is reduced. If the output voltage Vout is lower than the target voltage, a frequency (fs−Δf <fr) lower than the set frequency fs is set as shown in step S26, and step S22 is executed again. When the frequency (fs−Δf) is set low, the period during which the excitation current flows increases, the excitation energy of the reactance L1 increases, the primary side terminal voltage of the transformer T1 increases, and the boosting effect is increased. As a result, the output voltage Vout is increased. In this way, the frequency of the gate pulse is controlled and the output is kept constant.
　トランスＴ１の２次側では、２次側の電流が一次側のスイッチングに同期して整流（同期整流）され、共振回路１４に共振電流が流れている期間のみ２次側のスイッチング素子Ｑ５、Ｑ６がオンされる。定格入力電圧モードにおいては、1次側のスイッチング素子Ｑ１～Ｑ４のオンの期間は、共振電流が流れている期間Ｔｒよりも大きく（Ｔｓ＞２Ｔｒ）なるようにスイッチング周波数ｆｓが決定される。従って、定格入力電圧モードでは、トランスＴ１が有するインダクタンスの励磁エネルギーが積極的に利用され、トランスＴ１の１次側の端子電圧を昇圧させている。これに対して、小電力モードでは、定格入力電圧モード（ｆｓ）に比べ高い周波数（ｆｓ＋Δｆ）に設定されてスイッチング素子Ｑ１～Ｑ６がスイッチング動作される。スイッチング素子Ｑ１～Ｑ６のオン期間の最小値としては、共振電流が流れている期間と同等なるまで、スイッチング周波数が高く設定される。従って、共振回路１４において、トランスＴ１に励磁電流が流れる期間が減少され、励磁エネルギーが減少される、その結果、トランスＴ１の１次側端子電圧の昇圧が減少され、出力電圧を制御することが可能となる。 On the secondary side of the transformer T1, the secondary side current is rectified (synchronous rectification) in synchronization with the primary side switching, and the secondary side switching elements Q5, Q6 are only in the period when the resonance current is flowing in the resonance circuit 14. Is turned on. In the rated input voltage mode, the switching frequency fs is determined such that the ON period of the primary side switching elements Q1 to Q4 is larger than the period Tr in which the resonance current flows (Ts> 2Tr). Therefore, in the rated input voltage mode, the excitation energy of the inductance of the transformer T1 is actively used, and the terminal voltage on the primary side of the transformer T1 is boosted. On the other hand, in the low power mode, the switching elements Q1 to Q6 are switched by setting the frequency (fs + Δf) higher than that in the rated input voltage mode (fs). As the minimum value of the ON period of the switching elements Q1 to Q6, the switching frequency is set high until it becomes equal to the period during which the resonance current flows. Therefore, in the resonance circuit 14, the period during which the excitation current flows through the transformer T1 is reduced and the excitation energy is reduced. As a result, the boost of the primary terminal voltage of the transformer T1 is reduced, and the output voltage can be controlled. It becomes possible.
　尚、周波数制御においては、上述したように、周期（Ｔｓ）が可変とされが、この可変の範囲は、最少周期に対して５０％以上も長い最大周期を設定することが可能である。しかし、最少周期（Ｔｓmin）に対する最大周期（Ｔｓmax）をあまりにも大きく設定しすぎると、トランスＴ１に共振回路１４が出力電流を供給する電流共振時間の割合が小さくなってしまう。従って、共振電流が大きくなり、同通損失が大きくなり、その結果として、効率向上は望めなくなってしまう。実験的には、最少周期（Ｔｓmin）に対する最大周期（Ｔｓmax）は、３０％以下の範囲に設定され、この範囲内で周波数制御が実施されることが望ましいことが判明している。 In the frequency control, as described above, the cycle (Ts) is variable, and this variable range can set a maximum cycle longer than 50% with respect to the minimum cycle. However, if the maximum period (Tsmax) with respect to the minimum period (Tsmin) is set too large, the ratio of the current resonance time during which the resonance circuit 14 supplies the output current to the transformer T1 is decreased. Therefore, the resonance current increases and the communication loss increases, and as a result, improvement in efficiency cannot be expected. Experimentally, it has been found that the maximum period (Tsmax) with respect to the minimum period (Tsmin) is set to a range of 30% or less, and it is desirable to perform frequency control within this range.
　図１及び図２に示されるコンバータでは、電流共振回路１４において、共振キャパシタＣ８にトランスＴ１の励磁エネルギーがチャージされ、そのチャージされたエネルギーの放電時にトランスＴ１の１次側端子端に表れる電圧をトランスＴ１で昇圧することができ、また、放電エネルギーを用いることで出力を可変にすることができる。従って、入力端子１０Ａ，１０Ｂに表れるリップル電圧或いは入力電圧の変動は、電流共振回路で吸収される。結果として、出力電圧の変動を改善することができる。ここで、力率改善回路の出力電圧は、基本的には、一定であるが、リップル電圧或いは入力変動により僅かに変動される。 In the converter shown in FIGS. 1 and 2, in the current resonance circuit 14, the excitation energy of the transformer T1 is charged in the resonance capacitor C8, and the voltage appearing at the primary side terminal of the transformer T1 when the charged energy is discharged. The voltage can be boosted by the transformer T1, and the output can be made variable by using discharge energy. Accordingly, the ripple voltage or the fluctuation of the input voltage appearing at the input terminals 10A and 10B is absorbed by the current resonance circuit. As a result, fluctuations in output voltage can be improved. Here, the output voltage of the power factor correction circuit is basically constant, but slightly fluctuates due to ripple voltage or input fluctuation.
　また、図１及び図２に示されるＤＣ－ＤＣコンバータでは、全動作領域において、１次及び２次のスイッチング素子Ｑ１～Ｑ６がソフトスイッチングされているため高効率で動作される。また、回路部品点数が少ないため、小型軽量化が図れ、コストダウンだけでなく、部品故障に対する信頼性が向上される。 Further, the DC-DC converter shown in FIGS. 1 and 2 operates with high efficiency because the primary and secondary switching elements Q1 to Q6 are soft-switched in the entire operation region. In addition, since the number of circuit components is small, the size and weight can be reduced, and not only the cost is reduced, but also the reliability against component failure is improved.
　図９の（ａ）から図１６の（ｇ）を参照して図１及び図２に示されるＤＣ－ＤＣコンバータにおける定格入力モード及び小電力入力モードにおける回路動作について詳細に説明する。 The circuit operation in the rated input mode and the low power input mode in the DC-DC converter shown in FIGS. 1 and 2 will be described in detail with reference to FIGS.
　（１）定格入力電圧モード（電力一定）
　図９の（ａ）～図１２の（ｇ）は、図１に示されるＤＣ－ＤＣコンバータにおける定格入力電圧モードでの各部の動作を示している。この図９の（ａ）～図１２の（ｇ）を参照して図１に示されるＤＣ－ＤＣコンバータの動作を説明する。 (1) Rated input voltage mode (constant power)
9 (a) to 12 (g) show the operation of each section in the rated input voltage mode in the DC-DC converter shown in FIG. The operation of the DC-DC converter shown in FIG. 1 will be described with reference to FIGS. 9 (a) to 12 (g).
　（時点ｔ２～時点ｔ３の動作）
　定格入力モードにおいては、図９の（ａ）に示すように時点ｔ２のタイミングでドライブ・バッファ１７からスイッチング素子Ｑ１，Ｑ４のゲートに与えられるゲートパルス信号がオフされてスイッチング素子Ｑ１，Ｑ４がオフされる。時点ｔ２から時点ｔ３の間においては、図９の（ｃ）に示すように、トランスＴ１の励磁インダクタンスＬ１から流れる励磁電流がドレイン電流ｉＱ１，ｉＱ４として供給され、このドレイン電流ｉＱ１，ｉＱ４がスイッチング素子Ｑ１，Ｑ４のドレイン・ソース間容量Ｃ１、Ｃ４を充電する。従って、スイッチング素子Ｑ１，Ｑ４のドレイン電圧は、時点ｔ２から時点ｔ３に亘って、図９の（ｂ）に示すように穏やかに上昇される。ここで、スイッチング素子Ｑ１，Ｑ４のドレイン電圧は、時点ｔ２においては、零であることから、スイッチング素子Ｑ１，Ｑ４は、零電圧でスイッチングされる。 (Operation from time t2 to time t3)
In the rated input mode, as shown in FIG. 9A, the gate pulse signal applied from the drive buffer 17 to the gates of the switching elements Q1 and Q4 is turned off at the timing of time t2, and the switching elements Q1 and Q4 are turned off. Is done. Between time t2 and time t3, as shown in FIG. 9C, the exciting current flowing from the exciting inductance L1 of the transformer T1 is supplied as the drain currents iQ1 and iQ4, and the drain currents iQ1 and iQ4 are used as the switching elements. The drain-source capacitances C1 and C4 of Q1 and Q4 are charged. Therefore, the drain voltages of the switching elements Q1 and Q4 are gently increased from time t2 to time t3 as shown in FIG. 9B. Here, since the drain voltages of the switching elements Q1 and Q4 are zero at the time point t2, the switching elements Q1 and Q4 are switched at zero voltage.
　尚、トランスＴ１の励磁インダクタンスＬ１から流れる励磁電流は、無効電流に相当し、時点ｔ２における入力側（Vin)から供給される電流は、ゼロであり、この観点からスイッチング素子Ｑ１，Ｑ４は、時点ｔ２において、ゼロ供給電流でスイッチングされる。 The exciting current flowing from the exciting inductance L1 of the transformer T1 corresponds to a reactive current, and the current supplied from the input side (Vin) at time t2 is zero. From this viewpoint, the switching elements Q1 and Q4 are At t2, switching is performed with zero supply current.
　ここで、ブリッジ回路を構成する他方のスイッチング素子Ｑ２，Ｑ３は、時点ｔ２から時点ｔ３においては、図９の（ｄ）に示すようにオフ状態にあり、スイッチング素子Ｑ１，Ｑ４のオフに伴いトランスＴ１の励磁インダクタンスＬ１から励磁電流が流れるに伴い、スイッチング素子Ｑ２，Ｑ３のドレイン・ソース間のキャパシタＣ２、Ｃ３が図１０の（ｆ）に示されるように放電される。従って、スイッチング素子Ｑ２，Ｑ３のドレイン電圧は、時点ｔ２から時点ｔ３に亘って図９の（ｅ）に示すように穏やかに降下される。ここで、時点ｔ３においては、スイッチング素子Ｑ２，Ｑ３のドレイン電圧は、同様に零であることから、スイッチング素子Ｑ２，Ｑ３は、零電圧でスイッチングされることとなる。 Here, the other switching elements Q2 and Q3 constituting the bridge circuit are in the OFF state from time t2 to time t3 as shown in FIG. 9D, and the transformers are turned off as the switching elements Q1 and Q4 are turned off. As the exciting current flows from the exciting inductance L1 of T1, the capacitors C2 and C3 between the drain and source of the switching elements Q2 and Q3 are discharged as shown in FIG. Therefore, the drain voltages of the switching elements Q2 and Q3 are gently lowered from the time point t2 to the time point t3 as shown in FIG. Here, at the time t3, the drain voltages of the switching elements Q2 and Q3 are similarly zero, so that the switching elements Q2 and Q3 are switched at zero voltage.
　時点ｔ２～時点ｔ３間においては、キャパシタＣ８及びリーケージインダクタＬ１からの電流が分流されて電流ｉＱ１，ｉＱ４及び電流ｉＱ２，ｉＱ３として電圧共振回路１１に供給される。この電流の供給に伴い、図１０の（ｇ）に示すようにキャパシタＣ８間の電圧ＶＣ８がより低下され、トランスＴ１の１次側には、図１０の（ｉ）に示すようにトランス電流ｉＴ１が生じ、図１０(ｈ)に示すようにトランスＴ１の１次側の励磁電圧ＶＴ１がプラスからマイナスに緩やかに低下される。 From time t2 to time t3, currents from the capacitor C8 and the leakage inductor L1 are shunted and supplied to the voltage resonance circuit 11 as currents iQ1, iQ4 and currents iQ2, iQ3. As the current is supplied, the voltage VC8 between the capacitors C8 is further reduced as shown in FIG. 10 (g), and the transformer current iT1 is supplied to the primary side of the transformer T1 as shown in FIG. 10 (i). As shown in FIG. 10 (h), the excitation voltage VT1 on the primary side of the transformer T1 is gradually reduced from positive to negative.
　トランスＴ１の２次側では、１次側の励磁電圧ＶＴ１の変化に伴い昇圧された２次側電圧が表れる。ここで、時点ｔ２～時点ｔ３間においては、図１１の（ａ）及び（ｄ）に示すようにスイッチング素子Ｑ５，Ｑ６がオフされていることから、トランスＴ１の中間端子を基準にスイッチング素子Ｑ６のドレインには、図１１の（ｂ）に示すように穏やかに上昇するドレイン電圧が印加され、スイッチング素子Ｑ５のドレインには、図１１の（ｅ）に示すように穏やかに減少するドレイン電圧が印加される。 On the secondary side of the transformer T1, a secondary side voltage boosted with a change in the primary side excitation voltage VT1 appears. Here, since the switching elements Q5 and Q6 are turned off between time t2 and time t3 as shown in FIGS. 11A and 11D, the switching element Q6 is based on the intermediate terminal of the transformer T1. A drain voltage that rises gently as shown in FIG. 11B is applied to the drain of FIG. 11, and a drain voltage that gently decreases as shown in FIG. 11E is applied to the drain of the switching element Q5. Applied.
　（時点ｔ３～時点ｔ９の動作）
　時点ｔ３において、図９の（ｄ）に示されるように、スイッチング素子Ｑ２，Ｑ３のゲートにオン信号が印加され、時点ｔ３～時点ｔ９において、図９の（ｅ）に示すようにスイッチング素子Ｑ２，Ｑ３がオンされる。従って、図１０の（ｆ）に示すように、トランスＴ１のリーケージインダクタＬ１及び共振キャパシタＣ８の共振電流並びにトランスＴ１の励磁電流ｉＴ１を合わせた電流が分流されてドレイン電流ｉＱ２，ｉＱ３としてスイッチング素子Ｑ２，Ｑ３に供給される。図１０の（ｉ）に示すように時点ｔ３から時点ｔ６においては、リーケージインダクタＬ１及び共振キャパシタＣ８の共振電流の放出に伴う電流並びに時点ｔ３から時点ｔ９に亘って破線及び実線で示すように増加される励磁電流ｉＴ１がトランスＴ１の１次側に供給される。ここで、図１０の（ｉ）に示すように時点ｔ３～時点ｔ６までの間にドレインに流れる電流が共振電流に相当し、スイッチング素子Ｑ２，Ｑ３のオンに同期して共振電流が発生されている。ここでは、時点ｔ３～時点ｔ６の間に流れる共振電流の期間は、スイッチング素子Ｑ２，Ｑ３のオン期間の半周期に設定されている。また、時点ｔ６から時点ｔ９間において、励磁電流が共振キャパシタＣ８をチャージするに利用されることから、トランスＴ１の電圧はゆるやかに減少されている。 (Operation from time t3 to time t9)
At time t3, as shown in FIG. 9 (d), an ON signal is applied to the gates of the switching elements Q2 and Q3. From time t3 to time t9, as shown in FIG. 9 (e), the switching element Q2 , Q3 are turned on. Therefore, as shown in FIG. 10 (f), a current that is a sum of the resonance current of the leakage inductor L1 and the resonance capacitor C8 of the transformer T1 and the exciting current iT1 of the transformer T1 is shunted to form the drain currents iQ2 and iQ3 as the switching elements Q2 , Q3. As shown in FIG. 10 (i), from time t3 to time t6, current increases due to the discharge of the resonance current of the leakage inductor L1 and the resonance capacitor C8 and increases from time t3 to time t9 as indicated by a broken line and a solid line. The exciting current iT1 is supplied to the primary side of the transformer T1. Here, as shown in FIG. 10 (i), the current flowing through the drain between time t3 and time t6 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q2 and Q3 being turned on. Yes. Here, the period of the resonance current that flows between time t3 and time t6 is set to a half cycle of the ON period of switching elements Q2 and Q3. Further, since the exciting current is used to charge the resonance capacitor C8 between the time point t6 and the time point t9, the voltage of the transformer T1 is gradually decreased.
　ここで、既に述べたように定格入力電圧モードにおいては、1次側のスイッチング素子Ｑ１～Ｑ４のオンの期間は、共振電流が流れている期間よりも大きくなるようにスイッチング周波数（ｆｓ＜ｆｒ）が設定される。従って、定格入力電圧モードでは、トランスＴ１の励磁インダクタの励磁エネルギーが積極的に利用され、トランスＴ１の１次側の端子電圧を昇圧させている。 Here, as already described, in the rated input voltage mode, the switching frequency (fs <fr) is set so that the ON period of the primary side switching elements Q1 to Q4 is larger than the period during which the resonance current flows. Is set. Therefore, in the rated input voltage mode, the excitation energy of the excitation inductor of the transformer T1 is positively used, and the terminal voltage on the primary side of the transformer T1 is boosted.
　励磁電流ｉＴ１のトランスＴ１の１次側への供給に伴い、トランスＴ１の２次側に昇圧された電圧が発生されてトランスＴ１の中間端子を基準にスイッチング素子Ｑ６のドレインには、図１１の（ｂ）に示すように略一定のドレイン電圧が印加される。時点ｔ３から時点ｔ６の間において、図１１の（ｄ）に示すように印加スイッチング素子Ｑ５のゲートにオン信号が印加されてスイッチング素子Ｑ５がオンされることから、図１１の（ｅ）に示すようにスイッチング素子Ｑ５のドレイン電圧は、略零に低下されるとともにトランスＴ１の中間端子には、正弦半波状の共振電流が流れ、図１２の（ｆ）に示すようにこの共振電流に同期してオンされるスイッチング素子Ｑ５にドレイン電流（ダイオード電流）が流されることとなる。このダイオード電流は、図１２の（ｇ）に示すように整流回路１３から出力電流Ｉ０として出力される。 As the exciting current iT1 is supplied to the primary side of the transformer T1, a boosted voltage is generated on the secondary side of the transformer T1, and the drain of the switching element Q6 is connected to the drain of the switching element Q6 with reference to the intermediate terminal of the transformer T1. As shown in (b), a substantially constant drain voltage is applied. Between time t3 and time t6, as shown in FIG. 11 (d), an ON signal is applied to the gate of the applied switching element Q5 to turn on the switching element Q5. Therefore, as shown in FIG. 11 (e). As described above, the drain voltage of the switching element Q5 is reduced to substantially zero and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with this resonance current as shown in FIG. Thus, a drain current (diode current) flows through the switching element Q5 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
　時点ｔ６において、図１１の（ｄ）に示すように、印加スイッチング素子Ｑ５のゲートに与えられたゲート信号がオフされ、時点ｔ６から時点ｔ９間にて励磁電流が共振キャパシタＣ８をチャージするため、トランスＴ１の電圧は減少される。従って、図１１の（ｅ）に示すように、スイッチング素子Q5のドレイン電圧は、時点ｔ６～時点ｔ９に亘って僅かに上昇される。 At time t6, as shown in FIG. 11D, the gate signal applied to the gate of the applied switching element Q5 is turned off, and the excitation current charges the resonance capacitor C8 between time t6 and time t9. The voltage of the transformer T1 is decreased. Accordingly, as shown in FIG. 11E, the drain voltage of the switching element Q5 is slightly increased from the time point t6 to the time point t9.
　（時点ｔ９～時点ｔ１０の動作）
　時点ｔ９において、図９の（ｄ）に示すように、スイッチング素子Ｑ２，Ｑ３のゲートに与えられるゲート信号がオフされ、スイッチング素子ｉＱ２，ｉＱ３のドレイン電流は、トランスＴ１の励磁電流により、スイッチング素子Ｑ２，Ｑ３のドレイン・ソース間キャパシタ（容量）Ｃ２，Ｃ３を充電する。従って、図９の（ｅ）に示すように、スイッチング素子Ｑ２，Ｑ３のドレイン電圧が穏やかに上昇される。結果として、図１０の（ｈ）に示されるように、トランスＴ１の１次側のトランス電圧ＶＴ１は、反転される。この反転に伴い、スイッチング素子Ｑ５のドレイン電圧は、穏やかに上昇され、図１１の（ｂ）に示すようにスイッチング素子Ｑ６のドレイン電圧は穏やかに減少される。 (Operation from time t9 to time t10)
At time t9, as shown in FIG. 9D, the gate signals applied to the gates of the switching elements Q2 and Q3 are turned off, and the drain currents of the switching elements iQ2 and iQ3 are switched by the exciting current of the transformer T1. The drain-source capacitors (capacitances) C2 and C3 of Q2 and Q3 are charged. Therefore, as shown in FIG. 9E, the drain voltages of the switching elements Q2 and Q3 are gently increased. As a result, as shown in FIG. 10 (h), the transformer voltage VT1 on the primary side of the transformer T1 is inverted. Along with this inversion, the drain voltage of the switching element Q5 is gently increased, and the drain voltage of the switching element Q6 is gently decreased as shown in FIG.
　ここで、共振キャパシタＣ８にチャージされた電圧は、時点ｔ１０のタイミングにおいて、対角のスイッチング素子Ｑ１，Ｑ４がオンされる場合、トランスＴ１の端子電圧に対し、逆向きとなっている。即ち、共振キャパシタＣ８の電圧は、入力電圧に対して加算方向に発生される為に、入力電圧を昇圧した状態でトランスＴ１に印加される。 Here, the voltage charged in the resonance capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q1 and Q4 are turned on at the timing of the time point t10. That is, since the voltage of the resonance capacitor C8 is generated in the addition direction with respect to the input voltage, it is applied to the transformer T1 with the input voltage boosted.
　（時点ｔ１０～時点ｔ１６の動作）
　時点ｔ１０において、図９の（ａ）に示されるように、スイッチング素子Ｑ１，Ｑ４のゲートにオン信号が印加され、時点ｔ１０～時点ｔ１６において、図９の（ａ）に示すようにスイッチング素子Ｑ１，Ｑ４がオンされる。従って、図１０の（ｃ）に示すように、トランスＴ１のリーケージインダクタＬ１及び共振キャパシタＣ８の共振電流並びにトランスＴ１の励磁電流ｉＴ１を合わせた電流が分流されてドレイン電流ｉＱ１，ｉＱ４としてスイッチング素子Ｑ１，Ｑ４に供給される。図１０の（ｉ）に示すように時点ｔ１０から時点ｔ１６においては、リーケージインダクタＬ１及び共振キャパシタＣ８の共振電流の放出に伴う励磁電流並びに時点ｔ１０から時点ｔ１６に亘って破線及び実線で示すように増加される励磁電流ｉＴ１がトランスＴ１の１次側に供給される。ここで、図９の（ｃ）に示すように時点ｔ１０～時点ｔ１３までの間にドレインに流れる電流が共振電流に相当し、スイッチング素子Ｑ１，Ｑ４のオンに同期して共振電流が発生されている。ここでは、時点ｔ１０～時点ｔ１３の間に流れる共振電流の期間は、スイッチング素子Ｑ１，Ｑ４のオン期間の半周期に設定されている。また、時点ｔ１３から時点ｔ１６間において、励磁電流が共振キャパシタＣ８をチャージするに利用されることから、トランスＴ１の電圧はゆるやかに減少されている。 (Operation from time t10 to time t16)
At time t10, as shown in FIG. 9A, an ON signal is applied to the gates of the switching elements Q1 and Q4. From time t10 to time t16, as shown in FIG. 9A, the switching element Q1 , Q4 are turned on. Accordingly, as shown in FIG. 10 (c), a current that is a sum of the resonance current of the leakage inductor L1 and the resonance capacitor C8 of the transformer T1 and the excitation current iT1 of the transformer T1 is shunted to form the drain currents iQ1 and iQ4 as the switching element Q1. , Q4. As shown in FIG. 10 (i), from the time point t10 to the time point t16, as indicated by a broken line and a solid line from the excitation current accompanying the discharge of the resonance current of the leakage inductor L1 and the resonance capacitor C8 and from the time point t10 to the time point t16. The increased excitation current iT1 is supplied to the primary side of the transformer T1. Here, as shown in FIG. 9C, the current flowing through the drain between time t10 and time t13 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q1 and Q4 being turned on. Yes. Here, the period of the resonance current flowing between time t10 and time t13 is set to a half cycle of the ON period of switching elements Q1 and Q4. Further, since the exciting current is used to charge the resonance capacitor C8 between the time point t13 and the time point t16, the voltage of the transformer T1 is gradually decreased.
　ここで、既に述べたように定格入力電圧モードにおいては、1次側のスイッチング素子Ｑ１～Ｑ４のオンの期間は、共振電流が流れている期間よりも大きくなるようにスイッチング周波数（ｆｓ＜ｆｒ）が設定される。従って、定格入力電圧モードでは、トランスＴ１の励磁インダクタの励磁エネルギーが積極的に利用され、トランスＴ１の１次側の端子電圧を昇圧させている。 Here, as already described, in the rated input voltage mode, the switching frequency (fs <fr) is set so that the ON period of the primary side switching elements Q1 to Q4 is larger than the period during which the resonance current flows. Is set. Therefore, in the rated input voltage mode, the excitation energy of the excitation inductor of the transformer T1 is positively used, and the terminal voltage on the primary side of the transformer T1 is boosted.
　励磁電流ｉＴ１のトランスＴ１の１次側への供給に伴い、トランスＴ１の２次側に昇圧された電圧が発生されてトランスＴ１の中間端子を基準にスイッチング素子Ｑ５のドレインには、図１１の（ｅ）に示すように略一定のドレイン電圧が印加される。時点ｔ１０から時点ｔ１３の間において、図１１の（ａ）に示すように印加スイッチング素子Ｑ６のゲートにオン信号が印加されてスイッチング素子Ｑ６がオンされることから、図１１の（ｂ）に示すようにスイッチング素子Ｑ６のドレイン電圧は、略零に低下されるとともにトランスＴ１の中間端子には、正弦半波状の共振電流が流れ、図１２の（ｃ）に示すようにこの共振電流に同期してオンされるスイッチング素子Ｑ６にドレイン電流（ダイオード電流）が流されることとなる。このダイオード電流は、図１２の（ｇ）に示すように整流回路１３から出力電流Ｉ０として出力される。 As the exciting current iT1 is supplied to the primary side of the transformer T1, a boosted voltage is generated on the secondary side of the transformer T1, and the drain of the switching element Q5 is connected to the drain of the switching element Q5 with reference to the intermediate terminal of the transformer T1. As shown in (e), a substantially constant drain voltage is applied. Between time t10 and time t13, as shown in FIG. 11A, an ON signal is applied to the gate of the applied switching element Q6 to turn on the switching element Q6. As described above, the drain voltage of the switching element Q6 is reduced to substantially zero, and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with this resonance current as shown in FIG. As a result, a drain current (diode current) flows through the switching element Q6 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
　時点ｔ１３において、図１１の（ａ）に示すように、印加スイッチング素子Ｑ６のゲートに与えられたゲート信号がオフされ、時点ｔ１３～時点ｔ１６間にて励磁電流が共振キャパシタＣ８をチャージするため、トランスＴ１の電圧は減少される。従って、図１１の（ｂ）に示すように、スイッチング素子Ｑ６のドレイン電圧は、時点ｔ１３～時点ｔ１６間に亘って僅かに上昇される。 At time t13, as shown in FIG. 11A, the gate signal applied to the gate of the applied switching element Q6 is turned off, and the excitation current charges the resonance capacitor C8 between time t13 and time t16. The voltage of the transformer T1 is decreased. Accordingly, as shown in FIG. 11B, the drain voltage of the switching element Q6 is slightly increased from the time point t13 to the time point t16.
　以上のように時点ｔ２～時点ｔ１６で１サイクルの動作が完了する。 As described above, one cycle of operation is completed from time t2 to time t16.
　（２）小電力モード（入力電力一定）
　図１３の（ａ）～図１６の（ｇ）は、図１に示されるＤＣ－ＤＣコンバータにおける入力電力一定の小電力モードでの各部の動作を示している。この図１３の（ａ）～図１６の（ｇ）を参照して図１に示されるＤＣ－ＤＣコンバータの動作を説明する。 (2) Low power mode (constant input power)
FIG. 13 (a) to FIG. 16 (g) show the operation of each part in the low power mode with constant input power in the DC-DC converter shown in FIG. The operation of the DC-DC converter shown in FIG. 1 will be described with reference to FIGS. 13 (a) to 16 (g).
　（時点ｔ２～時点ｔ３の動作）
　定格入力モードにおいては、図１３の（ａ）に示すように時点ｔ２のタイミングでドライブ・バッファ１７からスイッチング素子Ｑ１，Ｑ４のゲートに与えられるゲートパルス信号がオフされてスイッチング素子Ｑ１，Ｑ４がオフされる。時点ｔ２から時点ｔ３の間においては、図１３の（ｃ）に示すように、トランスＴ１の励磁インダクタンスＬ１から流れる励磁電流がドレイン電流ｉＱ１，ｉＱ４として供給され、このドレイン電流ｉＱ１，ｉＱ４がスイッチング素子Ｑ１，Ｑ４のドレイン・ソース間容量Ｃ１、Ｃ４を充電する。従って、スイッチング素子Ｑ１，Ｑ４のドレイン電圧は、時点ｔ２から時点ｔ３に亘って、図１３の（ｂ）に示すように穏やかに上昇される。ここで、スイッチング素子Ｑ１，Ｑ４のドレイン電圧は、時点ｔ２においては、零であることから、スイッチング素子Ｑ１，Ｑ４は、零電圧でスイッチングされる。 (Operation from time t2 to time t3)
In the rated input mode, as shown in FIG. 13 (a), the gate pulse signal applied from the drive buffer 17 to the gates of the switching elements Q1 and Q4 is turned off at the time t2, and the switching elements Q1 and Q4 are turned off. Is done. Between time t2 and time t3, as shown in FIG. 13C, the exciting current flowing from the exciting inductance L1 of the transformer T1 is supplied as the drain currents iQ1 and iQ4, and the drain currents iQ1 and iQ4 are used as the switching elements. The drain-source capacitances C1 and C4 of Q1 and Q4 are charged. Accordingly, the drain voltages of the switching elements Q1 and Q4 are gently increased from the time point t2 to the time point t3 as shown in FIG. 13B. Here, since the drain voltages of the switching elements Q1 and Q4 are zero at the time point t2, the switching elements Q1 and Q4 are switched at zero voltage.
　尚、トランスＴ１の励磁インダクタンスＬ１から流れる励磁電流は、無効電流に相当し、時点ｔ２における入力側（Vin)から供給される電流は、ゼロであり、この観点からスイッチング素子Ｑ１，Ｑ４は、時点ｔ２において、ゼロ供給電流でスイッチングされる。 The exciting current flowing from the exciting inductance L1 of the transformer T1 corresponds to a reactive current, and the current supplied from the input side (Vin) at time t2 is zero. From this viewpoint, the switching elements Q1 and Q4 are At t2, switching is performed with zero supply current.
　ここで、ブリッジ回路を構成する他方のスイッチング素子Ｑ２，Ｑ３は、時点ｔ２から時点ｔ３においては、図１３の（ｄ）に示すようにオフ状態にあり、スイッチング素子Ｑ１，Ｑ４のオフに伴いトランスＴ１の励磁インダクタンスＬ１から励磁電流が流れるに伴い、スイッチング素子Ｑ２，Ｑ３のドレイン・ソース間のキャパシタＣ２、Ｃ３が図１４の（ｆ）に示されるように放電される。従って、スイッチング素子Ｑ２，Ｑ３のドレイン電圧は、時点ｔ２から時点ｔ３に亘って図１３の（ｅ）に示すように穏やかに降下される。ここで、時点ｔ３においては、スイッチング素子Ｑ２，Ｑ３のドレイン電圧は、同様に零であることから、スイッチング素子Ｑ２，Ｑ３は、零電圧でスイッチングされることとなる。 Here, the other switching elements Q2 and Q3 constituting the bridge circuit are in the OFF state from the time point t2 to the time point t3 as shown in FIG. 13D, and the transformers are turned off as the switching elements Q1 and Q4 are turned off. As the exciting current flows from the exciting inductance L1 of T1, the capacitors C2 and C3 between the drains and sources of the switching elements Q2 and Q3 are discharged as shown in FIG. Therefore, the drain voltages of the switching elements Q2 and Q3 are gently lowered from the time point t2 to the time point t3 as shown in FIG. Here, at the time t3, the drain voltages of the switching elements Q2 and Q3 are similarly zero, so that the switching elements Q2 and Q3 are switched at zero voltage.
　時点ｔ２～時点ｔ３間においては、キャパシタＣ８及びリーケージインダクタＬ１からの電流が分流されて電流ｉＱ１，ｉＱ４及び電流ｉＱ２，ｉＱ３として電圧共振回路１１に供給される。この電流の供給に伴い、図１４の（ｇ）に示すようにキャパシタＣ８間の電圧ＶＣ８がより低下され、トランスＴ１の１次側には、図１４の（ｉ）に示すようにトランス電流ｉＴ１が生じ、図１４(ｈ)に示すようにトランスＴ１の１次側の励磁電圧ＶＴ１がプラスからマイナスに緩やかに低下される。 From time t2 to time t3, currents from the capacitor C8 and the leakage inductor L1 are shunted and supplied to the voltage resonance circuit 11 as currents iQ1, iQ4 and currents iQ2, iQ3. As the current is supplied, the voltage VC8 between the capacitors C8 is further reduced as shown in FIG. 14 (g), and the transformer current iT1 is supplied to the primary side of the transformer T1 as shown in FIG. 14 (i). As shown in FIG. 14 (h), the excitation voltage VT1 on the primary side of the transformer T1 is gradually reduced from positive to negative.
　トランスＴ１の２次側では、１次側の励磁電圧ＶＴ１の変化に伴い昇圧された２次側電圧が表れる。ここで、時点ｔ２～時点ｔ３間においては、図１５の（ａ）及び（ｄ）に示すようにスイッチング素子Ｑ５，Ｑ６がオフされていることから、トランスＴ１の中間端子を基準にスイッチング素子Ｑ６のドレインには、図１５の（ｂ）に示すように穏やかに上昇するドレイン電圧が印加され、スイッチング素子Ｑ５のドレインには、図１５の（ｅ）に示すように穏やかに減少するドレイン電圧が印加される。 On the secondary side of the transformer T1, a secondary side voltage boosted with a change in the primary side excitation voltage VT1 appears. Here, since the switching elements Q5 and Q6 are turned off between the time point t2 and the time point t3 as shown in FIGS. 15A and 15D, the switching element Q6 is based on the intermediate terminal of the transformer T1. A drain voltage that rises gently as shown in FIG. 15B is applied to the drain of FIG. 15, and a drain voltage that gently decreases as shown in FIG. 15E is applied to the drain of the switching element Q5. Applied.
　（時点ｔ３～時点ｔ６の動作）
　時点ｔ３において、図１３の（ｄ）に示されるように、スイッチング素子Ｑ２，Ｑ３のゲートにオン信号が印加され、時点ｔ３～時点ｔ６において、図１３の（ｅ）に示すようにスイッチング素子Ｑ２，Ｑ３がオンされる。従って、図１４の（ｆ）に示すように、トランスＴ１のリーケージインダクタＬ１及び共振キャパシタＣ８の共振電流並びにトランスＴ１の励磁電流ｉＴ１を合わせた電流が分流されてドレイン電流ｉＱ２，ｉＱ３としてスイッチング素子Ｑ２，Ｑ３に供給される。図１４の（ｉ）に示すように時点ｔ３から時点ｔ６においては、リーケージインダクタＬ１及び共振キャパシタＣ８の共振電流の放出に伴う電流並びに時点ｔ３から時点ｔ６に亘って破線及び実線で示すように増加される励磁電流ｉＴ１がトランスＴ１の１次側に供給される。図１４の（ｆ）に示すように時点ｔ３から時点ｔ５の後の時点までの間にドレインに流れる電流が共振電流に相当し、スイッチング素子Ｑ２，Ｑ３のオンに同期して共振電流が発生されている。ここでは、時点ｔ３から時点ｔ５の後の時点の間に流れる共振電流の期間は、スイッチング素子Ｑ２，Ｑ３のオン期間の半周期よりも大きな期間に設定されている。また、時点ｔ５の後の時点から時点ｔ６間において、励磁電流が共振キャパシタＣ８をチャージするに利用されることから、トランスＴ１の電圧はゆるやかに減少されている。 (Operation from time t3 to time t6)
At time t3, as shown in FIG. 13 (d), an ON signal is applied to the gates of the switching elements Q2 and Q3. From time t3 to time t6, as shown in FIG. 13 (e), the switching element Q2 , Q3 are turned on. Accordingly, as shown in FIG. 14 (f), a current that is a combination of the resonance current of the leakage inductor L1 and the resonance capacitor C8 of the transformer T1 and the exciting current iT1 of the transformer T1 is shunted to form the drain currents iQ2 and iQ3 as the switching element Q2 , Q3. As shown in FIG. 14 (i), from time t3 to time t6, current increases due to discharge of the resonance current of the leakage inductor L1 and the resonance capacitor C8, and increases from time t3 to time t6 as indicated by a broken line and a solid line. The exciting current iT1 is supplied to the primary side of the transformer T1. As shown in FIG. 14 (f), the current flowing through the drain from the time point t3 to the time point after the time point t5 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q2 and Q3 being turned on. ing. Here, the period of the resonance current that flows between the time point t3 and the time point after the time point t5 is set to a period longer than the half cycle of the ON period of the switching elements Q2 and Q3. In addition, since the exciting current is used to charge the resonance capacitor C8 from the time point after the time point t5 to the time point t6, the voltage of the transformer T1 is gradually decreased.
　励磁電流ｉＴ１のトランスＴ１の１次側への供給に伴い、トランスＴ１の２次側に昇圧された電圧が発生されてトランスＴ１の中間端子を基準にスイッチング素子Ｑ６のドレインには、図１５の（ｂ）に示すように略一定のドレイン電圧が印加される。時点ｔ３から時点ｔ６の間において、図１５の（ｄ）に示すように印加スイッチング素子Ｑ５のゲートにオン信号が印加されてスイッチング素子Ｑ５がオンされることから、図１３の（ｅ）に示すようにスイッチング素子Ｑ５のドレイン電圧は、略零に低下されるとともにトランスＴ１の中間端子には、正弦半波状の共振電流が流れ、図１４の（ｆ）に示すようにこの共振電流に同期してオンされるスイッチング素子Ｑ５にドレイン電流（ダイオード電流）が流されることとなる。このダイオード電流は、図１６の（ｇ）に示すように整流回路１３から出力電流Ｉ０として出力される。 As the exciting current iT1 is supplied to the primary side of the transformer T1, a boosted voltage is generated on the secondary side of the transformer T1, and the drain of the switching element Q6 is referenced to the intermediate terminal of the transformer T1 as shown in FIG. As shown in (b), a substantially constant drain voltage is applied. Between time t3 and time t6, as shown in FIG. 15 (d), an ON signal is applied to the gate of the applied switching element Q5 to turn on the switching element Q5. Therefore, as shown in FIG. 13 (e). As described above, the drain voltage of the switching element Q5 is reduced to substantially zero, and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with this resonance current as shown in FIG. Thus, a drain current (diode current) flows through the switching element Q5 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
　（時点ｔ６～時点ｔ７の動作）
　時点ｔ６において、図１３の（ｄ）に示すように、スイッチング素子Ｑ２，Ｑ３のゲートに与えられるゲート信号がオフされ、スイッチング素子ｉＱ２，ｉＱ３のドレイン電流は、トランスＴ１の励磁電流により、スイッチング素子Ｑ２，Ｑ３のドレイン・ソース間キャパシタ（容量）Ｃ２，Ｃ３を充電する。従って、図１３の（ｅ）に示すように、スイッチング素子Ｑ２，Ｑ３のドレイン電圧が穏やかに上昇する。結果として、図１４の（ｈ）に示されるように、トランスＴ１の１次側のトランス電圧ＶＴ１は、反転される。この反転に伴い、スイッチング素子Ｑ５のドレイン電圧は穏やかに上昇され、図１５の（ｂ）に示すようにスイッチング素子Ｑ６のドレイン電圧は穏やかに減少される。 (Operation from time t6 to time t7)
At time t6, as shown in FIG. 13D, the gate signals applied to the gates of the switching elements Q2 and Q3 are turned off, and the drain currents of the switching elements iQ2 and iQ3 are switched by the exciting current of the transformer T1. The drain-source capacitors (capacitances) C2 and C3 of Q2 and Q3 are charged. Accordingly, as shown in FIG. 13E, the drain voltages of the switching elements Q2 and Q3 rise gently. As a result, as shown in (h) of FIG. 14, the transformer voltage VT1 on the primary side of the transformer T1 is inverted. Along with this inversion, the drain voltage of the switching element Q5 is gently increased and the drain voltage of the switching element Q6 is gently decreased as shown in FIG.
　ここで、共振キャパシタＣ８にチャージされた電圧は、時点ｔ７のタイミングにおいて、対角のスイッチング素子Ｑ１，Ｑ４がオンされる場合、トランスＴ１の端子電圧に対し、逆向きとなっている。即ち、共振キャパシタＣ８の電圧は、入力電圧に対して加算方向に発生される為に、入力電圧を昇圧した状態でトランスＴ１に印加される。 Here, the voltage charged in the resonant capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q1 and Q4 are turned on at the timing of the time point t7. That is, since the voltage of the resonance capacitor C8 is generated in the addition direction with respect to the input voltage, it is applied to the transformer T1 with the input voltage boosted.
　（時点ｔ７～時点ｔ１０の動作）
　時点ｔ７において、図１３の（ａ）に示されるように、スイッチング素子Ｑ１，Ｑ４のゲートにオン信号が印加され、時点ｔ７～時点ｔ１０において、図１３の（ａ）に示すようにスイッチング素子Ｑ１，Ｑ４がオンされる。従って、図１３の（ｃ）に示すように、トランスＴ１のリーケージインダクタＬ１及び共振キャパシタＣ８の共振電流並びにトランスＴ１の励磁電流ｉＴ１を合わせた電流が分流されてドレイン電流ｉＱ１，ｉＱ４としてスイッチング素子Ｑ１，Ｑ４に供給される。図１４の（ｉ）に示すように時点ｔ７から時点ｔ１０においては、リーケージインダクタＬ１及び共振キャパシタＣ８の共振電流の放出に伴う電流並びに時点ｔ７から時点ｔ１０に亘って破線及び実線で示すように増加される励磁電流ｉＴ１がトランスＴ１の１次側に供給される。図１３の（ｃ）に示すように時点ｔ７～時点ｔ９の後の時点までの間にドレインに流れる電流が共振電流に相当し、スイッチング素子Ｑ１，Ｑ４のオンに同期して共振電流が発生されている。ここでは、時点ｔ７～時点ｔ９の後の時点の間に流れる共振電流の期間は、スイッチング素子Ｑ１，Ｑ４のオン期間の半周期よりも大きな期間に設定されている。また、時点ｔ９の後の時点から時点ｔ１０間において、励磁電流が共振キャパシタＣ８をチャージするに利用されることから、トランスＴ１の電圧はゆるやかに減少されている。 (Operation from time t7 to time t10)
At time t7, an ON signal is applied to the gates of the switching elements Q1 and Q4 as shown in FIG. 13A. From time t7 to time t10, the switching element Q1 is turned on as shown in FIG. 13A. , Q4 are turned on. Accordingly, as shown in FIG. 13 (c), a current obtained by dividing the leakage current of the leakage inductor L1 and the resonance capacitor C8 of the transformer T1 and the exciting current iT1 of the transformer T1 is shunted to form the drain currents iQ1 and iQ4 as the switching element Q1. , Q4. As shown in FIG. 14 (i), from time t7 to time t10, the current accompanying discharge of the resonance current of the leakage inductor L1 and the resonance capacitor C8 and the increase from time t7 to time t10 as shown by the broken line and the solid line. The exciting current iT1 is supplied to the primary side of the transformer T1. As shown in FIG. 13 (c), the current flowing through the drain between time t7 and time t9 corresponds to the resonance current, and the resonance current is generated in synchronization with the switching elements Q1 and Q4 being turned on. ing. Here, the period of the resonance current flowing between the time point t7 and the time point after the time point t9 is set to a period longer than the half cycle of the ON period of the switching elements Q1 and Q4. In addition, since the exciting current is used to charge the resonant capacitor C8 from the time point after the time point t9 to the time point t10, the voltage of the transformer T1 is gradually reduced.
　ここで、既に述べたように小電力モードでは、定格入力電圧モードｆｓに比べ周波数（ｆｓ＋Δｆ）が高く設定されてスイッチング素子Ｑ１～Ｑ６がスイッチング動作される。スイッチング素子Ｑ１～Ｑ６のオン期間の最小値としては、共振電流が流れている期間と同等なるまで、スイッチング周波数（ｆｓ＜ｆｒ）が高く設定される。従って、共振回路１４において、リーケージインダクタＬ１に励磁電流が流れる期間が減少され、励磁エネルギーが減少される、その結果、トランスＴ１の１次側端子電圧の昇圧が減少され、出力電圧を制御することが可能となる。 Here, as already described, in the low power mode, the frequency (fs + Δf) is set higher than the rated input voltage mode fs, and the switching elements Q1 to Q6 are switched. As a minimum value of the ON period of the switching elements Q1 to Q6, the switching frequency (fs <fr) is set high until it becomes equal to the period during which the resonance current flows. Therefore, in the resonance circuit 14, the period during which the exciting current flows through the leakage inductor L1 is reduced and the excitation energy is reduced. As a result, the boosting of the primary side terminal voltage of the transformer T1 is reduced, and the output voltage is controlled. Is possible.
　励磁電流ｉＴ１のトランスＴ１の１次側への供給に伴い、トランスＴ１の２次側に昇圧された電圧が発生されてトランスＴ１の中間端子を基準にスイッチング素子Ｑ５のドレインには、図１５の（ｅ）に示すように略一定のドレイン電圧が印加される。時点ｔ７から時点ｔ１０の間において、図１５の（ａ）に示すように印加スイッチング素子Ｑ６のゲートにオン信号が印加されてスイッチング素子Ｑ６がオンされることから、図１５の（ｂ）に示すようにスイッチング素子Ｑ６のドレイン電圧は、略零に低下されるとともにトランスＴ１の中間端子には、正弦半波状の共振電流が流れ、図１５の（ｃ）に示すようにこの共振電流に同期してオンされるスイッチング素子Ｑ６にドレイン電流（ダイオード電流）が流されることとなる。このダイオード電流は、図１６の（ｇ）に示すように整流回路１３から出力電流Ｉ０として出力される。 As the exciting current iT1 is supplied to the primary side of the transformer T1, a boosted voltage is generated on the secondary side of the transformer T1, and the drain of the switching element Q5 is connected to the drain of the switching element Q5 with reference to the intermediate terminal of the transformer T1. As shown in (e), a substantially constant drain voltage is applied. Between time t7 and time t10, as shown in FIG. 15A, an ON signal is applied to the gate of the applied switching element Q6 to turn on the switching element Q6. As described above, the drain voltage of the switching element Q6 is reduced to substantially zero and a sinusoidal half-wave resonance current flows through the intermediate terminal of the transformer T1, and is synchronized with the resonance current as shown in FIG. As a result, a drain current (diode current) flows through the switching element Q6 that is turned on. This diode current is output as an output current I0 from the rectifier circuit 13 as shown in FIG.
　時点ｔ１０において、図１５の（ａ）に示すように、印加スイッチング素子Ｑ６のゲートに与えられたゲート信号がオフされ、時点ｔ１０から時点ｔ１１間にて励磁電流が共振キャパシタＣ８をチャージするため、トランスＴ１の電圧は減少される。従って、図１５の（ｂ）に示すように、スイッチング素子Ｑ６のドレイン電圧は、時点ｔ１０～時点ｔ１１に亘って僅かに上昇される。共振キャパシタＣ８にチャージされた電圧は、時点ｔ１１のタイミングにおいて対角のスイッチング素子Ｑ２，Ｑ３がオンする場合、トランスＴ１の端子電圧に対し、逆向きである。つまり、入力電圧に対して加算方向であるので、入力電圧を昇圧した状態でトランスＴ１に印加できる。 At time t10, as shown in FIG. 15A, the gate signal applied to the gate of the applied switching element Q6 is turned off, and the excitation current charges the resonance capacitor C8 between time t10 and time t11. The voltage of the transformer T1 is decreased. Accordingly, as shown in FIG. 15B, the drain voltage of the switching element Q6 is slightly increased from the time point t10 to the time point t11. The voltage charged in the resonant capacitor C8 is opposite to the terminal voltage of the transformer T1 when the diagonal switching elements Q2 and Q3 are turned on at the time t11. That is, since it is in the addition direction with respect to the input voltage, it can be applied to the transformer T1 in a state where the input voltage is boosted.
　以上のように時点ｔ２～時点ｔ１１で１サイクルの動作が完了する。 As described above, one cycle of operation is completed from time t2 to time t11.
　以上のように、この発明のＤＣ－ＤＣコンバータにおいては、絶縁トランスの入出力側（１次及び２次側）に使用するスイッチング素子が全てソフトスイッチングで制御されていることから、高効率のＤＣ－ＤＣコンバータとすることができる。また、共振リアクトルとして、トランスのリーケージインダクタンスが利用される。従って、高効率のＤＣ－ＤＣコンバータでありながら、個別の部品がいらずローコストを実現することができる。また、リーケージインダクタンスは、固体差が大きく共振周波数の値にばらつきがあるが、ソフトウェアでスイッチング制御していることから、個別の調整値を記録し、理想的な共振及び制御を実現することができる。更に、スイッチング周波数を低下させてスイッチング素子を制御することから、スイッチングにおける損失或いはトランスのコア損失も低下させることができ、より高効率を実現することができる。 As described above, in the DC-DC converter of the present invention, since the switching elements used on the input / output sides (primary and secondary sides) of the isolation transformer are all controlled by soft switching, a highly efficient DC -It can be a DC converter. Further, the leakage inductance of the transformer is used as the resonance reactor. Therefore, although it is a high-efficiency DC-DC converter, it is possible to realize low cost without requiring individual components. In addition, leakage inductance has a large individual difference and variation in the value of the resonance frequency, but since switching control is performed by software, individual adjustment values can be recorded, and ideal resonance and control can be realized. . Further, since the switching element is controlled by lowering the switching frequency, the loss in switching or the core loss of the transformer can be reduced, and higher efficiency can be realized.
　図１に示される整流回路は、センタータップ整流方式が採用されているが、後に述べるようにブリッジ整流回路の方式が採用されても良い。また、図１に示す同期整流回路１３では、スイッチング素子Ｑ５，Ｑ６のダイオードＤ５，Ｄ６の整流作用を利用しているが、スイッチング素子Ｑ５，Ｑ６が整流ダイオードＤ５、Ｄ６に代えられても良い。 1 employs a center tap rectification method, but a bridge rectification circuit method may be employed as will be described later. 1 uses the rectification action of the diodes D5 and D6 of the switching elements Q5 and Q6, the switching elements Q5 and Q6 may be replaced with the rectification diodes D5 and D6.
　より具体的には、同期整流回路１３は、図１に示すスイッチング素子Ｑ５、Ｑ６に代えて図１７に示すようにダイオードＤ５、Ｄ６で中間タップ整流回路１３に構成されても良く、また、図６に示すスイッチング素子Ｑ５～Ｑ８に代えて図１８に示すようにダイオードＤ５～Ｄ８でブリッジ整流回路１３に構成されても良い。図１７に示すスイッチング素子Ｑ５、Ｑ６に代えてダイオードＤ５、Ｄ６で構成される整流回路１３及び図１８に示すスイッチング素子Ｑ５～Ｑ８に代えてダイオードＤ５～Ｄ８で構成される整流回路１３では、ダイオードＤ５、Ｄ６或いはダイオードＤ５～Ｄ８が電圧の低下と共に自動消成されることから、スイッチング素子Ｑ５、Ｑ６或いはスイッチング素子Ｑ５～Ｑ８を採用した回路と同様に動作される。しかし、強制的にスイッチング素子Ｑ５、Ｑ６或いはスイッチング素子Ｑ５～Ｑ８を消成する場合に比べて同期整流回路１３で消費される電力が生じることから、同期整流回路１３は、スイッチング素子Ｑ５、Ｑ６或いはスイッチング素子Ｑ５～Ｑ８で構成することが好ましい。 More specifically, the synchronous rectifier circuit 13 may be configured as the intermediate tap rectifier circuit 13 with diodes D5 and D6 as shown in FIG. 17 instead of the switching elements Q5 and Q6 shown in FIG. Instead of the switching elements Q5 to Q8 shown in FIG. 6, the bridge rectifier circuit 13 may be constituted by diodes D5 to D8 as shown in FIG. In the rectifier circuit 13 constituted by diodes D5 and D6 instead of the switching elements Q5 and Q6 shown in FIG. 17 and in the rectifier circuit 13 constituted by diodes D5 to D8 instead of the switching elements Q5 to Q8 shown in FIG. Since D5, D6 or the diodes D5 to D8 are automatically turned off as the voltage decreases, the circuit operates in the same manner as the circuit employing the switching elements Q5, Q6 or the switching elements Q5 to Q8. However, since the power consumed in the synchronous rectifier circuit 13 is generated as compared with the case where the switching elements Q5, Q6 or the switching elements Q5 to Q8 are forcibly turned off, the synchronous rectifier circuit 13 includes the switching elements Q5, Q6 or It is preferable to configure with switching elements Q5 to Q8.
　図１７に示される整流回路では、トランスＴ１の二次側の高電圧端子と接地端子２０Ｂとの間には、同期整流回路１３を構成する整流ダイオードＤ６が接続され、トランスＴ１の２次側の低電圧端子と接地端子２０Ｂとの間には、同期整流回路１３を構成する整流ダイオードＤ５が接続されている。また、トランスＴ１の中間端子には、出力端子２０Ａが接続され、出力端子２０Ａ及び接地端子２０Ｂ間には、平滑回路１６のキャパシタＣ９が接続されている。 In the rectifier circuit shown in FIG. 17, a rectifier diode D6 constituting the synchronous rectifier circuit 13 is connected between the secondary high voltage terminal of the transformer T1 and the ground terminal 20B, and the secondary side of the transformer T1 A rectifier diode D5 constituting the synchronous rectifier circuit 13 is connected between the low voltage terminal and the ground terminal 20B. An output terminal 20A is connected to the intermediate terminal of the transformer T1, and a capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
　整流ダイオードＤ６は、そのカソードがトランスＴ１の二次側高圧側端子に接続され、整流ダイオードＤ６のアノードが接地側出力端子２０Ｂに接続されている。また、整流ダイオードＤ５のカソードは、トランスＴ１の二次側低電圧側端子に接続され、整流ダイオードＤ５のアノードが接地側出力端子２０Ｂに接続されている。 The cathode of the rectifier diode D6 is connected to the secondary high-voltage side terminal of the transformer T1, and the anode of the rectifier diode D6 is connected to the ground-side output terminal 20B. The cathode of the rectifier diode D5 is connected to the secondary low-voltage side terminal of the transformer T1, and the anode of the rectifier diode D5 is connected to the ground-side output terminal 20B.
　また、図１８に示すように、ブリッジ同期整流回路１３においては、整流ダイオードＤ５、Ｄ７の直列回路及び整流ダイオードＤ６、Ｄ８の直列回路がキャパシタＣ９に対して並列接続され、整流ダイオードＤ５、Ｄ７の接続部がトランスＴ１の二次側の高電圧端子に接続され、整流ダイオードＤ６、Ｄ８の接続部がトランスＴ１の二次側の低電圧端子に接続されている。また、出力端子２０Ａ及び接地端子２０Ｂ間には、平滑回路１６のキャパシタＣ９が接続されている。 As shown in FIG. 18, in the bridge synchronous rectifier circuit 13, a series circuit of rectifier diodes D5 and D7 and a series circuit of rectifier diodes D6 and D8 are connected in parallel to the capacitor C9, and the rectifier diodes D5 and D7 are connected. The connecting portion is connected to the secondary high voltage terminal of the transformer T1, and the connecting portion of the rectifier diodes D6 and D8 is connected to the secondary low voltage terminal of the transformer T1. A capacitor C9 of the smoothing circuit 16 is connected between the output terminal 20A and the ground terminal 20B.
　この発明によれば、高効率のＤＣ－ＤＣコンバータが提供される。 According to the present invention, a highly efficient DC-DC converter is provided.
　Ｑ１、Ｑ２、Ｑ３、Ｑ４、Ｑ５、Ｑ６．．．スイッチング素子、Ｄ１、Ｄ２、Ｄ３、Ｄ４、Ｄ５、Ｄ６．．．スイッチング素子の寄生ダイオード、Ｃ１、Ｃ２、Ｃ３、Ｃ４、Ｃ５、Ｃ６、Ｃ７．．．スイッチング素子のドレイン－ソース間の容量、Ｃ８．．．平滑キャパシタ、Ｄ５，Ｄ６，Ｄ７，Ｄ８．．．整流ダイオード、Ｌ１．．．昇圧リアクトル或いはトランスのリーケージインダクタンス、Ｔ１．．．トランス、１１．．．電圧共振回路、１４．．．電流共振回路、１３．．．同期整流回路、１２．．．スイッチング制御部、１７，１８．．．ドライブ・バッファ、３０．．．ＣＰＵ、３６．．．参照テーブル、 Q1, Q2, Q3, Q4, Q5, Q6. . . Switching elements D1, D2, D3, D4, D5, D6. . . Parasitic diodes of the switching elements, C1, C2, C3, C4, C5, C6, C7. . . Capacitance between drain and source of the switching element, C8. . . Smoothing capacitors, D5, D6, D7, D8. . . Rectifier diode, L1. . . Step-up reactor or transformer leakage inductance, T1. . . Transformer, 11. . . Voltage resonant circuit, 14. . . 12. current resonance circuit; . . Synchronous rectifier circuit, 12. . . Switching control unit 17, 18. . . Drive buffer, 30. . . CPU, 36. . . Reference table,

Claims (7)

  1. 　　交互にスイッチングされる第１及び第３のスイッチング素子から成る第１の直列回路及び交互にスイッチングされる第２及び第４のスイッチング素子から成る第２の直列回路が並列に接続されてフルブリッジ回路に構成されている第１のスイッチング回路を含み、出力電圧が変動する低電圧直流電源から直流電力が前記フルブリッジ回路に入力され、この直流電力がＤＣ－ＡＣ変換されて前記フルブリッジ回路から出力される電圧共振回路と、
    　１次側及び２次側を有する絶縁型高周波トランスと、
    　前記フルブリッジ回路と前記第１のトランスの１次側との間にインダクタンス及びキャパシタから成り、共振電流が流れる直列回路が接続されて前記電圧共振回路における電圧共振を継続させる電流共振回路と、
    　前記絶縁型高周波トランスの２次側に接続されている整流回路と、
    　この整流回路に接続されている平滑回路と、
    　前記第１及び第４のスイッチング素子をスイッチングする第１のスイッチング信号を生成し、また、第２及び第３のスイッチング素子をスイッチングする第２のスイッチング信号を生成して前記電圧共振回路における電圧共振を維持する第１のドライバ回路であって、前記第１のスイッチング信号は印加電圧が略零の第１のタイミングで前記第１及び第４のスイッチング素子をターンオフし、また、印加電圧が略零の第４のタイミングで前記第１及び第４のスイッチング素子をターンオンし、また、前記第２のスイッチング信号は印加電圧が略零の前記第１のタイミングに続く第２のタイミングで前記第２及び第３のスイッチング素子をターンオンし、また、印加電圧が略零の前記第４のタイミングに先立つ第３のタイミングで前記第２及び第３のスイッチング素子をターンオフする第１のドライバ回路と、
    　前記整流回路から出力された出力電圧に依存して前記第１及び第２のスイッチング信号の周波数を前記電流共振回路における共振周波数よりも低い範囲内で選定する制御回路であって、目標電圧に比べて前記出力電圧が大きい際に基準周波数よりも高い周波数を設定し、目標電圧に比べて前記出力電圧が小さい際に基準周波数よりも低い周波数を設定する制御回路と、
    　を具備することを特徴とするＤＣ―ＤＣコンバータ。     A full-bridge circuit in which a first series circuit consisting of first and third switching elements that are alternately switched and a second series circuit consisting of second and fourth switching elements that are alternately switched are connected in parallel. DC power is input to the full bridge circuit from a low-voltage DC power source whose output voltage varies, and the DC power is DC-AC converted and output from the full bridge circuit. A voltage resonant circuit to be
    An insulated high-frequency transformer having a primary side and a secondary side;
    A current resonance circuit comprising an inductance and a capacitor between the full bridge circuit and the primary side of the first transformer, connected to a series circuit through which a resonance current flows, and continuing voltage resonance in the voltage resonance circuit;
    A rectifier circuit connected to the secondary side of the insulated high-frequency transformer;
    A smoothing circuit connected to the rectifier circuit;
    A first switching signal for switching the first and fourth switching elements is generated, and a second switching signal for switching the second and third switching elements is generated to generate voltage resonance in the voltage resonance circuit. Wherein the first switching signal turns off the first and fourth switching elements at a first timing when the applied voltage is substantially zero, and the applied voltage is substantially zero. The first and fourth switching elements are turned on at a fourth timing, and the second switching signal is applied at the second timing following the first timing when the applied voltage is substantially zero. The third switching element is turned on, and at the third timing preceding the fourth timing when the applied voltage is substantially zero, 3 of a first driver circuit for turning off the switching element,
    A control circuit that selects a frequency of the first and second switching signals within a range lower than a resonance frequency in the current resonance circuit depending on an output voltage output from the rectifier circuit, the comparison circuit comparing with a target voltage A control circuit that sets a frequency higher than a reference frequency when the output voltage is large, and sets a frequency lower than the reference frequency when the output voltage is small compared to a target voltage;
    A DC-DC converter comprising:
  2. 　　交互にスイッチングされる第１及び第２のスイッチング素子から成る第１の直列回路でハーフブリッジ回路を構成する第１のスイッチング回路を含み、出力電圧が変動する低電圧直流電源から直流電力が前記ハーフブリッジ回路に入力され、この直流電力がＤＣ－ＡＣ変換されて前記ハーフブリッジ回路から出力される電圧共振回路と、
    　１次側及び２次側を有する絶縁型高周波トランスと、
    　前記ハーフブリッジ回路と前記第１のトランスの１次側との間にインダクタンス及びキャパシタから成り、共振電流が流れる直列回路が接続されて前記電圧共振回路における電圧共振を継続させる電流共振回路と、
    　前記絶縁型高周波トランスの２次側に接続されている整流回路と、
    　この整流回路に接続されている平滑回路と、
    　前記第１のスイッチング素子をスイッチングする第１のスイッチング信号を生成し、また、第２のスイッチング素子をスイッチングする第２のスイッチング信号を生成して前記電圧共振回路における電圧共振を維持する第１のドライバ回路であって、前記第１のスイッチング信号は印加電圧が略零の第１のタイミングで前記第１のスイッチング素子をターンオフし、また、印加電圧が略零の第４のタイミングで前記第１のスイッチング素子をターンオンし、また、前記第２のスイッチング信号は印加電圧が略零の前記第１のタイミングに続く第２のタイミングで前記第２のスイッチング素子をターンオンし、また、印加電圧が略零の前記第４のタイミングに先立つ第３のタイミングで前記第２のスイッチング素子をターンオフする第１のドライバ回路と、
    　前記整流回路から出力された出力電圧に依存して前記第１のスイッチング信号の周波数を前記電流共振回路における共振周波数よりも低い範囲内で選定する制御回路であって、目標電圧に比べて前記出力電圧が大きい際に基準周波数よりも高い周波数を設定し、目標電圧に比べて前記出力電圧が小さい際に基準周波数よりも低い周波数を設定する制御回路と、
    　を具備することを特徴とするＤＣ―ＤＣコンバータ。     A first switching circuit that constitutes a half-bridge circuit with a first series circuit composed of first and second switching elements that are alternately switched, and a DC power is supplied from the low-voltage DC power source whose output voltage varies. A voltage resonance circuit that is input to the bridge circuit, and the DC power is DC-AC converted and output from the half-bridge circuit;
    An insulated high-frequency transformer having a primary side and a secondary side;
    A current resonance circuit comprising an inductance and a capacitor between the half-bridge circuit and the primary side of the first transformer, connected to a series circuit in which a resonance current flows, and continuing voltage resonance in the voltage resonance circuit;
    A rectifier circuit connected to the secondary side of the insulated high-frequency transformer;
    A smoothing circuit connected to the rectifier circuit;
    A first switching signal for switching the first switching element is generated, and a second switching signal for switching the second switching element is generated to maintain voltage resonance in the voltage resonance circuit. In the driver circuit, the first switching signal turns off the first switching element at a first timing when the applied voltage is substantially zero, and the first switching signal is turned off at the fourth timing when the applied voltage is substantially zero. And the second switching signal turns on the second switching element at a second timing following the first timing when the applied voltage is substantially zero, and the applied voltage is substantially reduced. A first driver that turns off the second switching element at a third timing preceding the fourth timing at zero. And bar circuit,
    A control circuit that selects a frequency of the first switching signal within a range lower than a resonance frequency in the current resonance circuit depending on an output voltage output from the rectifier circuit, wherein the output is compared with a target voltage. A control circuit that sets a frequency higher than the reference frequency when the voltage is large, and sets a frequency lower than the reference frequency when the output voltage is small compared to the target voltage;
    A DC-DC converter comprising:
  3. 　　前記出力電圧が出力される第１及び第２の出力端子と、
    　高周波トランスは、2次側に高圧側端子、低圧側端子及び中間端子を有し、
    　前記整流回路は、交互にスイッチングされる第５及び第６のスイッチング素子であって、前記第５のスイッチング素子が前記高圧側端子と前記第１の出力端の間に接続され、前記第６のスイッチング素子が前記中間端子と前記第２の出力端の間に接続され、
    　前記第１及び第２のスイッチング信号に同期する第３及び第４のスイッチング信号を夫々前記第５及び第６のスイッチング素子に与えて導通電流が略零並びに印加電圧が略零のタイミングで前記第５及び第６のスイッチング素子をターンオン及びターンオフする第２のドライバ回路を更に具備することを特徴とする請求項１又は請求項２に記載のＤＣ－ＤＣコンバータ。     First and second output terminals from which the output voltage is output;
    The high-frequency transformer has a high-voltage side terminal, a low-voltage side terminal, and an intermediate terminal on the secondary side,
    The rectifier circuit is fifth and sixth switching elements that are alternately switched, wherein the fifth switching element is connected between the high-voltage side terminal and the first output end, A switching element is connected between the intermediate terminal and the second output end;
    The third and fourth switching signals synchronized with the first and second switching signals are applied to the fifth and sixth switching elements, respectively, and the conduction current is substantially zero and the applied voltage is substantially zero. 3. The DC-DC converter according to claim 1, further comprising a second driver circuit for turning on and off the fifth and sixth switching elements.
  4. 　　前記出力電圧が出力される第１及び第２の出力端子と、
    　高周波トランスは、2次側に高圧側及び低圧側端子を有し、
    　前記整流回路は、第１及び第２の出力端子間に接続された交互にスイッチングされる第５及び第６のスイッチング素子の第１の直列回路並びに第１及び第２の出力端子間に接続された交互にスイッチングされる第７及び第８のスイッチング素子の第２の直列回路であって、前記第５及び第６のスイッチング素子の接続点が前記高圧側端子に接続され、第７及び第８のスイッチング素子の接続点が前記低圧側端子に接続され、
    　前記第１及び第２のスイッチング信号に同期する第３のスイッチング信号を前記第５及び第８のスイッチング素子に与えて導通電流が略零並びに印加電圧が略零のタイミングで前記第５及び第８のスイッチング素子をターンオン及びターンオフし、前記第１及び第２のスイッチング信号に同期する第４のスイッチング信号を夫々前記第６及び第７のスイッチング素子に与えて導通電流が略零並びに印加電圧が略零のタイミングで前記第５及び第７のスイッチング素子をターンオン及びターンオフするする第２のドライバ回路を更に具備することを特徴とする請求項１又は請求項２に記載のＤＣ－ＤＣコンバータ。     First and second output terminals from which the output voltage is output;
    The high-frequency transformer has a high-voltage side and a low-voltage side terminal on the secondary side,
    The rectifier circuit is connected between a first series circuit of fifth and sixth switching elements alternately connected between the first and second output terminals and between the first and second output terminals. A second series circuit of seventh and eighth switching elements that are alternately switched, wherein a connection point of the fifth and sixth switching elements is connected to the high-voltage side terminal, The connection point of the switching element is connected to the low voltage side terminal,
    A third switching signal synchronized with the first and second switching signals is supplied to the fifth and eighth switching elements, and the fifth and eighth timings are set at a timing when the conduction current is substantially zero and the applied voltage is substantially zero. The switching elements are turned on and off, and a fourth switching signal synchronized with the first and second switching signals is applied to the sixth and seventh switching elements, respectively, so that the conduction current is substantially zero and the applied voltage is substantially 3. The DC-DC converter according to claim 1, further comprising a second driver circuit that turns on and off the fifth and seventh switching elements at zero timing.
  5. 　　前記インダクタンスは、前記第１のトランスが有するリーケージリアクタンスに相当することを特徴とする請求項１又は請求項２に記載のＤＣ－ＤＣコンバータ。 3. The DC-DC converter according to claim 1, wherein the inductance corresponds to a leakage reactance of the first transformer.
  6. 　前記第１及び第２のスイッチング素子は、夫々第１及び第２の容量を有し、
    　前記第１の容量には、前記第１のタイミングで充電電流が流入し、第３のタイミングで充電電流が流出され、前記第２及び第３のタイミングの間においては、前記第１の容量における流入流出電流が零に維持され、
    　前記第２の容量では、前記第１のタイミングで充電電流が流出され、前記第３のタイミングで充電電流が流入し、前記第４のタイミング及び次のサイクルにおける第１タイミングの間においては、前記第２の容量における流入流出電流が零に維持されることを特徴とする請求項２に記載のＤＣ－ＤＣコンバータ。     The first and second switching elements have first and second capacitors, respectively.
    A charging current flows into the first capacitor at the first timing, a charging current flows out at the third timing, and in the first capacitor between the second and third timings. The inflow / outflow current is maintained at zero,
    In the second capacitor, the charging current flows out at the first timing, the charging current flows in at the third timing, and between the fourth timing and the first timing in the next cycle, 3. The DC-DC converter according to claim 2, wherein the inflow / outflow current in the second capacity is maintained at zero.
  7. 　前記第１、第２、第３及び第４のスイッチング素子は、夫々第１、第２、第３及び第４の容量を有し、
    　前記第１及び第４の容量には、前記第１のタイミング（ｔ２，ｔ１６）で充電電流が流入し、第３のタイミングで充電電流が流出され、前記第２及び第３のタイミングの間においては、前記第１及び第４の容量における流入流出電流が零に維持され、
    　前記第２及び第３の容量では、前記第１のタイミングで充電電流が流出され、前記第３のタイミングで充電電流が流入し、前記第４のタイミング及び次のサイクルにおける第１タイミングの間においては、前記第２及び第３の容量における流入流出電流が零に維持されることを特徴とする請求項１に記載のＤＣ－ＤＣコンバータ。     The first, second, third and fourth switching elements have first, second, third and fourth capacitors, respectively.
    A charging current flows into the first and fourth capacitors at the first timing (t2, t16), a charging current flows out at the third timing, and between the second and third timings. The inflow and outflow currents in the first and fourth capacities are maintained at zero,
    In the second and third capacitors, the charging current flows out at the first timing, the charging current flows in at the third timing, and between the fourth timing and the first timing in the next cycle. 2. The DC-DC converter according to claim 1, wherein the inflow / outflow current in the second and third capacitors is maintained at zero.
PCT/JP2010/053269 2009-02-27 2010-03-01 Dc-dc converter WO2010098486A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-046143 2009-02-27
JP2009046143 2009-02-27

Publications (1)

Publication Number Publication Date
WO2010098486A1 true WO2010098486A1 (en) 2010-09-02

Family

ID=42665688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/053269 WO2010098486A1 (en) 2009-02-27 2010-03-01 Dc-dc converter

Country Status (1)

Country Link
WO (1) WO2010098486A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976952A (en) * 2010-10-08 2011-02-16 刘闯 Series resonance DC/DC converter of photovoltaic system
CN103441684A (en) * 2013-09-13 2013-12-11 刘闯 Fluctuating electric energy recycled high-accuracy DC/DC (direct current/direct current) converter
JP2020202645A (en) * 2019-06-10 2020-12-17 新電元工業株式会社 Converter and control method thereof
JP2020202644A (en) * 2019-06-07 2020-12-17 新電元工業株式会社 converter
CN112673561A (en) * 2018-09-13 2021-04-16 日产自动车株式会社 Power conversion device and control method for power conversion device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311743A (en) * 1993-04-23 1994-11-04 Sanken Electric Co Ltd Dc-dc converter
JPH07274498A (en) * 1994-03-31 1995-10-20 Sanken Electric Co Ltd Resonance-type switching power source
JP2006204048A (en) * 2005-01-24 2006-08-03 Shindengen Electric Mfg Co Ltd Series resonance converter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06311743A (en) * 1993-04-23 1994-11-04 Sanken Electric Co Ltd Dc-dc converter
JPH07274498A (en) * 1994-03-31 1995-10-20 Sanken Electric Co Ltd Resonance-type switching power source
JP2006204048A (en) * 2005-01-24 2006-08-03 Shindengen Electric Mfg Co Ltd Series resonance converter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101976952A (en) * 2010-10-08 2011-02-16 刘闯 Series resonance DC/DC converter of photovoltaic system
CN103441684A (en) * 2013-09-13 2013-12-11 刘闯 Fluctuating electric energy recycled high-accuracy DC/DC (direct current/direct current) converter
CN112673561A (en) * 2018-09-13 2021-04-16 日产自动车株式会社 Power conversion device and control method for power conversion device
JP2020202644A (en) * 2019-06-07 2020-12-17 新電元工業株式会社 converter
JP7329971B2 (en) 2019-06-07 2023-08-21 新電元工業株式会社 converter
JP2020202645A (en) * 2019-06-10 2020-12-17 新電元工業株式会社 Converter and control method thereof
JP7329972B2 (en) 2019-06-10 2023-08-21 新電元工業株式会社 Converter and converter control method

Similar Documents

Publication Publication Date Title
US7333348B2 (en) DC-DC converter
Wang A novel ZCS-PWM flyback converter with a simple ZCS-PWM commutation cell
US8125158B2 (en) Insulation type AC-DC converter and LED DC power supply device using the same
de Melo et al. A modified SEPIC converter for high-power-factor rectifier and universal input voltage applications
Oruganti et al. Soft-switched DC/DC converter with PWM control
CN101588139A (en) High power factor isolated buck-type power factor correction converter
KR20070038921A (en) Switching power supply circuit
WO2010107060A1 (en) Dc-dc converter
JP6012822B1 (en) Power converter
JP2007221915A (en) Dc-dc converter
JP5424307B2 (en) Isolated DC-DC converter
WO2010098486A1 (en) Dc-dc converter
JP2013236428A (en) Dc conversion device
JP2012010528A (en) Load driving device
TWI790657B (en) Controlling reverse current in switched mode power supplies to achieve zero voltage switching
JP2004242491A (en) Switching power supply circuit
JP5457204B2 (en) Full bridge composite resonance type DC-DC converter
JP5554591B2 (en) Power supply
JP5012905B2 (en) Isolated DC-DC converter
JP5831275B2 (en) Power converter and driving method thereof
JP3934654B2 (en) DC-DC converter
KR102306880B1 (en) High efficiency isolated pfc converter
JP2005304289A (en) Dc-dc converter
Khodabakhsh et al. A comparative study of conventional and T-type ZVS-PWM full-bridge converters
Ahmadi et al. Single-Switch Soft-Switched High-Step-Down Converter With Self-Driven Synchronous Rectifier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10746363

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10746363

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP