JP3934654B2 - DC-DC converter - Google Patents

Description

    The present invention relates to a DC-DC converter, and more particularly to an insulated DC-DC converter for a distributed power source that converts power from a distributed DC power source into medium-power capacity power, and a connection using the DC-DC converter. Related to inverters.

    A distributed power source that converts power from a distributed DC power source, for example, a household fuel cell, a solar power generation system, or a wind power generation system into a medium power capacity (0.3 kW to 10 kW) power, includes a power conversion device such as an inverter. In this power converter, insulation between the input (primary side) and the system (secondary side) is desired. Even if a high-frequency insulation type converter is used in such a power conversion device, there is a problem that efficiency is deteriorated as compared with a non-insulation type converter.

  In addition, since a power source such as a fuel cell inevitably increases the frequency of operation at an output less than the rated value, not only the efficiency is improved at the rated output as described above, but also the small power of 50% or less of the rated output is small. Improving efficiency during output operation is an important issue.

  The present invention has been made to solve the above problems, and an object thereof is to provide a highly efficient DC-DC converter.

According to this invention,
DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A first voltage resonance circuit for converting and outputting;
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
A first insulated high-frequency transformer having a primary side and a secondary side, into which an output voltage from the first voltage resonance circuit is input;
A first current resonance circuit connected to the secondary side of the first transformer;
A first rectifier circuit for rectifying an output current output from the first current resonance circuit;
A first smoothing circuit that outputs a first output voltage by smoothing the output voltage from the first rectifier circuit,
A second voltage resonance including a second switching circuit composed of second switching elements connected to be alternately switched, and DC-AC converted and output DC power from the low-voltage DC power supply Circuit,
A second driver for maintaining voltage resonance in the second voltage resonance circuit by turning on and off the second switching element at a timing when the conduction current is zero and the applied voltage is zero;
A second insulated high-frequency transformer having a primary side and a secondary side, into which an output voltage from the second voltage resonance circuit is input;
A second current resonance circuit connected to the secondary side of the second transformer;
A second rectifier circuit for rectifying an output current output from the second current resonance circuit;
A second smoothing circuit for outputting a second output voltage by smoothing the output voltage from the second rectifier circuit,
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a third switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the modulated voltage from the pulse width modulation circuit and outputting it as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the third switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by the on operation of the third switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DC-DC converter is provided.

Moreover, according to this invention,
DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A voltage resonant circuit that converts and outputs, and
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
An insulated high-frequency transformer having a primary side and a secondary side, into which the output voltage from the first voltage resonance circuit is input;
First and second current resonance circuits connected to the secondary side of the first transformer;
First and second rectifier circuits for rectifying output currents output from the first and second current resonance circuits;
First and second smoothing circuits for smoothing output voltages from the first and second rectifier circuits and outputting first and second output voltages, respectively;
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a second switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the output voltage from the pulse width modulation circuit and outputting the smoothed output voltage as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the second switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by an on operation of the second switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DC-DC converter is provided.

Furthermore, according to the present invention,
DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A voltage resonant circuit that converts and outputs, and
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
First and second isolated high-frequency transformers, each having a primary side and a secondary side, into which an output voltage from the first voltage resonance circuit is input;
First and second current resonance circuits respectively connected to the secondary sides of the first and second transformers;
First and second rectifier circuits for rectifying output currents output from the first and second current resonance circuits;
First and second smoothing circuits for smoothing output voltages from the first and second rectifier circuits and outputting first and second output voltages, respectively;
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a second switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the output voltage from the pulse width modulation circuit and outputting the smoothed output voltage as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the second switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by an on operation of the second switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DCDC converter is provided.

  According to the DC-DC converter of the present invention, high-efficiency conversion without switching loss can be realized.

  Hereinafter, a DC-DC converter according to an embodiment of the present invention will be described with reference to the drawings as necessary.

    Hereinafter, a DC-DC converter according to an embodiment of the present invention and a connected inverter using the same will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of a distributed power supply system 1 to which a connected inverter 2 including a converter unit 10 (DC-DC converter) and an inverter unit 20 that performs DC-AC conversion according to an embodiment of the present invention is applied. Show.

  In the distributed power supply system 1 in FIG. 1, the output (DC power) from a DC power supply 3 with a fluctuation in output, for example, a fuel cell, a solar cell, or wind power generation, is input to a connected inverter as a power conditioner, DC-DC conversion is performed in the converter unit in the interconnection inverter, and the converted DC output is converted into an AC output and a relatively small output (for example, about 0.3 kW to several tens of kW) by the inverter unit 20 to the load. For example, it is output as a commercial voltage (system voltage) to a household load. Here, the commercial voltage (system voltage) corresponds to 101V or 202V (in the case of single-phase three-wire connection) in Japan, and corresponds to 115V or 230V in the United States.

  In the fuel cell system, an input voltage of 80 V or less, currently 20 V to 60 V, is input to the converter unit 10, and the output voltage Vout is highest when there is no load, and the voltage becomes 25 as the load increases. % To about 30%. Moreover, in a solar power generation system provided with a solar cell module, the voltage of 17-21V is output by one solar cell module, and 170V-350V is output as a system. The output voltage Vout varies in the range of 120V to 450V. Furthermore, in the wind power generation system, an output voltage Vout of about 50V is generated, but when the blades are rotating, the output varies within a range of 30V to 50V.

  FIG. 2 is a block diagram showing a circuit configuration of converter unit 10 according to the embodiment of the present invention.

  The converter unit 10 is a high-frequency insulation type DC-DC converter, and is disposed between the high-frequency transformer 12, the DC power source 3 shown in FIG. 1 and the primary side of the high-frequency transformer 12, and outputs a high-frequency voltage. A voltage resonance circuit 11, a current resonance circuit 13 disposed on the secondary side of the high-frequency transformer 12, and a rectification circuit 14 that rectifies the output current from the current resonance circuit 13 are provided. The converter unit 10 further includes a switching control unit 17 that controls the voltage resonance circuit 11 in accordance with the output voltage Vout from the rectifier circuit 14. The DC-DC converter shown in FIG. 2 differs from the DC-DC converter applied to a normal high voltage power supply in that the voltage resonance circuit 11 is arranged on the primary side and the current resonance circuit 13 outputs a high voltage. Located on the next side. As will be described later, the output of this DC-DC converter is controlled, and a substantially constant voltage, for example, 400 V is output as a target voltage from the DC-DC converter.

  In a DC-DC converter applied to a normal high-voltage power supply, a current resonance circuit and a voltage resonance circuit are arranged on the primary side of the high-frequency transformer 12. However, since the DC-DC converter unit 10 shown in FIG. 2 is applied to the power supply 3 having a relatively low voltage, a current resonance circuit is arranged on the primary side of the high-frequency transformer 12 in the same manner as a normal DC-DC converter. In this case, if the amount of output power is increased, the current inevitably increases and the current value becomes too high. Therefore, in the converter 10 shown in FIG. 2, the voltage resonance circuit 11 is disposed on the primary side of the high-frequency transformer 12, and the current resonance circuit 13 is disposed on the secondary side of the high-frequency transformer 12 that outputs a high voltage. Assuming that the interconnection inverter is used in Japan, the DC-DC converter unit 10 is connected to the interconnection inverter unit of the normal system 200V, and a voltage of about 370V is output from the secondary side of the high-frequency transformer 12. The

  The voltage resonance circuit 11 disposed on the primary side includes a switching element such as an FET (field effect transistor) or an IGBT (insulated gate / bipolar transistor), and between the source and drain of the switching element (in the case of IGBT, an emitter-collector). A capacitor is connected between the voltage resonance circuit 11 and the voltage resonance circuit 11 is configured to perform voltage resonance. The current resonance circuit 13 arranged on the secondary side is configured to resonate by series resonance.

  The operation of the circuit in the circuit configuration including the switching element as described above will be briefly described below.

  In the voltage resonance circuit 11, when the output from the power source is decreased, the operating frequency of the switching element is increased so as to make the output voltage (high frequency voltage) Vout substantially constant. As the operating frequency increases, the impedance of the current resonance circuit is increased. That is, in the current resonance circuit, the output becomes the largest at the resonance frequency, and the frequency increases as the output becomes smaller.

  The switching loss in the voltage resonance circuit will be described in more detail with reference to FIGS. 3A and 3B. FIG. 3A shows the current and voltage waveform on the secondary side of the high-frequency transformer in the rated output mode where the output from the voltage resonance circuit is large, and FIG. 3B shows 2 of the high-frequency transformer in the small output mode where the output from the voltage resonance circuit is small. The current and voltage waveforms on the secondary side are shown. In the rated output mode in which the output from the power supply is sufficiently large, the switching element is operated at a predetermined operating frequency and the output current is changed in a sine wave as shown in FIG. 3A, whereas the output from the voltage resonance circuit is In the small output mode in which the output is reduced due to decrease, the current waveform becomes distorted and distorted as shown in FIG. 3B showing the current and voltage waveform on the secondary side of the high frequency transformer, and the frequency is increased.

  In the DC-DC converter according to the present embodiment, by changing the operating frequency of the current resonance circuit 13 and controlling the energy conversion of the DC-DC converter, the voltage resonance circuit 11 modulates the voltage to maintain resonance. However, high-efficiency zero voltage switching (ZVS) is achieved. As described above, in the embodiment of the present invention, when the frequency is changed, the operating point of the current resonance circuit 13 on the secondary side moves, the power increases when the frequency decreases, and the power decreases when the frequency increases. It uses the property that the amount of transmitted energy changes. Therefore, a highly efficient DC-DC converter can be realized.

The voltage resonance circuit 11 shown in FIG.
(1) Full circuit (2) Half bridge (3) Push-pull Three circuit configurations can be adopted. Specific circuit examples of these voltage resonance circuits are shown in FIGS.

Further, the current resonance circuit 13 shown in FIG.
(4) Full bridge rectifier circuit (5) Two circuit configurations of voltage doubler rectifier circuit can be adopted. Specific circuit examples of the current resonance circuit 13 are shown in FIGS.

  As is clear from the above description, there are a total of six combinations of the voltage resonance circuit 11 and the current resonance circuit 13, and the DC-DC converter circuit 10 shown in FIG. Can do.

  A circuit example of the voltage resonance circuit 11 will be described with reference to FIGS. 4 to 6, an ordinary electrolytic capacitor is used as the storage capacitor C1, but the description is omitted because it is common in each circuit. A case where an FET is used as the switching element will be described.

  FIG. 4 shows a first circuit example in which the voltage resonance circuit 11 is configured by a full bridge circuit.

  In the voltage resonance circuit shown in FIG. 4, the switching element Q1 and the switching element Q2 are connected in series, and the switching element Q3 and the switching element Q4 are connected in series. In the switching elements Q1 to Q4, capacitors C2 to C5 are connected in parallel between the source and drain of the switching elements, respectively. The series circuit of the switching elements Q1 and Q2 and the series circuit of the switching elements Q3 and Q4 are respectively connected in parallel to the DC power supply on the input side so as to form a full bridge circuit. That is, the drains of the switching elements Q1 and Q3 are connected to the positive side of the power supply, and the sources of the switching elements Q2 and Q4 are connected to the negative side of the power supply.

  Further, a connection part between the switching element Q1 and the switching element Q2 is connected to one end part of the transformer T1 on the output side, and a connection part between the switching element Q3 and the switching element Q4 is connected to the other end part of the transformer T1.

  In the full bridge circuit shown in FIG. 4, a switching control unit 17 is provided to turn on and off the switching elements Q1 to Q4 at a predetermined timing. The switching control unit 17 includes drivers DR1, DR2, MCU (micro control unit) 18, and interface IF. In the switching control unit 17, the output voltage Vout of the DC-DC converter circuit 10 is detected, and this detection signal is supplied to the MCU 18 via an interface IF, for example, an isolation amplifier, and the MCU 18 performs frequency control and phase control. Control signals are output to the drivers DR1 and DR2. Drivers DR1 and DR2 provide control signals to the gates of switching elements Q1 to Q4 as feedback signals to control switching elements Q1 to Q4.

  In the voltage resonance circuit shown in FIG. 4, a series connection of switching elements Q1 and Q2, a series connection of switching elements Q3 and Q4, and a series connection of capacitors C10 and C11 are further connected in parallel. One end of the choke coil LC is connected to the connection point of the capacitors C10 and C11, and the other end of the choke coil LC is connected to the intermediate point of the primary coil of the transformer T1. In this specification, a circuit including the capacitors C10 and C11 and the choke coil LC is referred to as a “commutation circuit”.

  This commutation circuit is provided in order to improve the efficiency at the time of small output of several percent to 30% of the rated output, and voltage resonance is maintained by this commutation circuit at the time of small output. Specifically, when a relatively high output such as a rated output is used, resonance is performed by a resonance circuit, that is, a resonance circuit formed by, for example, the transistor Q1 and the capacitor C2. Therefore, resonance is maintained by the choke coil LC and the capacitors C1, C2, C3, C4, and C5. Specifically, when the power is reduced, the current flowing through the transformer is reduced, but this current is supplemented by the current from the choke coil LC, so that resonance is maintained.

  Therefore, by providing a commutation circuit between the voltage resonance circuit 11 and the transformer as described above, resonance can be maintained even when the output is small, and high conversion efficiency can be realized even when the output is small. it can.

  The operation of the circuit shown in FIG. 4 will be described later.

  FIG. 5 shows a second circuit example in which the voltage resonance circuit 11 is configured by a half-bridge circuit. In FIG. 5, the same circuit components and the same parts as those in FIG.

  In the voltage resonance circuit shown in FIG. 5, a switching element Q1 and a switching element Q2 are connected in series, and capacitors C2 and C3 are connected in parallel between the source and drain of the switching element, respectively. Yes. In addition, in the series circuit of the switching elements Q1 and Q2, capacitors C6 and C7 connected in series are connected in parallel to form a half bridge circuit.

  A connection portion between the switching elements Q1 and Q2 is connected to one end portion of the transformer T1, and a connection portion between the capacitors C6 and C7 is connected to the other end portion of the transformer T1.

  The half-bridge circuit shown in FIG. 5 is provided with a driver DR1 for turning on / off the switching elements Q1, Q2 at a predetermined timing. The output voltage Vout of the DC-DC converter circuit 10 is detected and this signal is applied to the MCU 18 via the interface IF, and a control signal for frequency control is output from the MCU 18 to the driver DR1. From the driver DR1, a control signal is given as a feedback signal to the gates of the switching elements Q1, Q2, and the switching elements Q1, Q2 are controlled.

  FIG. 6 shows a third circuit example in which the voltage resonance circuit 11 is configured as a push-pull type. FIG. 6 shows a push-pull type voltage resonance circuit. In FIG. 6, the same reference numerals are given to the same circuit components and the same parts as those in FIG.

  In FIG. 6, the drain of the switching element Q1 is connected to one end of the transformer T1, the drain of the switching element Q2 is connected to the other end of the transformer T1, and the sources of the switching elements Q1 and Q2 are connected to the negative side of the DC power supply. It is connected. Further, the positive side of the DC power supply is connected to an intermediate portion between one end and the other end of the transformer T1.

  The push-pull type voltage resonance circuit 11 shown in FIG. 6 is provided with a driver DR1 in order to turn on and off the switching elements Q1 and Q2 at a predetermined timing. The output voltage Vout of the DC-DC converter circuit 10 is detected and this signal is applied to the MCU 18 via the interface IF, and a control signal for frequency control is output from the MCU 18 to the driver DR1. From the driver DR1, a control signal is given as a feedback signal to the gates of the switching elements Q1, Q2, and the switching elements Q1, Q2 are controlled.

  Next, a specific circuit example of the current resonance circuit 13 will be described with reference to FIGS.

  FIG. 7 shows a fourth circuit example in which the full bridge rectifier circuit 14 and the current resonance circuit 13 are combined.

  The current resonance circuit 13 is configured by connecting an inductor L and a capacitor C8 in series. In the current resonance circuit 13, an inductor L is connected to one end of the transformer T1, and a capacitor C8 is connected to the bridge rectifier circuit 14 on the output side. In the bridge rectifier circuit 14, the output side of the capacitor C8 is connected to the connection part of the diode D1 and the diode D2 connected in series, and the other end of the transformer T1 is connected to the connection part of the diode D3 and the diode D4. The diodes D1 and D2 are connected in series, the diodes D3 and D4 are connected in series, and the series connection of the diodes D1 and D2 and the series connection of D3 and D4 are connected in parallel to form a bridge circuit. On the output side of the bridge circuit, a smoothing capacitor C9 is connected in parallel to the bridge circuit. As the smoothing capacitor C9, an electrolytic capacitor is usually used. An interface IF is connected to the smoothing capacitor C9, and an output voltage signal Vout is output to the interface IF.

  FIG. 8 shows a fifth circuit example in which the step-up bridge circuit 14 and the current resonance circuit 13 are combined. In FIG. 8, the same circuit parts and the same parts as those of FIG.

  In the current resonance circuit 13, an inductor L and a capacitor C8 are connected in series as in the circuit shown in FIG. 7, the inductor L is connected to one end of the transformer T1, and the capacitor C8 is connected to the output side. In the step-up bridge circuit 14, the diode D1 and the diode D2 are connected in series, and the output side of the capacitor C8 is connected to the connection part of the diodes D1 and D2 connected in series. The other end of the transformer T1 is connected to the anode side of the diode D2, and is connected to one end of the capacitor C9. The anode side of the diode D2 is connected to one end of the capacitor C9, the cathode side of the diode D1 is connected to the other end of the capacitor C9, and the smoothing capacitor C9 is connected in parallel to the series circuit of the diodes D1 and D2. . The smoothing capacitor C9 is connected to the interface IF of the switching control unit 17, and the output voltage signal Vout is output to the interface IF.

  The operation of the DC-DC converter in the rated output mode, the small output mode, and the no-load mode will be described with reference to FIGS. FIG. 9 shows a circuit configuration of a DC-DC converter in which the full bridge rectifier circuit 14 shown in FIG. 7 is combined with the full bridge voltage resonance circuit 11 shown in FIG. 9, the same parts as those shown in FIGS. 4 and 7 are denoted by the same reference numerals, and the description thereof is omitted. FIG. 10 shows functional blocks for explaining the function of the MCU 18 of the switching control unit 17.

  As shown in FIG. 10, in the MCU 18, the output voltage signal Vout from the rectifier circuit 14 is compared with the target voltage Vref. When no load is connected to the rectifier circuit 14, the DC-DC converter is operated in the no-load mode. When a load is connected to the rectifier circuit 14 and an output voltage that falls within the rated voltage range corresponding to the target voltage Vref is detected, the DC-DC converter 11 is operated in the rated output mode. Furthermore, when a load is connected to the rectifier circuit 14 but an output voltage signal Vout slightly lower than the rated voltage corresponding to the target voltage Vref is detected, the DC-DC converter is operated in the small output mode. .

  In the no-load mode, the set target voltage Vref and the output voltage signal Vout are compared by the comparator 34. In the no-load mode, since the output voltage signal Vout is sufficiently larger or substantially equal to the target voltage Vref, a frequency fa larger than the resonance frequency f0 of the voltage resonance circuit shown in FIG. 9 is selected from the frequency table 30. From the phase table 32, the first and third FETs Q1 and Q3 are operated in the same phase, and the second and fourth FETs Q2 and Q4 are operated in the same phase. The pulse generator 35 applies the first to fourth gate pulses to the corresponding FETs Q1 to Q4 at the selected phase and frequency. In this no-load mode, basically, the DC-DC converter is operated so that the primary side of the high-frequency transformer T1 is alternately connected to the positive side and the negative side of the DC voltage source.

  In the rated mode, since the output voltage signal Vout compared by the comparator 34 is lower than the target voltage Vref, the frequency f0 substantially equal to the resonance frequency f0 of the voltage resonance circuit shown in FIG. In addition, the phase table 32 selects a phase in which the first and fourth FETs Q1 and Q4 are operated in the same phase, and the second and third FETs Q2 and Q3 are operated in the same phase. Here, a phase difference of 180 degrees is given to the first and third FETs Q1 and Q3, and a timing at which a phase difference of 180 degrees is given also to the second and fourth FETs Q2 and Q4 is the phase table 32. Selected from. The pulse generator 35 applies the first to fourth gate pulses to the corresponding FETs Q1 to Q4 at the selected phase and frequency. In this rated mode, basically, the DC-DC converter is operated so that both ends of the primary side of the high-frequency transformer T1 are periodically switched and connected to the positive side and the negative side of the DC voltage source.

  In the small output mode, since the output voltage signal Vout is higher than the target voltage Vref compared by the comparator 34, a frequency fb larger than the resonance frequency f0 of the voltage resonance circuit shown in FIG. The first and third FETs Q1 and Q4 have a phase difference between 0 to 180 degrees determined according to the output, and the phase where the second and fourth FETs Q2 and Q4 are selected from the phase table 32 Is done. The pulse generator 35 applies the first to fourth gate pulses to the corresponding FETs Q1 to Q4 at the selected phase and frequency. In this small output mode, basically, both ends of the primary side of the high-frequency transformer T1 are periodically switched to and connected to the positive side and the negative side of the DC voltage source and receive energy supply from the commutation circuit therebetween. The DC-DC converter is operated.

  In order to suppress the output of the DC-DC converter, the frequency selected from the frequency table 30 is selected to be high, and the impedance of the current resonance circuit is shifted from the resonance point. Therefore, the frequency selected in the frequency table together with the target voltage may be selected from outside the MCU 18.

  First, the operation of the DC-DC converter in the rated output mode in which the DC power supply 3 is rated and generates an output voltage (target voltage Vout) will be described with reference to FIGS. 11 (A) to 11 (H).

  When the DC-DC converter shown in FIG. 9 is connected to the DC power source 3 via a switch (not shown), charging of the capacitor C1 is started. Similarly, charging of the series circuit of capacitors C2 and C3 and the series circuit of capacitors C4 and C5 connected in parallel to the capacitor C1 is also started.

  At a certain time t1, a control pulse signal is given to the driver circuits DR1 and DR2, and the driver circuits DR1 and DR2 are operated. At this time t1, the first and fourth gate signals shown in FIG. 11E are switched from the high level to the low level in synchronization with the control pulse signal. Therefore, as shown in FIG. 11A, the FETs Q1 and Q4 to which the first and fourth gate pulses have been applied are kept off.

  After time t1, the voltage between the source and drain of the FETs Q2 and Q3 starts to decrease as shown in FIG. 11B due to the exciting current of the transformer, and as shown in FIG. The voltage across the drain begins to rise. Further, as shown in FIG. 11C, the primary side voltage of the high-frequency transformer T1 also starts to rise.

  When reaching a time point t2 after a predetermined time Δt has elapsed from the time point t1, the second and third gate signals shown in FIG. 11D are given to the gates of the FETs Q2 and Q3, and the source and drain are connected between FIG. As shown in B), the source-drain voltage of the FETs Q2 and Q3 is reduced to zero, and the FETs Q2 and Q3 are maintained in the on state. Further, the source-drain voltages of the FETs Q1 and Q4 that are kept off reach the input voltage as shown in FIG. Therefore, as shown in FIG. 11C, the primary side voltage of the high-frequency transformer T1 also reaches a predetermined voltage, current is supplied to the FETs Q2 and Q3, and the drain current is increased as shown in FIG. 11F. The This current is supplied as an exciting current to the primary side of the high-frequency transformer T1, and as a result, an induced voltage is generated on the secondary side.

  Since the impedance of the current resonance circuit connected to the secondary side of the high frequency transformer T1 is high immediately after the FETs Q2 and Q3 are turned on, the drain currents of the FETs Q2 and Q3 are gradually increased from zero. Further, at time t2 to time t3, a drain current having a half-wave sine wave is generated according to the resonance frequency of the current resonance circuit connected to the secondary side of the high-frequency transformer T1.

  At time t3, when the second and third gate signals applied to the FETs Q2 and Q3 are turned off, the FETs Q2 and Q3 are turned off, and the drain current becomes zero as shown in FIG. Accordingly, the supply of energy to the secondary side of the high-frequency transformer T1 is stopped. Further, the source-drain voltage of the FETs Q2 and Q3 turned off as shown in FIG. 11B is gradually increased, and the source-drain voltage of the FETs Q2 and Q4 turned off as shown in FIG. 11A. Is gradually raised. As the voltage between the source and drain of the FETs Q2 and Q3 increases, the voltage between the source and drain of the FETs Q1 and Q4 decreases. Accordingly, the primary voltage of the high-frequency transformer T1 is also gradually reduced.

  When reaching a time point t4 after a predetermined time Δt from the time point t3, the first and fourth gate signals shown in FIG. Conduction is performed as shown in A), and the source-drain voltages of the FETs Q1 and Q4 are reduced to zero. From time t4 to time t5, the FETs Q1 and Q4 are maintained in the on state. Further, the source-drain voltages of the FETs Q2 and Q4 that are kept off reach the input voltage as shown in FIG. Accordingly, as shown in FIG. 11C, the primary voltage of the high-frequency transformer T1 also reaches a predetermined voltage on the negative side, and current is supplied from the capacitors C1, C2, and C3 to the FETs Q2 and Q3 that are conducted, and the drain current thereof Is increased as shown in FIG. This current is supplied as an exciting current to the primary side of the high-frequency transformer T1, and as a result, an induced voltage is generated on the secondary side.

  Here, from time t3 to time t4, the capacitors C2 and C5 connected in parallel to the FETs Q1 and Q4 are slowly discharged, and therefore the source-drain voltages of the FETs Q1 and Q4 are also gradually lowered. Thereafter, the FETs Q1 and Q4 are turned on at time t4, but the change in the voltage between the source and drain of the FETs Q1 and Q4 at the moment of switching is extremely small, and a substantial zero voltage resonance switching (ZVS) is realized.

  From time t5, the same operation as at times t1 to t4 is repeated again to generate an induced voltage on the secondary side of the high-frequency transformer T1. Here, time points t5, t6, t7, and t8 correspond to time points t1, t2, t3, and t4, respectively, and refer to the description of the corresponding time points.

  Here, from time t5 to t6, the capacitors C2 and C5 connected in parallel to the FETs Q1 and Q4 are similarly slowly charged, and accordingly, the source-drain voltages of the FETs Q1 and Q4 are also gradually increased. . Thereafter, the FETs Q2 and Q3 are turned on at the time point t6, but the change in the voltage between the source and drain of the FETs Q2 and Q3 at the moment of switching is extremely small, and a substantial zero voltage resonance switching (ZVS) is realized.

  As described above, by operating the voltage resonance circuit, a voltage waveform and a current waveform as shown in FIGS. 12A and 11B are output to the secondary side of the high-frequency transformer T1. That is, a trapezoidal wave voltage appears on the secondary side of the high-frequency transformer T1, as shown in FIG. 12A, corresponding to the voltage waveform on the primary side of the high-frequency transformer T1 shown in FIG. Corresponding to the current waveform on the primary side of the high-frequency transformer T1 shown in FIG. 11 (H), a trapezoidal voltage appears on the secondary side of the high-frequency transformer T1 as shown in FIG. 12 (B).

  In the DC-DC converter described above, the first and fourth gate signals applied to the gates of the FETs Q1 and Q4 are generated in the same phase, and the second and second gate signals applied to the gates of the FETs Q2 and Q3. Since the three gate signals are generated in the same phase, no current is supplied to the commutation circuit including the choke coil LC and the capacitors C10 and C11, and the circuit is not substantially activated.

  The operation of the half-bridge voltage resonance circuit 11 shown in FIG. 5 and the push-pull type voltage resonance circuit 11 shown in FIG. 6 can be easily performed by those skilled in the art with reference to the description of the full-bridge voltage resonance circuit 11 shown in FIG. Therefore, the description thereof is omitted.

  In the above description of the operation of the DC-DC converter, it is assumed that the target power supply 3 is outputting a voltage with a rating. However, an ordinary power source, for example, a fuel cell, is often operated at a so-called small output (about 30% of the rating) below the rated output. In this case, the resonance cannot be maintained (that is, the soft switching becomes incomplete), and the efficiency is extremely lowered. Therefore, it is necessary to increase the efficiency in the small output mode, particularly in the small output operation of 50% or less of the rated output. Therefore, the control signal is adjusted so that the efficiency can be maintained even in the small output mode. That is, in the small output mode, when the secondary side voltage reaches a voltage higher than the rated voltage (above the target voltage, for example, 400 V or less), the MCU 18 gives the driver a control signal in the small output mode, and from the driver. As described below, the first to fourth gate signals having higher frequencies than those in the rated mode are generated. Further, the MCU 18 operates the driver circuits DR1 and DR2 so as to give a phase difference to the first and fourth gate signals as described below, and to give a phase difference to the second and third gate signals. .

  When the power supply 3 is in the small output mode (about 30% of the rating), the DC-DC converter shown in FIG. 9 constituted by the full-bridge circuit described in FIG. 4 performs an operation for maintaining the output. This will be described with reference to FIGS. As shown in FIG. 9, when the current IL1 flowing through the choke coil LC is a positive current, a current flows from the capacitor C7 to the intermediate tap of the transformer T1, and when IL1 is a negative current, the transformer C7 receives a transformer. It is assumed that current flows from the intermediate tap of T1. The current IT1 flowing to the primary side of the high-frequency transformer T1 has a positive direction flowing from the primary side of the high-frequency transformer T1 to the connection point of the transistors Q1 and Q2, and from the connection point of the transistors Q1 and Q2 to the primary side of the high-frequency transformer T1. The flow direction is negative. Similarly, the current IT2 flowing to the primary side of the high-frequency transformer T1 has a positive direction flowing from the primary side of the high-frequency transformer T1 to the connection point of the transistors Q3 and Q4, and from the primary side of the high-frequency transformer T1 from the connection point of the transistors Q1 and Q2. The flow direction is negative.

  When the DC-DC converter shown in FIG. 9 is connected to the DC power source 3 via a switch (not shown), charging of the capacitor C1 is started. Similarly, charging of the series circuit of capacitors C2 and C3 connected in parallel to the capacitor C1, the series circuit of capacitors C4 and C5, and the series circuit of capacitors C6 and C7 is also started.

  When the control pulse signal is supplied to the driver circuits DR1 and DR2 and the driver FETs DR1 and DR2 are operated and the transistors Q2 and Q4 are turned on before time t11, the state shown in FIG. As described above, the primary side of the high-frequency transformer T1 is connected to the minus side and becomes the ground potential. Therefore, if the capacitor C7 is in a charged state, the current IL1 starts to flow from the capacitor C7 to the primary side of the high-frequency transformer T1 through the choke coil LC as shown in FIG. This current IL1 is branched on the primary side of the high-frequency transformer T1, and flows to the negative side of the DC power supply via the FETs Q2 and Q4 to the primary side of the high-frequency transformer. As a result, as shown in FIGS. 13K and 13L, currents IT1 and IT2 flow through the primary side of the high-frequency transformer. Here, since the primary side of the high frequency transformer T1 remains at the ground potential, the current Ir is not output from the current resonance circuit 13 on the secondary side of the high frequency transformer T1.

  At a certain time t11, the second gate signal from the driver circuit DR1 is switched from the high level to the low level as shown in FIG. 13 (H), and the FET Q2 in the on state is turned off. Further, at time t12 when Δtk has elapsed from time t11, the first gate signal is switched from the low level to the high level as shown in FIG. Therefore, as shown in FIG. 13B, the source-drain voltage of the FET Q2 in the off state is increased.

  At time t11, as shown in FIG. 13F, the third gate signal is maintained at a low level. Therefore, as shown in FIG. 13C, the FET Q3 to which the third gate pulse is applied is maintained in the off state. Also at time t11, as shown in FIG. 13G, the fourth gate signal is maintained at a high level. Therefore, as shown in FIG. 13D, only the FET Q4 to which the fourth gate pulse is applied is maintained in the on state.

  After the time t11, the source-drain region of the FET Q2 is turned off by the gate cutoff voltage applied to the FET Q2. Accordingly, the voltage between the source and drain of the FET Q1 starts to decrease as shown in FIG. 13A, and the voltage between the source and drain of the FET Q2 switched to OFF increases as shown in FIG. 13B. start. Since the transistors Q3 and Q4 are kept off and on after time t11, the drain-source voltages of the transistors Q3 and Q4 are kept at a high level and a low level. . As the FET Q2 is turned off, the primary side potential of the transformer LC gradually rises from the minus side as shown in FIG. 13 (E), and the high-frequency transformer T1 of the high-frequency transformer T1 is shown in FIGS. The primary current IT1 reaches a peak and the current IT2 begins to increase. Further, as shown in FIG. 13J, the choke current IL1 is continuously supplied from the capacitor C7 via the choke coil LC11.

  When the time point t12 is reached, the first gate signal shown in FIG. 13 (I) is applied to the gate of the FET Q1, and the source and drain are made conductive as shown in FIG. 13 (A). The drain-to-drain voltage is reduced to zero, and the FET Q1 is kept on. Further, the source-drain voltage of the FET Q2 which is kept off reaches the input voltage as shown in FIG. Accordingly, the primary side voltage of the high frequency transformer T1 also reaches a predetermined voltage via the series circuit of the FETs Q1 and Q4 in the on state as shown in FIG. 13E, and the current IT1 on the primary side of the high frequency transformer T1 gradually increases. Decrease and increase current IT2. Even after time t12, current continues to be supplied from the capacitor C11 through the choke coil LC as shown in FIG. Therefore, the current Ir starts to be output from the current resonance circuit 13 on the secondary side of the high-frequency transformer T1, as shown in FIG.

  At time t13, as shown in FIG. 13G, when the fourth gate signal turns off the FET Q4, the voltage on the primary side of the high-frequency transformer T1 starts to drop, and also passes through the choke coil LC from the capacitor C7. The current supply decreases, and with this decrease, the current IT1 on the primary side of the high-frequency transformer T1 substantially stops, and the current IT2 starts to decrease from the peak. Therefore, from the secondary current resonance circuit 13 of the high-frequency transformer T1, the current Ir that has reached the negative peak starts to decrease as shown in FIG.

  At time t14 when a predetermined time Δt has elapsed from time t13, when the source / drain voltage of the FET Q3 becomes substantially zero, the third gate signal causes the FET Q3 to conduct as shown in FIG. 13 (F). Since the FETs Q1 and Q3 are turned on and the FETs Q2 and Q4 are turned off, the primary side of the high-frequency transformer T1 is maintained at the plus side voltage as shown in FIG. 13E, and as shown in FIG. The direction of the current flowing through the choke coil LC is changed so that the current flows through the choke coil LC in the direction of charging the capacitor C7. Therefore, the primary side of the high-frequency transformer T1 becomes the ground voltage as shown in FIG. 13E, and the current Ir is stopped from the current resonance circuit 13 as shown in FIG. 13M. Further, as shown in FIGS. 13K and 13L, the current IT1 flowing in the primary side of the high-frequency transformer T1 is also increased in the negative direction, and the current IT2 is also decreased.

  At time t15, when the FET Q1 is turned off by the first gate pulse, the drain-source voltage of the FET Q1 is increased, and the drain-source voltage of the FET Q2 is decreased. Here, since the FET Q3 is in the ON state, the voltage on the primary side of the high-frequency transformer T1 starts to decrease as shown in FIG.

  At time t16, when the FET Q2 is turned on by the second gate pulse, the source-drain is made conductive as shown in FIG. 13B, the source-drain voltage of the FET Q2 is lowered to zero, and the FET Q2 Is kept on. Further, the source-drain voltage of the FET Q1 maintained off is increased until it reaches the input voltage as shown in FIG. Therefore, as shown in FIG. 13E, the primary voltage of the high-frequency transformer T1 also reaches a predetermined negative voltage through the series circuit of the FETs Q2 and Q3 in the on state, and the negative voltage on the primary side of the high-frequency transformer T1. The current IT1 is gradually decreased, and the current IT2 is also increased on the negative side. Even after time t16, as shown in FIG. 13J, the current is continuously supplied to the capacitor C7 via the choke coil LC, and the capacitor C7 is charged. Therefore, a positive current Ir starts to be output from the current resonance circuit 13 on the secondary side of the high-frequency transformer T1, as shown in FIG.

  At time t17, as shown in FIG. 13G, when the third gate signal turns off the FET Q3, the primary voltage of the high-frequency transformer T1 starts to rise, and the choke coil for charging the capacitor C7. The supply of the current IL1 through the LC decreases, and the current IT1 on the primary side of the high-frequency transformer T1 substantially stops along with the decrease, and the negative current IT2 starts to decrease from the peak. Therefore, from the secondary side current resonance circuit 13 of the high-frequency transformer T1, the current Ir that has reached the peak on the positive side starts to decrease as shown in FIG.

  At time t18 after a predetermined time Δt has elapsed from time t17, when the source-drain voltage of the FET Q4 becomes substantially zero, the fourth gate signal causes the FET Q4 to conduct as shown in FIG. 13G. Since the FETs Q2 and Q4 are turned on and the FETs Q1 and Q3 are turned off, the primary side of the high frequency transformer T1 is maintained at zero voltage as shown in FIG. 13 (E), as shown in FIG. 13 (J). Current from the capacitor C7 to the choke coil LC is started. Therefore, the primary side of the high-frequency transformer T1 becomes the ground voltage as shown in FIG. 13E, and the current Ir is stopped from the current resonance circuit 13 as shown in FIG. 13M. Further, as shown in FIGS. 13K and 13L, the current IT1 flowing on the primary side of the high-frequency transformer T1 is also increased to the plus side, and the current IT2 is also increased to the plus side.

  When reaching the time point t19, the operation described with reference to the time points t11 to t18 is repeated again, and the current Ir is supplied from the current resonance circuit 13 as shown in FIG.

  The operation of the half-bridge voltage resonance circuit 11 shown in FIG. 5 and the push-pull type voltage resonance circuit 11 shown in FIG. 6 can be easily performed by those skilled in the art with reference to the description of the full-bridge voltage resonance circuit 11 shown in FIG. Therefore, the description thereof is omitted.

  14 (A) to 13 (M) show the waveforms of the respective parts shown in FIG. 9 when no load is connected to the rectifier circuit 14. Even when no load is connected to the rectifier circuit 14, the voltage resonance circuit 11 maintains the voltage resonance, but since no current is supplied from the high-frequency transformer T1 to the current resonance circuit 14, the current resonance circuit 14 , Will not work.

  When no load is applied, the second and fourth gate signals are generated in the same phase as shown in FIGS. 14F to 13I, and the first and third gate signals are generated in the same phase. 14A to 13D, the FETs Q2 and Q4 and the transistors Q1 and Q3 are turned on / off in synchronization. The operation of the circuit shown in FIG. 9 at no load will be described below.

  At time t11, in synchronization with the control pulse signal, the second and fourth gate signals are switched from the high level to the low level as shown in FIGS. 14 (G) and 14 (H). Accordingly, as shown in FIG. 14A, the FETs Q2 and Q4 to which the second and fourth gate pulses have been applied are kept off. At time t12, the first and third gate signals are generated as shown in FIGS. 14 (F) and 14 (I).

  Before time t11, the FETs Q2 and Q4 are kept on and the FETs Q1 and Q3 are kept off. Therefore, the primary side of the high-frequency transformer T1 is connected to the negative side of the DC power supply by the conductive FETs Q2 and Q4. Since the same potential is maintained, no potential difference occurs on the primary side, and the primary side voltage is maintained at zero. Accordingly, the current Ir1 is not output from the secondary side of the high-frequency transformer T1, as shown in FIG. 14 (M), and is maintained at zero. Further, as shown in FIG. 14 (J), the current IL1 is supplied from the charged capacitor C11 to the intermediate tap of the high-frequency transformer T1 through the choke coil L1, as shown in FIGS. 14 (K) and 13 (L). Currents IT1 and IT2 are supplied to the FETs Q2 and Q4 from the primary side.

  At time t11, as the FETs Q2 and Q4 are turned off, the increase in the current IL1 stops as shown in FIG. 14 (J), and the high-frequency transformer T1 as shown in FIGS. 14 (K) and 13 (L). Of the currents IT1 and IT2 flowing from the primary side to the FETs Q2 and Q4 is stopped. Even at this time t11, since the primary side of the high-frequency transformer T1 is maintained at the same potential, no potential difference is generated on the primary side, the primary-side voltage is maintained at zero, and the secondary side of the high-frequency transformer T1 is maintained. From the side, the current Ir1 is not output as shown in FIG.

  After time t11, the capacitors C2, C4 and C3, C5 are charged by the current of the choke coil L1, respectively. Therefore, the voltage between the source and drain of the FETs Q1 and Q3 starts to decrease as shown in FIGS. 14A and 14C, and as shown in FIGS. 14B and 14D, the FETs Q2 and Q3 are reduced. The voltage between the source and drain of Q4 starts to rise.

When reaching a time point t12 after a predetermined time Δt has elapsed from the time point t11, high-level first and third gate signals are given to the gates of the FETs Q1 and Q3 as shown in FIGS. 14 (F) and 13 (I). As shown in FIGS. 14 (A) and 13 (C), the source-drain voltage is made conductive, the source-drain voltage of the FETs Q1, Q3 is reduced to zero, and the FETs Q1, Q3 are kept on. The Further, the source-drain voltages of the FETs Q2 and Q4 that are kept off reach the input voltage as shown in FIGS. 14B and 14D. Since the primary side of the high-frequency transformer T1 is maintained at the same potential by the conducting FETs Q1 and Q3, no potential difference is generated on the primary side, and the primary side voltage is maintained at zero. Accordingly, the current Ir1 is not output from the secondary side of the high frequency transformer T1 as shown in FIG. 14 (M) and is maintained at zero. From time t12 to time t15, as shown in FIG. 14 (J). The current IL1 gradually decreases, and the capacitor C11 starts to be charged by the current from the positive side of the power supply. That is, the current IL1 changes from positive to negative and starts to charge the capacitor C11. As the current IL1 changes, the currents IT1 and IT2 change gradually from positive to negative as shown in FIGS. 14 (K) and 13 (L).

  At time t15, when the first and third gate signals applied to the FETs Q1 and Q3 are turned off, the FETs Q1 and Q3 are turned off, and the source-drain voltages of the FETs Q1 and Q3 are gradually increased.

  Further, at time t16 when a predetermined time Δt has elapsed from time t15, the second and fourth gate signals shown in FIGS. 14G and 14H are given to the gates of the FETs Q2 and Q4, and FIG. B) and the FETs Q2 and Q4 are turned on as shown in FIG. 14D, and the source-drain voltages of the FETs Q2 and Q4 are reduced to zero. The primary side of the high-frequency transformer T1 is connected to the negative side of the power supply via the FETs Q2 and Q4, and both ends thereof are maintained at the same potential. Therefore, no potential difference is generated on the primary side, and the primary side voltage is Similarly, the current Ir1 is not output from the secondary side of the high-frequency transformer T1, as shown in FIG. 14 (M), and is maintained at zero.

  Thereafter, at time 18 corresponding to time t11, FETs Q2 and Q4 are turned off, FETs Q1 and Q3 are turned on, and time t11 to time t18 are repeated.

  In the above-described interconnected inverter, the configuration for improving the conversion efficiency when the converter unit 10 has one DC-DC converter circuit has been described. However, as shown in FIG. 15, two DC-DC converter circuits, That is, it is good also as a circuit structure which has a unit. In such a converter unit 10, as described below, in order to improve efficiency, the connection of the two DC-DC converter units is switched and switched, and a voltage is output with high efficiency.

  In converter units 10-1 and 10-2 shown in FIG. 15, the primary circuit 11 is configured by any of the circuits shown in FIGS. 4 to 6, and the transformer T <b> 1 is any of FIGS. 4 to 9. This corresponds to the transformer T1 shown in FIG. The secondary side circuit 13 corresponds to the circuit shown in FIG. 7 or FIG. Therefore, the voltage across the capacitor C9 in the secondary circuit 13 is output as a voltage signal from the converter units 10-1 and 10-2. Since the converter units 10-1 and 10-2 have already been described with reference to these drawings, description thereof will be omitted.

  The primary side circuit 11 of the converter units 10-1 and 10-2 shown in FIG. 15 is not provided with the commutation circuit LC including the capacitors C10 and C11 and the choke coil L1 shown in FIGS. good. That is, in the circuit shown in FIG. 15, the first converter unit 10-1 and the second converter unit 10-2 are each composed of a choke coil L1 and capacitors C10 and C11 for supplementing power energy at the time of a small output. The flow circuit may not be provided, and the efficiency in the converter unit 10 can be improved.

  As shown in FIG. 15, the high potential side of the smoothing capacitor C9 corresponding to the high voltage side of the first converter unit 10-1 and the high potential side of the smoothing capacitor C9 corresponding to the high voltage side of the second converter unit 10-2. The low potential of the smoothing capacitor C9 corresponding to the low voltage side of the smoothing capacitor C9 corresponding to the low voltage side of the first converter unit 10-1 and the low voltage side of the second converter unit 10-2. Diodes D5 and D6 are respectively connected between the two sides. The anode sides of the diodes D5 and D6 are connected to the second converter unit 10-2, and the cathode sides of the diodes D5 and D6 are connected to the first converter unit 10-1. A transistor Q7 is provided between the low voltage side of the first converter unit 10-1 and the high voltage side of the second converter unit 10-2. The transistor Q7 is driven by a pulse width modulation (PWM) operation by the driver 17. Thereby, the voltage difference of switching is reduced and switching loss is reduced. In the circuit shown in FIG. 15, the output of the smoothing circuit 15 is fed back to the PWM generator 16, and based on this, a PWM signal is generated by the PWM generator 16 to drive the transistor Q7. The driver 17 includes a photocoupler, and the transistor QT is electrically isolated from the output side of the smoothing circuit 15.

  In the circuit shown in FIG. 15, as shown in FIGS. 16A and 16B, the first converter unit 10-1 and the second converter unit 10-2 receive constant output voltages Vout1 and Vout2. Is output. At a certain time t21, a PWM signal is generated from the PWM signal generator 16, and when the transistor Q7 is turned on by the driver 17 as shown in FIG. 16C, the diodes D5 and D6 are connected in series, and the diodes D5 and D6 are connected. The low voltage side of the first converter unit 10-1 is connected to the connection point between them, and the high voltage side of the second converter unit 10-2 is connected. Accordingly, as shown in FIG. 16D, a voltage Vout3 in which the power supply Vout1 and the power supply Vout2 are connected in series is output from the series circuit of the diodes D5 and D6, and this voltage Vout3 is input to the smoothing circuit 15. When the PWM signal is turned off at time t22, the secondary sides of the high-frequency transformers of the first converter unit 10-1 and the second converter unit 10-2 are connected in parallel to the smoothing circuit 15, and the first converter unit 10 -1 and the second converter unit 10-2 are supplied with voltage Vout1 or Vout2 from the secondary side of the high-frequency transformer to the smoothing circuit 15. Therefore, the input voltage of the smoothing circuit 15 is lowered as shown in FIG. Similarly, at time t23, when the PWM signal from the PWM signal generator 16 is turned on and the transistor Q7 is turned on as shown in FIG. 16C, the diodes D5 and D6 are connected in series, and between the diodes D5 and D6. Are connected to the low voltage side of the first converter unit 10-1 and to the high voltage side of the second converter unit 10-2. Accordingly, as shown in FIG. 16D, a voltage Vout3 in which the power supply Vout1 and the power supply Vout2 are connected in series is output from the series circuit of the diodes D5 and D6, and this voltage Vout3 is input to the smoothing circuit 15. When the PWM signal is turned off at time t24, the secondary sides of the high-frequency transformers of the first converter unit 10-1 and the second converter unit 10-2 are connected in parallel to the smoothing circuit 15, and the first converter unit 10 -1 and the second converter unit 10-2 are supplied with voltage Vout1 or Vout2 from the secondary side of the high-frequency transformer to the smoothing circuit 15. As shown in FIG. 16E, the smoothing circuit 15 outputs an output voltage Vout4 obtained by smoothing the input voltage Vout3 according to the pulse width of the PWM signal. Here, the output voltage Vout4 from the smoothing circuit 15 increases if the pulse width of the PWM signal is large, and the output voltage Vout4 from the smoothing circuit 15 decreases if the pulse width of the PWM signal is small. Accordingly, the output voltage from the smoothing circuit 15 is detected by the PWM signal generator 16, and the output of the smoothing circuit 15 can be made constant by selecting an appropriate pulse width.

As described above, when the transistor Q7 performs the PWM operation, the first converter unit 10-1 and the second converter unit 10-2 repeat series-parallel. At this time, when the circuit is composed of two units, the output Vout is
Vout≈Vout1 × PWM ratio + Vout2
And the output control range is
Vout = Vout1 × 2
It becomes. That is, as shown in FIG. 17, the output voltage Vout4 corresponding to the on / off state of the transistor Q7 is output.

  In the circuit of the converter unit 10 described above, two or more secondary circuits may be provided in one primary circuit as shown in FIG. That is, as shown in FIG. 18, the present invention can also be applied to a circuit in which a plurality of secondary windings are wound around one transformer T1. That is, the transformer T1 has one primary side and a plurality of, for example, two secondary sides, and the voltage resonance circuit shown in FIGS. 4 to 6 is connected to the primary side of the transformer T1, and 2 The first and second rectifier circuits 13-1 and 13-2 configured as shown in FIG. 7 or FIG. 8 are connected to the two secondary sides, respectively. And between the high potential side of the smoothing capacitor C9 of the first rectifier circuit 13-1 and the high potential side of the smoothing capacitor C9 of the second rectifier circuit 13-2 and the smoothing capacitor of the first rectifier circuit 13-1. Diodes D5 and D6 are respectively connected between the low potential side of C9 and the low potential side of the smoothing capacitor C9 of the second rectifier circuit 13-2. As in FIG. 15, a transistor Q7 that is pulse width modulated (PWM) operated by the driver 17 is connected between the diodes D5 and D6. In FIG. 18, the driver 17 and the PWM signal generator are not shown, but operate in the same manner as shown in FIGS.

  Further, as shown in FIG. 19, a plurality of transformers T1-1 and T1-2 may be prepared in one primary side circuit. In the circuit shown in FIG. 19, each of the plurality of transformers T <b> 1-1 and T <b> 1-2 includes first and second rectifier circuits 13-1 and 13-13 configured as shown in FIG. 7 or FIG. 8. -2 is connected. And between the high potential side of the smoothing capacitor C9 of the first rectifier circuit 13-1 and the high potential side of the smoothing capacitor C9 of the second rectifier circuit 13-2 and the smoothing capacitor of the first rectifier circuit 13-1. Diodes D5 and D6 are respectively connected between the low potential side of C9 and the low potential side of the smoothing capacitor C9 of the second rectifier circuit 13-2. As in FIG. 15, a transistor Q7 that is pulse width modulated (PWM) operated by the driver 17 is connected between the diodes D5 and D6. In FIG. 18, the driver 17 and the PWM signal generator are not shown, but operate in the same manner as shown in FIGS.

  It should be noted that the primary circuit 11 shown in FIGS. 18 and 19 does not have to be provided with the commutation circuit LC composed of the capacitors C10 and C11 and the choke coil L1 shown in FIGS. Keep it. The circuit according to the present embodiment is also applicable to a circuit that does not use a voltage-current resonance type DC-DC converter as long as there are two or more outputs on the secondary side.

  In the above-described DC-DC converter, the following embodiments are preferable. Note that the following embodiments may be applied independently or in appropriate combinations.

  (1) The voltage resonance circuit is either a bridge type or a push-pull type.

  (2) In (1), the bridge type voltage resonance circuit is connected so that a switching element and a capacitor connected in parallel constitute a bridge.

  (3) In (2), the bridge-type voltage resonance circuit includes first to fourth switching elements and first to fourth capacitors connected in parallel to the first to fourth switching elements, respectively. The third and fourth switching elements connected in series with the first and second switching elements connected in series are connected in parallel to form a bridge.

  In (2) and (3), the capacitor connected in parallel to the switching element can be substituted by the internal capacitance of the switching element.

  (4) The current resonance circuit includes a coil and a capacitor connected in series, the coil is connected to a first end of the transformer, and the capacitor is connected to a rectifier circuit.

  (5) The rectifier circuit is a full-bridge rectifier circuit or a voltage doubler rectifier circuit.

  (6) A commutation circuit for maintaining resonance at the time of low power input is provided between the voltage resonance circuit and the transformer.

  (7) The commutation circuit includes two capacitors connected in parallel to the bridge circuit and connected in series, and a coil connected to a connection point of the capacitors and a primary winding of the transformer. thing.

  As described above, it is possible to provide a DC-DC converter having high conversion efficiency not only at the rated output but also at the small output.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention at the stage of implementation. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements.

  In addition, for example, even if some structural requirements are deleted from all the structural requirements shown in each embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the effect of the invention Can be obtained as an invention.

FIG. 1 is a block diagram schematically showing a distributed power supply system to which a connected inverter comprising a converter unit and an inverter unit of the present invention is applied. It is a block diagram which shows the circuit structure of the DC-DC converter part concerning one Embodiment of this invention. It is a wave form diagram which shows roughly the output of the secondary side of a DC-DC converter. It is a wave form diagram which shows roughly the output of the secondary side of a DC-DC converter. FIG. 3 is a circuit diagram showing an example of a voltage resonance circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing another example of the voltage resonance circuit shown in FIG. 2. FIG. 6 is a circuit diagram showing still another example of the voltage resonance circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing a circuit example of the current resonance circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing another circuit example of the current resonance circuit shown in FIG. 2. FIG. 8 is a circuit diagram illustrating a circuit example according to the combination of FIG. 4 and FIG. 7. It is a control part block diagram which shows the function of MCU of the DC-DC converter shown in FIG. (A)-(H) is a wave form diagram which shows the waveform of each part in the rated output mode of the DC-DC converter shown in FIG. (A) And (B) is a wave form diagram which shows the voltage and electric current waveform of the secondary side of the high frequency transformer shown in FIG. 9 in a rated output mode. (A)-(M) is a wave form diagram which shows the waveform of each part in the small output mode of the DC-DC converter shown in FIG. (A)-(M) is a wave form diagram which shows the waveform of each part in the no-load mode of the DC-DC converter shown in FIG. FIG. 15 is a block diagram showing a circuit in which the converter unit shown in FIG. 1 is composed of two DC-DC converter units. (A)-(E) is a wave form diagram which shows the waveform of each part in the circuit shown in FIG. 16 is a graph showing changes in output voltage Vout in the circuit shown in FIG. 15. FIG. 16 is a block diagram showing a modification of the circuit shown in FIG. 15. FIG. 16 is a block diagram showing a modification of the circuit shown in FIG. 15.

Explanation of symbols

  C1 to C11 ... capacitors, Q1 to Q4 ... switching elements, T1 ... transformers, DR1, DR2 ... drivers, D1 to D6 ... diodes, L ... inductors, LC ... choke coils, QT ... transistors, 1 ... distributed power supply systems, 2 ... interconnected inverter, 3 ... power supply, 10 ... converter part, 11 ... voltage resonance circuit, 12 ... high frequency transformer, 13 ... current resonance circuit, 14 ... rectifier circuit, 16 ... PWM generator, 17 ... driver, 20 ... inverter part

Claims (12)

DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A first voltage resonance circuit for converting and outputting;
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
A first insulated high-frequency transformer having a primary side and a secondary side, into which an output voltage from the first voltage resonance circuit is input;
A first current resonance circuit connected to the secondary side of the first transformer;
A first rectifier circuit for rectifying an output current output from the first current resonance circuit;
A first smoothing circuit that outputs a first output voltage by smoothing the output voltage from the first rectifier circuit,
A second voltage resonance including a second switching circuit composed of second switching elements connected to be alternately switched, and DC-AC converted and output DC power from the low-voltage DC power supply Circuit,
A second driver for maintaining voltage resonance in the second voltage resonance circuit by turning on and off the second switching element at a timing when the conduction current is zero and the applied voltage is zero;
A second insulated high-frequency transformer having a primary side and a secondary side, into which an output voltage from the second voltage resonance circuit is input;
A second current resonance circuit connected to the secondary side of the second transformer;
A second rectifier circuit for rectifying an output current output from the second current resonance circuit;
A second smoothing circuit for outputting a second output voltage by smoothing the output voltage from the second rectifier circuit,
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a third switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the modulated voltage from the pulse width modulation circuit and outputting it as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the third switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by the on operation of the third switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DC-DC converter comprising: 2. The DC-DC converter according to claim 1, wherein the pulse generation circuit includes a photocoupler that electrically separates the third smoothing circuit and the third switching element.     2. The first and second switching circuits are configured by connecting and arranging the first and second switching elements in either a bridge type or a push-pull type, respectively. DC-DC converter.     The DC-DC converter according to claim 1, wherein the low-voltage direct current power source corresponds to a fuel cell, a solar power generation system, or a wind power generation system. DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A voltage resonant circuit that converts and outputs, and
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
An insulated high-frequency transformer having a primary side and a secondary side, into which the output voltage from the first voltage resonance circuit is input;
First and second current resonance circuits connected to the secondary side of the first transformer;
First and second rectifier circuits for rectifying output currents output from the first and second current resonance circuits;
First and second smoothing circuits for smoothing output voltages from the first and second rectifier circuits and outputting first and second output voltages, respectively;
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a second switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the output voltage from the pulse width modulation circuit and outputting the smoothed output voltage as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the second switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by an on operation of the second switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DC-DC converter comprising: 6. The DC-DC converter according to claim 5, wherein the pulse generation circuit includes a photocoupler that electrically separates the third smoothing circuit and the second switching element.     6. The DC-DC converter according to claim 5, wherein the first switching circuit is configured such that the first switching element is connected and arranged in either a bridge type or a push-pull type.     6. The DC-DC converter according to claim 5, wherein the low-voltage direct current power source corresponds to a fuel cell, solar power generation or wind power generation system. DC power is input from a low voltage DC power supply including a first switching circuit composed of first switching elements connected to be alternately switched, and the output voltage varies. A voltage resonant circuit that converts and outputs, and
A first driver that maintains voltage resonance in the first voltage resonance circuit by turning on and off the first switching element at a timing when the conduction current is zero and the applied voltage is zero;
First and second isolated high-frequency transformers, each having a primary side and a secondary side, into which an output voltage from the first voltage resonance circuit is input;
First and second current resonance circuits respectively connected to the secondary sides of the first and second transformers;
First and second rectifier circuits for rectifying output currents output from the first and second current resonance circuits;
First and second smoothing circuits for smoothing output voltages from the first and second rectifier circuits and outputting first and second output voltages, respectively;
A first diode connected between the high potential sides of the first and second output voltages, a second diode connected between the low potential sides of the first and second output voltages, and the first and second A pulse width modulation circuit configured of a second switching element connected in series between the second diodes and outputting a modulated voltage;
A third smoothing circuit for smoothing the output voltage from the pulse width modulation circuit and outputting the smoothed output voltage as a third output voltage;
A pulse generation circuit for generating a pulse for turning on and off the second switching element, wherein the first and second diodes are connected in series to the third smoothing circuit by an on operation of the second switching element; The first and second diodes are respectively connected in parallel to the third smoothing circuit in the off operation, and the pulse width of the pulse is set according to the third output voltage so that the third output voltage is substantially constant. A pulse generation circuit to
A DCDC converter comprising: 10. The DC-DC converter according to claim 9, wherein the pulse generation circuit includes a photocoupler that electrically separates the third smoothing circuit and the second switching element.     10. The DC-DC converter according to claim 9, wherein the first switching circuit is configured by connecting the first switching element to either a bridge type or a push-pull type. The DC-DC converter according to claim 9 , wherein the low-voltage direct current power source corresponds to a fuel cell, solar power generation or wind power generation system.

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