WO2010090798A2 - Substrate bonding with metal germanium silicon material - Google Patents

Substrate bonding with metal germanium silicon material Download PDF

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Publication number
WO2010090798A2
WO2010090798A2 PCT/US2010/020847 US2010020847W WO2010090798A2 WO 2010090798 A2 WO2010090798 A2 WO 2010090798A2 US 2010020847 W US2010020847 W US 2010020847W WO 2010090798 A2 WO2010090798 A2 WO 2010090798A2
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WIPO (PCT)
Prior art keywords
layer
substrate
forming
including metal
silicon
Prior art date
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Ceased
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PCT/US2010/020847
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English (en)
French (fr)
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WO2010090798A3 (en
Inventor
Ruben B. Montez
Alex P. Pamatat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
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Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Priority to JP2011548020A priority Critical patent/JP5679996B2/ja
Priority to EP10738898.5A priority patent/EP2389337A4/en
Priority to CN201080005182.1A priority patent/CN102292280B/zh
Publication of WO2010090798A2 publication Critical patent/WO2010090798A2/en
Publication of WO2010090798A3 publication Critical patent/WO2010090798A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83469—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83481—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83484—Tungsten [W] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/164—Material

Definitions

  • This invention relates in general to semiconductor devices and more specifically for techniques for bonding enclosures of a semiconductor device.
  • MEMS micro electrical mechanical system
  • MEMS accelerometers it is desirable to seal the MEMS accelerometer in a chamber to prevent contamination of the moving parts of a MEMS accelerometer during subsequent processes.
  • One method for sealing a MEMS device is to bond a cap wafer to a second wafer that includes the MEMS device.
  • the cap wafer and the second wafer form a cavity for the MEMS device.
  • the cap wafer may include a lead glass frit located around the cavity that bonds to the second wafer under pressure and temperature.
  • Figure 1 is a partial cutaway side view of a device wafer at one stage of manufacture according to one embodiment of the present invention.
  • Figure 2 is a partial top view of a device wafer at one stage of manufacture according to one embodiment of the present invention.
  • Figure 3 is a partial cutaway side view of a cap wafer at a stage of manufacture according to one embodiment of the present invention.
  • Figure 4 is a partial cutaway side view of a cap wafer at another stage of manufacture according to one embodiment of the present invention.
  • Figure 5 is a partial cutaway side view of a cap wafer placed against the device wafer at a stage of manufacture according to one embodiment of the present invention.
  • Figure 6 is a partial cutaway side view of a cap wafer pressed against the device wafer at another stage of manufacture according to one embodiment of the present invention.
  • a cap wafer is bonded to a device wafer by a metal poly silicon germanium material to form a sealed chamber around a semiconductor device.
  • a metal poly silicon germanium material On one wafer, a stack of silicon (Si), poly silicon germanium (SiGe), and poly germanium (Ge) is formed.
  • a metal structure is formed on a second wafer. The metal silicon germanium material is formed by placing the metal structure and germanium structure in contact and applying heat (and pressure in some embodiments).
  • Figure 1 is a side view of a device wafer 101 that includes a semiconductor device 105 to be sealed with a cap wafer (e.g. 301 of Figure 3).
  • device 105 is a MEMS device such as e.g. an accelerometer or switch.
  • device 105 includes a proof mass (not shown) made of polysilicon that is supported by springs and is movable with respect to substrate 103.
  • device 105 includes capacitive structures whose capacitance can be measured to detect the movement of the proof mass.
  • device 105 may be of other types of semiconductor devices in other embodiments.
  • device 105 may be a transducer.
  • Wafer 101 includes a substrate 103 which in one embodiment is made of bulk monocrystalline silicon.
  • An insulator layer 107 (e.g. Si ⁇ 2) is formed on substrate 103.
  • layer 107 is formed by a local oxidation of silicon (LOCOS) process, but may be formed by other methods in other embodiments.
  • LOC local oxidation of silicon
  • the back side (not shown) of wafer 101 may be ground and polished.
  • Layer 107 is formed with opening 111 located around the location of the subsequently formed semiconductor device 105. In other embodiments, opening 111 maybe formed by patterning layer 107.
  • layer 107 has a thickness of 25K Angstroms, but may be of other thicknesses in other embodiments.
  • layers 113, 120, and 122 are formed separately and then patterned prior to forming the next layer to form the desired structures of those layers.
  • dielectric layers e.g. layer 118 may be formed subsequently or prior to the forming of polysilicon layers 113 and 120 for the isolation of various structures formed from those layers.
  • sacrificial layers may be used for forming the desired structures that are later removed in subsequent processes.
  • layer 118 may be of a silicon rich nitride material
  • device 105 includes layers 113, 118, 120, 122. In such a device, those layers maybe patterned to remove a portion of the layer at various locations in the device. However, for simplicity, device
  • wafer 101 including device 105, may include other semiconductor layers and metal layers.
  • Wafer 101 includes a seal ring 117 surrounding device 105. Ring 117 is located over opening 111 wherein the polysilicon material of layer 113 is in contact with the silicon material of substrate 103 at opening 111.
  • contacts 121 and 123 include poly silicon layer 113, poly silicon layer 120, and metal layer 122 but do not include dielectric layer 118.
  • Each contact is electrically coupled to a structure of device 105 by a polysilicon runner (e.g. 211 of Figure 2) formed from layer 113.
  • polysilicon layer 113 is 3500 Angstroms thick, but may be of other thicknesses in other embodiments.
  • layer 113 is doped with an impurity e.g. phosphorus to increase conductivity by ion implantation but may be doped with other impurities and by other methods in other embodiments.
  • an impurity e.g. phosphorus to increase conductivity by ion implantation but may be doped with other impurities and by other methods in other embodiments.
  • polysilicon layer 120 is 32K Angstroms thick but may be of other thicknesses in other embodiments.
  • layer 120 is doped with e.g. phosphorus by a doped oxide diffusion process, but may be doped with other impurities to improve conductivity and by other methods in other embodiments.
  • Metal layer 122 is formed over a patterned layer 120.
  • layer 122 is formed of aluminum.
  • layer 122 is formed of 99.5% aluminum (by atomic weight) and .5% copper (by atomic weight).
  • layer 122 may be made of other metals or include other metals in other embodiments such gold, platinum, tungsten, titanium, cobalt, nickel, tin, and tantalum.
  • layer 122 may include some non metal materials such as germanium or silicon. In one embodiment, layer 122 includes 98% atomic weight or greater of a primary metal material (e.g. aluminum in some embodiments). In one embodiment, layer 122 has a thickness in the range of 3-4 microns, but maybe of other thicknesses in other embodiments.
  • device 105 includes a portion of metal layer 122. In one embodiment, a portion of layer 122 is utilized to add weight to a proof mass of device 105.
  • layer 122 is formed by physical vapor deposition, sputtering, evaporation, or plating. Layer 122 is subsequently patterned to form desired structures including on seal ring 117 and contacts 121 and 123.
  • Figure 2 shows a top view of wafer 101.
  • Ring 117 is shown as having a rectangle shape located around device 105.
  • Wafer 101 includes a number of contacts 201 , 203, 121 , 123, 205, and 207 that are electrically coupled by polysilicon runners 211 , 213, 215, 221 , 219 and 217 respectively, to structures of device 105.
  • the runners are made of poly silicon from layer 113.
  • runners 213, 215, 221 , and 219 pass through ring 117.
  • layer 113 of ring 117 is electrically isolated from the runners by nitride layer 118 and by other dielectric material at locations lateral to the runners.
  • ring 117 includes two parts of layer 113.
  • Part 212 appears a "C" structure starting at sidewall 218 and extending for three whole sides around device 105 to sidewall 220.
  • the second part 216 is located between a first set of runners 211 , 213, and 215, and a second set of runners 221 , 219, and 217.
  • Part 216 is separated from sidewall 218 to form an opening from runners 213 and 215 and part 216 is separated from sidewall 220 form an opening for runners 221 and 219.
  • Runners 211 and 217 are contiguous with the portion of layer 113 of ring 117. Thus, there are no dashed lines shown for these runners as crossing through ring 117 from the portion of the runners on the outside to the portion of the runners on the inside of the ring. Accordingly, ring 117 is electrically coupled to contacts 205 and 201. In one embodiment, contacts 205 and 201 serve as ground pads and are electrically coupled to substrate 103 by the runners and through conductive material in opening 111.
  • Opening 111 is located under those portions of layer 113 of ring 117 and runners 211 and 217 to provide ohmic contact to substrate 103. Opening 111 is not located under runners 213, 215, 221 , and 219 in order to isolate those structures from substrate 103.
  • the openings to the substrate 103 maybe at different locations, maybe of different sizes, and/or maybe of different shapes.
  • openings 111 are located under ring 117 only at the locations where runners 211 and 217 extend through ring 117.
  • the substrate openings may be located under runners 211 and 217 at locations outside of ring 117.
  • substrate openings may be located under contacts 201 and 205.
  • nitride dielectric layer 118 After the formation of nitride dielectric layer 118, a dielectric layer e.g. silicon dioxide (not shown) is deposited over wafer 101. An opening is then formed in nitride layer 118 at those portions of ring 117. Layer 120 is subsequently formed over wafer 101. The portion of layer 120 of ring 117 is in contact with the portion of layer 113 of ring 117 via the openings of nitride layer 118.
  • a dielectric layer e.g. silicon dioxide (not shown) is deposited over wafer 101.
  • An opening is then formed in nitride layer 118 at those portions of ring 117.
  • Layer 120 is subsequently formed over wafer 101. The portion of layer 120 of ring 117 is in contact with the portion of layer 113 of ring 117 via the openings of nitride layer 118.
  • FIG 3 is a partial side cutaway view of cap wafer 301.
  • cap wafer 301 includes a bulk silicon substrate 303 and a layer of oxide 305 formed there over.
  • layer 305 is thermally grown, but in other embodiments, it may be deposited.
  • Layer 305 is 4950 Angstroms thick, but may be of other thicknesses in other embodiments.
  • openings are formed in layer 305 at the locations of trenches 311 and 307.
  • Wafer 301 is then subjected to an etch process (either wet or dry) to form trenches 311 and 307 in substrate 303.
  • opening 309 is formed in layer 305 to expose substrate 303.
  • a polysilicon layer 401 is formed over wafer 301.
  • layer 401 has a thickness in the range of 750-2500
  • layer 401 is formed by a chemical vapor deposition process (CVD), but may be formed of other processes in other embodiments. In one embodiment, layer 401 is formed by a process at a temperature greater than 550 degrees Celsius.
  • CVD chemical vapor deposition process
  • Layer 401 acts as a seed layer for subsequently formed layer 403.
  • Layer 403 is made of silicon germanium.
  • layer 403 includes germanium in a range of 20-40 atomic percent with the remainder being of silicon. However, other embodiments may have a different atomic percentage of germanium.
  • the germanium concentration of layer 403 may vary with a lower concentration of germanium at the bottom of layer 403 and a higher concentration of germanium at the top of layer 403, relative to the view shown in Figure 4.
  • layer 403 is formed by a CVD process, but may be formed by other processes in other embodiments.
  • silicon germanium layer 403 has a thickness in the range of 500-2000 Angstroms, but may be of other thickness in other embodiments.
  • Layer 405 is formed over layer 403.
  • Layer 405 is made of poly crystalline germanium.
  • layer 405 has a thickness in the range of 2000-4000 Angstroms, but may be of other thicknesses in other embodiments.
  • layer 405 is formed by a CVD process, but may be formed by other processes in other embodiments.
  • the back side of wafer 301 may be ground and polished. Also in some embodiments, trenches (not shown) may be formed in the backside of wafer 301.
  • polycrystalline layers 401 , 403, and 405 are not doped with conductivity impurities (e.g. boron, phosphorous, arsenic). In other embodiments, they may be doped with conductivity or other types of impurities.
  • conductivity impurities e.g. boron, phosphorous, arsenic. In other embodiments, they may be doped with conductivity or other types of impurities.
  • Figure 5 is a partial cutaway side view showing wafer 301 being brought into contact with wafer 101 where ring 117 is aligned to opening 309, trench 311 is located over contacts 121 and 123, and trench 307 is located over device 105.
  • Figure 5 shows both wafers just prior to the application of heat (and pressure in some embodiments) for bonding the two wafers together.
  • Figure 6 is a partial cutaway side view after wafer 101 and 301 have been bonded together by applying heat to the to wafers.
  • the metal material of layer 122 of ring 117 reacts with the polysilicon of layer 401 , the polycrystalline silicon germanium of layer 403, and the polycrystalline germanium of layer 405 to form a bonding material 601 of aluminum, silicon, and germanium.
  • this material 601 is a ternary system of aluminum (or other metal in other embodiments), silicon, and germanium.
  • aluminum (or other material of layer 122 in other embodiments) is the largest component by volume, followed by germanium, and then silicon.
  • Material 601 is conductive.
  • material 601 may be described as a Al- Ge-Si eutectic compound. In one embodiment, material 601 may be described as a compound film. In one embodiment, the percentage by atomic weight of silicon of the material 601 is greater than 5%.
  • 601 provides for a hermetic seal for device 105 between wafers 101 and 301.
  • material 601 is conductive, in some embodiments, it provides for a conductive path (e.g. a ground path) between the two wafers.
  • the wafers are bonded at a temperature in the range of 425-500 C, and more preferably at a temperature in the range 450-475 C. However other temperatures may be used in other embodiments.
  • the use of aluminum for layer 122 is preferable in that it may allow for the use of bonding temperatures below 500 degrees Celsius. In some embodiments, during the bonding process, the gap between substrate 303 and substrate 103 is reduced from its position shown in Figure 5.
  • the wafers are bonded together under pressure in addition to the application of heat.
  • a tool force pressure in the range of 5000-10,000 milibars is applied, with a preferable pressure in some embodiments of 6500 milibars.
  • other applied bonding force pressures may be used.
  • forming layer 405 of poly crystalline germanium by a CVD process provides for a method of forming such a layer by a process that generates less particulates, which results in lower defect densities.
  • a CVD process including plasma enhanced CVD processes
  • poly crystalline germanium layer provides the layer with a roughness that allows for better bonding with the material of layer 122 in some embodiments.
  • Forming a polycrystalline layer of germanium (e.g. layer 405) on a polycrystalline layer of silicon germanium (e.g. layer 403) may in some embodiments avoid the formation of voids in material 601 at the location where seed layer 401 is located. It is believed that using the intermediate silicon germanium layer 403 inhibits silicon migration from seed polysilicon layer 401 to layer 405 during the bonding process. Accordingly, utilizing the intermediate silicon germanium layer 403 results in material 601 being of a stronger and more uniform material.
  • the resultant wafer (wafer 101 and wafer 301 bonded together in Figure 6) is further processed subsequent to the stage shown in Figure 6.
  • the portion of substrate 303 may be removed to expose contacts 121 and 123 for external connection of those bond pads.
  • the resultant wafer is singulated into multiple die where each of the die includes a device similar to device 105 that is sealed with a material similar to material 601. Such die may be packaged for incorporation in electronic systems.
  • cap wafer 301 may include semiconductor devices of an integrated circuit formed there on.
  • an integrated circuit e.g. a microprocessor
  • the integrated circuit may be electrically coupled to device 105.
  • a method includes forming a layer including metal over a first substrate, providing a second substrate, and forming a first layer comprising silicon supported by the second substrate. The method also includes forming a second layer comprising germanium and silicon on the first layer, forming a third layer comprising germanium on the second layer, and contacting the third layer to the layer including metal.
  • the method further includes after contacting the third layer to the layer including metal, forming a mechanical bonding material between the first substrate and the second substrate.
  • the forming a mechanical bonding material includes applying heat to the third layer and the layer including metal.
  • the bonding material includes a metal of the layer including metal and material of the third layer.
  • a method for providing a seal between a first substrate and a second substrate includes contacting the first substrate to the second substrate through a bonding stack.
  • the bonding stack includes a first layer comprising silicon, a second layer comprising germanium and silicon in contact with the first layer, a third layer comprising germanium in contact with the second layer, and a layer including metal in contact with the third layer.
  • the method includes applying heat and pressure to the bonding stack so that the bonding stack becomes a bond between the first and second substrates.
  • a semiconductor structure in another embodiment, includes a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate.
  • the conductive bond comprises metal, silicon, and germanium. An atomic percent of silicon in the conductive bond is greater than 5%.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Micromachines (AREA)
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PCT/US2010/020847 2009-01-21 2010-01-13 Substrate bonding with metal germanium silicon material Ceased WO2010090798A2 (en)

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JP2011548020A JP5679996B2 (ja) 2009-01-21 2010-01-13 金属ゲルマニウムシリコン材料を用いた基板接合
EP10738898.5A EP2389337A4 (en) 2009-01-21 2010-01-13 SUBSTRATE ADHESIVE WITH METAL GERMANIUM SILICON MATERIAL
CN201080005182.1A CN102292280B (zh) 2009-01-21 2010-01-13 与金属锗硅材料接合的衬底

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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE537499C2 (sv) * 2009-04-30 2015-05-26 Silex Microsystems Ab Bondningsmaterialstruktur och process med bondningsmaterialstruktur
DE102009026628A1 (de) * 2009-06-02 2010-12-09 Robert Bosch Gmbh Mikromechanisches Bauelement und Verfahren zum Herstellen eines mikromechanischen Bauelements
US8378490B2 (en) * 2011-03-15 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor apparatus including a metal alloy between a first contact and a second contact
US8652865B2 (en) * 2011-08-16 2014-02-18 Freescale Semiconductor, Inc. Attaching a MEMS to a bonding wafer
ITTO20110995A1 (it) * 2011-10-31 2013-05-01 St Microelectronics Srl Dispositivo micro-elettro-meccanico dotato di regioni conduttive sepolte e relativo procedimento di fabbricazione
US8633088B2 (en) 2012-04-30 2014-01-21 Freescale Semiconductor, Inc. Glass frit wafer bond protective structure
US8749036B2 (en) 2012-11-09 2014-06-10 Analog Devices, Inc. Microchip with blocking apparatus and method of fabricating microchip
US10160638B2 (en) 2013-01-04 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor structure
DE102014210852B4 (de) * 2014-06-06 2022-10-06 Robert Bosch Gmbh Bauteil mit zwei Halbleiter-Bauelementen, die über eine strukturierte Bond-Verbindungsschicht miteinander verbunden sind, und Verfahren zum Herstellen eines solchen Bauteils
US9418830B2 (en) 2014-06-27 2016-08-16 Freescale Semiconductor, Inc. Methods for bonding semiconductor wafers
US20170081178A1 (en) * 2015-09-22 2017-03-23 Freescale Semiconductor, Inc. Semiconductor device package with seal structure
GB2546830B (en) * 2016-01-29 2018-11-14 Cirrus Logic Int Semiconductor Ltd Integrated MEMS transducers
US10002844B1 (en) * 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10793427B2 (en) * 2017-04-04 2020-10-06 Kionix, Inc. Eutectic bonding with AlGe
US10167191B2 (en) 2017-04-04 2019-01-01 Kionix, Inc. Method for manufacturing a micro electro-mechanical system
CN109422234B (zh) * 2017-09-01 2021-04-09 中芯国际集成电路制造(上海)有限公司 测试结构及其制造方法
IT201700103511A1 (it) * 2017-09-15 2019-03-15 St Microelectronics Srl Dispositivo microelettronico dotato di connessioni protette e relativo processo di fabbricazione
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
CN108203076B (zh) * 2018-01-03 2020-04-14 上海华虹宏力半导体制造有限公司 晶圆键合方法
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11313877B2 (en) 2018-06-19 2022-04-26 Kionix, Inc. Near-zero power wakeup electro-mechanical system
US12374641B2 (en) 2019-06-12 2025-07-29 Adeia Semiconductor Bonding Technologies Inc. Sealed bonded structures and methods for forming the same
CN114552378B (zh) 2020-11-20 2023-03-31 中国科学院苏州纳米技术与纳米仿生研究所 窄线宽激光器
US20240347386A1 (en) * 2023-04-12 2024-10-17 Honeywell International Inc. Bonding layer between stacked integrated circuits

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55138874A (en) * 1979-04-18 1980-10-30 Fujitsu Ltd Semiconductor device and method of fabricating the same
US5693574A (en) * 1991-02-22 1997-12-02 Deutsche Aerospace Ag Process for the laminar joining of silicon semiconductor slices
JP3230638B2 (ja) * 1993-02-10 2001-11-19 シャープ株式会社 発光ダイオードの製造方法
US6090687A (en) * 1998-07-29 2000-07-18 Agilent Technolgies, Inc. System and method for bonding and sealing microfabricated wafers to form a single structure having a vacuum chamber therein
JP2002050764A (ja) * 2000-08-02 2002-02-15 Matsushita Electric Ind Co Ltd 薄膜トランジスタ、アレイ基板、液晶表示装置、有機ｅｌ表示装置およびその製造方法
DE60125952T2 (de) * 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6890835B1 (en) * 2000-10-19 2005-05-10 International Business Machines Corporation Layer transfer of low defect SiGe using an etch-back process
US6818938B1 (en) * 2002-12-10 2004-11-16 National Semiconductor Corporation MOS transistor and method of forming the transistor with a channel region in a layer of composite material
US6936491B2 (en) 2003-06-04 2005-08-30 Robert Bosch Gmbh Method of fabricating microelectromechanical systems and devices having trench isolated contacts
FR2859312B1 (fr) * 2003-09-02 2006-02-17 Soitec Silicon On Insulator Scellement metallique multifonction
US6936918B2 (en) 2003-12-15 2005-08-30 Analog Devices, Inc. MEMS device with conductive path through substrate
US7034393B2 (en) 2003-12-15 2006-04-25 Analog Devices, Inc. Semiconductor assembly with conductive rim and method of producing the same
US7442570B2 (en) * 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US7538401B2 (en) * 2005-05-03 2009-05-26 Rosemount Aerospace Inc. Transducer for use in harsh environments
US7245009B2 (en) 2005-06-29 2007-07-17 Motorola, Inc. Hermetic cavity package
US7358194B2 (en) * 2005-08-18 2008-04-15 Tokyo Electron Limited Sequential deposition process for forming Si-containing films
US20070045795A1 (en) * 2005-08-31 2007-03-01 Mcbean Ronald V MEMS package and method of forming the same
US7553687B2 (en) * 2006-06-28 2009-06-30 Intel Corporation Dual seed semiconductor photodetectors
JP4997913B2 (ja) * 2006-10-17 2012-08-15 日産自動車株式会社 半導体装置および半導体装置の製造方法
US8119431B2 (en) * 2009-12-08 2012-02-21 Freescale Semiconductor, Inc. Method of forming a micro-electromechanical system (MEMS) having a gap stop

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US20120068325A1 (en) 2012-03-22
JP2012516055A (ja) 2012-07-12
TWI503899B (zh) 2015-10-11
EP2389337A4 (en) 2016-09-07
US8058143B2 (en) 2011-11-15
WO2010090798A3 (en) 2010-09-30
CN102292280B (zh) 2015-09-23
JP5679996B2 (ja) 2015-03-04
EP2389337A2 (en) 2011-11-30
US20100181676A1 (en) 2010-07-22
TW201034091A (en) 2010-09-16
US8592926B2 (en) 2013-11-26

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