WO2010086919A1 - Memory access device and techniques related thereto - Google Patents

Abstract

A mode fixing unit fixes at least one parameter included in a rectangular command on the basis of an operation mode.  An access master sets an offset at an address position in a memory bank on the basis of the parameter.  The access master designates an arbitrary memory bank from memory banks.  A conflict determination unit specifies a memory bank causing a bank conflict.  A priority determination unit outputs an in-bank selector selection signal for designating a top-priority access master to the memory bank causing the bank conflict and outputs a stop signal to access masters other than the top-priority access master.

Description

Memory access device and related technology

The present invention relates to a memory access device that performs address conversion when accessing a memory having a plurality of banks, and a related technology (memory access method, video / audio display device, LSI, IP core, recording medium).

This application is incorporated herein by reference in its entirety, including Japanese Patent Application No. 2009-015433, filed on January 27, 2009, including the specification, drawings, and claims.

Conventionally, there has been proposed a method for specifying an area using special rectangular data when storing image data in a memory such as SRAM (Static Random Access Memory) or SDRAM (Synchronous Dynamic Random Access Memory). This method is said to be easy to handle in software.

FIG. 9 shows a specific rectangular command area 61 in the frame area 60 existing on the memory. In this example, the frame area 60 is located between address 0 and address 79, and a rectangular command area 61 for designating a rectangular command exists therein. The rectangular command indicates the start point by the offset X and offset Y in the frame, and indicates the width of the rectangular command area by the rectangular width and the rectangular height. As an example, the rectangular command parameters in the rectangular command area 61 are:
-Frame base address: 0,
・ Frame width: 8,
・ Frame height: 10,
・ Offset X: 2,
-Offset Y: 2,
・ Rectangle width: 4,
・ Rectangle height: 5,
It is composed of

The start address of the rectangle command is
[Frame base address] + [Offset X] + [Frame width] * [Offset Y]. The start address of the Nth line of the rectangular command is
[N-1st line start address] + [frame width]
It can be calculated by the following formula. As can be seen in this figure, the rectangular area has discontinuous addresses for each line.

In addition, there is a memory mapping technique in which different banks are accessed simultaneously by making a plurality of memories into a bank configuration.

In the world of image processing, image data handled from SD (Standard Definition) size, which is the standard image quality in the conventional analog display, to HD (High Definition) size used in digital broadcasting and the like is increased, and MPEG (Moving Picture Experts Group) 2 to H. The compression technology such as H.264 has high compression efficiency but the processing is complicated and the rectangular data to be handled is finer and the number is increasing, and a plurality of rectangular data are transferred in a shorter time. Technology is desired.

Japanese Patent Application Laid-Open No. 2004-164641

In the conventional technology, the data transfer capacity can be expanded by increasing the data width of the memory. However, the rectangular data has discontinuous addresses for each line. Therefore, in order to transfer a plurality of rectangular data in a short time, a plurality of memories are configured in a bank so that different banks can be accessed simultaneously, and the rectangular data is transferred simultaneously. However, bank contention occurs between a plurality of rectangular data, and it is difficult to realize efficient transfer.

The present invention was created in view of such circumstances, and mainly provides a memory access device and related technology for improving access efficiency when accessing with a plurality of rectangular commands mapped on a memory. It is aimed.

The memory access device according to the present invention includes a mode fixing device, a plurality of access masters, a contention determination device, a priority determination device, and a plurality of memory banks. Hereinafter, these components will be described.

The mode fixer fixes the parameters of the rectangular command according to the operation mode, outputs the fixed parameters to each access master (specifically, a rectangular command issuer described later), and also according to the operation mode. A mode signal is generated, and the generated mode signal is output to each access master (specifically, an in-master selector described later).

Each of the plurality of access masters is configured to input a fixed parameter by the mode fixer and generate a unique bank number and an offset in the memory.

The conflict determination unit is configured to determine a bank conflict based on the bank numbers output from all the access masters.

The priority determiner performs priority determination based on a determination result by the competition determiner, and outputs an in-bank selector selection signal to the memory bank corresponding to the access master that has output the highest priority bank number. The stop signal is output to an access master (specifically, a command converter described later) other than the access master that has output the highest priority bank number.

Each of the plurality of memory banks selects an offset supplied from all the access masters according to an in-bank selector selection signal supplied from the priority determiner, and accesses the bank memory at the selected offset position. Is configured to do.

Each access master is configured in detail as follows. That is, each of the plurality of access masters includes a rectangular command issuer, a command converter, a plurality of memory address converters, and an in-master selector as its constituent elements. The point is that a plurality of memory address converters are provided, and the plurality of memory address converters are selected by the in-master selector.

More specifically, the rectangular command issuer is configured to issue the rectangular command including the parameters fixed by the mode fixer. The fixed parameter and other parameters determine the rectangular command.

For example, if the fixed parameter is the rectangle width or rectangle position of the rectangle command,
The other parameters are the base address of the frame area, the offset X, the offset Y, and the rectangular height representing the rectangular command area (an example).

The command converter is configured to generate a subcommand based on the rectangular command and stop generating the subcommand based on the stop signal.

The memory address converter is configured to convert the subcommand into the bank number and the offset based on memory mapping information corresponding to one operation mode.

The intra-master selector is configured to select the bank number and the offset according to the operation mode.

The technical point of the memory access device of the present invention is that there are a plurality of memory address converters having a unique memory mapping corresponding to each operation mode, and each memory address converter is separated from the command converter according to the unique memory mapping. The subcommand supplied is converted to generate a bank number and an offset in the memory that are specific to the operation mode, and the in-master selector receives a signal from a plurality of memory address converters by a mode signal corresponding to the operation mode supplied from the mode fixer. The bank number and offset specific to the operation mode to be supplied are selected.

The effect | action by the said structure of this invention is as follows. The rectangular data has discontinuous addresses for each line. The memory is configured as a bank so that different memory banks can be accessed simultaneously. However, even with the same memory mapping, depending on how many times the rectangular width of the target rectangular command is the memory access width (bank width) (even multiple or odd multiple), the memory Due to the rotation deviation of multiple banks that differ for each mapping (the shift amount of the predetermined array with the progress of the line in the rectangular command area),
-Whether there is a bank conflict between multiple rectangular data,
-Whether a stop signal is output in response to the occurrence of bank conflicts,
• The length of time required to complete rectangular command processing varies.

According to the above configuration of the present invention, since the memory mapping is selected so that the processing time of the rectangular command is minimized, the time required to complete the processing of the rectangular command in an arbitrary operation mode is reduced. It is possible to minimize the time. That is, it is possible to improve the access efficiency when accessing a memory having a plurality of banks with a rectangular command.

In the memory access device of the present invention,
The mode fixer is
A signal for selecting the memory address converter having the memory mapping information corresponding to the fixed rectangular width and fixing the rectangular width of the rectangular command which is one of the parameters is generated as the mode signal.
There is a mode. This is a mode in which the memory address converter is switched based on the rectangular width. According to this aspect, it is possible to further improve the access efficiency by focusing on the rectangular width of the rectangular command.

In the memory access device of the present invention,
The mode fixer is
A signal for selecting the memory address converter having the memory mapping information corresponding to the position of the fixed rectangular command and fixing the position of the rectangular command in the frame area, which is one of the parameters, There is a mode of generating as a mode signal. This is an aspect in which the address converter is switched based on the position of the rectangular command in the frame area. According to this aspect, it is possible to further improve the access efficiency by focusing on the position of the rectangular command.

In addition, the video / audio display device according to the present invention includes:
A memory access device of the present invention;
A decoding device for decoding image data supplied from the memory access device;
A display device for displaying the output of the decoding device;
Is provided.

The memory access method according to the present invention includes:
At least one parameter included in a rectangular command for specifying an arbitrary rectangular area in a plurality of memory bank recording areas is fixed based on an operation mode set in accordance with the recording operation of the memory bank, and the operation A mode fixing step for generating a mode signal according to the mode;
Based on the parameter fixed by the mode fixing step, an offset on the address position in the memory bank is set, and an access master step for designating an arbitrary memory bank from the memory bank;
A conflict determination step for identifying the memory bank in which bank conflict occurs based on duplication designation by at least two of the access masters;
The priority in the at least two access masters that specify the memory bank in which the bank conflict occurs is determined, and an in-bank selector selection signal that specifies the access master to be given the highest priority is used as the memory in which the bank conflict occurs. A priority determination step of outputting a stop signal to the access master other than the access master to be the highest priority, and outputting to the bank;
A memory bank access step of accessing the rectangular area specified by the offset supplied from the access master specified by the intra-bank selector selection signal in the memory bank in which the bank conflict occurs;
including.

The access master step is
A rectangular command issuing step for issuing the rectangular command including the parameter fixed by the mode fixing step;
A command conversion step of generating a subcommand based on the rectangular command and stopping the generation of the subcommand based on the stop signal;
A memory address conversion step of converting the subcommand into the bank number and the offset based on memory mapping information corresponding to one operation mode;
In-master select step for selecting the bank number and the offset according to the operation mode;
Including
The memory address conversion step is performed a plurality of times corresponding to a plurality of the operation modes.

The present invention is not only realized as a memory access device and a memory access method, but also includes an LSI (Large Scale Integration) incorporating a function of the above memory access method, an FPGA (Field Programmable Gate Array), and CPLD. (Complex Programmable Logic Device) and other programmable logic device (PLD) IP (Intellectual Property) cores, computer-readable memory access optical disks, magneto-optical disks, and semiconductor memories that record programs for the IP core functions It may be realized in a recording medium such as a magnetic disk or a magnetic tape.

According to the present invention, it is possible to improve the access efficiency in access by a plurality of rectangular commands mapped on a memory having a plurality of banks. Further, by paying attention to the rectangular width and rectangular position of the rectangular command, the access efficiency can be further improved.

FIG. 1 is a block diagram showing a configuration of a memory access device according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing an operation example 1 of the memory access device according to the first exemplary embodiment of the present invention together with a comparative example (number of access masters 2, number of memory banks 2, rectangular width: odd multiple of bank width). FIG. 3 is a diagram showing an operation example 2 of the memory access device according to the first embodiment of the present invention together with a comparative example (number of access masters 2, number of memory banks 2, rectangular width: even multiple of bank width). FIG. 4 is a block diagram showing the configuration of the memory access device according to the second embodiment of the present invention. FIG. 5 is a diagram showing an operation example 1 of the memory access device according to the second exemplary embodiment of the present invention together with a comparative example (4 access masters, 4 memory banks, rectangular width: 4 times the bank width). FIG. 6 is a diagram (access master number 4, memory bank number 4, rectangular width: 5 times the bank width) showing an operation example 2 of the memory access device according to the second embodiment of the present invention together with a comparative example. FIG. 7 is a diagram (access master number 4, memory bank number 4, rectangular width: 6 times the bank width) showing an operation example 3 of the memory access device according to the second embodiment of the present invention together with a comparative example. FIG. 8 is a diagram (access master number 4, memory bank number 4, rectangular width: seven times the bank width) showing an operation example 4 of the memory access device according to the second embodiment of the present invention together with a comparative example. It is a figure which shows a specific rectangular command area | region in the frame area | region which exists on a memory.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a memory access device according to Embodiment 1 of the present invention. In the present embodiment, a system including two access masters 20 and 20 and two memory banks 30 and 30 is taken as an example. Hereinafter, the two access masters 20 and 20 are distinguished and referred to as access master # 1 and access master # 2. In the figure, the access master 20 located on the upper side is the first access master # 1, and the access master 20 located on the lower side is the second access master # 2. Further, the two memory banks 30 and 30 are distinguished and referred to as bank0 and bank1. In the figure, the memory bank 30 located on the upper side is bank0, and the memory bank 30 located on the lower side is bank1.

The memory access device according to the first embodiment includes a mode fixer 10, access masters # 1 and # 2, bank 0 and bank 1, a contention determination unit 40, and a priority determination unit 50 as components.

The mode fixing device 10 includes a parameter fixing unit 11 and a rectangular width / rectangular position holding unit 12. The parameter fixing unit 11 is configured to fix the rectangular width and rectangular position parameters in the rectangular command according to the operation mode. The rectangular width / rectangular position holding unit 12 is configured to hold the parameters fixed by the parameter fixing unit 11 and output information on the held rectangular width and rectangular position to the rectangular command issuing unit 21.

The access masters # 1 and # 2 include a rectangular command issuing unit 21, a command conversion unit 22, first and second memory address conversion units 23A and 23B, an offset generation unit 25, and an in-master selector 26. . The rectangular command issuing unit 21 outputs a rectangular command parameter. The command conversion unit 22 receives the parameters of the rectangular command, calculates the start address of the rectangular command and the access address after the start address, and generates a subcommand. Further, the command conversion unit 22 stops the generation of the subcommand based on the stop signal supplied from the priority determination unit 50. The first and second memory address conversion units 23A and 23B include a bank generation unit 24 and an offset generation unit 25. The bank generation unit 24 generates a bank number based on the calculated address. The offset generation unit 25 generates an offset in the memory based on the calculated address.

The rectangular command issuing unit 21 generates parameters of rectangular width (the information is given from the rectangular width / rectangular position holding unit 12) and parameters of rectangular commands other than the rectangular position, and these parameters are converted into the command conversion unit 22. Configured to output. The rectangular command issuing unit 21 uses the above parameters as
The base address of the frame area,
-Offset X, which is the position of the rectangular command on the frame area
・ Offset Y,
The rectangle height representing the rectangle command area,
Is generated.

The command conversion unit 22 calculates the start address of the rectangular command and the access address after the start address from the parameters of the rectangular command, and outputs the calculation result to the first and second memory address conversion units 23A and 23B. . In the first and second memory address conversion units 23A and 23B, the bank generation unit 24 and the offset generation unit 25 perform the following operations. The bank generation unit 24 selects a memory bank based on the address calculated by the command conversion unit 22 and generates a bank number of the selected memory bank. The offset generation unit 25 generates an offset in the memory unit 32 based on the address calculated by the command conversion unit 22.

The first and second memory address conversion units 23A and 23B each correspond to memory mapping suitable for a unique operation mode. Here, as shown in FIGS. 2 and 3, two types of mappings (first and second mappings m1 and m2) are prepared for the memory mapping.

The first mapping m1 is a mapping when different lines in the frame region are shown in the same way in bank0 and bank1. In other words, both the bank 0 and the bank 1 have the same positional relationship in the horizontal direction in both the odd and even lines. That is, both bank0 and bank1 are continuous in the vertical direction.

The second mapping m2 is a mapping in which the upper and lower banks are different in different lines in the frame area. That is, bank1 exists in the even line adjacent in the vertical direction of the region that is bank 0 in the odd line, and bank 0 exists in the even line that is adjacent in the vertical direction in the region that is bank 1 in the odd line. That is, bank0 and bank1 exhibit a checkered pattern.

The first mapping m1 is applied to the first memory address conversion unit 23, and the second mapping m2 is applied to the lower memory address conversion unit 23 (the first access master # 1 also has the second access master). Same for # 2.)

In both the first and second access masters # 1 and # 2, the first memory address conversion unit 23A is configured to perform address conversion (bank number generation and offset generation) in accordance with the first mapping m1. The second memory address conversion unit 23B is configured to perform address conversion in accordance with the second mapping m2.

The rectangular width / rectangular position holding unit 12 generates a mode signal corresponding to the operation mode based on the held rectangular width and rectangular position information. The mode signal functions as a selection signal supplied to the in-master selector 26. The intra-master selector 26 is configured to select and output one each from the plurality of bank numbers and the plurality of offsets output from the plurality of memory address conversion units 23 based on the mode signal.

The mode signal output from the rectangular width / rectangular position holding unit 12 to the in-master selector 26 is set as follows. That is, in the rectangular command handled by the first and second access masters # 1 and # 2, in the state where the rectangular width information included in the command indicates “even multiple” of the memory access width, the mode signal is In the access masters # 1 and # 2, the in-master selector 26 is controlled so as to select the first memory address conversion unit 23A (see (a) of FIG. 3). The first memory address conversion unit 23A corresponds to the first mapping m1. On the other hand, in the rectangular commands handled by the first and second access masters # 1 and # 2, when the rectangular width information included in the commands indicates “odd multiple” of the memory access width, the mode signal is In the access masters # 1 and # 2, the in-master selector 26 is controlled so as to select the lower memory address conversion unit 23B (see FIG. 2B). The second memory address conversion unit 23B corresponds to the second mapping m2.

Bank 0 and bank 1 include an in-bank selector 31 and a memory unit 32. The intra-bank selector 31 responds to the intra-bank selector selection signal supplied from the priority determination unit 50, and the offset os1 and the second access master supplied via the intra-master selector 26 of the first access master # 1. The offset os2 supplied via the # 2 intra-master selector 26 is selected. The memory unit 32 can access an address position corresponding to the offset position supplied via the in-bank selector 31. The memory unit 32 is an SRAM here as an example, but may be another SDRAM, a flash memory that is a nonvolatile memory, a ReRAM (ResistivesisRandom Access Memory), an MRAM (Magnetoresistive Random Access Memory), or the like.

The contention determination unit 40 compares the bank number supplied via the intra-master selector 26 of the first access master # 1 and the bank number supplied via the intra-master selector 26 of the second access master # 2. Based on the above, it is configured to determine whether or not bank contention has occurred in both access masters # 1 and # 2. The bank competition determination result is output to the priority determination unit 50.

In the priority determination unit 50, a priority is fixed in advance for each bank number. When the conflict determination unit 40 confirms the occurrence of bank conflict, the priority determination unit 50 determines the priority of the access masters # 1 and # 2 at the time when the bank conflict occurs based on the priority. In addition, the priority determination unit 50 outputs a stop signal to the command conversion unit 22 of the first access master # 1 or the second access master # 2 that is determined to have lost bank competition (low priority). Further, the priority determination unit 50 outputs an in-bank selector selection signal to the in-bank selector 31 of bank0 and the in-bank selector 31 of bank1. The in-bank selector selection signal is a selection signal for instructing to select an offset supplied from the first access master # 1 or the second access master # 2 determined to have won the bank conflict. The stop signal output from the priority determination unit 50 is input to the command conversion unit 22 in the first access master # 1 or the second access master # 2 determined to have lost bank competition. The command conversion unit 22 stops the generation of the implemented memory address based on the received stop signal.

Next, the operation of the memory access device of the present embodiment configured as described above will be described. The parameter fixing unit 11 in the mode fixing unit 10 fixes the rectangular width and rectangular position parameters in the rectangular command. Information regarding the fixed rectangular width and rectangular position is temporarily held by the rectangular width / rectangular position holding unit 12 and then output to the rectangular command issuing unit 21. The rectangular width / rectangular position holding unit 12 generates a mode signal corresponding to the operation mode based on information on the fixed rectangular width and rectangular position, and outputs the mode signal to the intra-master selector 26.

In the rectangular command issuing unit 21, the rectangular width given from the rectangular width / rectangular position holding unit 12, the parameters of the rectangular command other than the rectangular position, that is, the base address of the frame area, and the offset that is the position of the rectangular command on the frame area X, offset Y, rectangular height representing the rectangular command area, and the like are generated and output to the command conversion unit 22. The command conversion unit 22 calculates the start address of the rectangular command and the access address after the start address from the parameters of the rectangular command, and outputs the subcommand to the first and second memory address conversion units 23A and 23B. In the first and second memory address conversion units 23A and 23B, the bank generation unit 24 generates a bank number indicating a designated bank and outputs the bank number to the intra-master selector 26. The bank number designates a bank selected based on the address calculated by the command conversion unit 22. The offset generation unit 25 generates an offset in the memory unit 32 based on the address calculated by the command conversion unit 22.

In the first and second access masters # 1 and # 2, the first memory address conversion unit 23A performs address conversion (bank number generation and offset generation) in accordance with the first mapping m1, and the second memory The address conversion unit 23B performs address conversion (bank number generation and offset generation) in accordance with the second mapping m2. The generated bank number and offset are output to the intra-master selector 26.

The intra-master selector 26 selects one of the outputs (bank numbers and offsets) of the first and second memory address conversion units 23A and 23B from the mode signal (rectangular position / rectangular position holding unit 12). Select and output based on width and rectangle position information). The contention determination unit 40 determines bank contention in the first and second access masters # 1 and # 2 based on the bank numbers supplied from the first and second access masters # 1 and # 2, and the determination The result is output to the priority determination unit 50. When the occurrence of bank conflict is confirmed by the conflict determination unit 40, the priority determination unit 50 determines in advance the priority determination of the first and second access masters # 1 and # 2 at the time when the bank conflict occurs. This is performed based on a priority that is fixedly determined every time. The priority determination unit 50 outputs a stop signal to the command conversion units 22 of the first and second access masters # 1 and # 2 that are determined to have lost bank competition (low priority).

The command conversion unit 22 that has received the stop signal stops the generation of the subcommand being executed. The priority determination unit 50 outputs an in-bank selector selection signal to the in-bank selectors 31 of bank0 and bank1. The intra-bank selector 31 selects an offset output from the first access master # 1 or the second access master # 2 that has won the bank conflict based on the intra-bank selector selection signal. Bank 0 and bank 1 access the memory unit 32 based on the offset selected by the in-bank selector 31.

Hereinafter, specific operation examples will be described with reference to FIGS. 2 shows an operation example 1 and FIG. 3 shows an operation example 2. 2A and 2B are operation examples of the comparative example, and FIG. 2C and FIG. 2D are operation examples of the present embodiment. 3A and 3B are operation examples of the present embodiment, and FIG. 3C and FIG. 3D are operation examples of a comparative example.

(1) Operation example 1
FIG. 2 shows an operation example when the rectangular widths of the rectangular commands a1 and a2 are “odd multiple” (three times) of the bank width (memory access width) together with a comparative example. Specifically, in the operation example and the comparative example, in the rectangular command a1 and the second rectangular command a2, the rectangular width is “odd multiple” (three times) of the memory access width (the width of bank0 or bank1). It is an example in the state.

Assume that the same first rectangular command a1 is assigned to the first mapping m1 and the second mapping m2, and the same second rectangular command a2 is assigned to the first mapping m1 and the second mapping m2. To do.

2B and 2D, the first access master # 1 issues the first rectangular command a1, and the second access master # 2 issues the second rectangular command a2. 5 is a timing chart showing an operation until completion of rectangular command transfer in FIG. Among these, FIG. 2B is a timing chart when the first mapping m1 is applied, and FIG. 2D is a timing chart when the second mapping m2 is applied. Bank0 and bank1 can be used at the same time, but bank0 and bank0 cannot be used at the same time, and bank1 and bank1 cannot be used at the same time. The first access master # 1 that requested such simultaneous use is used. In the second access master # 2, a priority relationship is set in advance for the use of the bank. In the present embodiment, the first access master # 1 is given the right to use the bank preferentially over the second access master # 2.

(A) Description of Operation in FIGS. 2A and 2B In this operation mode, the master selector 26 generates a mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. Based on this, the output of the first memory address conversion unit 23A is selected. In both the first access master # 1 and the second access master # 2, the bank number and offset output from the in-master selector 26 are both supplied from the first memory address conversion unit 23A. The first mapping m1 corresponds to the first memory address conversion unit 23A.

In FIG. 2 (a) and FIG. 2 (b) related to the first mapping m1, the first access master # 1 that issues the first rectangular command a1 starts mapping from bank0. Also in the second access master # 2 that issues the second rectangular command a2, mapping is started from bank0.

(Timing t1)
At timing t1, in both the first access master # 1 and the second access master # 2, the intra-master selector 26 selects the bank number and offset supplied via the first memory address conversion unit 23A. The bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 indicates bank0, and the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the second access master # 2. The supplied bank number also indicates bank0. In this way, bank0 associated with the first access master # 1 and bank0 associated with the second access master # 2 are the same. Since the same bank cannot be used at the same time, the contention determination unit 40 determines that bank contention occurs at timing t1. In the priority determination unit 50, the first access master # 1 is set to have a higher priority than the second access master # 2. Therefore, the priority determination unit 50 that receives the determination result from the competition determination unit 40
Output a stop signal to the command conversion unit 22 of the second access master # 2 that has been set to have a low priority;
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at the timing t1, the first access master # 1 sets “1” in the first row and the first column of the first rectangular command a1 issued by the first access master # 1. Is selected and bank0 is accessed corresponding to this "1". On the other hand, at timing t1, access from the second access master # 2 is prohibited.

(Timing t2)
At timing t2, the bank number supplied to the contention determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank1, while via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is bank0. As a result of the simultaneous use of bank1 and bank0, the conflict determination unit 40 determines that bank conflict does not occur. Upon receiving the determination result from the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 bank selector 31 to select the offset supplied from the master selector 26 of the second access master # 2.
Instruct the bank 1 selector 31 in bank to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at the timing t2, in the first access master # 1, “2” in the first row and second column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 1 is accessed corresponding to this “2”. On the other hand, at the timing t2, the second access master # 2 selects “1” in the first row and the first column of the second rectangular command a2 issued by the second access master # 2. Corresponding to this “1”, bank 0 is accessed. Thus, the access timing (in this case, the timing t2) for the bank 0 in the second access master # 2 is 1 bank compared to the access timing (the timing t1 in this case) for the bank 0 in the first access master # 1. Has been delayed.

(Timing t3)
At timing t3, the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank0, while via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is switched to bank1. Therefore, the conflict determination unit 40 determines that bank conflict does not occur. Upon receiving the determination result from the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied from the in-master selector 26 of the first access master # 1.
Instruct the bank 1 selector 31 in bank to select the offset supplied from the in-master selector 26 of the second access master # 2.
The control operation is executed.

As a result of performing the above control operation, at the timing t3, the first access master # 1 sets “3” in the first row and third column of the first rectangular command a1 issued by the second access master # 1. Is selected, and bank 0 is accessed corresponding to this “3”. On the other hand, at the timing t3, the second access master # 2 selects “2” in the first row and the second column of the second rectangular command a2 issued by the second access master # 2. Corresponding to this “2”, bank 1 is accessed.

(Timing t4)
At the timing t4, the bank number supplied to the conflict determination unit 40 via the selector 26 in the first access master # 1 continues to the bank 0 after the timing t3, and the selector in the master of the second access master # 2 is maintained. The bank number supplied to the competition determination unit 40 via H.26 is switched to bank0. bank0 and bank0 are the same and cannot be used simultaneously. As described above, the banks of the first and second access masters # 1 and # 2 become the same at the timing t4. In this specific example, the rectangular widths of the first and second rectangular commands a1 and a2 are the same. This is because the memory access width is “odd multiple” (three times).

Since the banks specified by the first and second access masters # 1 and # 2 are the same, the contention determination unit 40 determines that bank contention occurs at timing t4. In the priority determination unit 50, as described above, the first access master # 1 is set to have a higher priority than the second access master # 2. Therefore, the priority determination unit 50 that receives the determination result from the competition determination unit 40
Output a stop signal to the command conversion unit 22 of the second access master # 2 that has been set to have a low priority;
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of the above control operation being performed, at timing t4, in the first access master # 1, “4” in the second row and first column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank0 is accessed corresponding to this “4”. On the other hand, at timing t4, access from the second access master # 2 is prohibited.

(Timing t5)
At timing t5, the bank number supplied to the contention determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank1, while via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is bank0. Therefore, the bank 1 specified by the first access master # 1 and the bank 0 specified by the second access master # 2 can be used simultaneously. As a result, the conflict determination unit 40 determines that bank conflict does not occur. Upon receiving the determination result from the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 bank selector 31 to select the offset supplied from the master selector 26 of the second access master # 2.
Instruct the bank 1 selector 31 in bank to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at timing t5, in the first access master # 1, “5” in the second row and second column of the first rectangular command a1 issued by the first access master # 1. Is selected and bank1 is accessed corresponding to this "5". On the other hand, at timing t5, in the second access master # 2, “3” in the first row and third column of the second rectangular command a2 issued by the first access master # 2 is selected. Corresponding to this “3”, bank 0 is accessed.

(Timing t6)
At the timing t6, the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank0, while via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is maintained at bank0 following the timing t5. The bank 0 associated with the first access master # 1 and the bank 0 associated with the second access master # 2 are the same and cannot be used simultaneously. As described above, the banks of the first and second access masters # 1 and # 2 become the same at the timing t6. In this specific example, the rectangular widths of the first and second rectangular commands a1 and a2 are the same. This is because the memory access width is “odd multiple” (three times).

Since the banks associated with the first and second access masters # 1 and # 2 are the same, the contention determination unit 40 determines that bank contention occurs at timing t6. In the priority determination unit 50, as described above, the first access master # 1 is set to have a higher priority than the second access master # 2. Therefore, the priority determination unit 50 that receives the determination result from the competition determination unit 40
Output a stop signal to the command conversion unit 22 of the second access master # 2 that has been set to have a low priority;
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at timing t6, in the first access master # 1, “6” in the second row and third column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank0 is accessed corresponding to this “6”. On the other hand, access from the second access master # 2 is prohibited.

(Timing t7)
At timing t7, the bank number supplied to the contention determination unit 40 via the intra-master selector 26 of the first access master # 1 maintains bank0 following timing t6, and is within the master of the second access master # 2. The bank number supplied to the competition determination unit 40 via the selector 26 also maintains bank0.

Since the bank associated with the first access master # 1 is the same as the bank associated with the second access master # 2, the contention determination unit 40 determines that bank contention occurs at timing t7. In the priority determination unit 50, as described above, the first access master # 1 is set to have a higher priority than the second access master # 2. Therefore, the priority determination unit 50 that receives the determination result from the competition determination unit 40
Output a stop signal to the command conversion unit 22 of the second access master # 2 that has been set to have a low priority;
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at the timing t7, the first access master # 1 sets “7” in the third row and first column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 0 is accessed corresponding to this “7”. On the other hand, access from the second access master # 2 is prohibited.

(Timing t8)
At the timing t8, the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank1, but via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is bank0. Thus, since the banks of the first and second access masters # 1 and # 2 are different, the conflict determination unit 40 determines that no bank conflict occurs. Upon receiving the determination result from the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 bank selector 31 to select the offset supplied from the master selector 26 of the second access master # 2.
Instruct the bank 1 selector 31 in bank to select the offset supplied from the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at timing t8, in the first access master # 1, “8” in the third row and second column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 1 is accessed corresponding to this “8”. On the other hand, at timing t8, the second access master # 2 selects “4” in the second row and first column of the second rectangular command a2 issued by the second access master # 2. Corresponding to this “4”, bank 0 is accessed.

(Timing t9)
At timing t9, the bank number supplied to the conflict determination unit 40 via the selector 26 in the master of the first access master # 1 is switched to bank0, and via the selector 26 in the master of the second access master # 2. The bank number supplied to the competition determination unit 40 is switched to bank1. Therefore, the first and second access masters # 1 and # 2 have different banks. Thereby, the competition determination unit 40 determines that bank competition does not occur. Upon receiving the determination result from the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied via the master selector 26 in the first access master # 1.
Instruct the bank 1 selector 31 in bank to select the offset supplied via the in-master selector 26 of the second access master # 2.
The control operation is executed.

As a result of performing the above control operation, at timing t9, in the first access master # 1, “9” in the third row and third column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank0 is accessed corresponding to this “9”. On the other hand, at timing t9, the second access master # 2 selects “5” in the second row and second column of the second rectangular command a2 issued by the second access master # 2, Corresponding to this “5”, bank 1 is accessed. At this timing t9, the access of the first rectangular command a1 by the first access master # 1 is completed.

After the timing t10, bank contention does not occur between the first access master # 1 and the second access master # 2. At timing t10, the second access master # 2 selects “6” in the second row and third column of the second rectangular command a2 issued by the second access master # 2, and then selects the “6” "Bank0 is accessed in response to". At timing t11, the second access master # 2 selects “7” in the third row and first column of the second rectangular command a2 issued by the second access master # 2, and then selects “7” "Bank0 is accessed in response to". At timing t12, the second access master # 2 selects “8” in the third row and second column of the second rectangular command a2 issued by the second access master # 2, and then selects the “8”. "Bank1 is accessed." At timing t13, the second access master # 2 selects “9” in the third row and third column of the second rectangular command a2 issued by the second access master # 2, and then selects the “9” "Bank0 is accessed in response to".

The second access master # 2 is inactive at each of the first, fourth, sixth, and seventh banks in the first access master # 1. The reason is that, as described above, the rectangular widths of the first and second rectangular commands a1 and a2 are “odd multiples” (three times) of the memory access width, and bank0 and bank1 are continuous in the vertical direction. Because. Since a total of four banks are suspended, the processing in the second access master # 2 ends after four banks (timing t13) of the end processing in the first access master # 1.

(B) Description of Operation in FIGS. 2C and 2D In this operation mode, the master selector 26 generates a mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. Based on this, the output of the second memory address conversion unit 23B is selected. In both the first access master # 1 and the second access master # 2, the bank number and offset output from the intra-master selector 26 are both supplied via the second memory address conversion unit 23B. The second mapping m2 corresponds to the second memory address conversion unit 23B.

In (c) of FIG. 2 and (d) of FIG. 2 relating to the second mapping m2, the first access master # 1 that issues the first rectangular command a1 starts mapping from bank0. Also in the second access master # 2 that issues the second rectangular command a2, mapping is started from bank0.

(Timing t1)
At the timing t1, the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 is bank0, and conflict occurs via the intra-master selector 26 of the second access master # 2. The bank number supplied to the determination unit 40 is also bank0. Thus, the bank 0 of the first access master # 1 and the bank 0 of the second access master # 2 are the same and cannot be used simultaneously. Therefore, the conflict determination unit 40 determines that bank conflict occurs. In the priority determination unit 50, the first access master # 1 is set to have a higher priority than the second access master # 2. Upon receiving the determination result of the competition determination unit 40, the priority determination unit 50
Output a stop signal to the command conversion unit 22 of the second access master # 2.
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied via the master selector 26 in the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at the timing t1, the first access master # 1 sets “1” in the first row and the first column of the first rectangular command a1 issued by the first access master # 1. Is selected and bank0 is accessed corresponding to this "1". On the other hand, at timing t1, access from the second access master # 2 is prohibited.

(Timing t2)
At timing t2, the bank number supplied via the intra-master selector 26 of the first access master # 1 is switched to bank1, while the contention determination unit 40 is switched via the intra-master selector 26 of the second access master # 2. The bank number supplied to bank 0 is bank0. Therefore, the conflict determination unit 40 determines that bank conflict does not occur. Upon receiving the determination result of the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied via the master selector 26 in the second access master # 2.
Instructs the bank 1 selector 31 in bank 1 to select the offset supplied via the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of performing the above control operation, at the timing t2, in the first access master # 1, “2” in the first row and second column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 1 is accessed corresponding to this “2”. On the other hand, at the timing t2, the second access master # 2 selects “1” in the first row and the first column of the second rectangular command a2 issued by the second access master # 2. Corresponding to this “1”, bank 0 is accessed. Thus, the access timing (in this case, the timing t2) for the bank 0 in the second access master # 2 is 1 bank compared to the access timing (the timing t1 in this case) for the bank 0 in the first access master # 1. Has been delayed.

(Timing t3)
At timing t3, the bank number supplied to the conflict determination unit 40 via the intra-master selector 26 of the first access master # 1 is switched to bank0, while via the intra-master selector 26 of the second access master # 2. Thus, the bank number supplied to the competition determination unit 40 is switched to bank1. Therefore, the conflict determination unit 40 determines that bank conflict does not occur. Upon receiving the determination result of the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied via the master selector 26 in the first access master # 1.
Instruct the bank 1 selector 31 in bank to select the offset supplied via the in-master selector 26 of the second access master # 2.
The control operation is executed.

As a result of the above control operation being performed, at timing t3, in the first access master # 1, “3” in the first row and third column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 0 is accessed corresponding to this “3”. On the other hand, at the timing t3, the second access master # 2 selects “2” in the first row and the second column of the second rectangular command a2 issued by the second access master # 2. Corresponding to this “2”, bank 1 is accessed.

(Timing t4)
At timing t4, control different from the case of FIGS. 2A and 2B is performed. At timing t4, the bank number supplied to the conflict determination unit 40 via the in-master selector 26 of the first access master # 1 is switched to bank1, and through the in-master selector 26 of the second access master # 2. The bank number supplied to the competition determination unit 40 is switched to bank0. Therefore, the conflict determination unit 40 determines that bank conflict does not occur. The contention does not occur at the timing t4 because, as described above, the rectangular width of the first and second rectangular commands a1 and a2 is “odd multiple” (three times) the memory access width.

Upon receiving the determination result of the competition determination unit 40, the priority determination unit 50
-No stop signal is output to any command conversion unit 22,
Instruct the bank 0 selector 31 in bank 0 to select the offset supplied via the master selector 26 in the second access master # 2.
Instructs the bank 1 selector 31 in bank 1 to select the offset supplied via the in-master selector 26 of the first access master # 1.
The control operation is executed.

As a result of the above control operation being performed, at timing t4, in the first access master # 1, “4” in the second row and first column of the first rectangular command a1 issued by the first access master # 1. Is selected, and bank 1 is accessed corresponding to this “4”. On the other hand, in the second access master # 2, “3” in the first row and third column of the second rectangular command a2 issued by the second access master # 2 is selected, and then this “3”. Bank0 is accessed in response to.

The second mapping m2 in which bank0 and bank1 have a checkerboard pattern is compatible with the fact that the rectangular width of the rectangular command is “odd multiple” (three times) the memory access width, and the timing after timing t5 This good compatibility applies at all timings t1 to t9 including the period up to t9. That is, it is possible to perform continuous processing without breaks while alternately switching between bank 0 and bank 1 between the first access master # 1 and the second access master # 2.

The temporary conclusion in the explanation of the operation here using FIGS. 2A to 2D is as follows.

In this example, when the transfer of the first rectangular command a1 and the second rectangular command a2 starts at the same time, the second mapping m2 (at timing t10) rather than the first mapping m1 (ending at timing t13). (End) ends processing earlier by 3 memory access times. Therefore, when the rectangular width such as the first rectangular command a1 or the second rectangular command a2 is “odd multiple” of the memory access width, the performance can be improved by selecting the second mapping m2. It becomes. The selection of the second mapping m2 means that the first access master # 1 and the second access master # 2 are based on the mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. However, this means that the master selector 26 is controlled to select the lower memory address conversion unit 23B. The factor causing the master selector 26 to select the lower input is that the rectangular widths of the first rectangular command a1 and the second rectangular command a2 are “odd multiple” (three times) the memory access width. is there.

(2) Operation example 2
FIG. 3 shows an operation example when the rectangular width of the rectangular commands b1 and b2 is “even multiple” (double) of the bank width (memory access width) together with a comparative example. Specifically, in these operation examples and comparative examples, the first rectangular command b1 and the second rectangular command b2 have an even width that is equal to the memory access width (the width of bank0 or bank1). This is an example in a state of (double).

Assume that the same first rectangular command b1 is assigned to the first mapping m1 and the second mapping m2, and the same second rectangular command b2 is assigned to the first mapping m1 and the second mapping m2. To do. The first mapping m1 and the second mapping m2 are the same as those in FIG.

3B and 3D, the first access master # 1 issues the first rectangular command b1, and the second access master # 2 issues the second rectangular command b2. 5 is a timing chart showing an operation until completion of rectangular command transfer in FIG. Among these, (b) of FIG. 3 is a timing chart when the first mapping m1 is applied, and (d) of FIG. 3 is a timing chart when the second mapping m2 is applied. Note that in the bank usage priority relationship between the first access master # 1 and the second access master # 2, as described above, the first access master # 1 has priority over the second access master # 2. The right to use bank is given.

(A) Explanation of operation according to (a) of FIG. 3 and (b) of FIG. 3 In this operation mode, the selector 26 in the master outputs a mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. Based on this, the output of the first memory address conversion unit 23A is selected. In both the first access master # 1 and the second access master # 2, the bank number and offset output from the in-master selector 26 are both supplied from the first memory address conversion unit 23A. The first mapping m1 corresponds to the first memory address conversion unit 23A.

In FIG. 3A and FIG. 3B related to the first mapping m1, bank0 is arranged on the same line (odd line or even line), and bank1 is also on the same line (odd line or even line). Arranged. Such a bank alignment state is compatible with the fact that the rectangular width of the rectangular command is “even times” (twice) the memory access width. Therefore, unlike the timing chart of FIG. 2B, the timing chart of FIG. 3B shows the same development as the timing chart of FIG. The bank at the timing t9 at which the processing at the second access master # 2 ends is one bank behind the bank at the timing t8 at which the processing at the first access master # 1 ends.

On the other hand, in (c) of FIG. 3 and (d) of FIG. 3 related to the second mapping m2, at timing t3, the first access master # 1 targets bank1, and the second access master # 2 is also Since bank1 is targeted, bank contention occurs. As a result, the command conversion unit 22 of the second access master # 2 is stopped and the access master # 2 is suspended. The reason why such bank conflict occurs is that, as described above, the rectangular width indicated by the rectangular commands b1 and b2 is “even times” (twice) the memory access width. The bank at the end of the processing at the second access master # 2 (timing t10) is two minutes after the bank at the end processing at the first access master # 1 (timing t8).

The conclusion in the operation explanation with reference to (a) to (d) of FIG. 3 is as follows. In this example, when the first rectangular command b1 and the second rectangular command b2 start data transfer at the same time, the first mapping m1 is earlier than the second mapping m2 by one memory access time. End data transfer. As a result, when the rectangular width such as the first rectangular command b1 or the second rectangular command b2 is “even multiple” of the memory access width, the performance can be improved by selecting the first mapping m1. It becomes.

The selection of the first mapping m1 means that the second access is performed even for the first access master # 1, based on the mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. That is, even in the master # 2, the in-master selector 26 is controlled so as to select the first memory address conversion unit 23A. The factor that causes the selector 26 in the master to select the data supplied via the first memory address converter 23A is that the rectangular widths of the first rectangular command a1 and the second rectangular command a2 are “even numbers” of the memory access width. Double (2 times).

To summarize the above, in a state where the rectangular width of the rectangular commands handled by the plurality of access masters 20 is “odd multiple” of the memory access width, even the first access master # 1 has the second Even in the access master # 2, the rectangular width / rectangular position holding unit 12 generates a mode signal so that the second memory address conversion unit 23B is selected by the intra-master selector 26. Conversely, when the rectangular width of the rectangular command handled by the first and second access masters # 1 and # 2 is “even multiples” of the memory access width, even the first access master # 1 has the second This means that the rectangular width / rectangular position holding unit 12 only needs to generate the mode signal so that the in-master selector 26 selects the first memory address conversion unit 23A.

As described above, according to the present embodiment, since the memory mapping is selected so that the processing time of the rectangular command becomes the shortest, the processing of the rectangular command in the arbitrary operation mode is completed. The time required can be minimized. That is, the access efficiency can be improved in the access by the rectangular command to the memory having a plurality of banks.

(Embodiment 2)
FIG. 4 is a block diagram showing the configuration of the memory access device according to the second embodiment of the present invention. In this embodiment, a system in which four access masters 20 are provided and four memory banks 30 are provided is taken as an example.

The four access masters 20 are distinguished and referred to as access masters # 1, # 2, # 3, and # 4. Each of the access masters # 1, # 2, # 3, and # 4 includes four first to fourth memory address conversion units 23A, 23B, 23C, and 23D (in FIG. 4, the first and fourth memory addresses). Only the conversion units 23A and 23D are shown, and the second and third memory address conversion units 23B and 23C are not shown). Although the mode fixing device 10 including the parameter fixing unit 11 and the rectangular width / rectangular position holding unit 12 is provided, the illustration is omitted. The intra-master selector 26 selects one of the first to fourth memory address conversion units 23A to 23D according to a mode signal corresponding to the operation mode supplied from the rectangular width / rectangular position holding unit 12. It has become. In the present embodiment, four memory banks 30 are provided. These four memory banks 20 are distinguished and referred to as bank 0, bank 1, bank 2, and bank 3 in order from the top in the figure.

The in-bank selector 31 responds to the in-bank selector selection signal supplied from the priority determination unit 50, and outputs four offsets output from the in-master selectors 26 of the first to fourth access masters # 1 to # 4. 1 is selected.

The first to fourth memory address conversion units 23A to 23D each correspond to memory mapping suitable for a unique operation mode. Here, four types of memory mapping are prepared as shown in FIGS. In the first mapping m1, bank0, bank1, bank2, and bank3 are arranged in order in each line, and the arrangement of the arrangement is repeated. In the second mapping m2, the arrangement of the banks in the first mapping m1 is rotated to the right by one bank for each line. The third mapping m3 rotates the bank arrangement in the first mapping m1 rightward by 2 banks per line. In the fourth mapping m4, the banks in the first mapping m1 are rotated to the right by 3 banks per line.

The first mapping m1 is applied to the first memory address conversion unit 23A, the second mapping m2 is applied to the second memory address conversion unit 23, and the third mapping m3 is applied to the third memory address conversion unit 23. The fourth mapping m4 is applied to the fourth memory address conversion unit 23. The first to fourth mappings m1 to m4 are common to the first to fourth access masters # 1 to # 4.

(1) Operation example 1 (when the rectangular width is 4N times the bank width)
FIG. 5 shows an operation example when the rectangular width is 4N times the bank width (N is an arbitrary positive integer) together with a comparative example. Specifically, this is an operation example when N = 1 and the rectangular width is four times the bank width.

a1 is the rectangular command of the first access master # 1, a2 is the rectangular command of the second access master # 2, a3 is the rectangular command of the third access master # 3, and a4 is the fourth command This is a rectangular command for access master # 4. These first to fourth rectangular commands a1 to a4 are common to the first to fourth mappings m1 to m4, and the rectangular width is four times the memory access width (bank width).

The operation examples shown in FIG. 5B, FIG. 5D, FIG. 5F, and FIG.
The first access master # 1 issues the first rectangular command a1,
The second access master # 2 issues a second rectangular command a2,
The third access master # 3 issues a third rectangular command a3,
The fourth access master # 4 issues a fourth rectangular command a4,
6 is a timing chart showing an operation until completion of rectangular command transfer in a case.

5B is a timing chart when the first mapping m1 is applied, and FIG. 5D is a timing chart when the second mapping m2 is applied. 5 (f) is a timing chart when the third mapping m3 is applied, and FIG. 5 (h) is a timing chart when the fourth mapping m4 is applied. In any timing chart, the first to fourth access masters # 1 to # 4 simultaneously start transferring.

In the first to fourth access masters # 1 to # 4, the priority relationship is such that the first access master # 1 has the highest priority, and the order is # 1> # 2> # 3> # 4. It shall be.

In bank 0, bank 1, bank 2, and bank 3, different banks can be used simultaneously, but the same bank (bank 0 and bank 0, bank 1 and bank 1, bank 2 and bank 2, bank 3 and bank 3) cannot be used simultaneously.

The operation of the present embodiment (when there are four access master memory banks) is in principle the same as the operation of the first embodiment (when there are two access master memory banks). In the present embodiment, in the rectangular command of the first mapping m1, the memory banks in the rectangle are arranged in an orderly manner with bank0,1,2,3,0,1,2,3. That is, a white bank → a checkered bank → a gray bank → a black bank is repeated. Also, the rectangular start positions are aligned. Even if the start positions of the rectangular commands are different, the bank arrangement is orderly.

According to the present embodiment, the selection of the first mapping m1 causes all rectangular commands a1 to a4 to have the same timing or earlier than other mappings even though bank contention has occurred since the start of transfer. Complete with timing.

(2) Operation example 2 (when the rectangular width is (4N + 1) times the bank width)
FIG. 6 shows an operation example when the rectangular width is (4N + 1) times the bank width together with a comparative example. Specifically, this is a case where N = 1 and the rectangular width is five times the bank width. The first to fourth mappings m1 to m4 are the same as described above. The first to fourth rectangular commands b1 to b4 are common to the first to fourth mappings m1 to m4, and the rectangular width is five times the memory access width (bank width).

FIG. 6B is a timing chart when the first mapping m1 is applied, and FIG. 6D is a timing chart when the second mapping m2 is applied. f) is a timing chart when the third mapping m3 is applied, and FIG. 6H is a timing chart when the fourth mapping m4 is applied. In any timing chart, the first to fourth access masters # 1 to # 4 simultaneously start transferring. In FIG. 6B, the cross mark (x) in the access master # 2 indicates that it is blank (not a bank).

In this example, the rectangular command of the fourth mapping m4 is such that the memory banks in the rectangle are neatly arranged as bank 0, 1, 2, 3, 0, 1, 2, and 3, and the rectangular start positions are aligned. Even if the start positions of the rectangular commands are different, the arrangement of the banks is orderly.

Furthermore, in the second mapping m2, the access master # 1 and the access master # 2 are started at the same time, and bank contention is reduced due to the relative positional relationship of the start positions in such a rectangular command. Yes. Therefore, in the second mapping m2, all transfers are completed in the same time as the fourth mapping m4. As described above, even if the arrangement of the banks in the rectangle is orderly arranged in an arbitrary mapping, there may be a difference in efficiency between the arbitrary mapping and another mapping depending on the setting of the start position of the rectangle. is there. Therefore, it is only necessary to select a mapping suitable for each combination of the rectangle width and the rectangle start position in consideration of whether transfer of all rectangle commands can be completed most efficiently. In this operation example, if the second mapping m2 or the fourth mapping m4 is selected, transfer of all rectangular commands can be completed most efficiently.

(3) Operation example 3 (when the rectangular width is (4N + 2) times the bank width)
FIG. 7 shows an operation example when the rectangular width is (4N + 2) times the bank width together with a comparative example. Specifically, these operation examples and comparative examples are examples in a state where N = 1 and the rectangular width is six times the bank width. The first to fourth mappings m1 to m4 are the same as described above. The first to fourth rectangular commands c1 to c4 are common to the first to fourth mappings m1 to m4, and the rectangular width is six times the memory access width (bank width).

7B is a timing chart when the first mapping m1 is applied, and FIG. 7D is a timing chart when the second mapping m2 is applied. FIG. 7F is a timing chart when the third mapping m3 is applied, and FIG. 7H is a timing chart when the fourth mapping m4 is applied. Each of them shows a timing chart when the first to fourth access masters # 1 to # 4 simultaneously start transfer.

In this example, in the rectangular command of the third mapping m3, the memory banks in the rectangle are arranged in an orderly manner with bank 0, 1, 2, 3, 0, 1, 2, and 3, and the start positions of the rectangles are aligned. Even if the start positions of the rectangular commands are different, the arrangement of the banks is orderly.

In the second and fourth mappings m2 and m4, the access master # 1 and the access master # 2 start at the same time. Due to the relative positional relationship of the start positions in such a rectangular command, bank conflicts Is decreasing. Thus, both mappings m2 and m4 complete all transfers in a shorter time than the first mapping m1. Thus, even if the arrangement of the banks in the rectangle is arranged in an arbitrary mapping, there may be a difference in efficiency between the arbitrary mapping and another mapping depending on the start position of the rectangle. Therefore, it is only necessary to select a mapping suitable for each combination of the rectangle width and the rectangle start position in consideration of whether transfer of all the rectangle commands can be completed most efficiently. In this operation example, if the second mapping m2 and the fourth mapping m4 are selected, transfer of all rectangular commands can be completed most efficiently.

(4) Operation example 4 (when the rectangular width is (4N + 3) times the bank width)
FIG. 8 shows an operation example when the rectangular width is (4N + 3) times the bank width together with a comparative example. Specifically, these operation examples and comparative examples are examples in a state where N = 1 and the rectangular width is seven times the bank width. The first to fourth mappings m1 to m4 are the same as described above. The first to fourth rectangular commands d1 to d4 are common to the first to fourth mappings m1 to m4, and the rectangular width is seven times the memory access width (bank width).

FIG. 8B is a timing chart when the first mapping m1 is applied, and FIG. 8D is a timing chart when the second mapping m2 is applied. f) is a timing chart when the third mapping m3 is applied, and (h) of FIG. 8 is a timing chart when the fourth mapping m4 is applied. Each of them shows a timing chart when the first to fourth access masters # 1 to # 4 simultaneously start transfer.

In this example, in the rectangular command of the second mapping m2, the memory banks in the rectangle are arranged in an orderly manner with bank 0, 1, 2, 3, 0, 1, 2, and 3, and the start positions of the rectangles are aligned. Even if the start positions of the rectangular commands are different, the arrangement of the banks is orderly.

In the fourth mapping m4, the access master # 1 and the access master # 2 are started at the same time, and bank contention is reduced due to the relative positional relationship of the start positions in such a rectangular command. . Therefore, the fourth mapping m4 completes all transfers in the same time as the second mapping m2. Thus, even if the arrangement of the banks in the rectangle is arranged in an arbitrary mapping, there may be a difference in efficiency between the arbitrary mapping and another mapping depending on the start position of the rectangle. Therefore, it is only necessary to select a mapping suitable for each combination of the rectangle width and the rectangle start position in consideration of whether transfer of all rectangle commands can be completed most efficiently. In this operation example, if the second mapping m2 and the fourth mapping m4 are selected, transfer of all rectangular commands can be completed most efficiently.

In this embodiment, the case where the number of access masters and memory banks is 2 and 4 is shown, but the same effect can be produced even when the number is 3 or 5 or more.

As described above, in this embodiment, the memory mapping is selected so that the processing time of the rectangular command is minimized. Therefore, the time required to complete the rectangular command processing in an arbitrary operation mode can be minimized. Thereby, the access efficiency can be improved in the access by the rectangular command to the memory having a plurality of banks.

(Other)
Note that the memory access device may be realized by an LSI in which each function of the memory access device is incorporated. LSIs are semi-custom LSIs such as full custom LSI (Large Scale Integration) and ASIC (Application Specific Integrated Circuit), programmable logic such as FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device). The device may be configured as a dynamic reconfigurable device whose circuit configuration can be dynamically rewritten.

Furthermore, the design data that configures each function of the memory access device in the LSI may be a program (HDL program) described in a hardware description language. Further, it may be a gate level netlist obtained by logical synthesis of an HDL program. Alternatively, macro cell information in which arrangement information, process conditions, and the like are added to a gate level netlist may be used. Further, it may be mask data in which dimensions, timing, and the like are defined. Here, examples of hardware description languages include VHDL (Very high speed integrated circuit Hardware Description Language), Verilog-HDL, and SystemC.

Furthermore, the design data may be recorded on a recording medium readable by a hardware system such as a computer system or an embedded system. Furthermore, the program may be read and executed by another hardware system via the recording medium. Then, the design data read by the other hardware system via these recording media may be downloaded to the programmable logic device via the download cable. Here, the computer system-readable recording medium includes an optical recording medium (such as a CD-ROM), a magnetic recording medium (such as a hard disk), a magneto-optical recording medium (such as an MO), and a semiconductor memory (such as a memory card).

Alternatively, the design data may be held in a hardware system connected to a network such as the Internet or a local area network. Furthermore, it may be downloaded to another hardware system via a network and executed. And the design data acquired by other hardware systems via these networks may be downloaded to a programmable logic device via a download cable. Here, as a network, there are a terrestrial broadcast network, a satellite broadcast network, a PLC (Power Line Communication), a mobile telephone network, a wired communication network (IEEE802.3, etc.), and a wireless communication network (IEEE802.11, etc.).

Alternatively, the design data may be recorded in a serial ROM so that it can be transferred to the FPGA when energized. The design data recorded in the serial ROM may be directly downloaded to the FPGA when energized.

Alternatively, the design data may be generated by the microprocessor when energized and downloaded to the FPGA.

The technique of the present invention is useful as an interface with a semiconductor chip or an external memory in a memory access device for controlling a plurality of rectangular data on a memory.

DESCRIPTION OF SYMBOLS 10 Mode fixing device 11 Parameter fixing part 12 Rectangular width / rectangular position holding part 20 Access master 21 Rectangular command issuing part 22 Command conversion part 23 Memory address conversion part 24 Bank generation part 25 Offset generation part 26 Master selector 30 Memory bank 31 Bank Inner selector 32 Memory unit 40 Contention determination unit 50 Priority determination unit 60 Frame region 61 Rectangular command region m1 First mapping m2 Second mapping m3 Third mapping m4 Fourth mapping a1 to a4 Rectangular command b1 to b4 Rectangular Command c1 to c4 Rectangular command d1 to d4 Rectangular command

Claims (10)

1. Multiple memory banks,
   At least one parameter included in a rectangular command for specifying an arbitrary rectangular area in the recording area of the memory bank is fixed based on an operation mode set according to the recording operation of the memory bank, and is set in the operation mode. A mode fixer that generates a mode signal in response,
   Based on the parameters fixed by the mode fixer, an offset on the address position in the memory bank is set, and a plurality of access masters designating an arbitrary memory bank from the memory bank,
   A contention determination unit that identifies the memory bank in which bank contention occurs based on duplication designation by at least two of the access masters;
   The priority in the at least two access masters that specify the memory bank in which the bank conflict occurs is determined, and an in-bank selector selection signal that specifies the access master to be given the highest priority is used as the memory in which the bank conflict occurs. A priority determiner that outputs to the bank and outputs a stop signal to the access master other than the access master to be the highest priority;
   Comprising
   Memory access device.
2. In the memory bank, the rectangular area is specified by the offset supplied from the access master specified by the selector selection signal in the bank,
   The access master is
   A rectangular command issuer for issuing the rectangular command including the parameter fixed by the mode fixer;
   A command converter for generating a subcommand based on the rectangular command and stopping the generation of the subcommand based on the stop signal;
   A memory address converter for converting the subcommand into the bank number and the offset based on memory mapping information corresponding to one operation mode;
   In-master selector that selects the bank number and the offset according to the operation mode;
   With
   A plurality of the memory address converters are provided corresponding to the plurality of operation modes.
   The memory access device according to claim 1.
3. The mode fixer is
   A signal for selecting the memory address converter having the memory mapping information corresponding to the fixed rectangular width and fixing the rectangular width of the rectangular command which is one of the parameters is generated as the mode signal.
   The memory access device according to claim 2.
4. The mode fixer is
   A signal for selecting the memory address converter having the memory mapping information corresponding to the position of the fixed rectangular command and fixing the position of the rectangular command in the frame area, which is one of the parameters, Generate as a mode signal,
   The memory access device according to claim 2.
5. A memory access device according to claim 1;
   A decoding device for decoding image data supplied from the memory access device;
   A display device for displaying the output of the decoding device;
   Comprising
   Video / audio display device.
6. At least one parameter included in a rectangular command for specifying an arbitrary rectangular area in a plurality of memory bank recording areas is fixed based on an operation mode set in accordance with the recording operation of the memory bank, and the operation A mode fixing step for generating a mode signal according to the mode;
   Based on the parameter fixed by the mode fixing step, an offset on the address position in the memory bank is set, and an access master step for designating an arbitrary memory bank from the memory bank;
   A conflict determination step for identifying the memory bank in which bank conflict occurs based on duplication designation by at least two of the access masters;
   The priority in the at least two access masters that specify the memory bank in which the bank conflict occurs is determined, and an in-bank selector selection signal that specifies the access master to be given the highest priority is used as the memory in which the bank conflict occurs. A priority determination step of outputting a stop signal to the access master other than the access master to be the highest priority, and outputting to the bank;
   A memory bank access step of accessing the rectangular area specified by the offset supplied from the access master specified by the intra-bank selector selection signal in the memory bank in which the bank conflict occurs;
   including,
   Memory access method.
7. The access master step includes
   A rectangular command issuing step for issuing the rectangular command including the parameter fixed by the mode fixing step;
   A command conversion step of generating a subcommand based on the rectangular command and stopping the generation of the subcommand based on the stop signal;
   A memory address conversion step of converting the subcommand into the bank number and the offset based on memory mapping information corresponding to one operation mode;
   In-master select step for selecting the bank number and the offset according to the operation mode;
   Including
   The memory address conversion step is performed a plurality of times corresponding to a plurality of the operation modes.
   The memory access method according to claim 6.
8. An LSI incorporating the function of the memory access method according to claim 7.
9. An IP core in which the function of the memory access method according to claim 7 is configured in a programmable logic device (PLD) such as FPGA or CPLD.
10. A computer-readable recording medium for memory access in which a program of the function of the memory access method according to claim 7 is recorded.

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