JP2008225775A - Memory control unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control unit which can cope with a memory operating at high speed, can suppress noise generation by reduction of radio frequency circuits and can reduce electric power consumption. <P>SOLUTION: A memory controller 21 operates on 1/2<SP>N</SP>frequency of a memory clock (N is an integer ≥2), issues 2<SP>N</SP>phases of each memory control signal which controls memory and issues write data by 2<SP>M</SP>phase (M is an integer ≥2). A memory interface circuit 22 converts a memory control signal of 2<SP>N</SP>phase to 1 phase, and write data of 2<SP>M</SP>phase into 1 phase so as to synchronize with the memory clock frequency, and converts read data from the memory into 2<SP>M</SP>phase from 1 phase. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory control device that adjusts data transfer timing between a memory having different operation speeds and a module that desires access to the memory, and in particular, the operation speed is increased as in a DDR2 or DDR3 memory. The present invention relates to a memory control device suitable for memory access.

  For memory that operates at high speed, issue signals to control the memory such as command signals and address signals (hereinafter referred to as memory control signals), and control the data transfer timing of write data (Read Data) and read data (Read Data). Various memory control devices including a memory controller to be adjusted have been proposed (see, for example, Patent Documents 1 to 8).

Patent Document 1 discloses a semiconductor memory device that receives CAS latency information from the outside and has a function of adjusting the timing of a memory control signal, and its timing control.
In this memory device, the main target memory is SDRAM-DDR, and a memory operating at high speed such as DDR2 or DDR3 is not assumed.

  Patent Document 2 discloses a memory control device corresponding to various memories. This memory control device also does not assume a memory that operates at high speed, such as DDR2 or DDR3.

  Patent Document 3 discloses a memory bandwidth control device that makes it possible to use a bandwidth without waste by adjusting the order in which access requests to a memory are made and increasing the bandwidth efficiency by using a data buffer.

Patent Document 4 discloses a memory control system for using a plurality of memory devices in synchronization.
This memory control device also does not assume a memory that operates at high speed, such as DDR2 or DDR3.

Patent Document 5 discloses a method and a circuit for receiving dual edge clock data having a circuit for receiving dual edge clock data.
This circuit needs to include a circuit for transmitting and receiving dual edge clock data to the memory interface circuit.

  Patent Document 6 discloses a memory interface circuit intended to be compatible with various types of memories, as in Patent Document 2.

Patent Document 7 discloses a memory subsystem intended to increase the bandwidth by converting the data width and the data rate, or to reduce the package cost by reducing the number of external data pins. Yes.
In this memory subsystem, one pin of the memory controller is connected to a plurality of memory arrays to increase the data rate, thereby increasing the bandwidth.

Patent Document 8 discloses a bus interface circuit and a data transfer system for processing data synchronized with both edges (rising and falling) of a clock, as in Patent Document 5.
JP 2005-129210 A JP 2005-293013 A JP 2005-84907 A JP-A-11-328004 JP 2005-523548 A JP 09-31816 A Japanese Patent No. 3644265 Japanese Patent Application Laid-Open No. 07-282000

  However, the techniques disclosed in Patent Documents 1, 2, 4, and 6 cannot cope with a memory that operates at high speed, such as DDR2 and DDR3.

  In the technique disclosed in Patent Document 3, the bandwidth efficiency is increased by the data buffer. However, there is a possibility that the circuit scale increases and the circuit becomes complicated, and it is difficult to optimally increase the bandwidth efficiency. There is a fear.

  In the technique disclosed in Patent Document 7, the bandwidth is increased by connecting one pin of a memory controller to a plurality of memory arrays to increase the data rate. However, it is not considered to improve the bandwidth by reducing the blank period between data exchanges by adjusting the latency of the data, which is difficult to realize.

  Further, in the techniques disclosed in Patent Documents 5 and 8, since dual edge clock data is handled, the control and the circuit have to be complicated.

Hereinafter, a general memory control device corresponding to the DDR-333 memory will be described.
FIG. 1 is a block diagram showing a configuration example of a general memory control system corresponding to the DDR-333 memory.

  The memory control system 10 includes a memory controller 11, a memory interface circuit 12, and a DDR-333 memory 13, as shown in FIG.

FIG. 2 is a diagram showing timings of output signals of the memory controller 11 and the interface circuit 12 of FIG.
In FIG. 1, RQPT outputs a request permission signal to another module, MARQ outputs a memory access request signal from another module, MIS outputs a memory information signal from another module, and MCS 11 outputs from the memory controller 11 to the memory interface circuit 12. MCS 12 indicates a memory control signal output from the memory interface circuit 12 to the memory 13. The memory control signal MCS includes a command signal CMD and an address signal ADR.

In the memory control system 10 of FIG. 1, the memory control signal MCS is issued at 166 MHz, which is the same as the memory clock, and only the data is converted from 166 MHz to 333 MHz in the memory interface circuit 13.
That is, for example, when the target memory is DDR-333, in the memory control system 10 of FIG. 1, the memory clock is 166 MHz, the memory controller 11 is also operated at the same 166 MHz, and only the data is 166 MHz in the memory interface circuit 13. The data and the signal were sent to the memory 13 by performing conversion from 2 phase to 1 phase at 333 MHz.

However, the speed of the memory has increased, and high-speed memories such as DDR2-667 and DDR2-800 have appeared, and further high-speed memories such as DDR3-800, DDR3-1066, and DDR3-1333 will appear in the future. When the high-speed memory is the target memory and the frequency of the memory controller is increased in accordance with the memory clock as in the case of DDR-333, the high-frequency noise generated by the high-speed operation of the memory control circuit is a peripheral circuit. There are not a few effects on it.
In addition, it is expected that the power consumption due to the entire memory control circuit operating at a high speed will also increase from the current level.

  An object of the present invention is to provide a memory control device that can deal with a memory that operates at high speed, can reduce high-frequency circuits, can suppress noise generation, and can reduce power consumption. .

A first aspect of the present invention is a memory control device that controls access to a memory, and a memory controller that issues a memory control signal for controlling the memory and adjusts timing of write data and read data to the memory; A memory interface circuit for transferring write data to the memory and transferring read data from the memory to the memory controller in response to a memory control signal from the memory controller. Operates at 1/2 ^N frequency of clock (N is an integer of 2 or more), issues 2 ^N phases of each memory control signal to control the memory, and issues write data in 2 ^M phases (M is an integer of 2 or more) Then, the memory interface circuit converts the 2 ^N- phase memory control signal into one phase to synchronize with the memory clock frequency. ^M phase write data is converted to 1 phase, and read data from memory is converted from 1 phase to 2 ^M phase.

  A second aspect of the present invention is a memory control device that controls access to a memory, and a memory controller that issues a memory control signal for controlling the memory and adjusts timing of write data and read data to the memory; A memory interface circuit for transferring write data to the memory and transferring read data from the memory to the memory controller in response to a memory control signal from the memory controller. Operates at half the clock frequency, synchronizes each memory control signal for controlling the memory with half the frequency, issues it in two phases (in parallel), issues write data in four phases, The interface circuit sends the above two-phase memory control signals to one phase so as to synchronize with the memory clock frequency. Converts the write data of four phases to one phase, it converts the read data from the memory in four phases from one phase.

According to the present invention, the memory controller is operated at 1/2 ^N frequency of the memory clock (N is an integer of 2 or more). The memory controller issues 2 ^N- phase memory control signals for controlling the memory, issues write data in 2 ^M- phase (M is an integer of 2 or more), and outputs it to the memory interface circuit.
The memory interface circuit converts 2 ^N- phase memory control signals to 1 phase, 2 ^M- phase write data to 1 phase, and 1-phase to 2 ^M- phase read data from the memory to synchronize with the memory clock frequency. Convert.

According to the present invention, it is possible to cope with a memory that operates at high speed, the number of high-frequency circuits can be reduced, and noise generation can be suppressed.
And power consumption can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram illustrating a configuration example of a memory control system employing the memory control device according to the embodiment of the present invention.
FIG. 4 is a diagram showing timings of output signals of the memory controller and interface circuit of FIG.

The memory control system 20 includes a memory controller 21, a memory interface circuit 22, and a DDR2-667 memory 23, as shown in FIG. The memory controller 21 and the memory interface circuit 22 constitute a memory control device.
Hereinafter, after describing the signals shown in FIG. 3, the configuration and function of each unit will be described.

  In FIG. 3, RQPT is a request permission signal to another module, MARQ is a memory access request signal from another module, MIS is a memory information signal from another module, WDT is write data, RDT is read data, MCS 211 is a first phase memory control signal output from the memory controller 21 to the memory interface circuit 22, MCS 212 is a second phase memory control signal output from the memory controller 21 to the memory interface circuit 22, and WCPS is from the memory controller 21. RCPS indicates a read command position signal output from the memory controller 21 to the memory interface circuit 22, and DLYI indicates a memory controller 21. The delay information output from the memory controller 21 to the memory interface circuit 22, WDT 21, the write data output from the memory controller 21 to the memory interface circuit 22, and REN the read enable signal output from the memory controller 21 to the memory interface circuit 22. The RDT 22 outputs read data output from the memory interface circuit 22 to the memory controller circuit 21, the MCS 22 outputs memory control signals output from the memory interface circuit 22 to the memory 23, and the WDT 22 outputs from the memory interface circuit 22 to the memory 23. Write data RDT 23 indicates read data read from the memory 23.

  “Memory control signal MCS” in FIG. 3 means a command signal CMD and an address signal ADR issued to the memory (DDR2), and in the timing diagram, only the command signal is described with the address signal omitted. ing.

The “memory information signal MIS” in FIG. 3 means information signals necessary for optimizing the issuance of the memory control signal MCS, such as CAS latency, memory size, and data width.
For example, the memory information includes CAS latency, memory size, data width, and memory operating frequency. For example, the memory information can be changed by a register writable by a CPU (not shown), or the memory 23 in a module (not shown). It is configured to obtain information by receiving the SPD from.

  “Write command position signal WCPS” in FIG. 3 is a determination signal indicating whether the write command output in two phases comes in the first phase or the second phase. In addition to the “delayed information signal DLYI by CL”, the memory interface circuit 23 plays a role of adjusting the amount of latency applied to the write data WDT22.

  Regarding the difference between the “Write command position signal WCPS” and the “delayed information signal DLYI by CL”, the former is a signal that always changes dynamically according to the position of the write command output from the memory controller 21. Is a static signal set by the user via a register or the like, depending on the CAS latency, which is the memory specification.

  Although not shown in the figure, in the system of FIG. 3, the data mask signal is input / output with appropriate timing adjustment as well as the data.

  In the memory control system 10 of the present embodiment, in order not to waste the bandwidth, the write command can be issued from either the first phase or the second phase, and the write command can be issued from the first phase and the second phase. A signal notifying whether it has been issued in one of the phases is passed from the command issuing circuit to the memory interface circuit 22, and the memory interface circuit 22 is configured to adjust the latency of the write data WDT based on this signal.

In the present embodiment. A circuit mechanism is provided that minimizes the circuit area of the portion that adjusts the latency applied to the memory control signal, write data, and read data.
The circuit mechanism that minimizes the circuit area here means that, for example, if the memory clock requires a 5 cyc latency, the latency of 2 cyc is 1 cyc at the same frequency as the memory clock. This means that the circuit mechanism can minimize the number of flip-flops used.

  Next, the configuration and function of each unit will be described.

The memory controller 21 operates in synchronization with the memory controller clock MCCLK of 166 MHz, for example, and outputs a request permission signal RQPT to a module (not shown) accessible to the memory 23, for example, at a high level “HIGH”. When the memory access request signal MARQ is received and the memory access request signal MARQ is received, the request permission signal is switched to the low level “LOW”.
The memory controller 21 selects an appropriate memory control signal (command and address) from the memory information signal MIS and the requested amount of data, and synchronizes it with a clock having a half frequency of the memory clock, as shown in FIG. (Act / Nop) (Write / Nop)... Is output to the memory interface circuit 22 in a two-phase form.
When the memory controller 21 issues the next memory control signal MCS from either the first phase (MCS 211) or the second phase (MCS 212) from the memory access request signal MARQ sent from another module, the memory controller 21 It is determined whether there is no waste in the width, and the timing is adjusted accordingly.

Further, the memory controller 21 uses signals “CL delay information signal DLYI by CL” and “write” for performing latency adjustment with the command and write data WDT in the memory interface circuit 22 based on CAS latency information and memory size information regarding the memory 23. (Write) Command position signal “WCPS is generated.
Also, the memory controller 21 uses a signal “CL delay information signal DLYI by CL” for adjusting the latency given to the command and read enable in the memory interface circuit 22 based on the CAS latency information and the memory size information about the memory 23. And “Read command position signal” RCPS.

  FIG. 5 is a diagram illustrating a configuration example of a memory control signal two-phase circuit in the memory controller according to the present embodiment.

  The memory control signal two-phase circuit 21A of FIG. 5 includes a command decoder 211 and a next command timing adjustment signal generator 212.

The command decoder 211 selects an appropriate memory control signal (command and address) from the memory information signal MIS and the requested data amount, and is synchronized with a clock having a half frequency of the memory clock as shown in FIG. Act / Nop) (Write / Nop)... Is output to the memory interface circuit 22 in a two-phase form. At the same time, the “request permission signal RQPT” is set to “HIGH” in order to receive the next request signal.
At this time, in view of the currently issued memory control signals MCS21 and MCS22, the command decoder 211 issues the next memory control signal in order to issue the next memory control signal at a timing that does not waste the bandwidth of the memory 23. The control signal enable signal S211 is output to the next command timing adjustment signal generator 212.

  The next command timing adjustment signal generator 212 issues a memory control signal to be issued next from either the first phase or the second phase from the enable signal S211 and the memory access request signal MARQ sent from another module. If it is determined that there is no waste in bandwidth, a timing adjustment signal S212 for that purpose is returned to the command decoder 211.

  In the circuit diagram of FIG. 5, the latency adjusting flip-flop (FF) and the FF for stabilizing the signal are omitted.

The memory interface circuit 22 synchronizes the two-phase control signals MCS21, MCS22 ((Act / Nop) (Write / Nop)...) Received from the memory controller 21 with the memory clock MCLK of 333 MHz (Act) (Nop) ( Write) ... and output to the memory 23.
Further, the memory interface circuit 22 adjusts the latency given to the memory control signal MCS22 / Write data WDT22 in accordance with the write command position signal WCPS issued from the memory controller circuit 21 and the delay information signal DLYI by CL. Write data WDT22 is output to the memory 23 at an appropriate timing. At this time, the memory interface circuit 22 also converts the write data from 128 bits to 32 bits.
The memory interface circuit 22 adjusts the latency given to the memory control signal MCS22 / Read enable signal in accordance with the read command position signal RCPS issued from the memory controller circuit 21 and the delay information signal DLYI by CL. Read data RDT23 output from the memory 23 is received at an appropriate timing, and further read enable is returned to the memory controller 21. At this time, the memory interface circuit 22 converts the read data from 32 bits to 128 bits.

FIG. 6 is a diagram illustrating a configuration example of a memory control signal conversion circuit from two phases to one phase of a memory control signal in the memory interface circuit according to the present embodiment.
FIG. 7 is a timing chart of the conversion circuit of FIG.

  The memory control signal conversion circuit 22A of FIG. 6 includes a memory control signal select signal generation unit 221 and a memory control signal selection unit 222.

  The select signal generation unit 221 includes FFs (flip-flops) 2211 to 2214, an AND circuit 2215, and an OR circuit 216.

  The FF 2211 sets and outputs the inverted output in synchronization with the 166 MHz memory controller clock MCCLK. The FF 2212 sets the output of the FF 2211 in synchronization with the 333 MHz memory clock MCLK. That is, the clock frequency is changed from 166 MHz to 333 MHz by the FF 2212. Then, the FF 2213 sets and outputs the output of the FF 2212 with the memory clock MCLK, further adjusts the timing via the AND circuit 2215, the OR circuit 2216, and the FF 2214, and selects a memory control signal whose cycle is equivalent to the memory controller clock. A signal S221 is generated and output to the memory control signal selection unit 222.

The memory control signal selection unit 222 includes a selector 2221 and FFs 2222 and 2223.
For example, the selector 2221 selects the first-phase memory control signal MCS21 when the memory control signal select signal S221 is at a high level, and selects the second-phase memory control signal MCS22 when the memory control signal select signal S221 is at a low level. Output.
The FF 2222 sets and outputs the memory control signal selected by the selector 2221 in synchronization with the memory clock MCLK.
The FF 2223 sets and outputs the memory control signal output from the FF 2222 in synchronization with the inverted clock XMCLK of the memory clock MCLK.

In the circuit diagram of FIG. 6, latency adjusting FFs and FFs for stabilizing signals are omitted.
Further, in the timing chart of FIG. 7, only the one-phase conversion from the two phases of the command signal is depicted, but the address signal is actually converted from the two-phase to the one-phase in the same manner.

FIG. 8 is a diagram illustrating a configuration example of a write data conversion circuit from four phases to one phase of write data in the memory interface circuit according to the present embodiment.
FIG. 9 is a timing chart of the write data conversion circuit of FIG.

  The write data conversion circuit 22B of FIG. 8 includes a write data selection unit 223, a write data select signal generation unit 224, and a write data output unit 225.

  The write data selection unit 223 includes selectors 2231 to 2233 and FFs 2234 and 2235R.

The selector 2231 divides the 128-bit write data WDT21 transferred from the memory controller 21 into 64 bits each in accordance with the memory control signal select signal S221 generated by the select signal generation unit 221 of the memory control signal conversion circuit 22A. Select and output to FF 2234 and selector 2232.
The selector 2231 selects the upper 64 bits [127: 64] of the write data WDT21 when the memory control signal select signal S221 is at a high level, and the lower 64 bits [63 of the write data WDT21 when the memory control signal select signal S221 is at a low level. : 0].

  The FF 2234 sets and outputs the output of the selector 2231 in synchronization with the 333 MHz memory clock MCLK.

The selector 2232 selects the output of the selector 2231 or the output of the FF 2234 according to the write command position signal WCPS from the memory controller 21 and outputs the selected output to the FF 2235 and the selector 2233.
The selector 2232 selects the output of the selector 2231 when the write command position signal WCPS is at a low level, and selects the output of the FF 2234 when it is at a high level.

  The FF 2235 sets and outputs the output of the selector 2232 in synchronization with the 333 MHz memory clock MCLK.

The selector 2233 selects the output of the selector 2232 or the output of the FF 2235 in accordance with the delay information signal DLYI by CL by the memory controller 21, and outputs it to the write data output unit 225 as the signal S223.
The selector 2233 selects the output of the selector 2232 when the delay information signal DLYI by CL is at a low level, and selects the output of the FF 2235 when it is at a high level.

  The write data select signal generation unit 224 includes FFs (flip-flops) 2241 to 2244, an AND circuit 2245, and an OR circuit 246.

  The FF 2241 sets and outputs its inverted output in synchronization with the 333 MHz memory clock MCLK. The FF 2242 sets the output of the FF 2241 in synchronization with the 667 MHz memory data clock MDCLK. That is, the clock frequency is changed from 333 MHz to 667 MHz by FF2242. Then, the FF 2243 sets and outputs the output of the FF 2242 with the memory data clock MDCLK, and further adjusts the timing via the AND circuit 2245, the OR circuit 2246, and the FF 2244, and the select signal of the write data whose cycle is the same as the memory clock. S224 is generated and output to the write data output unit 225.

  The write data output unit 225 includes FFs 2251 to 2255 and a selector 2256.

The FF 2251 sets and outputs the upper 32 bits [63:32] of the 64-bit data selected by the write data selection unit 223 in synchronization with the memory data clock MDCLK.
The FFs 2252 and 2253 are connected in cascade, and set and output the lower 32 bits [31: 0] of the 64-bit data selected by the write data selection unit 223 in synchronization with the memory data clock MDCLK.

The selector 2256 selects the output data of the FF 2251 when the write data select signal S224 is at the low level, and selects the output of the FF 2253 when it is at the high level, and outputs it to the FF 2254.
The FF 2254 sets and outputs the write data selected by the selector 2256 in synchronization with the memory data clock MDCLK.
The FF 2255 sets and outputs the write data output from the FF 2254 in synchronization with the inverted clock XMDCLK of the memory data clock MDCLK.

  In the circuit diagram of FIG. 8, the FF for latency adjustment and the FF for stabilizing the signal are omitted.

FIG. 10 is a diagram illustrating a configuration example of a read data conversion circuit from one phase to four phases of read data in the memory interface circuit according to the present embodiment.
FIG. 11 is a timing chart of the read data conversion circuit of FIG.

  The read data conversion circuit 22C in FIG. 10 includes a read data fetch unit 226 and a read data output unit 227.

The read data fetch unit 226 is configured by FFs 2261 to 2268.
The FF 2261 receives the signal DQS It is preset by MSKI, and its negative output is set in synchronization with the signal DQS [0] having the same frequency as the memory clock, and is output as an enable signal (en) for FF 2262 to FF 2268.
The FF 2262 and FF 2264 are synchronized with the signal DQS [0], and the FF 2263 and FF 2265 are, for example, 8-bit read data DQ [7: 0] read from the memory 23 in synchronization with the inverted signal of the signal DQS [0]. Set and output.
The FF 2266, FF 2267, and FF 2268 set and output the outputs of the FF 2262, FF 2263, and FF 2264 in synchronization with the inverted signal of the signal DQS [0].
Then, the output data of FF 2266, FF 2267, FF 2268, and FF 2265 are combined into 32 bits and supplied to the read data output unit 227.

  The read data output unit 227 includes FFs 2271 to 2274 and selectors 2275 and 2276.

The FF 2271 sets read data by the read data fetch unit 226 in synchronization with the 166 MHz memory controller clock MCCLK, and outputs the read data to the FF 2272.
The FF 2272 sets read data from the FF 2271 in synchronization with the 166 MHz memory controller clock MCCLK and outputs the read data to the selector 2276.
The FF 2273 sets read data by the read data fetch unit 226 in synchronization with the inverted signal of the 166 MHz memory controller clock MCCLK and outputs the read data to the FF 2274.
The FF 2274 sets read data from the FF 2273 in synchronization with the 166 MHz memory controller clock MCCLK, and outputs the read data to the selector 2276.

The selector 2275 selects the read command position signal RCPS when the delay information signal DLYI by CL is at a low level, and selects the inverted signal of the read command position signal RCPS when the delay information signal DLYI by CL is at a high level, and selects the selector 2276 as a select signal S2275. Output to.
The selector 2276 selects the output of the FF 2272 when the select signal S2275 is the read command position signal RCPS, and selects the output of the FF 2274 when it is an inverted signal of the read command position signal RCPS.

In the circuit diagram of FIG. 10, FFs for latency adjustment and FFs for stabilizing signals are omitted.
In addition, although only DQ [7: 0] is handled in the timing chart of FIG. 11, a similar circuit is configured for other DQ [31: 8], and read data [127: 32] is output. Has been.

  Next, the operation according to the above configuration will be described separately for a write operation and a read operation.

<For Write>
Only when the “request permission signal RQPT” is “HIGH”, the module that wishes to perform memory access to the memory 23 issues a write memory access request signal MARQ to the memory controller 21.
The memory controller 21 receives the memory access request signal MARQ from the module and switches the level of the “request permission signal RQPT” to “LOW”.

The command decoder 211 of the memory controller 21 selects an appropriate memory control signal (command CMD and address ADR) MCS from the memory information signal MIS and the requested data amount, and synchronizes it with the clock MCCLK having a frequency half the memory clock MCLK. As shown in FIG. 4, the data is output to the memory interface circuit 22 in a two-phase form such as (Act / Nop) (Write / Nop). At the same time, in order to receive the next memory access request signal MARQ, the level of the “request permission signal RQPT” is switched to “HIGH”.
At this time, in view of the currently issued memory control signal MCS, the command decoder 211 issues the next memory control signal MCS in order to issue the next memory control signal MCS at a timing that does not waste the bandwidth of the memory 23. The signal enable signal S211 is output to the next command timing adjustment signal generator 212.

When the next command timing adjustment signal generator 212 issues a memory control signal to be issued next from either the first phase or the second phase from the enable and the memory access request signal MARQ sent from another module. It is determined whether or not the bandwidth is wasted, and a timing adjustment signal S212 for that purpose is returned to the command decoder 212.
Further, in the memory controller 21, a signal “delay information signal DLYI by CL” for adjusting the latency by the command and write data in the memory interface circuit 22 from the CAS latency information and the memory size information regarding the memory 23 is generated. Generate. Furthermore, the memory controller 21 also generates a “Write command position signal WCPS” from the command issued from the command decoder 211 for the same purpose.

In the memory control signal conversion circuit 22A, the memory interface circuit 22 synchronizes the received two-phase control signals (Act / Nop) (Write / Nop)... With the memory clock MCLK (Act) (Nop) (Write). It is output as a single phase.
Further, the memory interface circuit 22 adjusts the latency given to the memory control signal MCS and the write data according to the write command position signal WCPS issued from the memory controller circuit 21 and the delay information signal DLYI by CL, thereby writing Data WDT 22 is output to memory 23 at an appropriate timing. At this time, the write data conversion circuit 22B of the memory interface circuit 22 also converts the write data from 128 bits to 32 bits.
Then, the memory 23 stores the write data WDT22 according to the input memory control signal MCS22.

<For Read>
Only when the “request permission signal RQPT” is “HIGH”, the module that wants to perform memory access to the memory 23 issues a read memory access request signal MARQ to the memory controller 21.
The memory controller 21 receives the memory access request signal MARQ from the module and switches the level of the “request permission signal RQPT” to “LOW”.

The command decoder 211 of the memory controller 21 selects an appropriate memory control signal (command CMD and address ADR) MCS from the memory information signal MIS and the requested data amount, and synchronizes it with the clock MCCLK having a frequency half the memory clock MCLK. As shown in FIG. 4, the data is output to the memory interface circuit 22 in a two-phase form such as (Act / Nop) (Write / Nop). At the same time, in order to receive the next memory access request signal MARQ, the level of the “request permission signal RQPT” is switched to “HIGH”.
At this time, in view of the currently issued memory control signal MCS, the command decoder 211 issues the next memory control signal MCS in order to issue the next memory control signal MCS at a timing that does not waste the bandwidth of the memory 23. The signal enable signal S211 is output to the next command timing adjustment signal generator 212.

When the next command timing adjustment signal generator 212 issues a memory control signal to be issued next from either the first phase or the second phase from the enable and the memory access request signal MARQ sent from another module. It is determined whether or not the bandwidth is wasted, and a timing adjustment signal S212 for that purpose is returned to the command decoder 212.
In the memory controller 21, a signal “delay information signal DLYI by CL” for adjusting the latency given to the command and read enable in the memory interface circuit 22 from the CAS latency information and the memory size information about the memory 23. Is generated. Further, the memory controller 21 generates a “Read command position signal RCPS” from the command issued from the command decoder 211 for the same purpose.
Further, the memory interface circuit 22 adjusts the latency given to the memory control signal MCS and the read enable signal in accordance with the read command position signal RCPS issued from the memory controller circuit 21 and the delay information signal DLYI by CL. As a result, the read data RDT23 output from the memory 23 is received at an appropriate timing, and the read enable is further returned to the memory controller 21. At this time, the read data is converted from 32 bits to 128 bits by the read data conversion circuit 22C.

As described above, according to the present embodiment, the memory controller 21 selects an appropriate memory control signal (command and address) from the memory information signal MIS and the requested data amount, and has a frequency half that of the memory clock. In synchronization with the clock, as shown in FIG. 4, a memory access request signal sent from another module is output to the memory interface circuit 22 in a two-phase form such as (Act / Nop) (Write / Nop). From MARQ, it is determined whether the memory control signal MCS to be issued next is issued from the first phase (MCS21) or the second phase (MCS22), and the bandwidth is not wasted, and the timing adjustment is performed for that. Also, the memory controller 21 determines the memory interface from the CAS latency information and memory size information regarding the memory 23. The signal “delay information signal DLYI by CL” and “write command position signal” WCPS for adjusting the latency by the command and the write data WDT are generated by the source circuit 22, and the memory controller 21 stores the memory 23 "Delay information signal DLYI by CL" and "Read command position signal" for adjusting latency given to the command and read enable in the memory interface circuit 22 from the CAS latency information and memory size information, etc. Generate RCPS.
The memory interface circuit 22 synchronizes the two-phase control signals MCS211 and MCS212 ((Act / Nop) (Write / Nop)...) Received from the memory controller 21 with the memory clock MCLK of 333 MHz (Act) (Nop ) (Write)... Are output to the memory 23, and the memory interface circuit 22 follows the write command position signal WCPS issued from the memory controller circuit 21 and the delay information signal DLYI based on the CL. By adjusting the latency given to the MCS22 / Write data WDT22, the write data WDT22 is output to the memory 23 at an appropriate timing. At this time, the memory interface circuit 22 also converts the write data from 128 bits to 32 bits.
Further, the memory interface circuit 22 adjusts the latency given to the memory control signal / read enable signal in accordance with the read command position signal RCPS issued from the memory controller circuit 21 and the delay information signal DLYI by CL. Read data RDT23 output from the memory 23 is received at an appropriate timing, and read enable is returned to the memory controller 21. At this time, the memory interface circuit 22 converts the read data from 32 bits to 128 bits.

  Therefore, according to this memory control system, it is possible to cope with a memory that operates at high speed, it is possible to reduce high-frequency circuits, suppress noise generation, reduce power consumption, and reduce bandwidth. There is an advantage that efficiency improvement can be realized.

It is also possible to adopt a configuration in which the memory controller 21 and the memory interface circuit 22 are integrated.
It is also possible to have a function of setting the number of phases for issuing a memory control signal by an external select signal.
It is also possible to configure so that the clock supply to the circuit corresponding to the phase that does not operate can be stopped.

<Modification 1>
FIG. 12 is a diagram showing a first modification of the memory control system that employs the memory control device according to the embodiment of the present invention.
FIG. 13 is a diagram showing timings of output signals of the memory controller and interface circuit of FIG.

  The memory control system 20A in FIG. 12 is different from the memory control system 20 in FIG. 3 in that the memory control signal has two phases and the data is changed from four phases to eight phases. .

  In this modification example having four phases, a “write data latency adjustment signal WLAJ” in which the “write command position signal” and the “delay information signal by CL” shown in FIGS. 3 and 4 are combined is used. . In addition, a “Read enable latency adjustment signal WLAJ” in which “Read command position signal” and “CL delay information signal” are combined.

The upper 2 bits of the “Write data latency adjustment signal WLAJ” are responsible for the CL delay information, and are static signals obtained by setting the value of CL, which is the spec of the memory, in the register.
On the other hand, the lower 2 bits have the role of adjusting the write data to give a delay of 0 to 3 cyc. This signal is the value of CL, which is the memory specification, and the phase of the active command Act issued. It is a dynamic signal that is comprehensively judged from the information and phase information for which a write command (Write) is issued and output.

A memory control system with a memory controller and memory interface that outputs memory control signals at 1/2 ^N clock frequency and 2 ^N phase and inputs / outputs data at 2 ^M phase with the same concept. Can be formed.

That is, based on the same concept as the configuration of FIGS. 3 and 12, the memory controller is operated at 1/2 ^N frequency (N is an integer of 2 or more) of the memory clock, the control signal is issued in 2 ^N phase, and the write is performed in the same manner. Data is issued in 2 ^M- phase (M is an integer of 2 or more), the memory interface circuit converts the memory control circuit from 2 ^N- phase to 1-phase, Write data is converted from 2 ^M- phase to 1-phase, and memory It is possible to configure a memory control system with a mechanism that converts the read data from 1 phase to 2 ^M phase.
Also in this case, in the circuit that issues the memory control signal from the memory controller 21 in multiple phases, the memory controller issues a signal for determining the phase at which the Write (Read) command is issued, and the memory interface circuit By receiving the signal and optimally adjusting the latency of the write (read) data, it is possible to reduce the high-frequency circuit portion without reducing the bandwidth efficiency.
It is also possible to provide a circuit mechanism that minimizes the circuit area of the portion that adjusts the latency applied to the memory control signal / write and read data.
The circuit mechanism that minimizes the circuit area here is, for example, when the memory clock requires a latency of Xcyc, Rcyc (R is an integer of 2 or more) at 1/2 ^N frequency of the memory clock. the latency of the quotient) obtained by dividing X by 2 ^N, Pcyc at the same frequency as the memory clock (P is to provide a latency remainder) obtained by dividing X by 2 ^N, the number of flip-flops to be used It means a circuit mechanism that can be minimized.

<Modification 2>
FIG. 14 is a diagram showing a second modified example of the memory control system employing the memory control device according to the embodiment of the present invention.
FIG. 15 is a diagram showing timings of output signals of the memory controller and interface circuit of FIG.

In the above embodiment, since the bandwidth is not wasted as the second stage, the write command can be issued from either the first phase or the second phase, and the write command is the first phase. A signal notifying whether it has been issued in one of the second phases is passed from the command decoder to the memory interface circuit, and based on this signal, a memory interface circuit for adjusting the latency of the write data is obtained.
In the second modification, the specification of the memory controller is changed so that a write command is issued only in the first phase.
Therefore, it is necessary to insert a Nop command before issuing the second Active-Nop-Write-Nop-Nop command, and as a result, a 1 cyc blank cycle can be made (at 333 MHz) when Write data is transferred. Therefore, although the bandwidth is inferior to the above embodiment in terms of efficiency improvement, it is possible to cope with a memory that operates at high speed, it is possible to reduce high-frequency circuits, suppress noise generation, and power consumption. Can be reduced.

It is a block diagram which shows the structural example of the general memory control system corresponding to DDR-333 memory. FIG. 2 is a diagram illustrating timings of output signals of the memory controller and interface circuit of FIG. 1. It is a figure which shows the structural example of the memory control system which employ | adopted the memory control apparatus which concerns on embodiment of this invention. It is a figure which shows the timing of the output signal of the memory controller and interface circuit of FIG. It is a figure which shows the structural example of the memory control signal two-phase circuit in the memory controller which concerns on this embodiment. It is a figure which shows the structural example of the memory control signal conversion circuit from 2 phases of the memory control signal in the memory interface circuit which concerns on this embodiment to 1 phase. 7 is a timing chart of the memory control signal conversion circuit of FIG. 6. It is a figure which shows the structural example of the write data conversion circuit from 4 phases of the write data to 1 phase in the memory interface circuit which concerns on this embodiment. 9 is a timing chart of the write data conversion circuit of FIG. 8. It is a figure which shows the structural example of the read data conversion circuit from 1 phase of read data to 4 phases in the memory interface circuit which concerns on this embodiment. 11 is a timing chart of the read data conversion circuit in FIG. 10. It is a figure which shows the 1st modification of the memory control system which employ | adopted the memory control apparatus which concerns on embodiment of this invention. FIG. 13 is a diagram showing timings of output signals of the memory controller and interface circuit of FIG. It is a figure which shows the 2nd modification of the memory control system which employ | adopted the memory control apparatus which concerns on embodiment of this invention. FIG. 15 is a diagram illustrating timings of output signals of the memory controller and interface circuit of FIG. 14.

Explanation of symbols

20, 20A, 20B ... Memory control system, 21, 21A, 21B ... Memory controller, 22 ... Memory interface circuit, 23 ... Memory.

Claims (13)

A memory control device for controlling access to a memory,
A memory controller that issues a memory control signal for controlling the memory and adjusts the timing of write data and read data to the memory;
A memory interface circuit for transferring write data to the memory and transferring read data from the memory to the memory controller in response to a memory control signal by the memory controller;
The memory controller
Operates at 1/2 ^N frequency of the memory clock (N is an integer of 2 or more), issues 2 ^N phases of each memory control signal to control the memory, and writes data in 2 ^M phases (M is an integer of 2 or more) Issue,
The memory interface circuit is
The above 2 ^N phase memory control signal is converted to 1 phase, 2 ^M phase write data is converted to 1 phase, and read data from the memory is converted from 1 phase to 2 ^M phase so as to synchronize with the memory clock frequency Memory control apparatus. The memory controller
Issue a decision signal to determine whether the write command or read command included in the memory control signal was issued in any phase from the 1st phase to the 2nd ^N phase,
The interface circuit of the memory is
The memory control device according to claim 1, wherein the memory control device optimally adjusts the latency of write data or read data in response to the determination signal. 3. The memory control device according to claim 2, further comprising a circuit mechanism that minimizes a circuit area of a portion that adjusts a latency applied to the memory control signal, the write data, and the read data. The memory controller
3. The memory control according to claim 2, wherein the memory information of the target memory is received from outside and a signal instructing the memory interface to adjust the latency of the memory control signal, the write data, and the read data according to the memory information is output. apparatus. The memory control device according to claim 4, further comprising a circuit mechanism that minimizes a circuit area of a portion that adjusts a latency applied to the memory control signal, the write data, and the read data. A memory control device for controlling access to a memory,
A memory controller that issues a memory control signal for controlling the memory and adjusts the timing of write data and read data to the memory;
A memory interface circuit for transferring write data to the memory and transferring read data from the memory to the memory controller in response to a memory control signal by the memory controller;
The memory controller
Operates at 1/2 the frequency of the memory clock, and synchronizes each memory control signal that controls the memory to 1/2 frequency, issues it in 2 phases (in parallel), issues write data in 4 phases,
The memory interface circuit is
A memory control device for converting the two-phase memory control signal to one phase, converting four-phase write data to one phase, and converting read data from the memory from one phase to four phases so as to synchronize with a memory clock frequency. The memory controller
Issuing a determination signal for determining which side of the first phase or the second phase a write command or read command included in the memory control signal is issued,
The interface circuit of the memory is
The memory control device according to claim 6, wherein the determination signal is received to optimally adjust the latency of the write data or read data. The memory control device according to claim 7, further comprising a circuit mechanism that minimizes a circuit area of a portion that adjusts a latency applied to the memory control signal, the write data, and the read data. The memory controller
8. The memory control according to claim 7, wherein the memory information of the target memory is received from outside and a signal instructing the memory interface to adjust the latency of the memory control signal and the write data and read data according to the memory information. apparatus. The memory control device according to claim 9, further comprising a circuit mechanism that minimizes a circuit area of a portion that adjusts a latency applied to the memory control signal, the write data, and the read data. The memory control device according to claim 1, wherein the memory controller and a memory interface circuit are integrated. The memory controller
The memory control device according to claim 1, wherein the memory control device has a function of setting a number of phases for issuing a memory control signal by an external select signal. The memory control device according to any one of claims 1 to 12, wherein the clock supply to a circuit corresponding to a phase that does not operate can be stopped.

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