JPH1155484A - Image data storage processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To utilize the high speed page mode in the case of rotating an image by designating optionally a longitudinal/lateral size of the image to be processed so as to utilize a memory effectively. SOLUTION: An image address is divided in the unit of 2<n> ×2<m> addresses, high-order (total bit number - (n+m)) bits of an image address consisting of a prescribed bits used as a logic address are generated by an adder/subtractor 73. An in-block main scanning counter 61 counts the image in the main scanning direction in the unit of one address and n-bits among low-order (n+m) bits of the image address are outputted. An in-block subscanning counter 62 counts addresses in the unit of one address in the subscanning direction to provide an output of m-bits among the low-order (n+m) bits of the image address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital copying machine,
The present invention relates to an image data storage processing device applied to an apparatus that handles image data, such as a scanner, a printer, and a facsimile.

[0002]

2. Description of the Related Art In recent years, with the advance of digitalization of copying machines, processing and editing using an image memory have become active. For example, there are image rotation, image repeat by address operation at the time of memory reading, and into1 for copying a plurality of originals onto one transfer sheet by address operation at the time of writing. In order to satisfy the above functions, a digital copying machine having a memory function generally has an image memory corresponding to at least one document. Image memory has a relatively large capacity and requires high speed,
DRAM (Dynamic Random Accesses)
s Memory). DR
Various modes are provided for accessing the AM depending on how the control signal is applied. In general, a normal mode in which a single address is accessed is used for normal reading and writing, and when high speed is required, a high speed page mode can be used on condition that continued access is to the same row. When this high-speed page mode is used for a copying machine,
Image data transferred from the scanner in raster format
It is possible to store data at consecutive addresses in the DRAM using the high-speed page mode. However, in the case where the stored image is read by applying a rotation of 90 degrees or 270 degrees, the address to be accessed is not on the same line unless some measures are taken, and the high-speed page mode cannot be used.

[0003]

Therefore, as a conventional technique which makes it possible to use the high-speed page mode at the time of rotation,
The one described in JP-A-6-96196 is known. In this prior art, the main scanning counter and the sub-scanning counter are separated, and the lower order of both counter outputs is added to a column (column) address. Is switched, the high-speed page mode is enabled by the number of bits added to the column address from the sub-scanning counter. However, in the prior art, the main scanning counter and the sub scanning counter are separated,
Since the vertical and horizontal image size is selected to be 2 n, the vertical and horizontal size of the image is determined, and if the vertical and horizontal size of the image is arbitrary, the memory is wasted and it cannot be used effectively. there were.

Therefore, a first object of the present invention is to allow the user to arbitrarily specify the vertical and horizontal sizes of an image to be handled,
Accordingly, it is an object of the present invention to provide an image data storage processing device that can effectively use a memory without waste and can use a high-speed page mode even when rotating an image. A second object of the present invention is to provide an image data storage processing device which can flexibly correspond to the type of image memory to be used and the like and can respond to a system to be used.

A third object of the present invention is to provide an image data storage processing device capable of reducing the access frequency of an image memory and increasing the transfer rate of input / output image data. . A fourth object of the present invention is to reduce the amount of data to be stored or read in an image memory for input / output image data, thereby making it possible to cope with a higher transfer rate of input / output image data. An object of the present invention is to provide an image data storage processing device capable of reducing the capacity and reducing the cost.

[0006]

According to the first aspect of the present invention, there is provided an image memory capable of reading and writing image data, and an image address generating means for generating an image address consisting of predetermined bits. The image address output from the image memory is divided into a row address and a column address, the address of the image memory is designated, and the image data input in raster format is stored at the designated address of the image memory. In the image data storage processing device capable of rotating and reading the image data, the image address generating means divides the image address into 2 ⁿ × 2 ^m address units, -(N + m)) logical address generating means for generating a bit as a logical address, and one address along the main scanning direction of the image. A main scanning counter in a block that outputs n bits of the lower (n + m) bits of the image address, and counts one address along the sub-scanning direction of the image, and counts the lower (n + m) of the image address. The first object is achieved by providing an intra-block sub-scanning counter which outputs m bits of the bits.

According to a second aspect of the present invention, in the image data storage processing apparatus according to the first aspect, the logical address generating means sets a base address register for setting a base logical address and a rotation angle of the image. A rotation angle register; and a main scanning length register for setting a main scanning length of the image when the image memory is two-dimensional. A value obtained by multiplying the number of times of overflow or underflow of the scanning counter by a number of times and a value of the number of times corresponding to the number of times of overflow or underflow of the main scanning counter in the block by the rotation angle set in the rotation angle register. Accordingly, the logical address is added or subtracted from the base address set in the base address register. By outputting the less, to achieve the first object.

According to a third aspect of the present invention, in the image data storage processing device according to the first or second aspect, the intra-block main scanning counter comprises a plurality of counters having different numbers of bits. One of the counters is made freely selectable, and the block sub-scanning counter comprises a plurality of counters having different numbers of bits, and one of these counters is made freely selectable, thereby achieving the second object.

According to a fourth aspect of the present invention, in the image data storage processing device according to the first aspect, one of the image memories is provided.
The third object is achieved by storing data of a plurality of pixels in an address and changing the arrangement of the data before or after writing to the image memory according to the rotation angle set in the rotation angle register. To achieve.

According to a fifth aspect of the present invention, in the image data storage processing device according to the fourth aspect, the data for a plurality of pixels stored in the image memory is subjected to a data compression process before being stored in the image memory. The fourth object is achieved by using the above-mentioned code data.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration when the image data storage processing device of the present invention is applied to a digital copying machine. As shown in FIG. 1, the digital copying machine reads a document image and obtains image data according to the reading. An image forming apparatus performs image forming based on image data from the reading unit 1 and the like. Unit 2, a storage unit 4 for storing image data from the reading unit 1, a selector unit 5 for selecting image data to be transferred to the image forming unit 2 from the reading unit 1 or the storage unit 4, and an operator (operator). An operation unit 6 for performing various instructions and a system control unit 7 for controlling each unit based on the instructions from the operation unit 6 are provided.

Next, the process of reading an image by the reading section 1 will be briefly described. A document 12 set on a document table 11 is exposed and scanned by an exposure lamp 13, and reflected light from the document 12 is reflected via a reflection mirror 14 and the like as a CCD (Charge Coupled) serving as an image sensor.
Device 15). The CCD 15 performs photoelectric conversion and outputs an electric signal according to the intensity of light. I
The PU (image processing unit) 16 performs processing such as shading correction on the electric signal,
A / D conversion is performed on an 8-bit digital signal, and image processing such as scaling processing and dither processing is performed. The image signal is sent to the image forming unit 2 and the like together with an image synchronization signal. The scanner control unit 17 performs detection of various sensors, controls a drive motor and the like, and sets various parameters for the IPU 16 in order to execute the above document reading process.

Next, the image forming process of the image forming section 2 will be briefly described. In the image forming unit 2, the photoreceptor 22, which is uniformly charged by the charging charger 21 and rotates at a constant speed, is exposed to laser light modulated by image data from the writing unit 23. As a result, an electrostatic latent image is formed on the photoreceptor 22, and the electrostatic latent image is developed into a toner image by developing with the toner by the developing device 24. The paper feed tray 25 is fed by the paper feed roller 25 in advance.
The transfer paper, which has been fed and conveyed from the registration roller 27, is conveyed to the photoconductor 22 in a timely manner, and the toner on the photoconductor 22 is electrostatically transferred to the transfer paper by the transfer charger 28. As a result, the transfer paper is separated from the photoconductor 22. Thereafter, the toner image on the transfer paper is heated and fixed by the fixing device 30, and is discharged onto a discharge tray 32 by a discharge roller 31. On the other hand, the toner remaining on the photoconductor 22 after the electrostatic transfer is removed by pressing the cleaning device 33 against the photoconductor 22, and the photoconductor 22 is discharged by the discharging charger 34. The plotter control unit 35 detects various sensors and controls a drive motor and the like in order to execute the above-described image forming process.

The system control unit 7 detects the input state of the operator to the operation unit 6 and scans the scanner control unit 17 of the reading unit 1, the storage unit 4, and the plotter control unit 35 of the image forming unit 2.
The setting of various parameters to the server, the process execution instruction, etc. are performed by communication. The status of the entire system is displayed on the operation unit 6. An instruction to the system control unit 7 is performed by a key input to the operation unit 6 by the operator. Selector section 5
Changes the state of the selector (switching contact) according to an instruction from the system control unit 7 and selects the source of image data on which the image forming unit 2 performs image formation from the reading unit 1 or the storage unit 4. The storage unit 4 stores image data of one document normally input from the IPU 16 and is used for a copy application such as a repeat copy and a rotation copy. The instruction to store the image data in the storage unit 4 is given by the system control unit 7.

Next, an image synchronizing signal output from the IPU 16 of the reading section 1 will be described with reference to FIG. As shown in FIG. 4, the frame gate signal (/ FGATE)
Is a signal indicating an image effective range for an image area in the sub-scanning direction, and image data is valid while the frame gate signal is at a low level (low active).
The frame gate signal (/ FGATE) is asserted or negated at the falling edge of the line synchronization signal (/ LSYNC). Line synchronization signal (/
LSYNC) is asserted for a predetermined number of clocks at the rising edge of the pixel synchronization signal (PCLK), and after the rising of this signal, the image data in the main scanning direction becomes valid after a predetermined clock. The transmitted image data is one for one cycle of the pixel synchronization signal (PCLK), and is divided into 400 dpi equivalents from the arrow portion in FIG. The image data is sent out as raster format data starting from the arrow. The effective sub-scanning range of image data is usually determined by the size of the transfer paper.

Next, the detailed configuration of the storage unit 4 shown in FIG. 1 will be described with reference to the block diagram of FIG. The storage unit 4 includes, as shown in FIG.
1, a pixel synchronization signal generator 42, a selector 43, a selector 44, a memory controller 45, an image memory 46, and the like. The line synchronizing signal generator 41 is constituted by a logic circuit such as TTL, and normally generates and outputs a line synchronizing signal based on the polygon motor synchronizing signal from the image forming unit 2. The pixel synchronization signal generator 42 is configured by an oscillation circuit and outputs a clock of a predetermined frequency.

The selector 43 includes a pixel synchronization signal generator 42
, Or an input pixel synchronization signal according to an instruction signal from the memory control unit 45. This selector 43 is constituted by a TTL gate. The selector 44 selects one of the line synchronization signal from the line synchronization signal generator 41 and the input line synchronization signal in accordance with an instruction signal from the memory controller 45. This selector 44 is constituted by a TTL gate. The memory control unit 45 is configured as shown in FIG. 5, and the details of the configuration will be described later. The image memory 46 stores image data under the control of the memory control unit 45, and
M and other storage elements. This image memory 46
The total of the memory capacity is usually 4 Mbytes, but it can be increased to increase the memory capacity for a plurality of documents.

Next, the detailed configuration of the memory control unit 45 shown in FIG. 3 will be described with reference to the block diagram of FIG. The memory control unit 45, as shown in FIG.
(Microprocessor) 51, input data processing unit 52,
It comprises an output data processing section 53, an arbiter 54, an input image address counter 55, an output image address counter 56, an address selector 57, and an access control circuit 58. Among these components, each block other than the MPU 51 is formed of a logic circuit.

The MPU 51 communicates with the system control unit 7, receives a command, performs an operation setting corresponding to the command for each block, and transmits status information to notify the state of the storage unit 4 to the system control unit 7. Transmit to the unit 7. The input data processing unit 52 fetches 1-bit input image data together with an input image synchronization signal, packs the data into a 4-bit data width, synchronizes the input image data with an internal operation clock, and supplies an input memory to the arbiter 54. An access request signal is output. Further, in response to an input memory access permission signal from the arbiter 54, 4-bit data is sequentially output to the image data bus at a predetermined timing in 1-bit serial. Conversely, the output data processing section 53 outputs an output memory access request signal to the arbiter 54 at the image output timing. Then, in response to the output memory access permission signal from the arbiter 54, the image data is taken in from the image data bus at a predetermined timing and output as 1-bit output image data together with the output image synchronization signal. Since the output clock is different from the internal operation clock, the output image data is synchronized with the output clock.

The input image address counter 55 and the output image address counter 56 have the same configuration. The input image address counter 55 counts up according to the input memory access permission signal.
Counts up by the output memory access permission signal. The arbiter 54 arbitrates an input memory access request signal from the input data processing unit 52 and an output memory access request signal from the output data processing unit 53. The address selector 57 selects a read (read) or write (write) address according to a selection signal from the arbiter 54, and divides the selected address into a row address and a column address corresponding to the DRAM as the image memory 46. Output to a 12-bit image address bus. The access control circuit 58 controls the DRAM control signals (RAS, CAS, W
E) is output. The high-speed page mode access shown in the lower part of FIG. 8 is a timing chart of the access control signal of this embodiment, and one access requires 12 operation clocks. In this high-speed page mode, four addresses are successively accessed, and a half of the time required in the normal mode access in which a single address is accessed is half of that in the case where four addresses are accessed. is there.

Next, the configuration of the input image address counter 55 and the output image address counter 56 shown in FIG.
This configuration will be described with reference to an explanatory diagram of the addressing of the image memory for the two-dimensional image in FIG. In this embodiment, as shown in FIG. 7, an image address is divided into 2 ⁿ × 2 ^m address units in the main scanning direction and the sub-scanning direction, and the divided address units are used as one logical block. is there. Therefore, in this embodiment, the coefficients n and m indicating the size of the logical block are
Assuming that n = m = 2, as shown in FIG. 7, 4 addresses × 4 addresses in the main scanning direction and the sub-scanning direction will be described as one logical block. In general addressing (address designation), the numerical value “16, 17, 18, 19” in FIG. 7 becomes a sequential address of “4, 5, 6, 7”. In this embodiment, The address counter outputs a sequential address in the logical block.

In order to specify such an address, the input image address counter 55 of this embodiment is used.
As shown in FIG. 6, the (output image address counter 56) is composed of a main scanning counter 61 in the block and a sub-scanning counter 62 in the block. An address is generated, and based on the output values of the intra-block main scanning counter 61 and the intra-block sub-scanning counter 62, the address of the upper bit side of the image address is output from the adder / subtractor 73 as a logical address. (See the upper side of FIG. 12).

Next, the details of the input image address counter 55 (output image address counter 56) will be described. The intra-block main scanning counter 61 is a 2-bit counter that counts in units of one address along the main scanning direction of the image, and counts the clock output from the selector & clock generation circuit 63. The intra-block sub-scanning counter 62 is a 2-bit counter that counts in units of one address along the sub-scanning direction of the image, and counts the clock output from the selector & clock generation circuit 63.

The selector & clock generation circuit 63 is adapted to operate the decoder 6 based on the rotation information of the rotation angle register 64 image.
5, the clocks output to the intra-block main scanning counter 61 and the intra-block sub-scanning counter 62 are exchanged by the XYCHG signal indicating the exchange between the main scanning direction and the sub-scanning direction. That is, when there is no rotation of the image, the selector & clock generation circuit 63 generates four pulses each time the access permission signal is input, outputs the generated four pulses to the output terminal “2Y”, and outputs one pulse from the line end signal. It is generated and output to the output terminal "1Y". When the image is rotated by 90 °, the XYCHG signal becomes active, and the selector & clock generation circuit 63 generates four pulses each time the access permission signal is input, and outputs the generated four pulses to the output terminal “1Y”, and the line end is output. One pulse is generated from the signal and output to the output terminal “2Y”. Here, the line end signal is a signal generated every time writing or reading of one line of image data is completed.

Similarly, selector & load generating circuit 66
Replaces the timing of initializing the counter value by the XYCHG signal. That is, when the image is not rotated, the selector & load generating circuit 66 generates one pulse in response to the input of the start signal and outputs the output terminal “1”.
Y ”, generates one pulse from the line end signal, and outputs it to the output terminal“ 2Y ”. When the image is rotated by 90 °, the XYCHG signal becomes active and the selector &
The load generation circuit 66 outputs 1 in response to the input of the start signal.
A pulse is generated and output to the output terminal "2Y", and one pulse is generated from the line end signal and output to the output terminal "2Y".

On the basis of the rotation information from the rotation angle register 64, the decoder 65 sets the main scanning counter 6 in the block.
1. Generate an XDOWN signal and a YDOWN signal indicating an increase or a decrease in the address value of the intra-block sub-scanning counter 62, and generate the intra-block main scanning counter 61 and the intra-block sub-scanning counter 62 by using the generated XDOWN signal and YDOWN signal. Is configured to specify addition or subtraction. The intra-block main scanning counter 61 is
Each time an overflow or underflow occurs, the counter 67 is informed of the overflow or underflow. The intra-block sub-scanning counter 62 is configured to notify the F / F 72 each time an overflow or underflow occurs.

The main scanning length register 68 sets the main scanning length x (the number of logical addresses in the main scanning direction) of the image as shown in FIG. The adder / subtractor 69 has an F / F7
2, the main scan length register 68
Is added or subtracted by the YDOWN signal obtained based on the setting of the rotation angle register 64. Therefore, the output value of the adder / subtractor 69 is the head address in the sub-scanning direction of the logical address that is the upper bit of the image address. The base address register 70 sets a logical address serving as a base. For example, when there is no rotation of an image, “0” is set. The selector 71 is connected to the base address register 7
The set value of 0 and the output value of the adder / subtractor 69 are selected by the selector &
It is configured to selectively output according to a signal from the output terminal “1Y” of the load generation circuit 66. Selector 71
Are configured to be transferred to the F / F 72 and stored.

The F / F 72 is configured such that when the intra-block sub-scanning counter 62 overflows or underflows and is notified each time, the stored contents are erased. The counter 67 is configured to receive a notification each time the intra-block main scanning counter 61 overflows or underflows, and to count the number of times. Also, the counter 67
Is the output terminal "2Y" of the selector & load generation circuit 66.
It is configured to be initialized by a signal from. The adder / subtractor 73 calculates the count value of the counter 67, which is the logical address in the main scanning direction, with respect to the leading logical address in the sub-scanning direction stored in the F / F 72, based on the setting of the rotation angle register 64, XDOWN. The signal is configured to add or subtract. Therefore, this adder / subtractor 7
As shown in the upper part of FIG. 12, the output value of 3 outputs the upper bit of the image address composed of predetermined bits as a logical address.

FIGS. 9 and 10 are timing charts of the input processing and the output processing in the memory control unit 45, respectively, in which four addresses are read / written in the high-speed page mode by one access. The value written below the write data or read data in the figure indicates a logical address, and this logical address corresponds to FIG. The input processing in FIG. 9 is the one at the beginning of the fifth line when the image is not rotated, and the output processing in FIG. 10 is the one at the beginning of the third line in which the image is rotated by 270 °.

As described above, in this embodiment, since the configuration is as described above, even when the image is rotated, four addresses to be continuously accessed become the same line, and the high-speed page mode can be used and handled. The vertical and horizontal sizes of the image can be arbitrarily specified, whereby the image memory can be effectively used without waste.

Next, a first modification of the embodiment of the present invention will be described. This first modification is different from the input image address counter 55 and the output image address counter 5 shown in FIG.
6 is configured as shown in FIG. That is, the input image address counter 55 selects two input image address counters 55a and 55b and one of the two counters 55a and 55b in accordance with the data set in the register 75 by the MPU.
c. Here, the input image address counter 55a includes a coefficient n indicating the size of the logical block,
The value of m corresponds to n = m = 2, and the value of the coefficient of the input image address counter 55b corresponds to n = m = 6. Similarly, the input image address counter 56 includes two input image address counters 56a,
6b and one of the two counters 56a, 56b,
And a selector 56c for selecting the register 75 according to the data set by the MPU. here,
The input image address counter 56a has a coefficient value corresponding to n = m = 2, and the input image address counter 56b has a coefficient value corresponding to n = m = 6.

FIG. 12 shows an image address output according to the first modification configured as described above. As can be seen from the figure, when n = m = 2, the output values of the intra-block main scanning counter and the intra-block sub-scanning counter are assigned to the lower two bits of the image address.
If n = m = 6, the output value is assigned to the lower 6 bits of the image address.

As described above, in the first modification, two address counters having different values of coefficients n and m indicating the size of a logical block are provided, and one of them can be selected. Therefore, it is possible to flexibly cope with an image memory (DRAM) of a type in which the number of bits of the row and column addresses is different, and the number of continuous accesses of a high-speed page according to the frequency of image rotation of the system to be used. Can be set, and it is possible to respond to various system needs.

In the first modified example, the input image address counter 55 shown in FIG.
Although the configuration is made up of 55b, specifically, in addition to the 2-bit intra-block main scanning counter 61 and the intra-block sub-scanning counter 62 shown in FIG. It is preferable to prepare an internal sub-scanning counter and use it selectively. In this regard, the same applies to the output image address counter 56 shown in FIG.

Next, a second modification of the embodiment of the present invention will be described. In the second modification, the input data processing unit 52 and the output data processing unit 53 of FIG. 5 are configured as shown in FIG. 13, and a plurality of image data are stored for one address of the image memory. This is handled collectively in block units of pixels × 4 lines. That is, as shown in FIG.
Block conversion unit 81, compression unit 82, write memory I / F
(83). To elaborate this, the raster /
The block converter 81 has two sets of line memories for four lines, and outputs image data input for each line in a raster format for four lines, and outputs the image data in blocks of 4 pixels × 4 lines. The compression unit 82 performs ／ fixed-length compression on 16-pixel image data of 4 pixels × 4 lines, converts the data into code data having a data amount equivalent to 3 pixels, and outputs the code data. The write memory I / F (83) has a plurality of stages of buffer memories, outputs an access request signal to the arbiter 54 in a state where data to be written is completed, and outputs data to the image data bus according to the permission signal. .

The output data processing section 53 comprises a read memory I / F (84), a decompression section 85, an in-block rotation section 86, and a block / raster conversion section 87, as shown in FIG. More specifically, the read memory I / F (8
4) has a plurality of stages of buffer memories, outputs an access request signal to the arbiter 54 in a state where the data to be output to the decompression unit 85 is empty, and takes in data from the image data bus according to the permission signal. When the code data compressed as described above is input, the decompression unit 85 converts the code data into image data of 4 pixels × 4 lines of 16 pixels and outputs the image data. The in-block rotation unit 86 changes the arrangement of pixels in the image data extracted and expanded for each block in accordance with the rotation information from the rotation angle register 64. The block / raster conversion unit 87 has two sets of line memories for four lines, divides image data input in block units of 4 pixels × 4 lines for four lines, and outputs each line in a raster format.

As described above, in the second modification, a plurality of pixels are assigned to one address, so that the frequency of access to the image memory (RAM) is reduced and the transfer rate of input / output image data is increased. It is possible to respond. Further, since the image data stored in the image memory 46 is encoded by performing compression processing before being stored in the image memory 46, the amount of data to be written to or read from the image memory 46 for input / output image data Can be reduced. For this reason, it is possible to cope with an increase in the transfer rate of input / output image data, and it is possible to reduce the cost by reducing the storage capacity of the image memory 46.

[0038]

According to the first and second aspects of the present invention, the image address is divided into 2 ⁿ × 2 ^m address units, and the upper bit address of the predetermined bit image address is set as the logical address. At the same time, the intra-block main scanning counter and the intra-block sub-scanning counter generate the lower bit address of the image address. For this reason, the vertical and horizontal sizes of the image to be handled can be arbitrarily specified, whereby the memory can be effectively used without waste, and the high-speed page mode can be used even when rotating the image.

According to the third aspect of the present invention, the intra-block main scanning counter includes a plurality of counters having different numbers of bits, and one of these counters can be selected freely.
In addition, the block sub-scanning counter comprises a plurality of counters having different numbers of bits, and one of these counters can be freely selected. Therefore, a different type of image memory (RAM) having a different number of bits of the column address
, And the number of continuous high-speed page accesses can be set according to the frequency of image rotation of the system used, so that it is possible to meet the needs of various systems.

According to the fourth aspect of the present invention, one of the image memories is used.
Data for a plurality of pixels is stored in the address, and the data array is changed before or after storage in the image memory according to the rotation angle of the image. For this reason, it is possible to reduce the access frequency of the image memory, and to cope with an increase in the transfer rate of input / output image data.

According to the fifth aspect of the present invention, data of a plurality of pixels stored in the image memory is code data after data compression processing is performed before storage. Therefore, the amount of data to be stored in or read from the image memory with respect to the input / output image data can be reduced, whereby it is possible to cope with a higher transfer rate of the input / output image data, and the memory capacity decreases. Low cost can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration when an image data storage processing device of the present invention is applied to a digital copying machine.

FIG. 2 is a plan view showing a relationship between a document table and a document.

FIG. 3 is a block diagram showing a detailed configuration of a storage unit shown in FIG.

FIG. 4 is a diagram illustrating an image synchronization signal output from the IPU of the reading unit in FIG. 1;

FIG. 5 is a block diagram showing an internal configuration of a memory control unit shown in FIG. 3;

6 is a block diagram showing a detailed configuration of an input image address counter (output image address counter) shown in FIG.

FIG. 7 is an explanatory diagram of addressing of an image memory for a two-dimensional image.

FIG. 8 is a time chart for normal mode access and high-speed page mode access.

FIG. 9 is a timing chart of an input process in a memory control unit.

FIG. 10 is a timing chart of an output process in a memory control unit.

FIG. 11 is a block diagram showing a configuration of a first modification of the embodiment of the present invention.

FIG. 12 is a diagram illustrating an image address output according to a first modified example.

FIG. 13 is a block diagram showing a configuration of a second modification of the embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reading unit 2 image forming unit 4 storage unit 7 system control unit 45 memory control unit 51 MPU 52 input data processing unit 53 output data processing unit 54 arbiter 55 input image address counter 56 output image address counter 57 address selector 58 access control circuit 61 Main scanning counter in block 62 Sub-scanning counter in block 64 Rotation angle register 67 Counter 68 Main scanning length register 70 Base address register 73 Adder / subtractor

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 1/387 H04N 1/41 B 1/41 G06F 15/66 350

Claims (5)

[Claims] 1. An image memory capable of reading and writing image data, and image address generating means for generating an image address consisting of predetermined bits, wherein an image address output from the address generating means is a row address and a column address. An image data storage processing device that specifies an address of the image memory, stores image data input in a raster format at the specified address of the image memory, and rotates and reads the stored image data. In the above, the image address generating means divides the image address into 2 ⁿ × 2 ^m address units,
Logical address generating means for generating a higher-order (total number of bits- (n + m)) bits of the image address composed of the predetermined bits as a logical address; counting in units of one address along the main scanning direction of the image; A main scanning counter in a block that outputs n bits of the lower (n + m) bits, and counts in units of one address along the sub-scanning direction of the image, and outputs m bits of the lower (n + m) bits of the image address And a sub-scanning counter within the block. 2. The image processing apparatus according to claim 1, wherein the logical address generating means includes: a base address register for setting a logical address serving as a base; a rotation angle register for setting a rotation angle of the image; A main scanning length register for setting a scanning length, a value obtained by multiplying the number of times of overflow or underflow of the sub-scanning counter in the block by the main scanning length set in the main scanning length register, and the block The count value corresponding to the number of overflows or underflows of the inner main scanning counter is added to the base address set in the base address register, according to the rotation angle set in the rotation angle register, or 2. The image data storage process according to claim 1, wherein the image data is subtracted and output as a logical address. Apparatus. 3. The intra-block main scanning counter comprises a plurality of counters having different numbers of bits, and one of these counters can be freely selected, and the block sub-scanning counter comprises a plurality of counters having different numbers of bits. 3. The image data storage processing device according to claim 1, wherein one of said counters is freely selectable. 4. An image memory for storing data of a plurality of pixels at one address, and changing an arrangement of the data before or after writing to the image memory according to a rotation angle set in the rotation angle register. 2. The image data storage processing device according to claim 1, wherein: 5. The image data storage according to claim 4, wherein the data for a plurality of pixels stored in the image memory is code data after a data compression process is performed before the image data is stored in the image memory. Processing equipment.