JPH09146828A - Memory controller and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read the data while writing the data in a memory and to prevent read from a memory area where the data are not written by permitting a memory access request only for a period shorter by twice the memory access time than a fixed cycle T after the end of memory access by a first data source performing memory write with the cycle T. SOLUTION: An address selector 24 selects an address generated by a first address generation part 21 when input/output memory access signals are active and an arbiter 25 outputs memory access permission signals to a compression/ expansion part. For the output conditions, compared result signals inputted from an address comparison part 23 are active, the input/output memory access signals are not active and further, the following conditions are present. That is, it is only for the period shorter than the T for the time which is the double of the memory access time after the end of the memory access of one memory address by the input/output memory access signals outputted in the fixed cycle T from a picture input part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device used in a digital copying machine, a facsimile device, a printer, a scanner, an information processing device, and the like, and more particularly to a plurality of data sources or data transfer destinations and one memory. The present invention relates to a memory control device capable of performing memory writing or memory reading of a data string in parallel.

[0002]

2. Description of the Related Art A digital copying machine is equipped with a dual-port frame memory for one page, for example, for copying a large number of pages, and while writing image data read by a scanner in the frame memory, image data is read from the frame memory. It is read out and stored in a storage memory (for example, a magnetic disk device). Similarly, in a facsimile machine, while writing the image data read by the scanner in the frame memory, the image data is read from the frame memory and transmitted, or the received image data is written in the frame memory and the image data is read. It is also printed on recording paper. FIG. 12 and FIG. 13 show a conventional technique in which a plurality of data sources or data transfer destinations and one memory are concurrently written to or read from a data string as described above. FIG. 12 shows an example using the dual port memory 51.
The data from the data source 56 is written to the dual port memory 51 from the first port 54 via the first bus 52, and the dual port memory 51 is written via the second bus 53.
The data in the dual port memory 51 is read from the second port 55 and transferred to the data transfer destination 57. FIG. 13 shows an example in which a DMA controller 59 having a plurality of channels is used. A data source 56, a data transfer destination 57, a memory 58, and a DMA controller 59 are connected to one bus 60, and one channel of the DMA controller 59 is addressed. The data source 56 is written to the memory 58 in accordance with the above, while the data is read from the memory 58 to the data transfer destination 57 according to the addressing of another channel of the DMA controller 59.

[0003]

However, in the system using the dual port memory as described above, the number of terminals for the memory address bus and data bus is two.
Therefore, not only the cost is increased, but also the packaging density is decreased, and in the method using the DMA controller, the control is complicated and the cost is increased if the DMA controller has a high function. If the function is a DMA controller, there are many restrictions on application. In addition, in either method, when reading while writing, even if the read address is larger than the write address, memory access is allowed. Occurs. The present invention solves the above-mentioned problems of the related art, can read the data while writing the data in the memory, and at the time, can prevent the reading from the memory area where the data is not yet written, and It is to provide a memory control device and the like that can be realized at low cost.

[0004]

As a means for solving the above-mentioned problems, the invention according to claim 1 of the memory control device according to the present invention is such that between a plurality of data sources or data transfer destinations and one memory, In a memory control device for writing or reading a data string in parallel, a memory access of one memory address by a first data source or a data transfer destination for writing or reading memory in units of one memory address at a constant cycle T From the end
The memory access request from the data source or the data transfer destination other than the first data source or the data transfer destination is permitted only during a period that is twice the memory access time shorter than the constant period T. According to a second aspect of the present invention, there is provided a memory control device according to the first aspect, wherein the first data source has a first address generator for writing to the memory and at least one data transfer. The second address generator for reading the memory is compared with the addresses generated by the two address generators, and the address generated by the second address generator is generated by the first address generator. The address comparison unit outputs the memory access permission signal only when the address comparison address is not larger than the address. According to a third aspect of the present invention, there is provided a memory control device in which a plurality of data sources or data transfer destinations and a memory perform parallel writing and reading of a data string in two frames. The memory and the image data input from one data source are stored in the two frame memories at the same time, and after the memory is stored, the image data stored in either one of the frame memories is read out to the first data transfer destination. The first storage control unit for outputting and the first storage control unit reads the stored image data from the other frame memory while the first storage control unit is reading the image data from one frame memory after storing the image data, A second storage controller for transferring to a transfer destination is provided.

[0005]

In the memory device according to the first aspect, the memory access by the first data source or the data transfer destination is performed at a constant cycle T, and the first data source does not interfere with the memory access. Memory access by a data source or a data transfer destination other than the data source or the data transfer destination can be performed in parallel to the same memory. 3. The memory device according to claim 2, wherein when the first data source is writing to the memory and the data transfer destination reads the data from the memory, the data transfer destination is the memory from the memory area where the first data source is not writing data. There is no need to read. According to another aspect of the memory device of the present invention, the same data written in the memory by one data source can be read in parallel at a timing at which two data transfer destinations do not depend on each other.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows an example in which the memory control device of the present invention is used in a digital copying machine. As shown in the figure, this digital copying machine includes a scanner controller 31, an exposure lamp 32, and an image sensor (for example, CCD) 3.
3 is provided with the reading unit 3, and the exposure lamp 32 movable along the document table 34 in the reading unit 3 scan-exposes the document S, and the reflected light is image sensor 33.
Photoelectric conversion is performed by. The photoelectrically converted electric signal is subjected to various image processings by an IPU (image processing unit) 35 in the reading unit 3, and is stored in the storage unit 1 together with an image synchronizing signal as digitized image data.
Alternatively, it is sent to the writing unit 41 of the image forming unit 4. The scanner control unit 31 detects various sensors, controls the drive motor, and sets parameters in the IPU 35 when executing the above process. In the image forming unit 4, the photoconductor 42 which is uniformly charged by the charging charger 43 and which is constantly rotated.
Are exposed by the laser light modulated by the image data from the writing section 41. As a result, an electrostatic latent image is formed on the 6 photoconductor 42, and the electrostatic latent image is developed with toner by the developing device 44 to form a visualized toner image.

Further, the transfer paper which has been previously fed and fed from the paper feed tray 50 by the paper feed roller and which has been waiting by the registration roller is conveyed in synchronization with the rotation of the photoconductor 42, and is transferred onto the photoconductor by the transfer charger 45. Toner is electrostatically transferred onto the transfer paper, and the transfer paper is separated from the photoconductor 42 by the separation charger 46. After that, the toner image on the transfer paper is heated and fixed by the fixing device 47, and is discharged to the paper discharge tray by the paper discharge roller. On the other hand, the photoconductor 4 after electrostatic transfer
The toner image remaining on No. 2 is removed by the cleaning device, and the photoconductor 42 is destaticized by the destaticizing charger 48. The plotter control unit 49 detects various sensors and controls the drive motor and the like in order to execute the above processes.

FIG. 2 is a timing chart of signals output from the IPU 35 in the reading unit 3. The frame gate signal (/ FGATE) shown in the figure is a signal indicating the image effective range of the image area in the sub-scanning direction (see FIGS. 1 and 3), and the image data while this signal is at the Low level is effective. As shown in the figure, the / FGATE signal goes to the Low level at the falling edge of the line sync signal (/ LSYNC), and then goes to the High level at the trailing edge of the second / LSYNC. The / LSYNC signal is in the "signal present" state (Low level) at the beginning of each main scan (see FIG. 3) in synchronization with the rising edge of the pixel synchronization signal (PCLK).
With a signal having a predetermined pulse width of, the "signal present" state for the next main scanning line is output in synchronization with the second and subsequent PCLK. Note that the image data is validated as / L
A predetermined number (16 in the example of FIG. 10) from the falling edge of the SYNC signal.
This is from the time when PCLK is output later. Image data is PC
One image data is output in one cycle of LK, but this one image data is 400D in the main scanning direction starting from the arrow position in FIG.
One pixel divided by PI (dot / inch) indicates "black" or "white".

The system control unit 5 of FIG. 2 detects an input state by the user on the operation unit 6 and sets parameters in the storage unit 1, the reading unit 3, the image forming unit 4, and the FAX unit 7.
And process execution instructions. In addition, the state of the entire system is managed and the result is displayed on the operation unit 6.
The FAX section 7 receives the image data sent from the reading section 3 as G3, G4FA according to an instruction from the system control section 5.
Based on the data transfer regulation of X, the binary compression is 6 and transferred to the telephone line. Further, the data transferred to the FAX unit 7 through the telephone line is decoded into binary image data and sent to the writing unit 41 of the image forming unit 4. The selector unit 8 is the system control unit 5.
The state of the selector is changed in accordance with an instruction from the reading unit 3, the storage unit 1, and the data source of the image data for forming an image.
It is selected from any of the FAX units 7. The storage unit 1 to which the memory control device of the present invention belongs is usually used for a copying application such as multi-copying by storing image data of a document input from the IPU 35. Also, FA
It is also used as a buffer memory for temporarily storing the binary image data from the X section 7. The system control unit 5 gives these data storage instructions.

FIG. 4 is a block diagram of the storage unit 1 including the memory control device 2 according to the first embodiment of the present invention. As illustrated, the storage unit 1 includes a memory control device 2, an image input / output unit 11 that is a first data source and a data transfer destination, a compression / decompression unit 12 that is a second data source and a data transfer destination, and an image. Input / output unit 11 and compression / expansion unit 12
A frame memory 13 for storing image data written by
A storage memory (for example, a magnetic disk device) 14 that stores the image data compressed by the compression / expansion unit 12 is provided. The image input / output unit 11 includes a CPU and a logic circuit, communicates with the memory control device 2 to receive a command, sets an operation according to the command, and informs the state of the image input / output unit 11. The status information is transmitted to the memory control device 2. When an image input command is received, the input image data is transferred to the input image synchronization signal (PCL
According to K), it is output as memory data in units of 8 pixels to the memory control device 2 together with the input / output memory access signal at a constant cycle. Also, when receiving an image output command,
The image data from the memory control device 2 is output in a constant cycle in synchronization with the output pixel synchronization signal.

The compression / expansion unit 12 is composed of a CPU and a logic circuit, communicates with the memory control unit 2 to receive a command, sets an operation according to the command, and
Status information is transmitted to the memory control device 2 to notify the state of the compression / expansion processing. When a compression command is received, a memory access request signal is output to the memory control device 2, and when the memory access permission signal is active (signal present), image data is received and compression processing is performed.
The compressed data is stored in the storage memory 14. When a decompression command is received, the 6-compressed data stored in the storage memory 14 is read out, decompressed, and output to the memory controller 2 by the same access method as that used for compression. The memory control device 2 is composed of a CPU and a logic circuit, communicates with the system control unit 5 to receive a command, sets an operation according to the command, and outputs status information to inform the state of the storage unit 1. It is transmitted to the system control unit 5. The operation commands from the system control unit 5 include image input, image output, compression, decompression, etc.
The image output command is sent to the image input / output unit 11, and the compression / expansion command is sent to the compression / expansion unit 12.

FIG. 5 shows details of the memory control device 2.
As shown in the figure, the memory control device 2 of this embodiment has a first address generator 21 shown as an input image address counter and a second address generator 21 shown as a transfer image address counter.
Address generator 22, an address comparator 23 that compares the magnitudes of the addresses generated by the two address generators, and outputs the comparison result, an address selector 24, and an arbiter 2.
5 and the like. The first address generating unit 21 is the image input / output unit 1 which is the first data source or the data transfer destination.
1 is an address counter that counts up in response to an input / output memory access signal output in a constant cycle. When the image input / output unit 11 is a data source, it indicates a storage location where input image data is stored Output memory address. The second address generator 22 is an address counter that counts up in response to a memory access request signal from the compression / expansion unit 12 which is the second data source or the data transfer destination. When the compression / expansion unit 12 is the data transfer destination. Outputs, for example, a 19-bit memory address indicating the storage location where the transfer image data is stored.

The address comparison unit 23 compares the sizes of the addresses generated by the first address generation unit 21 and the second address generation unit 22, and the image input / output unit 11 is the data source and the compression / expansion unit 12 is the data source. In the case of the transfer destination, if the address generated by the second address generator 22 is less than or equal to the address generated by the first address generator 21, the comparison result signal output to the arbiter 25 is activated. As a result,
As shown in FIG. 6, the transfer image data is always read only from the area in which the image data is written (area F in the drawing). The address selector 24 is a selector that is selected by the input / output memory access signal. If the input / output memory access signal is active, the address generated by the first address generation unit 21 is selected. The arbiter 25 outputs a memory access permission signal for memory access of the compression / expansion unit 12. The condition for outputting the memory access permission signal is that the comparison result signal input from the address comparison unit 23 is active, the input / output memory access signal is not active, and the following condition is satisfied. In other words, the further condition is that from the end of the memory access of one memory address by the input / output memory access signal output from the image input / output unit (first data source or data transfer destination) at the constant cycle T, Is only a time period which is twice as long as the memory access time A, and when the three conditions are satisfied, a data source other than the image input / output unit (first data source or data transfer destination) or data transfer The memory access request from the beginning is permitted (see FIG. 7).

FIG. 7A shows a signal in the arbiter 25, which shows that the memory is being accessed by the first data source, and the input / output memory access signal from the image input / output unit 11 is active (there is a signal). Becomes active (High level), the arbiter 25 becomes inactive (Low level) when it receives a memory ready signal (a signal indicating that access for one memory address has been completed) from the frame memory 13. That is, as shown, this signal is active only during the memory access time A.

FIG. 8B shows a memory access permission signal output from the arbiter 25. As shown in FIG. 8, a mono signal that outputs a signal that is activated only during the period B is triggered by the edge where the memory ready becomes active. It is generated by a multivibrator (one-shot circuit) 26. However, as shown in the figure, the mono-multi vibrator 2
The reset terminal R of 6 contains a signal that is reset when the input / output memory access signal is active and when the comparison result signal from the address comparison unit 23 is inactive (at Low level). Even if the memory becomes ready during this reset, the memory access permission signal is not output. In the above, the pulse width of B is set in advance so that B = T−2A. That is, a data source or a data transfer destination other than the first data source or the data transfer destination, such as the compression / expansion unit 14, is permitted to access the memory only when the first data source or the data transfer destination is accessed. Period 6 from the end to A time before the next memory access of the first data source or the data transfer destination starts. If the memory access of the compression / expansion unit 14 or the like is permitted after the time A has passed, the access time of A is required for the memory access, so that the next input is made in the cycle T before the memory access is completed. Input / output memory access signal of is input. Therefore, as shown in FIG. 7C, the memory access request signals R1 and R2 are permitted to be accessed, and the memory access request signals R3 are not permitted to be accessed.

In the first embodiment of the present invention, as described above, the free time (when the memory is being accessed) when the input image data is written in the frame memory 13 by the simple and low-cost arbiter 25 as shown in FIG. (When not), the image data written in the frame memory 13 is read out, compressed and stored in the storage memory 1 such as a magnetic disk device.
4, and if the image input / output unit 11 operates as a first data transfer destination for transferring data to the image forming unit 4, the image data stored in the storage memory 14 is read out,
While decompressing and writing in the frame memory 13, the written image data can be read out from the frame memory 13 and output to recording paper. Therefore, the copy operation, such as when copying a large number of copies, is speeded up. In addition, the image input / output unit 1
When 1 is the data source, the compression / expansion unit 12 does not read the data of the address which the image input / output unit 11 has not yet written in the frame memory 13. Depending on the value of the data transfer cycle (memory access cycle) T of the first data source or data transfer destination, while the first data source or data transfer destination makes one memory access (one memory address), Other data sources or data transfer destinations can also access the memory multiple times (for multiple memory addresses).

FIG. 9 is a block diagram of a memory device 1a showing a second embodiment of the present invention. As shown,
The memory device 1a of this embodiment has two frame memories 1.
3a, 13b, a first storage control unit 15, a second storage control unit 16, and the like. First storage controller 15
Is an image input / output unit, which is composed of a CPU and a logic circuit, communicates with the system control unit 5, receives a command, sets an operation according to the command, and further, the memory device 1a and the storage memory. Status information is transmitted to the system control unit 5 to notify the state of the storage unit 1 configured by 14. The outputs to the interface portions (buses B1 to B4) with the frame memories 13a and 13b are three-state outputs, and can be successively brought into a high impedance state in response to an instruction from the system control 65. The operation commands from the system control unit 5 include image input, image output, compression, decompression, and the like. When the image input command is received, the input image data is transferred to the frame memories 13a and 13a in accordance with the input image synchronization signal.
It is simultaneously stored in b (see FIG. 10). When receiving an image output command, the frame memory 13a or 1
Image data is read from 3b and output to, for example, the image forming unit 4 in synchronization with the output image synchronization signal (see FIG. 11).
The frame memory that is not the read target at that time is in a high impedance state. This is because the bus B1 and the bus B2 are wired-OR so that the number of terminals of the frame memory 13a is not doubled, and the bus B3 and the bus B4 are wired-OR so that the number of terminals of the frame memory 13b is 2.
This is because we do not double it. In addition, compression,
When a decompression command is received from the system control unit 5, the second timing is synchronized with the start or end of image input / output.
To the storage control unit 16.

The second storage control unit 16 is, for example, a compression / decompression unit, is composed of a CPU and a logic circuit, communicates with the first storage control unit 15, receives a command, and operates according to the command. The status information is transmitted in order to set and inform the state of compression / decompression processing. The output of the interface portion with the frame memories 13a and 13b is a three-state output, and can be successively brought into a high impedance state in response to an instruction from the first storage control unit 15. If you receive a command to compress,
Image data is read out from the frame memory 13a or 13b, compression processing is performed, and the compressed data is accumulated in the memory 14
To memorize. (See FIG. 11). The frame memory that is not the read target at that time is in a high impedance state. When receiving a decompression command, the compressed data stored in the storage memory 14 is read out, decompressed, and transferred to the frame memory 13a or 13b.

When reading the image data from the frame memory upon receiving the above-mentioned compression command, for example, as shown in FIG. 11, the first storage controller 15 reads the image data from the frame memory 13a. If so, the reading is performed in parallel with the reading from the frame memory 13b to the first storage control unit 15. In this way, according to the second embodiment, for example, when applied to a digital copying machine, when the number of tabs is several, the storage memory 1
4 can be output on the recording paper while being stored in the storage medium 4, and can be output from the storage memory 14 while being read from the storage memory 14 by reading from the other frame memory while writing from the storage memory 14 to one frame memory. Moreover, since writing and reading are not performed in parallel with respect to the same frame memory in this embodiment, writing and reading can be performed in parallel even if the memory access cycle T for image input / output is shortened.

[0020]

As described above, according to the present invention,
First, the first data source performs a memory access by the data transfer destination at a constant cycle T, and a memory by a data source or a data transfer destination other than the first data source or the data transfer destination without interrupting the memory access. Since access to the same memory can be performed in parallel, it is possible to increase the speed of multi-copying in a digital copying machine which requires temporarily storing data read from a document in a storage memory. Further, since it is not necessary to use the dual port memory and the voice of the arbiter saw is easy, the cost can be reduced.

Second, when the data transfer destination reads the data from the memory while the first data source writes to the memory, the memory area where the first data source does not write the data without the user's attention. Therefore, the data transfer destination does not read the memory, which improves usability. Third, in the configuration including two frame memories, the same data written in the memory by one data source can be read in parallel at the timings where the two data transfer destinations do not depend on each other. Even when the device or the like is high-speed, the memory access by the output device and the memory access by the storage memory can be performed in parallel.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a digital copying machine in which the present invention is implemented.

FIG. 2 is a timing chart of signals of a main part of a digital copying machine in which the present invention is implemented.

FIG. 3 is an explanatory diagram of document scanning of a digital copying machine in which the present invention is implemented.

FIG. 4 is a configuration block diagram of a storage unit including a memory control device according to an embodiment of the present invention.

FIG. 5 is a configuration block diagram of a memory control device showing an embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of a main part of the memory control device showing the embodiment of the present invention.

7 (a), (b) and (c) are other operation explanatory views of the main part of the memory control device showing the embodiment of the present invention.

FIG. 8 is a configuration block diagram of a main part of a memory control device showing an embodiment of the present invention.

FIG. 9 is a configuration block diagram of a memory device showing an embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of the memory device according to the embodiment of the present invention.

FIG. 11 is another operation explanatory diagram of the memory device according to the embodiment of the present invention.

FIG. 12 is a block diagram of a memory device showing an example of a conventional technique.

FIG. 13 is a block diagram of a memory device showing another example of the related art.

[Explanation of symbols]

1 ... storage unit, 2 ... memory control device, 3 ... reading unit, 4 ... image forming unit, 11 ... image input / output unit, 12 ... compression / decompression unit, 13 ... Frame memory, 14 ... Accumulation memory, 15 ... First storage control unit, 16 ... Second storage control unit, 21 ... First address generation unit, 22 ... Second Address generator, 23
... Address comparison unit, 25 ... Arbiter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 1/40 H04N 1/40 G

Claims (3)

[Claims] 1. A memory control device for writing data to or reading data from a memory in parallel between a plurality of data sources or data transfer destinations and one memory, and a memory in units of one memory address at a constant cycle T. From the end of the memory access of one memory address by the first data source or the data transfer destination for writing or reading the memory, only the period of time shorter than the constant period T by twice the memory access time, the first data A memory control device characterized in that a memory access request from a data source or a data transfer destination other than the source or the data transfer destination is permitted. 2. The memory control device according to claim 1, wherein a first address generator for writing the memory of the first data source and a second address for reading the memory of at least one data transfer destination. The generation unit and the addresses generated by the two address generation units are compared in size, and memory access is permitted only when the address generated by the second address generation unit is not larger than the address generated by the first address generation unit. A memory control device having a configuration including an address comparison unit that outputs a signal. 3. A memory device for writing or reading a data string in parallel between a plurality of data sources or data transfer destinations and a memory, wherein two frame memories and one data source are input. Image data is stored in the two frame memories at the same time, and after the image data is stored, the stored image data is read out from either one of the frame memories and output to a first data transfer destination.
Storage controller and the first storage controller read the image data from the other frame memory while the image data is being read from one of the frame memories after the storage of the image data and transfer the image data to the second transfer destination. And a second storage control unit for controlling the memory device.