JP4890807B2 - Memory access device and memory access method - Google Patents

Description

  The present invention relates to a memory access apparatus that serves as an interface between a master device device such as a processor and an image processing apparatus and a memory device.

  In recent years, the number of objects handled by processors and image processing apparatuses built in semiconductor integrated devices has increased significantly, and MPEG, It extends to HD (High Density) images such as H.264, high image quality and 3D graphics represented by games, digital recorders, and the like. Along with this, there has been a demand for larger capacity and higher speed for memory devices. Specifically, it is required to reduce access overhead in order to increase data transfer speed and transfer efficiency.

  Generally, as a method for realizing high-speed data transfer, (1) a method for increasing the data transfer speed, (2) a method for widening the memory bus width, or these methods (1) and (2) are used. The method of using it together is known.

In addition to these, due to the progress of the semiconductor device, a memory having a capacity for several frames of an image is built in the semiconductor device, and a memory externally attached to the semiconductor device (hereinafter referred to as an external memory). A method of using a memory (hereinafter referred to as a built-in memory) in combination is known (see, for example, Patent Document 1 or Patent Document 2). According to this method, data with high access frequency (for example, data related to images) is stored in the built-in memory, and data with low access frequency is stored in the external memory. The internal memory is frequently accessed by the memory interface circuit, and the external memory is accessed as necessary.
JP 2003-132347 A Japanese Patent Laid-Open No. 10-222459

  However, in the conventional techniques described above, (1) the method for increasing the data transfer speed requires the use of a high-speed memory, which increases the power consumption and the difficulty in designing the board. In addition, a memory having a high clock frequency is generally expensive and has a problem that the system cost increases.

  For example, the MPEG2MP @ HL standard used in recent digital TV broadcasting, H.264, etc. When processing such as encoding / decoding based on the 264-HD standard, POST filter processing, image output processing, high-quality graphics processing, IP conversion processing, processor, etc. is built in the same semiconductor device, The performance required for the memory is several G [Byte / s]. In order to cope with this performance, it is necessary to employ a high-speed memory such as SDRAM, DDR-SDRAM, DDR2-SDRAM and RamBus XDR which have a high clock frequency and are suitable for burst transfer.

  For this reason, (2) using a method of widening the bus width of the memory increases the number of terminals of the semiconductor device, increases the manufacturing cost of the LSI, and increases the system cost due to the use of a plurality of memories. It will have another problem.

  Further, in the method using both the external memory and the built-in memory (Patent Document 1 and Patent Document 2), it is necessary to store frequently accessed data required for specific processing such as graphics in the built-in memory. When the amount of processing that is extremely large and requires a large amount of memory, for example, MPEG encoding and decoding, high image quality processing, IP conversion processing, etc., overlap at the same time, increase the capacity of the built-in memory, frequency, bus As a result, the width and the like are increased. As a result, the chip area increases, the manufacturing cost of the semiconductor device increases, and the design difficulty increases.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a memory access device capable of reducing cost while ensuring a required data transfer rate and capacity.

To achieve the above object, a memory access device according to the present invention includes (a) a first memory device to which a first address space is allocated, and (b) latency required for access is the first memory device. A second memory device having a second address space shorter than the second memory device, and (c) the first address space is divided into a plurality of first partial address spaces, and the second address space is a plurality of In the case where the first partial address space is divided into the second partial address spaces, and the first partial address spaces and the second partial address spaces are alternately arranged and logically continuous logical address spaces are defined as the first logical address spaces. (D) in response to the first command for instructing access to the first logical address space, the first address space and the second address space. Memory device control means for controlling access, and when the memory device control means accesses the first partial address space in response to the first command, the memory device control means controls the first partial address space. When the first type control signal group indicating access is supplied to the first memory device and the second partial address space is accessed, the second type indicating access to the second partial address space is provided. When a control signal group is supplied to the second memory device, and the memory device control means accesses the first partial address space and the second partial address space, the first memory device controls the first memory device. The seed control signal group and the second kind control signal group are supplied in parallel. The memory access device further accesses the address space of the second memory device within a time period from the end of the access to the second address space to the start of the next access to the first address space. An arbiter is provided for supplying the second type of control signal group shown in FIG.

  As a result, the data transfer rate can be improved while securing the capacity by using the second memory device having a latency required for access shorter than that of the first memory device, and the required data transfer rate can be increased. Can be satisfied. Further, by reducing the frequency as the transfer rate increases, the design can be facilitated, the use of components operating at a high frequency can be avoided, and the cost can be reduced.

  Note that the present invention can be realized not only as a memory access device but also as a memory access method for transferring data between a master device and a memory device.

  According to the memory access apparatus of the present invention, for example, in a configuration including a first memory device (external DRAM) and a second memory device (built-in memory), the MPEG2MP @ HL standard, The first memory device while ensuring the data transfer rate and capacity required for encoding processing and decoding processing based on the 264-HD standard, POST filter, image output processing, high-quality graphics processing, IP conversion processing, etc. Increasing the bus width and the number of chips of (external DRAM) can be suppressed. Accordingly, the operating frequency and power consumption of the first memory device (external DRAM) can be reduced, and the cost of the semiconductor device and the set system cost can be simultaneously reduced. Also, by saving unnecessary data stored in the second memory device (built-in memory) to the first memory device (external DRAM), the total capacity can be greatly increased. Of course, the second memory device (built-in memory) can take full advantage of the high processing speed and response speed, improve transfer efficiency and latency, reduce processor performance and LSI cost. be able to.

  That is, since the first memory device (external DRAM) and the second memory device (built-in memory) are accessed in parallel, the occupied time per command in the first memory device (external DRAM) And the rate of the first memory device (external DRAM) can be reduced. As a result, the frequency can be reduced and an inexpensive memory device can be used. Further, by reducing the frequency, the ease of design can be improved and the power consumption can be reduced.

  Further, the first memory device (external DRAM) and the second memory device (built-in memory) are compared with the case where all data having a high rate and high access frequency are stored in the second memory device (built-in memory). By using together, it is possible to halve the capacity required for the second memory device (external DRAM) with substantially the same latency.

(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.

  The memory access device according to the present embodiment includes (a) a first memory device to which a first address space is allocated, and (b) a latency required for access is shorter than that of the first memory device, and the second address A second memory device to which space is allocated; and (c) a first address space is divided into a plurality of first partial address spaces, a second address space is divided into a plurality of second partial address spaces, In the case where a logical address space in which the first partial address space and the second partial address spaces are alternately arranged and logically continuous is used as the first logical address space, (d) the first logical address space A memory device controller that controls access to the first address space and the second address space in response to a first command that instructs access to Characterized in that it comprises.

Based on the above points, the memory access device in the present embodiment will be described.
First, the configuration of the memory access device in the present embodiment will be described.

  As shown in FIG. 1, the memory access device 10 receives an access request for a logical address space from a master device (not shown) such as a processor, an image compression engine, a graphics engine, etc. In response, the device accesses each memory device under control.

  The “logical address space” is an address space managed in association with the address space of each memory device under control by a logical address.

  The master device may be mounted together with the memory access device 10 or may be mounted separately from the memory access device 10.

  Here, as an example, the memory access device 10 includes a memory device 101, a memory device 102, an internal bus IF 140, an internal bus IF 141, an arbiter 142, a memory device control unit 143, a buffer 144, a buffer 145, and the like. The memory device 101 is externally attached to the controller 100. The memory device 102, the internal bus IF 140, the internal bus IF 141, the arbiter 142, the memory device control unit 143, the buffer 144, and the buffer 145 are built in the controller 100.

  The memory device 101 is a memory device that can be accessed in bursts and can continuously transfer high-speed and large-capacity data. For example, a memory device such as a DRAM that can transfer data using a burst mode and can be accessed at high speed. Here, as an example, a DRAM is used. Examples of DRAM include SDRAM, DDR-SDRAM, DDR2-SDRAM, and RamBus XDR.

  The memory device 102 is a memory device capable of high-speed latency, random access, and expansion / reduction of the bus width at the time of design. For example, it is a memory device such as an SRAM, which has a short latency and a high-speed random access. Here, as an example, an SRAM is used. Note that the type of the memory device 102 is not limited to the SRAM, but may be a built-in DRAM, flash, FeRAM, or the like. The memory device 102 may be either internal or external.

  Each of the internal bus IF 140 and the internal bus IF 141 receives an access request for the logical address space from the master device, and issues a command corresponding to the received access request to the arbiter 142.

  The arbiter 142 receives a command issued from the internal bus IF 140 or the internal bus IF 141, performs access arbitration on the received command based on access priority, data rate guarantee, etc., and controls the command to the memory device. Forward to the unit 143.

  The memory device control unit 143 receives a command transferred from the arbiter 142, and controls a group of control signals necessary for accessing each memory device under control while controlling timing based on the received command. Supply to devices in parallel. Specifically, when the memory device control unit 143 accesses the memory device 101 according to the received command, the first type control signal group indicating access to the memory device 101 via the signal line 146. (DRAM control signals, address signals, etc.) are supplied. When accessing the memory device 102, a second type control signal group (SRAM control signal, address signal, etc.) indicating access to the memory device 102 is supplied via the signal line 147.

  The buffer 144 is a buffer storage area in which data transferred from the internal bus IF 140 or the internal bus IF 141 to the memory device 101 or the memory device 102 is temporarily stored.

  Here, when the memory device control unit 143 is supplied with the first type control signal group for reading, the memory device 101 supplies the data specified by the supplied first type control signal group to the buffer 144. Write. Similarly, when the memory device control unit 143 is supplied with the second type control signal group for reading, the memory device 102 sends the data specified by the supplied second type control signal group to the buffer 144. Write.

  The buffer 145 is a buffer storage area in which data transferred from the memory device 101 or the memory device 102 to the internal bus IF 140 or the internal bus IF 141 is temporarily stored.

  Here, when the memory device controller 143 receives the first type control signal group for writing from the memory device control unit 143, the memory device 101 transfers the data specified by the supplied first type control signal group from the buffer 145. Store in the read memory device 101. Similarly, when the second type control signal group for writing is supplied from the memory device control unit 143, the memory device 102 transfers data specified by the supplied second type control signal group from the buffer 145. Store in read memory device 102.

  Next, a logical address space managed by the memory device control unit 143 in this embodiment will be described.

  As illustrated in FIG. 2, the memory device control unit 143 controls access to each of the address space of the memory device 101 and the address space of the memory device 102 according to the logical address space 110.

  The logical address space 110 includes a logical address space 103 (size X), a logical address space 104 (size Z), and a logical address space 105 (size Y). Here, a logical address space having at least three access forms is included.

  The logical address space 103 (size X) is a logical address space associated with the address space (size X) of the memory device 102. That is, it is a storage area that can be accessed using the memory device 102 as a continuous space. It is also a logical address space capable of high-speed latency and random access.

  The logical address space 104 (size Z) is a logical address space associated with an address space (size Z) assigned to the memory device 101 separately from the address space 106 (size L). That is, it is a storage area accessible by the memory map of the memory device 101. It is also a logical address space that can be accessed in bursts and enables continuous high-speed and large-capacity data transfer.

  In the logical address space 105 (size Y), the address space 106 (size L) is divided into a plurality of first partial address spaces, and the address space 107 (size K) is divided into a plurality of second partial address spaces. This is a logical address space in which one partial address space and each second partial address space are alternately arranged and logically continuous. That is, the logical address space is a composite of the address space 106 (size L) assigned to the memory device 101 and the address space 107 (size K) assigned to the memory device 102. In addition, the storage area can be accessed by a shared memory map of the memory device 101 and the memory device 102. The logical address space enables high-speed latency and high-speed and large-capacity data transfer.

  Here, the size Y of the logical address space 105 is the size L of the address space 106 allocated from the memory device 101 (0 ≦ L ≦ maximum size of the memory device 101) and the size of the address space 107 allocated from the memory device 102. This is a size obtained by adding K (0 ≦ K ≦ maximum size of the memory device 102). That is, the logical address space 105 (size Y) is a logical address space (size Y = L + K) straddling the memory device 101 and the memory device 102.

  Next, the logical address space 105 managed by the memory device control unit 143 will be described. Here, a case where a logically continuous data string is stored in the logical address space 105 according to the logical address map will be described as an example. As an example, the memory device 101 is a DRAM with a data input / output width of 4 [Bytes], the memory device 102 is an SRAM with a data input / output width of 16 [Bytes], and M = N = 16 [Bytes].

  As shown in FIG. 3A, the memory device control unit 143 stores the logically continuous data string (hereinafter referred to as a series of data) in the logical address space 105 from the top. 16 [Byte] data (first data string) is stored in the first partial address space 111 (size M), and the subsequent 16 [Byte] data (second data string) is stored in the second partial address space. A first type control signal group and a second type control signal group are supplied so as to be stored in 112 (size N).

  Here, the first partial address space 111 is an address space from the start address “E” to the end address “E + 15” in the memory device 101, and is also a logical address space belonging to the logical address space 105. The second partial address space 112 is an address space from the start address “F” to the end address “F + 15” in the memory device 102, and is a logical address space belonging to the logical address space 105.

  Further, the memory device control unit 143 stores the subsequent 16 [Byte] data (first data string) in the first partial address space 113 (size M), and continues the 16 [Byte] data (second data). The first type control signal group and the second type control signal group are supplied so that the data sequence is stored in the second partial address space 114 (size N).

  Here, the first partial address space 113 is an address space from the start address “E + 16” to the end address “E + 31” in the memory device 101, and is also a logical address space belonging to the logical address space 105. The second partial address space 114 is an address space from the start address “F + 16” to the end address “F + 31” in the memory device 102, and is a logical address space belonging to the logical address space 105.

  That is, the memory device controller 143 alternately divides a logically continuous data string into a first data string (size M) and a second data string (size N), and each first data string is The first type control signal group and the second type control signal are stored in the first partial address space and the second data column adjacent to each first data column is stored in the second partial address space. Feed the group.

  Accordingly, of the series of data, the first data string (size M) of m = 2n−1 (n is a natural number) starts from the start address “E + 16 × (n−1)” in the memory device 101. Stored in the address space up to the end address “E + 16 × n−1”, and the m = 2n-th second data string (size N) ends from the start address “F + 16 × (n−1)” in the memory device 102. It is stored in the address space up to the address “F + 16 × n−1”.

  At this time, it is indicated that the memory device control unit 143 performs data transfer in units of size M (M is a natural number) to the memory device 101 (external DRAM) based on the command received from the arbiter 142. A type 1 control signal group is supplied, and a type 2 control signal group indicated to perform data transfer in units of size N (N is a natural number) is supplied to the memory device 102 (built-in memory).

  When a series of data is stored in the address space 105 (size Y), the series of data transferred from the internal bus IF 140 or the internal bus IF 141 is stored once in the buffer 144 and then stored in the buffer 144. Are alternately divided into the memory device 101 and the memory device 102, and written in parallel to the memory device 101 and the memory device 102. Similarly, in the case of reading, the memory device 101 and each address space of the memory device are read in parallel and the memory device 101 and the memory device 102 are alternately divided into the buffer 145 according to a series of data structures. Then, the data is transferred to each master via the internal bus 140 or the internal bus IF 141.

  Next, a case where the memory device 101 is replaced with a multi-bank DRAM will be described.

As shown in FIG. 3B, when the memory device 101 is replaced with a DRAM having a multi-bank configuration, the memory device control unit 143 stores data stored in the memory device 101 among a series of data. Address space 121 (m = 1), address space 123 (m = third), address space 125 (m = 5), address space 127 (m = 7) are stored in this order. As described above, the first type control signal group is supplied.
Here, the address space 121 is an address space from the start address “E1” to the end address “E1 + 15” in the first bank of the memory device 101, and is also an address space belonging to the logical address space 105. The address space 123 is an address space from the start address “E1 + 16” to the end address “E1 + 31” in the first bank of the memory device 101, and is also an address space belonging to the logical address space 105.

  Further, the address space 125 is an address space from the start address “E2” to the end address “E2 + 15” in the second bank of the memory device 101, and is also an address space belonging to the logical address space 105. The address space 127 is an address space from the start address “E2 + 16” to the end address “E2 + 31” in the second bank of the memory device 101, and is also an address space belonging to the logical address space 105.

  That is, the memory device control unit 143 switches the bank of the memory device 101 to the address space 106 by alternately switching a set of the first partial address space and the second partial address space in units of i (i is a natural number). to access.

  Accordingly, for example, when i first partial address spaces are allocated per bank, m = 2n−1th (n = (j−1) i + k: i, j is a natural number) in a series of data. K is a natural number satisfying 1 ≦ k ≦ i.) In the j-th bank of the memory device 101, the first data string is changed from the start address “Ej + 16 × (k−1)” to the end address “Ej + 16 × k−1”. Are stored in the first partial address space up to "."

  Next, an operation for reading and accessing data stored in the logical address space 105 will be described. Here, a case where the internal bus IF 140 receives an access request for the logical address space 104 twice and a case where the internal bus IF 140 receives an access request for the logical address space 105 are described as an example.

  As shown in FIG. 4A, when the memory device control unit 143 receives the command issued from the internal bus IF 140 at the timing 150 via the arbiter 142, the first type control is performed according to the received command. The signal group is supplied to the memory device 101 (occupation time 152). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 154).

  Further, when the memory device control unit 143 receives the command issued from the internal bus IF 140 at the timing 151 via the arbiter 142, the memory device control unit 143 supplies the first type control signal group to the memory device 101 according to the received command. (Occupation time 153). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 155). Then, the internal bus IF 140 reads data reconstructed from the data specified by the first type control signal group supplied from the memory device control unit 143 from the buffer 145, and reads the read data to the logical address space 104. To the master device that issued the access request.

  Here, as an example, a case where the logical address space 104 is accessed under the following conditions (1) to (3) will be described.

(1) The input / output data width of the memory device 101 (external DRAM) is set to 4 [Bytes].
(2) It is assumed that data is stored in the logical address space 104 in units of 16 [Bytes].
(3) It is assumed that access is performed with an access data length of 16 [Byte] from the 12th [Byte] of the 16 [Byte] data increments.

  In this case, the memory device 101 (external DRAM) is accessed for all 16 [Byte] data. However, the access is made across the first bank and the second bank of the memory device 101. Specifically, the first bank of the memory device 101 (external DRAM) is accessed for the data string (4 [Bytes]) from the 12th [Byte] to the 15th [Byte]. The second bank of the memory device 101 (external DRAM) is accessed for the data string (12 [Byte]) from the 16th [Byte] to the 27th [Byte].

  As a result, the latency for accessing the memory device 101 (external DRAM) is 4 cycles (= 16 [Byte] / 4 [Byte]). Further, since the access is made across the first bank and the second bank of the memory device 101 (external DRAM), if the access data length is short, the command that is the access specification of the memory device 101 (external DRAM) Overhead (α) due to (activait, precharge, read, write) restrictions is added. As a result, in this case, 4 cycles + α are required.

  On the other hand, as shown in FIG. 4B, when the memory device control unit 143 receives the command issued from the internal bus IF 140 at the timing 160 via the arbiter 142, the memory device control unit 143 executes the command in parallel according to the received command. Then, the first type control signal group is supplied to the memory device 101, and the second type control signal group is supplied to the memory device 102 (occupation time 162). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 164). In addition, the memory device 102 outputs the data specified by the second type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 165). The internal bus IF 140 reads data reconstructed from the data specified by the first type control signal group and the second type control signal group supplied from the memory device control unit 143 from the buffer 145, and reads the read data. Is output to the master device that has issued an access request to the logical address space 105.

  When the memory device control unit 143 receives the command issued from the internal bus IF 140 at the timing 161 via the arbiter 142, the memory device control unit 143 sends the first type control signal group to the memory device in parallel according to the received command. The second type control signal group is supplied to the memory device 102 (occupation time 163). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 166). Further, the memory device 102 outputs the data specified by the second type control signal group supplied from the memory device control unit 143 to the buffer 145 (occupation time 167). As a result, compared with FIG. 4A, the latency required for the data transfer process is significantly improved (time 158, time 168).

  Here, as an example, a case where the logical address space 105 is accessed under the following conditions (1) to (4) will be described.

(1) The input / output data width of the memory device 101 (external DRAM) is set to 4 [Bytes].
(2) The input / output data width of the memory device 102 (built-in memory) is 16 [Bytes].
(3) It is assumed that data is stored in the logical address space 105 in units of 16 [Bytes].
(4) It is assumed that access is made with an access data length of 16 [Byte] from the 12th [Byte] of the 16 [Byte] data increments.

  In this case, 16 [Byte] data is accessed across the memory device 101 and the memory device 102. Specifically, the first bank of the memory device 101 (external DRAM) is accessed for the data string (4 [Bytes]) from the 12th [Byte] to the 15th [Byte]. The memory device 102 (internal SRAM) is accessed for the data string (12 [Byte]) from the 16th [Byte] to the 27th [Byte].

  As a result, the latency for accessing the memory device 101 (external DRAM) is one cycle (= 4 [Byte] / 4 [Byte]). In addition, the latency with respect to access of the memory device 102 (built-in memory) is one cycle (= 12 [Byte] / 16 [Byte]: 1 or less is rounded to 1). From these, a total of 2 cycles. Furthermore, the memory device control unit 143 performs the first-type control signal group and the second-type control signal group in parallel by matching the timing of the memory device 101 (external DRAM) access and the memory device 102 (built-in memory) access. When supplied, the access progresses in parallel and ideally takes one cycle + α even in consideration of overhead for one cycle.

  That is, when an access request for the logical address space 104 is received (see FIG. 4A), the access is made across the first bank and the second bank of the memory device 101 as in the prior art. Cycle + α is required. On the other hand, when an access request for the logical address space 105 is received (see FIG. 4B), since access is made across the memory device 101 and the memory device 102, one cycle + α is required. As a result, it is possible to improve the latency of 3 cycles by accessing the logical address space 105.

  As described above, according to the memory access device 10 according to the present embodiment, since the memory device 101 and the memory device 102 are accessed in parallel, the occupation time per command in the memory device 101 is shortened. And the rate of the memory device 101 can be reduced. As a result, the frequency can be reduced and an inexpensive memory device can be used. Further, by reducing the frequency, the ease of design can be improved and the power consumption can be reduced.

  Furthermore, the memory device 102 and the memory device 102 are used in combination with the memory device 102 (built-in memory) to store all data with a high rate and a high access frequency, so that the memory device 102 has substantially the same latency. It is possible to halve the capacity required for the operation.

(Embodiment 2)
Next, Embodiment 2 according to the present invention will be described with reference to the drawings.

  In the memory access device according to the present embodiment, the logical address space associated with the address space of the memory device 102 within the time from when the access to the address space 107 is completed until the next access to the address space 106 is started. An arbiter is provided that supplies a second type control signal group indicating access to the logical address space 103 to the memory device 102 when a command for instructing access to the memory 103 is received.

  Based on the above points, the memory access device in the present embodiment will be described. Note that the same components as those of the memory access device 100 according to the first embodiment are denoted by the same reference numerals and description thereof is omitted.

First, the configuration of the memory access device in the present embodiment will be described.
As shown in FIG. 5, when the memory access device 20 is accessible compared to the memory access device 10 except that the memory device 101 and the memory device 102 operate synchronously, The difference is that the memory device 102 is accessed.

  Here, as an example, the memory access device 20 includes the memory device 101, the memory device 102, the internal bus IF 240, the internal bus IF 241, the command arbiter 242, the memory device control unit 243, the buffer 244, the buffer 245, the selector 246, the buffer 247, A buffer 248, a selector 249, an arbiter 250, a selector 251 and the like are provided. The memory device 101 is externally attached to the controller 100. The memory device 102, internal bus IF 240, internal bus IF 241, command arbiter 242, memory device controller 243, buffer 244, buffer 245, selector 246, buffer 247, buffer 248, selector 249, arbiter 250, and selector 251 are included in the controller 200. Built in.

  The memory device 101 is a memory device that can be accessed in bursts and can continuously transfer high-speed and large-capacity data. For example, a memory device such as a DRAM that can transfer data using a burst mode and can be accessed at high speed. Here, as an example, a DRAM is used. Examples of DRAM include SDRAM, DDR-SDRAM, DDR2-SDRAM, and RamBus XDR.

  The memory device 102 is a memory device capable of high-speed latency, random access, and expansion / reduction of the bus width at the time of design. For example, it is a memory device such as an SRAM, which has a short latency and a high-speed random access. Here, as an example, an SRAM is used. Note that the type of the memory device 102 is not limited to the SRAM, but may be a built-in DRAM, flash, FeRAM, or the like. The memory device 102 may be either internal or external.

  Each of the internal bus IF 240 and the internal bus IF 241 receives an access request for the logical address space 105 from the master device, and issues a command corresponding to the received access request to the command arbiter 242. Further, it receives an access request for the logical address space 103 from the master device, and issues a command corresponding to the received access request to the arbiter 250.

  The command arbiter 242 receives a command issued from the internal bus IF 140 or the internal bus IF 141, performs access arbitration based on the access priority, data rate guarantee, etc. for the received command, and sends the command to the memory device. Transfer to the control unit 243.

  The memory device control unit 243 receives the command transferred from the command arbiter 242, and controls each group of control signals necessary for accessing each memory device under control while controlling the timing based on the received command. Supply to memory devices in parallel. Specifically, when the memory device control unit 243 accesses the memory device 101 according to the received command, the first type control signal group indicating access to the memory device 101 via the signal line 146. (DRAM control signals, address signals, etc.) are supplied. When accessing the memory device 102, a second type control signal group (SRAM control signal, address signal, etc.) indicating access to the memory device 102 is supplied via the signal line 147.

  Note that the logical address space managed by the memory device control unit 243 is the same as the logical address space in the first embodiment (see FIG. 2), and thus description thereof is omitted.

  The buffer 244 is a buffer storage area in which data transferred from the internal bus IF 240 or the internal bus IF 241 to the memory device 101 or the memory device 102 is temporarily accumulated.

  The buffer 245 is a buffer storage area in which data transferred from the internal bus IF 240 or the internal bus IF 241 to the memory device 102 is temporarily stored.

  The selector 246 switches the input source (buffer 244 or buffer 245) according to a control signal (not shown) output from the memory device control unit 243, and outputs data stored in the input source to the memory device 102.

  The buffer 247 is a buffer storage area in which data transferred from the memory device 102 to the internal bus IF 240 or the internal bus IF 241 is temporarily accumulated.

  The buffer 248 is a buffer storage area in which data transferred from the memory device 101 or the memory device 102 to the internal bus IF 240 or the internal bus IF 241 is temporarily accumulated.

  The selector 249 switches the output destination (buffer 247 or buffer 248) according to a control signal (not shown) output from the memory device control unit 243, and accumulates the data output from the memory device 102 in the output destination.

  The arbiter 250 receives the command issued from the internal bus IF 240 or the internal bus IF 241, estimates the free time of access to the memory device 102, and performs the second type control in which access to the memory device 102 is indicated according to the received command A signal group (SRAM control signal, address signal, etc.) is supplied.

  The selector 251 switches the input source (memory device control unit 243 or arbiter 250) in accordance with a control signal (not shown) output from the memory device control unit 243, and is a second type control signal group supplied from the input source. Is output to the memory device 102.

  Note that the memory device control unit 243 controls the selector 246 to select the buffer 244 as an input source when accessing the memory device 101 and the memory device 102 in parallel. Further, the selector 249 is controlled to select the buffer 248 as an output destination. Further, the selector 251 is controlled to select an output from the memory device control unit 243 as an input source.

  Further, when the arbiter 250 receives an access request for the logical address space 103 within a period from the end of the access to the address space 107 to the start of the next access to the address space 106, the arbiter 250 accesses the logical address space 103. The second type control signal group shown is supplied to the memory device 102. At this time, the memory device control unit 243 controls the selector 246 to select the buffer 245 as an input source. Further, the selector 249 is controlled to select the buffer 247 as an output destination. Further, the selector 251 is controlled to select the arbiter 250 as an input source.

  Next, the logical address space 105 managed by the memory device control unit 243 will be described. Here, a case where a logically continuous two-dimensional data array is stored in the logical address space 105 according to the logical address map will be described as an example. As an example, the memory device 101 is a DRAM composed of four banks, and the memory device 102 is an SRAM.

  As illustrated in FIG. 6, the memory device control unit 243, when storing a logically continuous two-dimensional data array 230 in the logical address space 105, is based on the following (a1) to (a4). The first type control signal group and the second type control signal group are supplied so that the first data array and the second data array adjacent to the first data array are stored in pairs.

  The “first data array” refers to a data array having a size M (M is a natural number) in the horizontal direction and a size H (H is a natural number) in the vertical direction. The “second data array” refers to a data array having a size N (N is a natural number) in the horizontal direction and a size H (H is a natural number) in the vertical direction.

  (A1) For each of the part 233 and the part 235 in the area 231, two sets of the first data array and the second data array are stored. At this time, the first data array is stored in the first partial address space allocated to the bank 212 of the memory device 101, and the second data array is stored in the second partial address space allocated to the memory device 102. Is done.

  Here, the “first partial address space” is each address space obtained by dividing the address space 106 into a plurality of sizes, and the size M (M is a natural number) in the horizontal direction and the size H (H is a natural number) in the vertical direction. ) In the address space in which the first data array is stored. The “second partial address space” is an address space obtained by dividing the address space 107 into a plurality, and is a first of a size N (N is a natural number) in the horizontal direction and a size H (H is a natural number) in the vertical direction. This is an address space in which two data arrays are stored.

  (A2) For each of the part 233 and the part 235 in the area 232, two sets of the first data array and the second data array are stored. At this time, the first data array is stored in the first partial address space assigned to the bank 214 of the memory device 101, and the second data array is stored in the second partial address space assigned to the memory device 102. Is done.

  (A3) For each of the part 234 and the part 236 in the area 231, two sets of the first data array and the second data array are stored. At this time, the first data array is stored in the first partial address space allocated to the bank 211 of the memory device 101, and the second data array is stored in the second partial address space allocated to the memory device 102. Is done.

  (A4) For each of the part 234 and the part 236 in the area 232, two sets of the first data array and the second data array are stored. At this time, the first data array is stored in the first partial address space assigned to the bank 213 of the memory device 101, and the second data array is stored in the second partial address space assigned to the memory device 102. Is done.

  That is, when storing a logically continuous two-dimensional data array in the logical address space 105, the memory device control unit 243 repeats the following (b1) and (b2) alternately in the horizontal direction, Alternatively, the following (b2) and (b4) are alternately repeated, and in the vertical direction, the following (b1) and (b3) are alternately repeated, or the following (b3) and (b4) are alternately repeated.

  (B1) The first type control signal group and the second type control signal group are supplied so that the set of the first data array and the second data array is stored in the set of I (I is a natural number). At this time, the first data array is stored in the first partial address space allocated to the bank 212 of the memory device 101, and the second data array is stored in the second partial address space allocated to the memory device 102. Is done.

  (B2) The first type control signal group and the second type control signal group are supplied so that a set of the first data array and the second data array is stored in an I (I is a natural number) set. At this time, the first data array is stored in the first partial address space assigned to the bank 214 of the memory device 101, and the second data array is stored in the second partial address space assigned to the memory device 102. Is done.

  (B3) The first-type control signal group and the second-type control signal group are supplied so that a set of the first data array and the second data array is stored as I (I is a natural number). At this time, the first data array is stored in the first partial address space allocated to the bank 211 of the memory device 101, and the second data array is stored in the second partial address space allocated to the memory device 102. Is done.

  (B4) The first type control signal group and the second type control signal group are supplied so that a set of the first data array and the second data array is stored as I (I is a natural number). At this time, the first data array is stored in the first partial address space assigned to the bank 213 of the memory device 101, and the second data array is stored in the second partial address space assigned to the memory device 102. Is done.

  For example, as shown in FIG. 7, when writing image frame data into the logical address space 105, the memory device control unit 243 repeats the following (c1) and (c2) alternately in the horizontal direction. Alternatively, the following (c2) and (c4) are alternately repeated, and in the vertical direction, the following (c1) and (c3) are alternately repeated, or the following (c3) and (c4) are alternately repeated. It is assumed that the size of the pixel 265, that is, the size of one pixel is 1 [Byte].

  (C1) The first type control signal group and the second type control signal group are supplied so that two sets of the data array 261 and the data array 260 are stored. (C2) The first type control signal group and the second type control signal group are supplied so that two sets of the data array 263 and the data array 260 are stored. (C3) The first type control signal group and the second type control signal group are supplied so that two sets of the data array 262 and the data array 260 are stored. (C4) The first type control signal group and the second type control signal group are supplied so that two sets of the data array 264 and the data array 260 are stored.

  The data array 260 is a second data array of N pixels in the horizontal direction and H pixels in the vertical direction, and is stored in the second partial address space allocated to the memory device 102. The data array 261 is a first data array of M pixels in the horizontal direction and H pixels in the vertical direction, and is stored in a first partial address space assigned to the bank 212 of the memory device 101. The data array 263 is a first data array of M pixels in the horizontal direction and H pixels in the vertical direction, and is stored in a first partial address space assigned to the bank 214 of the memory device 101. The data array 262 is a first data array of M pixels in the horizontal direction and H pixels in the vertical direction, and is stored in the first partial address space assigned to the bank 211 of the memory device 101. The data array 264 is a first data array of M pixels in the horizontal direction and H pixels in the vertical direction, and is stored in a first partial address space assigned to the bank 213 of the memory device 101. The same applies to those indicated by the same hatch in the figure.

  Next, an operation for accessing data stored in the logical address space 105 will be described. Here, an example will be described in which the internal bus IF 240 receives an access request for the logical address space 105 from the master device twice, and the internal bus IF 241 receives an access request for the logical address space 103 from the master device once. To do.

  As illustrated in FIG. 8, when the memory device control unit 243 receives a command issued from the internal bus IF 240 at the timing 160 via the command arbiter 242, the memory device control unit 243 performs the first process in parallel according to the received command. The seed control signal group is supplied to the memory device 101, and the second kind control signal group is supplied to the memory device 102 (occupation time 162). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 243 to the buffer 248 (occupation time 164). Further, the memory device 102 outputs the data specified by the second type control signal group supplied from the memory device control unit 243 to the buffer 248 (occupation time 165). The internal bus IF 240 reads data reconstructed from the data specified by the first type control signal group and the second type control signal group supplied from the memory device control unit 243 from the buffer 248 and reads the read data. Is output to the master device that has issued an access request to the logical address space 105.

  Similarly, when the memory device control unit 243 receives the command issued from the internal bus IF 240 at the timing 161 via the command arbiter 242, the memory device control unit 243 generates the first type control signal group in parallel according to the received command. The second type control signal group is supplied to the memory device 102 (occupation time 163). Accordingly, the memory device 101 outputs data specified by the first type control signal group supplied from the memory device control unit 243 to the buffer 248 (occupation time 166). Further, the memory device 102 outputs the data specified by the second type control signal group supplied from the memory device control unit 243 to the buffer 248 (occupation time 167).

  At this time, when the arbiter 250 receives a command issued from the internal bus IF 241 at the timing 260, the supply of the second type control signal group is completed until the supply of the next first type control signal group is started. In other words, after the data corresponding to the second type control signal group is output from the memory device 102 to the buffer 248, the data corresponding to the next first type control signal group is transferred from the memory device 102 to the buffer 248. Within the time until output starts, the second type control signal group corresponding to the received command is supplied to the memory device 102. Accordingly, the memory device 102 outputs the data specified by the second type control signal group supplied from the arbiter 250 to the buffer 247 (occupation time 261). The internal bus IF 241 reads the data specified by the second type control signal group supplied from the arbiter 250 from the buffer 247 and outputs the read data to the master device that has issued an access request to the logical address space 103. .

  As shown in FIG. 9, the clock frequency of the memory device 102 may be changed according to the address space to be accessed. At this time, the clock frequency of the memory device 102 is set to F [MHz] when accessing the logical address space 105, and E [MHz] (F ≦ E ≦ nF: when accessing the logical address space 103. n = 2, 3,...), and the clock frequency is increased in bursts, whereby the latency and the transfer amount may be increased for single access of the memory device 102 (time 361, time 362). .

  The second memory device 102 operates at the access frequency A [MHz] for access to the logical address space 105 (address space 107), and accesses to the logical address space 103 (all address spaces of the memory device 102). May operate at an access frequency B [MHz] higher than the access frequency A [MHz]. As a result, the data transfer can be completed within the time when the data bus of the memory device 102 is played, and a plurality of data transfers can also be performed.

  Furthermore, the access frequency B [MHz] may be a natural number multiple of the access frequency A [MHz]. This facilitates timing and facilitates design.

  The memory device 101 operates at an access frequency C [MHz] for access to the logical address space 105 (address space 106), and the memory device 102 performs access to the logical address space 105 (address space 107). It may be operated at an access frequency D [MHz] higher than the access frequency C [MHz]. As a result, the data transfer can be completed within the time when the data bus of the memory device 102 is played, and a plurality of data transfers can also be performed.

  Furthermore, the access frequency D [MHz] may be a natural number multiple of the access frequency C [MHz]. This facilitates timing and facilitates design.

  As described above, according to the memory access device 20 according to the present embodiment, in response to an access request to the logical address space 105 (size Y = L + K), the memory device 101 (external DRAM) and the memory device 102 ( By controlling the access so as to straddle the area of the built-in memory), it is possible to further increase the margin of required latency. Of course, since access is distributed to the memory device 101 (external DRAM) and the memory device 102 (built-in memory), the access time occupied by the memory device 101 (external DRAM) can be reduced. In other words, the access rate to the memory device 101 (external DRAM) is kept low. As a result, when a high-speed external memory is originally required, it becomes possible to select a memory device having a lower speed.

  Further, by designing the bus width of the memory device 102 (built-in memory) so that large data is transferred in one cycle, the data is transferred in synchronization with the data of the memory device 101 (external DRAM). As a result, there is time to play the data bus of the memory device 102 (built-in memory). By accessing data that requires latency at this time, access that requires latency and access that requires transfer efficiency can be run in parallel, and the latency and the transfer amount can be improved. Further, by increasing the clock frequency of the memory device 102 in a burst manner, the latency and the transfer amount can be further improved.

  Furthermore, by using together the memory device 101 (external DRAM) having the same capacity as the memory device 102 (built-in memory), it becomes possible to access an address space twice the capacity of the memory device 102. Further, when the memory device 102 (built-in memory) is built in an LSI and the capacity of the memory device 102 is insufficient depending on the application, the memory device 102 operates in conjunction with the external memory device 101 to Space can be expanded or reduced. In addition, large-capacity data processing can be realized without increasing the capacity of the built-in memory device 102. With the minimum capacity, it can absorb the capacity that increases with the addition of applications.

(Other)
Note that the memory access device may be realized by a full custom LSI (Large Scale Integration). Further, it may be realized by a semi-custom LSI such as ASIC (Application Specific Integrated Circuit). Further, it may be realized by a programmable logic device such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). Further, it may be realized as a dynamic reconfigurable device whose circuit configuration can be dynamically rewritten.

  Further, design data for forming one or more functions constituting the memory access device in these LSIs is a hardware description language such as VHDL (Very High Speed Integrated Circuit Hardware Description Language), Verilog-HDL, SystemC, etc. The program described below (hereinafter referred to as HDL program) may be used. Alternatively, it may be a gate level netlist obtained by logical synthesis of an HDL program. Alternatively, macro cell information in which arrangement information, process conditions, and the like are added to a gate level netlist may be used. Further, it may be mask data in which dimensions, timing, and the like are defined.

  Further, an optical recording medium (for example, a CD-ROM), a magnetic recording medium (for example, a hard disk), a magneto-optical recording medium (for example, so that it can be read by a hardware system such as a computer system, an embedded system, or the like. For example, the design data may be recorded on a computer-readable recording medium such as an MO and a semiconductor memory (for example, a RAM). The design data read by the other hardware system via these recording media may be downloaded to the programmable logic device via the download cable.

  Alternatively, the design data may be held in the hardware system on the transmission path so that it can be acquired by another hardware system via the transmission path such as a network. Furthermore, design data acquired from a hardware system to another hardware system via a transmission line may be downloaded to a programmable logic device via a download cable.

  Alternatively, logic synthesis, arrangement, and wiring design data may be recorded in a serial ROM so that the design data can be transferred to the FPGA when energized. The design data recorded in the serial ROM may be directly downloaded to the FPGA when energized.

  The present invention relates to a memory access device that performs an interface between a master device device and a memory device such as a processor and a codec, and particularly a memory access device that improves the transfer speed between the master device device and the memory device at low cost. It can be used as such.

It is a figure which shows the structure of the memory access apparatus in Embodiment 1 which concerns on this invention. It is a figure which shows the correspondence of the logical address space managed by the memory device control part in Embodiment 1 which concerns on this invention, and the address space of each memory device. In the memory device according to the first embodiment of the present invention, (a) is a single bank, and (b) is a diagram showing a configuration of an address space in the case of multiple banks. The memory access device according to the first embodiment of the present invention shows the latency when (a) is accessed alone and (b) is when accessed in parallel. It is a figure which shows the structure of the memory access apparatus in Embodiment 2 which concerns on this invention. It is a figure which shows the correspondence of the logical address space managed by the memory device control part in Embodiment 2 which concerns on this invention, and the address space of each memory device. It is a figure which shows the image frame data stored in the logical address space managed by the memory device control part in Embodiment 2 which concerns on this invention. It is a figure which shows the latency at the time of accessing in parallel with the memory access apparatus in Embodiment 2 which concerns on this invention. It is a figure which shows the latency at the time of raising the clock frequency of a memory device with the memory access apparatus in Embodiment 1 which concerns on this invention, and accessing.

Explanation of symbols

10, 20 Memory access device 100, 200 Controller 101 Memory device 102 Memory device 140, 240 Internal bus IF
141,241 Internal bus IF
142 Arbiters 143 and 243 Memory device controller 144 Buffer 145 Buffer 242 Command arbiter 244 Buffer 245 Buffer 246 Selector 247 Buffer 248 Buffer 249 Selector 250 Arbiter 251 Selector

Claims (10)

A first memory device assigned a first address space;
A second memory device having a latency required for access shorter than that of the first memory device and assigned a second address space;
The first address space is divided into a plurality of first partial address spaces, the second address space is divided into a plurality of second partial address spaces, and each first partial address space and each second partial address When a logical address space that is alternately arranged and logically continuous is a first logical address space,
Memory device control means for controlling access to the first address space and the second address space in response to a first command for instructing access to the first logical address space;
With
When the memory device control means accesses the first partial address space in response to the first command, the memory device control means sets the first type control signal group indicating access to the first partial address space as the first type control signal group. When the second partial address space is accessed by supplying to the first memory device, a second type control signal group indicating access to the second partial address space is supplied to the second memory device. And
When the memory device control means accesses the first partial address space and the second partial address space, the memory device control means uses the first type control signal group and the second type control signal group. A memory access device characterized by being supplied in parallel,
The memory access device further includes:
Third type control in which access to the address space of the second memory device is indicated within the time from the end of access to the second address space to the start of the next access to the first address space features and to Rume memory access device further comprising an arbiter for supplying a signal group to said second memory device. The second memory device operates at a first access frequency for access to the second address space, and for access to the address space of the second memory device than the first access frequency. The memory access device according to claim 1 , wherein the memory access device operates at a high second access frequency. The first memory device is
For access to the first address space, it operates at a first access frequency;
The second memory device is
Wherein the access to the second address space, the memory access apparatus according to claim 1, characterized in that to operate at a higher second access frequency than the first access frequency. The arbiter than said address space in which the third type control signal group access, memory access apparatus according to claim 1, wherein the priority of access to the first logical address space. The first partial address space is an address space in which a first data string having a size M (M is a natural number) is stored, and the second partial address space is a size N (N is a natural number). An address space in which the second data string is stored,
The memory device control means includes
A logically continuous data string is alternately divided into the first data string and the second data string, and each first data string is stored in each first partial address space. Supplying the first type signal group and the second type signal group so that a second data string adjacent to the data string is stored in a second address space adjacent to the first address space. The memory access device according to claim 1. The first partial address space is an address space in which a first data array having a size M (M is a natural number) in the first direction and a size H (H is a natural number) in the second direction is stored. The second partial address space is an address space in which a second data array having a size N (N is a natural number) in the first direction and a size H (H is a natural number) in the second direction is stored. There,
The memory device control means includes
A logically continuous two-dimensional data array is alternately divided into the first data array and the second data array, and each first data array is stored in each first partial address space. The first type signal group and the second type signal group are set such that a second data array adjacent to one data array is stored in a second partial address space adjacent to each first partial address space. The memory access device according to claim 1, wherein the memory access device is supplied. The first memory device is a memory device composed of a plurality of banks,
The memory device control means includes
Accessing the first address space by alternately switching banks of the first memory device in units of I (I is a natural number) as a set of the first partial address space and the second partial address space The memory access device according to claim 1, wherein: A logical address space associated with a third address space allocated to the first memory device separately from the first address space is defined as a second logical address space, and separately from the second address space. In the case where the logical address space associated with the fourth address space allocated to the second memory device is the third logical address space,
The memory device control means includes
In response to a second command instructing access to the second logical address space, to access the third address space and in response to a third command instructing access to the third logical address space, The memory access device according to claim 1, wherein the fourth address space is accessed. The first memory device is a DRAM externally attached separately from the memory device control means,
The memory access apparatus according to claim 1, wherein the second memory device is a memory device built in with the memory device control unit. Memory for accessing a first memory device to which a first address space is assigned and a second memory device to which a latency required for access is shorter than that of the first memory device and to which a second address space is assigned An access method,
The memory access method includes:
The first address space is divided into a plurality of first partial address spaces, the second address space is divided into a plurality of second partial address spaces, and each first partial address space and each second partial address When a logical address space that is alternately arranged and logically continuous is a first logical address space,
A control step of controlling access to the first address space and the second address space in response to a first command instructing access to the first logical address space;
In the control step, when accessing the first partial address space according to the first command, a first type control signal group indicating access to the first partial address space is set to the first partial address space. When supplying to the memory device and accessing the second partial address space, a second type control signal group indicating access to the second partial address space is supplied to the second memory device,
In the control step, when accessing the first partial address space and the second partial address space, the first type control signal group and the second type control signal group are supplied in parallel. It is characterized by
The memory access method further includes:
Third type control in which access to the address space of the second memory device is indicated within the time from the end of access to the second address space to the start of the next access to the first address space A method for accessing a memory , comprising: supplying a signal group to the second memory device .

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