WO2010067483A1 - Thin film transistor and method for manufacturing the thin film transistor - Google Patents

Thin film transistor and method for manufacturing the thin film transistor Download PDF

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Publication number
WO2010067483A1
WO2010067483A1 PCT/JP2009/003499 JP2009003499W WO2010067483A1 WO 2010067483 A1 WO2010067483 A1 WO 2010067483A1 JP 2009003499 W JP2009003499 W JP 2009003499W WO 2010067483 A1 WO2010067483 A1 WO 2010067483A1
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silicon layer
concentration region
layer
film transistor
low concentration
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PCT/JP2009/003499
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French (fr)
Japanese (ja)
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岡部達
博彦 錦
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a bottom gate (inverse stagger) type thin film transistor and a manufacturing method thereof.
  • TFTs Thin film transistors
  • organic EL electroactive electrowetting
  • FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.
  • the TFT 105 corresponds to the gate electrode 111 provided on the glass substrate 110, the gate insulating film 112 provided so as to cover the gate electrode 111, and the gate electrode 111 on the gate insulating film 112.
  • the semiconductor layer 113 provided in an island shape at a position where the source electrode 114a and the drain electrode 114b are provided so as to be separated from each other on the semiconductor layer 113.
  • the semiconductor layer 113 includes a lower intrinsic amorphous silicon layer 113a and an upper n + amorphous silicon layer 113b doped with phosphorus, and includes a source electrode 114a and a drain electrode. Intrinsic amorphous silicon layer 113a exposed from 114b constitutes channel portion C.
  • the n + amorphous silicon film constituting the n + amorphous silicon layer 113b by performing channel etching for removing by dry etching, the channel section C is formed.
  • the n + amorphous silicon film constituting the n + amorphous silicon layer 113b and the intrinsic amorphous silicon film constituting the intrinsic amorphous silicon layer 113a have similar film qualities, in the channel etching, It is difficult to increase the selectivity between the n + amorphous silicon film and the intrinsic amorphous silicon film.
  • substrates constituting liquid crystal display panels and organic EL display panels that is, substrates for forming TFTs are becoming larger and larger.
  • a TFT is formed on a large glass substrate having a side of 1500 mm or more.
  • the variation of the film thickness of the n + amorphous silicon layer becomes about ⁇ 20% within the substrate surface.
  • a gate electrode, a gate insulating film, an operating semiconductor layer, an n-type impurity semiconductor layer, and a conductor layer are formed on a glass substrate, and the conductor layer and the n-type impurity semiconductor layer are etched. Then, in the method of manufacturing a liquid crystal display device having a TFT in which the upper layer of the operating semiconductor layer on the gate electrode is exposed to form a source electrode and a drain electrode, the conductor layer and the n-type impurity semiconductor layer are etched. And forming a residual layer on the glass substrate that is etched simultaneously. According to this, it is described that a liquid crystal display device having a channel etch type TFT having stable characteristics can be manufactured by reliably detecting the end point of channel etching.
  • the n-type impurity semiconductor layer (n + amorphous silicon film) is used as the film thickness of the residual layer.
  • the film thickness in the substrate surface at the time of forming the n + amorphous silicon film and at the time of dry etching In view of the variation of the above, it is difficult to reliably form TFTs having stable characteristics.
  • the selection ratio at the time of dry etching of the intrinsic amorphous silicon film and the n + amorphous silicon film, that is, the semiconductor layer is formed. Therefore, it is desired to increase the selectivity during etching of the first silicon layer and the second silicon layer.
  • the present invention has been made in view of such a point, and an object of the present invention is to make the selectivity ratio of the first silicon layer and the second silicon layer constituting the semiconductor layer as high as possible. It is in.
  • the first silicon layer has a low concentration region having a hydrogen content of 3 atomic% or less.
  • a thin film transistor includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a channel provided on the gate insulating film so as to overlap the gate electrode.
  • the hydrogen content is 3 atomic% or less in the low concentration region of the first silicon layer, the hydrogen content (for example, about 10 atomic%) of the first silicon layer of the conventional thin film transistor. Is also low.
  • Table 1 the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n + amorphous silicon film formed by simply CVD. Obtained.
  • the first silicon layer and the first silicon layer constituting the semiconductor layer are suppressed. It becomes possible to increase the selectivity during etching of the two silicon layers as much as possible.
  • each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method. Therefore, it is possible to increase the selectivity as in dry etching using hydrogen gas as a main component, so that it is not necessary to increase the thickness of an intrinsic amorphous silicon film as a sacrificial layer in the conventional manner. There is an advantage that tact time can be shortened and material cost can be reduced.
  • the low concentration region may be disposed on the entire first silicon layer.
  • the low concentration region is disposed on the entire first silicon layer, formation of the second silicon layer exposed from the source electrode and the drain electrode is formed in order to form the second silicon layer and the channel portion. Even if the layer is removed by dry etching, the removal of the first silicon layer below the layer is specifically suppressed.
  • the film thickness of the first silicon layer may be 200 mm or more and 800 mm or less.
  • the first silicon layer since the thickness of the first silicon layer is 200 mm or more and 800 mm or less, the first silicon layer has an appropriate film thickness to function as an intrinsic semiconductor layer. It becomes possible to improve.
  • the first silicon layer is disposed in the channel portion so as to correspond to the source electrode and the drain electrode on the outside of the low concentration region and the low concentration region, and has a higher hydrogen content than the low concentration region. And may have a region.
  • the low concentration region with a relatively low hydrogen content has a relatively high crystallinity
  • the high concentration region with a relatively high hydrogen content has a relatively low crystallinity.
  • the high-concentration region becomes a buffer region for relaxing the electric field between the low-concentration region and the source and drain electrodes, and the off-state current of the thin film transistor can be reduced.
  • the first silicon layer may have crystallinity.
  • the mobility of the first silicon layer is increased to, for example, about 1 cm 2 / Vs to 500 cm 2 / Vs, and the first silicon layer
  • a high-functional circuit such as a gate driver or a source driver can be configured.
  • the thin film transistor manufacturing method includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a gate insulating film provided on the gate insulating film so as to overlap the gate electrode.
  • a method of manufacturing a thin film transistor having a second silicon layer doped with an impurity between the first silicon layer and the source electrode and the drain electrode, wherein the first silicon film to be the first silicon layer is formed A low concentration region forming step for forming a low concentration region having a hydrogen content of 3 atomic% or less, and a substrate on which the low concentration region is formed, A semiconductor layer forming etching step of removing a part of the semiconductor layer forming layer to be the semiconductor layer by performing dry etching using an elementary gas or wet etching using an etchant containing hydrogen peroxide and fluorine. It is characterized by providing.
  • the low concentration region having a hydrogen content of 3 atomic% or less is formed in the first silicon film to be the first silicon layer.
  • the hydrogen content (for example, about 10 atomic%) of the first silicon layer of the thin film transistor is lower.
  • Table 1 below the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n + amorphous silicon film formed by simply CVD.
  • the hydrogen content of at least a part (low concentration region) of the first silicon film is suppressed to 3 atomic% or less by laser annealing, and further, semiconductor layer formation etching is performed.
  • semiconductor layer formation etching is performed.
  • each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method.
  • the low concentration region may be formed by irradiating the first silicon film with laser light.
  • the crystallinity of the low concentration region of the first silicon film can be improved.
  • a high-performance thin film transistor having a mobility of about 1 cm 2 / Vs to 500 cm 2 / Vs can be manufactured.
  • the low-concentration region is formed in at least a region to be the channel portion of the first silicon film, and the second silicon layer is formed on the first silicon film in which the low-concentration region is formed.
  • the channel portion may be formed by removing the layer forming layer.
  • the low concentration region is formed in at least the region to be the channel portion of the first silicon film, and in the source / drain forming step, the second silicon layer forming layer is formed in the low concentration region.
  • a source electrode and a drain electrode are formed thereon, and the second silicon layer formation layer exposed from the source electrode and the drain electrode is removed in the semiconductor layer formation etching step. To be manufactured.
  • the low concentration region is formed in the first silicon layer forming layer that is the first silicon layer exposed from the source electrode and the drain electrode, and in the semiconductor layer forming etching step, the low concentration region is formed.
  • the channel portion is disposed corresponding to the source electrode and the drain electrode and has a higher hydrogen content than the low concentration region.
  • a concentration region may be formed.
  • the low concentration region is formed in the first silicon layer forming layer exposed from the source electrode and the drain electrode in the low concentration region forming step, and is disposed outside the low concentration region in the semiconductor layer forming etching step. A part of the first silicon layer forming layer to be removed is removed to form a high concentration region in the channel portion.
  • the low concentration region having a relatively low hydrogen content has a relatively high crystallinity
  • the high concentration region having a relatively high hydrogen content has a relatively low crystallinity.
  • the wavelength of the laser beam may be 248 nm or more and 355 nm or less.
  • the wavelength of the laser beam applied to the first silicon film is not less than 248 nm and not more than 355 nm, even if the first silicon film is formed thin, the laser beam is transmitted through the first silicon film. Is suppressed, and a high-performance thin film transistor can be manufactured without damaging the gate electrode and the gate insulating film.
  • the substrate may be a rectangular glass substrate having a short side of 1500 mm or more.
  • the substrate is a large glass substrate, the effects of the present invention are effectively exhibited.
  • the etching selectivity of the first silicon layer and the second silicon layer constituting the semiconductor layer can be made as high as possible.
  • FIG. 1 is a cross-sectional view of a TFT 5a according to the first embodiment.
  • FIG. 2 is a flowchart for manufacturing the TFT 5a.
  • FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step according to the first embodiment.
  • FIG. 4 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the first embodiment.
  • FIG. 5 is a cross-sectional view of the TFT 5b according to the second embodiment.
  • FIG. 6 is a flowchart for manufacturing the TFT 5b.
  • FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process according to the second embodiment.
  • FIG. 8 is a cross-sectional view of the substrate in the low concentration region forming step according to the second embodiment.
  • FIG. 9 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the second embodiment.
  • FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.
  • Embodiment 1 of the Invention 1 to 4 show a first embodiment of a thin film transistor (TFT) and a method for manufacturing the same according to the present invention. Specifically, FIG. 1 is a cross-sectional view of the TFT 5a of this embodiment.
  • TFT thin film transistor
  • the TFT 5 a corresponds to the gate electrode 11 provided on the insulating substrate 10, the gate insulating film 12 provided so as to cover the gate electrode 11, and the gate electrode 11 on the gate insulating film 12.
  • the semiconductor layer 13 is provided in an island shape at a position where the source electrode 14 a and the drain electrode 14 b are provided so as to be separated from each other on the semiconductor layer 13.
  • the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13a provided as a first silicon layer and an upper phosphorus-doped n + amorphous silicon layer 13b provided as a second silicon layer.
  • the intrinsic amorphous silicon layer 13a exposed from the source electrode 14a and the drain electrode 14b constitutes the channel portion C.
  • the entire intrinsic amorphous silicon layer 13a is a low concentration region Ra having a hydrogen content of 3 atomic% or less.
  • the TFT 5a having the above-described configuration is provided as a switching element connected to each pixel electrode of an active matrix substrate in which a plurality of pixel electrodes are arranged in a matrix, for example, and the active matrix substrate is opposed to the opposing one.
  • a liquid crystal display panel is constituted with a substrate and a liquid crystal layer sealed between the two substrates.
  • the manufacturing method of the TFT 5a of this embodiment includes a gate electrode formation step, a GI / i-Si layer formation step, a low concentration region formation step, an n + -Si film formation step, an n + A Si layer forming step, a source / drain forming step, a semiconductor layer forming etching step, and a resist stripping step;
  • FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step of the present embodiment
  • FIG. 4 is a cross-sectional view of the substrate in the semiconductor layer forming etching step of the present embodiment.
  • a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate (for example, 0.7 mm ⁇ 1500 mm ⁇ 1800 mm) by a sputtering method to a thickness of 3000 mm. Film is formed to the extent.
  • a photosensitive resin film is applied to the entire substrate on which the first metal film has been formed by spin coating, and then patterned to form a first resist pattern.
  • the first resist pattern is peeled off to form the gate electrode 11.
  • a gate insulating film is formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm on the entire substrate on which the gate electrode 11 has been formed in the gate electrode formation step by a CVD (Chemical Vapor Deposition) method. 12 is formed.
  • an intrinsic amorphous silicon film is formed as a first silicon film with a thickness of about 200 to 800 mm on the entire substrate on which the gate insulating film 12 is formed by a CVD method.
  • the intrinsic amorphous silicon film formed by the CVD method is generally formed by introducing silane gas or hydrogen gas into the reaction chamber, the hydrogen content is 10 atomic% or more.
  • a second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film has been formed by spin coating, followed by patterning.
  • the second resist pattern is peeled off to form an intrinsic amorphous silicon layer (13a).
  • ⁇ Low concentration region forming step (St13)> As shown in FIG. 3, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer (13a) formed in the GI / i-Si layer forming process. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra.
  • laser annealing is exemplified as a method for forming the low concentration region Ra, but lamp annealing, oven annealing, or the like may be used.
  • the ratio of H 2 gas flow rate / SiH 4 gas flow rate may be set.
  • the CVD conditions may be set so that the film is formed at a temperature of 20 or more and the hydrogen content is lowered.
  • n + amorphous silicon film doped with phosphorus as a second silicon film is formed to a thickness of about 500 mm on the entire substrate on which the low concentration region Ra has been formed in the low concentration region forming step by the CVD method.
  • the n + amorphous silicon film is formed by introducing hydrogen gas as in the case of the intrinsic amorphous silicon film described above, the hydrogen content is 10 atomic% or more.
  • a third resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the n + amorphous silicon film has been formed in the n + -Si film forming process by spin coating, followed by patterning. Form.
  • the third resist pattern is peeled off to form a second silicon layer forming layer (semiconductor layer forming layer).
  • N + amorphous silicon layer forming layer 13ba is formed (see FIG. 4).
  • the n + amorphous silicon film can be easily formed by reactive dry etching using a fluorine-based gas such as sulfur hexafluoride gas or carbon tetrafluoride gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas. (See Table 1).
  • a second metal film such as an aluminum film, a copper film, or a titanium film is sputtered to a thickness of about 3000 mm on the entire substrate on which the n + amorphous silicon layer forming layer 13ba has been formed in the n + -Si layer forming step.
  • the film is formed by
  • a photosensitive resin film is applied to the entire substrate on which the second metal film has been formed by spin coating, and then patterned to form a fourth resist pattern.
  • the second metal film exposed from the fourth resist pattern is removed by dry etching to form the source electrode 14a and the drain electrode 14b (see FIG. 4).
  • n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is subjected to reactive ion etching or plasma using hydrogen gas as a main component.
  • reactive ion etching or plasma using hydrogen gas as a main component.
  • the n + amorphous silicon layer 13b is formed.
  • the intrinsic amorphous silicon layer 13a having a hydrogen content of 3 atomic% or less is hardly removed by the generated hydrogen radicals or hydrogen ions because the hydrogen content is small.
  • n + amorphous silicon layer forming layer 13ba whose amount is 10 atomic% or more, it is easily removed by the generated hydrogen radicals or hydrogen ions, and therefore between the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer forming layer 13ba. High selectivity can be realized.
  • the n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is oxidized as shown in FIG.
  • Wet etching may be performed with an etchant containing hydrogen and fluorine and using a fluorine compound as a main component.
  • the fluorine compound is known to etch silicon, but the n + amorphous silicon layer having a high hydrogen content has a higher etching rate than the intrinsic amorphous silicon layer 13a having a low hydrogen content.
  • the fluorine compound can etch titanium metal
  • the source / drain formation step (St16) can be performed at the same time when a single layer or a multilayer wiring is used for the source / drain metal. There is an advantage that can be reduced.
  • ⁇ Resist stripping step (St18)> The fourth resist pattern is peeled off from the substrate on which the n + amorphous silicon layer 13b is formed in the semiconductor layer formation etching step.
  • the TFT 5a of this embodiment can be manufactured.
  • the low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer 13a in the low concentration region forming step.
  • the hydrogen content for example, about 10 atomic% of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower.
  • an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing The etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, as compared with an intrinsic amorphous silicon film or an n + amorphous silicon film formed simply by a CVD method.
  • an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method.
  • the hydrogen content of the intrinsic amorphous silicon layer 13a (low concentration region Ra) is suppressed to 3 atomic% or less by laser annealing, and in the semiconductor layer formation etching step, When the n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b is removed by performing dry etching using a gas or wet etching using an etchant containing hydrogen peroxide and fluorine, an intrinsic property is obtained.
  • the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 13b (n + amorphous silicon layer forming layer 13ba) constituting the semiconductor layer 13 are etched. Selectivity It can be increased retroactively.
  • the film thickness of the intrinsic amorphous silicon layer 13a is not less than 200 mm and not more than 800 mm, the intrinsic amorphous silicon layer 13a has an appropriate film thickness to function as an intrinsic semiconductor layer. ON characteristics and productivity can be improved.
  • the semiconductor layer 13 including the intrinsic amorphous silicon layer 13a can constitute not only a TFT provided in each pixel of a liquid crystal display panel or an organic EL display panel, but also a high function circuit such as a gate driver or a source driver.
  • the wavelength of the laser light L applied to the intrinsic amorphous silicon layer 13a is not less than 248 nm and not more than 355 nm. Therefore, even if the intrinsic amorphous silicon layer 13a is formed thin. The transmission of the laser light L in the intrinsic amorphous silicon layer 13a is suppressed, and a high-performance TFT can be manufactured without damaging the gate electrode 11 and the gate insulating film 12.
  • FIG. 5 is a cross-sectional view of the TFT 5b of the second embodiment.
  • the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the TFT 5b includes a gate electrode 11 provided on the insulating substrate 10, a gate insulating film 12 provided so as to cover the gate electrode 11, and a gate, as shown in FIG.
  • a semiconductor layer 13 provided in an island shape at a position corresponding to the gate electrode 11 on the insulating film 12, and a source electrode 14 c and a drain electrode 14 d provided on the semiconductor layer 13 so as to be separated from each other are provided.
  • the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13c provided as a first silicon layer, and an upper phosphorus + doped n + amorphous silicon layer 13d provided as a second silicon layer.
  • the intrinsic amorphous silicon layer 13c exposed from the source electrode 14c, the drain electrode 14d, and the n + amorphous silicon layer 13d constitutes the channel portion C.
  • the channel portion C of the intrinsic amorphous silicon layer 13c is disposed corresponding to the source electrode 14c and the drain electrode 14d on the outer side of the low concentration region Ra having a hydrogen content of 3 atomic% or less and the low hydrogen concentration.
  • the manufacturing method of the TFT 5b of this embodiment includes a TFT pattern forming step, a low concentration region forming step, and a hydrogen gas etching step (semiconductor layer forming etching step) as shown in the flowchart of FIG.
  • FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process of the present embodiment
  • FIG. 8 is a cross-sectional view of the substrate in the low-concentration region forming process of the present embodiment
  • ⁇ TFT pattern forming step (St21)> First, for example, a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate with a thickness of about 3000 mm by a sputtering method.
  • a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate with a thickness of about 3000 mm by a sputtering method.
  • a photosensitive resin film is applied to the entire substrate on which the first metal film has been formed by spin coating, and then patterned to form a first resist pattern.
  • the first resist pattern is peeled off to form the gate electrode 11.
  • a gate insulating film 12 is formed on the entire substrate on which the gate electrode 11 has been formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm by a CVD (Chemical Vapor Deposition) method.
  • CVD Chemical Vapor Deposition
  • an intrinsic amorphous silicon film having a thickness of about 2000 mm is formed as a first silicon film on the entire substrate on which the gate insulating film 12 is formed by CVD, and then phosphorus is doped as the second silicon film.
  • + Amorphous silicon film is formed with a thickness of about 500 mm.
  • a second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film and the n + amorphous silicon film are sequentially formed by spin coating, followed by patterning.
  • the second resist pattern is peeled off to form a semiconductor layer forming layer.
  • a second metal film such as an aluminum film, a copper film, or a titanium film is formed by sputtering on the entire substrate on which the semiconductor layer forming layer has been formed by sputtering.
  • a photosensitive resin film is applied to the entire substrate on which the second metal film is formed by spin coating, and then patterned to form a third resist pattern.
  • the second metal film exposed from the third resist pattern is removed by dry etching to form the source electrode 14c and the drain electrode 14d (see FIG. 7).
  • the upper layer portion of the n + amorphous silicon layer forming layer exposed from the source electrode 14c and the drain electrode 14d and the intrinsic amorphous silicon layer forming layer disposed below the n + amorphous silicon layer forming layer is made of fluorine such as sulfur hexafluoride gas or carbon tetrafluoride gas.
  • the TFT pattern 15 is formed as shown in FIG. 7 by removing by reactive dry etching using a system gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas.
  • ⁇ Low concentration region forming step (St22)> As shown in FIG. 8, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer forming layer 13ca of the TFT pattern 15 formed in the TFT pattern forming step. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra.
  • laser light L for example, excimer laser light having a wavelength of 308 nm
  • the amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra.
  • the source electrode 14c and the drain electrode 14d are made of a highly reflective material such as an aluminum film or a silver film
  • the laser beam L is applied to the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d. Not irradiated. Therefore, the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d is not laser-annealed, so that the high concentration region Rb is formed outside the low concentration region Ra.
  • n + amorphous silicon layer formation layer 13da exposed from the source electrode 14a and the drain electrode 14b and the intrinsic amorphous silicon layer formation layer 13ca disposed below the n + amorphous silicon layer formation layer 13ca
  • a hydrogen plasma P generated by ionic dry etching using hydrogen gas as a main component is used for the upper layer portion by utilizing an isotropic high-density plasma etching apparatus using a coil or the like.
  • the intrinsic amorphous silicon layer 13c and the n + amorphous silicon layer 13d are formed by removing.
  • the intrinsic amorphous silicon layer formation layer 13ca has a low hydrogen concentration of 3 atomic% or less, but the low concentration region Ra has low ionicity and is hardly removed.
  • the high concentration region Rb having a hydrogen content of about 10 atomic% and the n + amorphous silicon layer forming layer 13ba having a hydrogen content of about 10 atomic% have high ionicity and are easily removed.
  • the amorphous silicon layer forming layer 13ca and the n + amorphous silicon layer da are removed by about 1 ⁇ m to the side.
  • the TFT 5b of this embodiment can be manufactured.
  • the hydrogen content in the intrinsic amorphous silicon layer forming layer 13ca to be the intrinsic amorphous silicon layer 13c is 3 atomic% or less in the low concentration region forming step. Since the low concentration region Ra is formed, the hydrogen concentration (for example, about 10 atomic%) of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower in the low concentration region Ra.
  • an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method.
  • a low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer forming layer 13ca exposed from the source electrode 14c and the drain electrode 14d by laser annealing. Dry etch using By removing a part of the semiconductor layer forming layer that becomes the semiconductor layer by forming the high concentration region Rb in the channel portion C, the low concentration region Ra of the intrinsic amorphous silicon layer forming layer 13ca is removed.
  • the high concentration region Rb and the n + amorphous silicon layer formation layer da of the intrinsic amorphous silicon layer formation layer 13ca disposed outside the low concentration region Ra are removed, so that the intrinsic amorphous silicon layer constituting the semiconductor layer 13c is removed.
  • the selection ratio during dry etching of 13c (intrinsic amorphous silicon layer forming layer 13ca) and n + amorphous silicon layer 13d (n + amorphous silicon layer forming layer 13da) can be made as high as possible.
  • the low concentration region Ra having a relatively low hydrogen content has a relatively high crystallinity and a relatively high hydrogen content. Since the high concentration region Rb is relatively low in crystallinity, the high concentration region Rb becomes a buffer region for relaxing the electric field between the low concentration region Ra and the source electrode 14c and drain electrode 14d. The off current can be reduced.
  • the defect portion in the silicon generated after irradiation with the laser beam L can be terminated by hydrogen plasma, so that the TFT characteristics (mobility and off-current) are improved. Can be made.
  • St23 of this embodiment dry etching using hydrogen gas is performed, but wet etching using an etchant containing hydrogen peroxide and fluorine may be performed.
  • an n-channel TFT in which the second silicon layer is doped with phosphorus is exemplified, but the present invention is also applicable to a p-channel TFT in which the second silicon layer is doped with boron. Can do.
  • the present invention is useful for, for example, an active matrix liquid crystal display panel and an organic EL display panel.

Abstract

Disclosed is a thin film transistor (TFT) (5a) comprising a substrate (10), a gate electrode (11) provided on the substrate (10), a gate insulating film (12) provided so as to cover the gate electrode (11), and a semiconductor layer (13) provided on the gate insulating film (12).  The semiconductor layer (13) comprises a first silicon layer (13a) that has a channel part (C) provided so as to overlap with the gate electrode (11), and a source electrode (14a) and a drain electrode (14b) that are provided away from each other on the semiconductor layer (13) so as to expose the channel part (C).  The semiconductor layer (13) further comprises an impurity-doped second silicon layer (13b) provided between the first silicon layer (13a) and the source and drain electrodes (14a, 14b).  The first silicon layer (13a) has a low-concentration region (Ra) having a hydrogen content of not more than 3 atomic%.

Description

薄膜トランジスタ及びその製造方法Thin film transistor and manufacturing method thereof
　本発明は、薄膜トランジスタ及びその製造方法に関し、特に、ボトムゲート（逆スタガー）型の薄膜トランジスタ及びその製造方法に関するものである。 The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a bottom gate (inverse stagger) type thin film transistor and a manufacturing method thereof.
　薄膜トランジスタ（Thin Film Transistor　以下、ＴＦＴと省略する）は、アクティブマトリクス駆動方式の液晶表示パネルや有機ＥＬ（electroluminescence）表示パネルのスイッチング素子として、広く利用されている。 Thin film transistors (hereinafter referred to as TFTs) are widely used as switching elements for active matrix liquid crystal display panels and organic EL (electroluminescence) display panels.
　図１０は、一般的なボトムゲート型のＴＦＴ１０５の断面図である。 FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.
　ＴＦＴ１０５は、図１０に示すように、ガラス基板１１０上に設けられたゲート電極１１１と、ゲート電極１１１を覆うように設けられたゲート絶縁膜１１２と、ゲート絶縁膜１１２上でゲート電極１１１に対応する位置に島状に設けられた半導体層１１３と、半導体層１１３上で互いに離間するように設けられたソース電極１１４ａ及びドレイン電極１１４ｂとを備えている。ここで、半導体層１１３は、例えば、図１０に示すように、下層の真性アモルファスシリコン層１１３ａと、その上層のリンがドープされたｎ＋アモルファスシリコン層１１３ｂとを備え、ソース電極１１４ａ及びドレイン電極１１４ｂから露出する真性アモルファスシリコン層１１３ａがチャネル部Ｃを構成している。 As shown in FIG. 10, the TFT 105 corresponds to the gate electrode 111 provided on the glass substrate 110, the gate insulating film 112 provided so as to cover the gate electrode 111, and the gate electrode 111 on the gate insulating film 112. The semiconductor layer 113 provided in an island shape at a position where the source electrode 114a and the drain electrode 114b are provided so as to be separated from each other on the semiconductor layer 113. Here, for example, as shown in FIG. 10, the semiconductor layer 113 includes a lower intrinsic amorphous silicon layer 113a and an upper n + amorphous silicon layer 113b doped with phosphorus, and includes a source electrode 114a and a drain electrode. Intrinsic amorphous silicon layer 113a exposed from 114b constitutes channel portion C.
　このＴＦＴ１０５を製造する際には、ソース電極１１４ａ及びドレイン電極１１４ｂを形成した後に、ｎ＋アモルファスシリコン層１１３ｂを構成するｎ＋アモルファスシリコン膜をドライエッチングで除去するチャネルエッチングを行うことにより、チャネル部Ｃが形成される。ここで、ｎ＋アモルファスシリコン層１１３ｂを構成するｎ＋アモルファスシリコン膜と、真性アモルファスシリコン層１１３ａを構成する真性アモルファスシリコン膜とは、互いに似通った膜質を有しているので、上記チャネルエッチングにおいて、ｎ＋アモルファスシリコン膜と真性アモルファスシリコン膜との選択比を高くすることが困難である。また、近年、液晶表示パネルや有機ＥＬ表示パネルを構成する基板、すなわち、ＴＦＴを形成するための基板は、益々大型化しているので、例えば、１辺が１５００ｍｍ以上の大型のガラス基板上にＴＦＴを形成する場合には、ｎ＋アモルファスシリコン膜を基板上に成膜する際の膜厚のばらつき、及びそのｎ＋アモルファスシリコン膜の一部をドライエッチングで除去する際のエッチング量のばらつきにより、ｎ＋アモルファスシリコン層の膜厚のばらつきが基板面内で±２０％程度になってしまう。そのため、従来のＴＦＴの製造では、本来３００Å程度に薄く形成すればよい真性アモルファスシリコン膜を３０００Å近くまで厚く成膜する必要があるので、ＴＦＴの生産性を低下させるだけでなく、余分な真性アモルファスシリコン層が抵抗成分となることによりＴＦＴのオン特性も低下させるという問題があった。 In making the TFT105, after forming the source electrode 114a and drain electrode 114b, the n + amorphous silicon film constituting the n + amorphous silicon layer 113b by performing channel etching for removing by dry etching, the channel section C is formed. Here, since the n + amorphous silicon film constituting the n + amorphous silicon layer 113b and the intrinsic amorphous silicon film constituting the intrinsic amorphous silicon layer 113a have similar film qualities, in the channel etching, It is difficult to increase the selectivity between the n + amorphous silicon film and the intrinsic amorphous silicon film. Also, in recent years, substrates constituting liquid crystal display panels and organic EL display panels, that is, substrates for forming TFTs are becoming larger and larger. For example, a TFT is formed on a large glass substrate having a side of 1500 mm or more. When forming the n + amorphous silicon film on the substrate, the variation in the film thickness, and the variation in the etching amount when removing a part of the n + amorphous silicon film by dry etching, The variation of the film thickness of the n + amorphous silicon layer becomes about ± 20% within the substrate surface. Therefore, in the manufacture of the conventional TFT, it is necessary to form an intrinsic amorphous silicon film that should be formed as thin as about 300 mm, so that it can be as thick as nearly 3000 mm. There is a problem in that the on-characteristics of the TFT are also lowered due to the silicon layer becoming a resistance component.
　そこで、例えば、特許文献１には、ガラス基板上にゲート電極、ゲート絶縁膜、動作半導体層、ｎ型不純物半導体層、導電体層を形成し、導電体層とｎ型不純物半導体層とをエッチングして、ゲート電極上の動作半導体層の上層を露出させてソース電極及びドレイン電極を形成するＴＦＴを備えた液晶表示装置の製造方法において、導電体層とｎ型不純物半導体層とのエッチングの際に同時にエッチングされる残存層をガラス基板上に形成することが開示されている。そして、これによれば、チャネルエッチングの終点を確実に検出することにより、特性の安定したチャネルエッチ型ＴＦＴを有する液晶表示装置を製造できる、と記載されている。 Therefore, for example, in Patent Document 1, a gate electrode, a gate insulating film, an operating semiconductor layer, an n-type impurity semiconductor layer, and a conductor layer are formed on a glass substrate, and the conductor layer and the n-type impurity semiconductor layer are etched. Then, in the method of manufacturing a liquid crystal display device having a TFT in which the upper layer of the operating semiconductor layer on the gate electrode is exposed to form a source electrode and a drain electrode, the conductor layer and the n-type impurity semiconductor layer are etched. And forming a residual layer on the glass substrate that is etched simultaneously. According to this, it is described that a liquid crystal display device having a channel etch type TFT having stable characteristics can be manufactured by reliably detecting the end point of channel etching.
特開２００２－１５１６９４号公報JP 2002-151694 A
　ここで、特許文献１に開示された製造方法では、ダミーの残存膜が除去されると、ゲート絶縁膜が露出するので、ｎ型不純物半導体層（ｎ＋アモルファスシリコン膜）を残存層の膜厚分だけエッチングすることができるものの、チャネルエッチングの終点を時間で決めている方法と変わらないので、上述したように、ｎ＋アモルファスシリコン膜の成膜時及びドライエッチング時の基板面内における膜厚のばらつきを考慮すると、特性の安定したＴＦＴを確実に形成することは困難である。そのため、ＴＦＴの製造では、チャネルエッチングの絶対的な終点が決まらない根本の原因を解消するために、真性アモルファスシリコン膜及びｎ＋アモルファスシリコン膜のドライエッチング時の選択比、すなわち、半導体層を構成する第１シリコン層及び第２シリコン層のエッチング時の選択比を高くすることが要望されている。 Here, in the manufacturing method disclosed in Patent Document 1, since the gate insulating film is exposed when the dummy residual film is removed, the n-type impurity semiconductor layer (n + amorphous silicon film) is used as the film thickness of the residual layer. Although it can be etched by the amount of time, it is not different from the method of determining the end point of channel etching by time, so as described above, the film thickness in the substrate surface at the time of forming the n + amorphous silicon film and at the time of dry etching In view of the variation of the above, it is difficult to reliably form TFTs having stable characteristics. Therefore, in the manufacture of TFT, in order to eliminate the root cause that the absolute end point of channel etching is not determined, the selection ratio at the time of dry etching of the intrinsic amorphous silicon film and the n + amorphous silicon film, that is, the semiconductor layer is formed. Therefore, it is desired to increase the selectivity during etching of the first silicon layer and the second silicon layer.
　本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、半導体層を構成する第１シリコン層及び第２シリコン層のエッチング時の選択比を可及的に高くすることにある。 The present invention has been made in view of such a point, and an object of the present invention is to make the selectivity ratio of the first silicon layer and the second silicon layer constituting the semiconductor layer as high as possible. It is in.
　上記目的を達成するために、本発明は、第１シリコン層において、水素含有量が３アトミック％以下の低濃度領域を有するようにしたものである。 In order to achieve the above object, according to the present invention, the first silicon layer has a low concentration region having a hydrogen content of 3 atomic% or less.
　具体的に本発明に係る薄膜トランジスタは、基板に設けられたゲート電極と、上記ゲート電極を覆うように設けられたゲート絶縁膜と、上記ゲート絶縁膜上に設けられ上記ゲート電極に重なるようにチャネル部が配置された第１シリコン層を有する半導体層と、上記半導体層上に設けられ上記チャネル部が露出するように互いに離間して配置されたソース電極及びドレイン電極とを備え、上記半導体層が上記第１シリコン層と上記ソース電極及びドレイン電極との間に不純物がドープされた第２シリコン層を有する薄膜トランジスタであって、上記第１シリコン層は、水素含有量が３アトミック％以下の低濃度領域を有していることを特徴とする。 Specifically, a thin film transistor according to the present invention includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a channel provided on the gate insulating film so as to overlap the gate electrode. A semiconductor layer having a first silicon layer with a portion disposed thereon, and a source electrode and a drain electrode provided on the semiconductor layer and spaced apart from each other so that the channel portion is exposed, the semiconductor layer comprising: A thin film transistor having a second silicon layer doped with an impurity between the first silicon layer and the source and drain electrodes, wherein the first silicon layer has a low concentration of hydrogen content of 3 atomic% or less It has the area | region.
　上記の構成によれば、第１シリコン層の低濃度領域では、水素含有量が３アトミック％以下であるので、従来の薄膜トランジスタの第１シリコン層の水素含有量（例えば、１０アトミック％程度）よりも低くなっている。ここで、本発明者らは、以下の表１に示すように、例えば、ＣＶＤ法により成膜した真性アモルファスシリコン膜の水素含有量をレーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜よりも、水素ガスを主成分として用いたドライエッチングにおいてエッチング速度が極端に遅い（例えば、１／１８程度）という独自の知見を得た。そして、これによれば、例えば、レーザーアニールによって第１シリコン層の少なくとも一部（低濃度領域）の水素含有量を３アトミック％以下に抑えることにより、半導体層を構成する第１シリコン層及び第２シリコン層のエッチング時の選択比を可及的に高くすることが可能になる。 According to the above configuration, since the hydrogen content is 3 atomic% or less in the low concentration region of the first silicon layer, the hydrogen content (for example, about 10 atomic%) of the first silicon layer of the conventional thin film transistor. Is also low. Here, as shown in Table 1 below, the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n + amorphous silicon film formed by simply CVD. Obtained. According to this, for example, by suppressing the hydrogen content of at least a part (low concentration region) of the first silicon layer to 3 atomic% or less by laser annealing, the first silicon layer and the first silicon layer constituting the semiconductor layer are suppressed. It becomes possible to increase the selectivity during etching of the two silicon layers as much as possible.
Figure JPOXMLDOC01-appb-T000001
 　加えて、水素ガスを主成分として用いたドライエッチングの代わりに、過酸化水素水及びフッ素を含むエッチャントを用いて、それぞれの膜をウエットエッチングすることによって、以下の表２に示すように、レーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜のエッチング速度が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜のエッチング速度よりも遅いことも確認した。そのため、水素ガスを主成分として用いたドライエッチングと同様に選択比を高くすることが可能になるので、従来のように犠牲層として真性アモルファスシリコン膜を予め膜厚を厚くする必要がなく、生産タクトの短縮や材料コストの低減が可能になる、というメリットがある。
Figure JPOXMLDOC01-appb-T000001
 In addition, instead of dry etching using hydrogen gas as a main component, each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method. Therefore, it is possible to increase the selectivity as in dry etching using hydrogen gas as a main component, so that it is not necessary to increase the thickness of an intrinsic amorphous silicon film as a sacrificial layer in the conventional manner. There is an advantage that tact time can be shortened and material cost can be reduced.
Figure JPOXMLDOC01-appb-T000002
 　上記低濃度領域は、上記第１シリコン層の全体に配置されていてもよい。
Figure JPOXMLDOC01-appb-T000002
 The low concentration region may be disposed on the entire first silicon layer.
　上記の構成によれば、低濃度領域が第１シリコン層の全体に配置されているので、第２シリコン層及びチャネル部を形成するために、ソース電極及びドレイン電極から露出する第２シリコン層形成層がドライエッチングにより除去されても、その下層の第１シリコン層の除去が具体的に抑制される。 According to the above configuration, since the low concentration region is disposed on the entire first silicon layer, formation of the second silicon layer exposed from the source electrode and the drain electrode is formed in order to form the second silicon layer and the channel portion. Even if the layer is removed by dry etching, the removal of the first silicon layer below the layer is specifically suppressed.
　上記第１シリコン層の膜厚は、２００Å以上且つ８００Å以下であってもよい。 The film thickness of the first silicon layer may be 200 mm or more and 800 mm or less.
　上記の構成によれば、第１シリコン層の膜厚が２００Å以上且つ８００Å以下であるので、第１シリコン層が真性半導体層として機能させる適正な膜厚になり、薄膜トランジスタのオン特性及び生産性を向上させることが可能になる。 According to the above configuration, since the thickness of the first silicon layer is 200 mm or more and 800 mm or less, the first silicon layer has an appropriate film thickness to function as an intrinsic semiconductor layer. It becomes possible to improve.
　上記第１シリコン層は、上記チャネル部において、上記低濃度領域と、該低濃度領域の外側に上記ソース電極及びドレイン電極に対応して配置され該低濃度領域よりも水素含有量が高い高濃度領域とを有していてもよい。 The first silicon layer is disposed in the channel portion so as to correspond to the source electrode and the drain electrode on the outside of the low concentration region and the low concentration region, and has a higher hydrogen content than the low concentration region. And may have a region.
　上記の構成によれば、水素含有量が相対的に低い低濃度領域は、結晶性が相対的に高く、水素含有量が相対的に高い高濃度領域は、結晶性が相対的に低くなるので、高濃度領域が低濃度領域とソース電極及びドレイン電極との間の電界を緩和するための緩衝領域になり、薄膜トランジスタのオフ電流を低減させることが可能になる。 According to the above configuration, the low concentration region with a relatively low hydrogen content has a relatively high crystallinity, and the high concentration region with a relatively high hydrogen content has a relatively low crystallinity. The high-concentration region becomes a buffer region for relaxing the electric field between the low-concentration region and the source and drain electrodes, and the off-state current of the thin film transistor can be reduced.
　上記第１シリコン層は、結晶性を有していてもよい。 The first silicon layer may have crystallinity.
　上記の構成によれば、第１シリコン層が結晶性を有しているので、第１シリコン層の移動度が、例えば、１ｃｍ２／Ｖｓ～５００ｃｍ２／Ｖｓ程度に高くなり、第１シリコン層を含む半導体層により、液晶表示パネルや有機ＥＬ表示パネルの各画素に設けられるスイッチング素子だけでなく、ゲートドライバやソースドライバなどの高機能回路を構成することが可能になる。 According to the above configuration, since the first silicon layer has crystallinity, the mobility of the first silicon layer is increased to, for example, about 1 cm 2 / Vs to 500 cm 2 / Vs, and the first silicon layer In addition to the switching element provided in each pixel of the liquid crystal display panel or the organic EL display panel, a high-functional circuit such as a gate driver or a source driver can be configured.
　また、本発明に係る薄膜トランジスタの製造方法は、基板に設けられたゲート電極と、上記ゲート電極を覆うように設けられたゲート絶縁膜と、上記ゲート絶縁膜上に設けられ上記ゲート電極に重なるようにチャネル部が配置された第１シリコン層を有する半導体層と、上記半導体層上に設けられ上記チャネル部が露出するように互いに離間して配置されたソース電極及びドレイン電極とを備え、上記半導体層が上記第１シリコン層と上記ソース電極及びドレイン電極との間に不純物がドープされた第２シリコン層を有する薄膜トランジスタを製造する方法であって、上記第１シリコン層となる第１シリコン膜に水素含有量が３アトミック％以下の低濃度領域を形成する低濃度領域形成工程と、上記低濃度領域が形成された基板に対して、水素ガスを用いたドライエッチング、又は、過酸化水素及びフッ素を含むエッチャントを用いたウエットエッチングを行うことにより、上記半導体層となる半導体層形成層の一部を除去する半導体層形成エッチング工程とを備えることを特徴とする。 The thin film transistor manufacturing method according to the present invention includes a gate electrode provided on a substrate, a gate insulating film provided so as to cover the gate electrode, and a gate insulating film provided on the gate insulating film so as to overlap the gate electrode. A semiconductor layer having a first silicon layer in which a channel portion is disposed, and a source electrode and a drain electrode provided on the semiconductor layer and spaced apart from each other so that the channel portion is exposed. A method of manufacturing a thin film transistor having a second silicon layer doped with an impurity between the first silicon layer and the source electrode and the drain electrode, wherein the first silicon film to be the first silicon layer is formed A low concentration region forming step for forming a low concentration region having a hydrogen content of 3 atomic% or less, and a substrate on which the low concentration region is formed, A semiconductor layer forming etching step of removing a part of the semiconductor layer forming layer to be the semiconductor layer by performing dry etching using an elementary gas or wet etching using an etchant containing hydrogen peroxide and fluorine. It is characterized by providing.
　上記の方法によれば、低濃度領域形成工程において、第１シリコン層となる第１シリコン膜に水素含有量が３アトミック％以下の低濃度領域が形成されるので、その低濃度領域では、従来の薄膜トランジスタの第１シリコン層の水素含有量（例えば、１０アトミック％程度）よりも低くなっている。ここで、本発明者らは、以下の表１に示すように、例えば、ＣＶＤ法により成膜した真性アモルファスシリコン膜の水素含有量をレーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜よりも、水素ガスを主成分として用いたドライエッチングにおいてエッチング速度が極端に遅い（例えば、１／１８程度）という独自の知見を得た。そして、これによれば、低濃度領域形成工程において、例えば、レーザーアニールによって第１シリコン膜の少なくとも一部（低濃度領域）の水素含有量を３アトミック％以下に抑え、さらに、半導体層形成エッチング工程において、水素ガスを主成分として用いたドライエッチングを行うことにより、半導体層となる半導体層形成層の一部を除去する際に、第１シリコン膜の低濃度領域の除去が抑制されるので、半導体層を構成する第１シリコン層及び第２シリコン層のエッチング時の選択比を可及的に高くすることが可能になる。 According to the above method, in the low concentration region forming step, the low concentration region having a hydrogen content of 3 atomic% or less is formed in the first silicon film to be the first silicon layer. The hydrogen content (for example, about 10 atomic%) of the first silicon layer of the thin film transistor is lower. Here, as shown in Table 1 below, the present inventors, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The original knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, compared to an intrinsic amorphous silicon film or n + amorphous silicon film formed by simply CVD. Obtained. According to this, in the low concentration region forming step, for example, the hydrogen content of at least a part (low concentration region) of the first silicon film is suppressed to 3 atomic% or less by laser annealing, and further, semiconductor layer formation etching is performed. By performing dry etching using hydrogen gas as a main component in the process, removal of the low-concentration region of the first silicon film is suppressed when removing a part of the semiconductor layer forming layer that becomes the semiconductor layer. It becomes possible to make the selection ratio of the first silicon layer and the second silicon layer constituting the semiconductor layer as high as possible.
Figure JPOXMLDOC01-appb-T000003
 　加えて、水素ガスを主成分として用いたドライエッチングの代わりに、過酸化水素水及びフッ素を含むエッチャントを用いて、それぞれの膜をウエットエッチングすることによって、以下の表２に示すように、レーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜のエッチング速度が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜のエッチング速度よりも遅いことも確認した。そのため、水素ガスを主成分として用いたドライエッチングと同様に選択比を高くすることが可能になるので、従来のように犠牲層として真性アモルファスシリコン膜を事前に膜厚を厚くする必要がなく、生産タクトの短縮や材料コストの低減が可能になる、というメリットがある。
Figure JPOXMLDOC01-appb-T000003
 In addition, instead of dry etching using hydrogen gas as a main component, each film is wet etched using an etchant containing hydrogen peroxide and fluorine, as shown in Table 2 below. It was also confirmed that the etching rate of the intrinsic amorphous silicon film, which is 3 atomic% or less by annealing, is slower than the etching rate of the intrinsic amorphous silicon film or n + amorphous silicon film formed by the CVD method. Therefore, since it becomes possible to increase the selection ratio similarly to dry etching using hydrogen gas as a main component, it is not necessary to increase the thickness of the intrinsic amorphous silicon film as a sacrificial layer in advance as in the prior art, There is an advantage that production tact time can be shortened and material cost can be reduced.
Figure JPOXMLDOC01-appb-T000004
 　上記低濃度領域形成工程では、上記第１シリコン膜に対してレーザー光を照射することにより、上記低濃度領域を形成してもよい。
Figure JPOXMLDOC01-appb-T000004
 In the low concentration region forming step, the low concentration region may be formed by irradiating the first silicon film with laser light.
　上記の方法によれば、第１シリコン膜に対してレーザー光を照射することにより、低濃度領域が形成されるので、第１シリコン膜の低濃度領域の結晶性を高めることが可能になり、移動度が１ｃｍ２／Ｖｓ～５００ｃｍ２／Ｖｓ程度の高性能の薄膜トランジスタを製造することが可能になる。 According to the above method, since the low concentration region is formed by irradiating the first silicon film with the laser beam, the crystallinity of the low concentration region of the first silicon film can be improved. A high-performance thin film transistor having a mobility of about 1 cm 2 / Vs to 500 cm 2 / Vs can be manufactured.
　上記低濃度領域形成工程では、上記第１シリコン膜の少なくとも上記チャネル部となる領域に上記低濃度領域を形成し、上記低濃度領域が形成された第１シリコン膜上に上記第２シリコン層となる第２シリコン層形成層を形成した後に、上記ソース電極及びドレイン電極を形成するソースドレイン形成工程を有し、上記半導体層形成エッチング工程では、上記ソース電極及びドレイン電極から露出する上記第２シリコン層形成層を除去して、上記チャネル部を形成してもよい。 In the low-concentration region forming step, the low-concentration region is formed in at least a region to be the channel portion of the first silicon film, and the second silicon layer is formed on the first silicon film in which the low-concentration region is formed. A source / drain formation step of forming the source electrode and the drain electrode after forming the second silicon layer formation layer, and the second silicon exposed from the source electrode and the drain electrode in the semiconductor layer formation etching step. The channel portion may be formed by removing the layer forming layer.
　上記の方法によれば、低濃度領域形成工程において、第１シリコン膜の少なくともチャネル部となる領域に低濃度領域を形成し、ソースドレイン形成工程において、低濃度領域に第２シリコン層形成層を積層した後に、その上にソース電極及びドレイン電極を形成し、半導体層形成エッチング工程において、ソース電極及びドレイン電極から露出する第２シリコン層形成層を除去するので、チャネルエッチ型の薄膜トランジスタが具体的に製造される。 According to the above method, in the low concentration region forming step, the low concentration region is formed in at least the region to be the channel portion of the first silicon film, and in the source / drain forming step, the second silicon layer forming layer is formed in the low concentration region. After stacking, a source electrode and a drain electrode are formed thereon, and the second silicon layer formation layer exposed from the source electrode and the drain electrode is removed in the semiconductor layer formation etching step. To be manufactured.
　上記低濃度領域形成工程では、上記ソース電極及びドレイン電極から露出する上記第１シリコン層となる第１シリコン層形成層に上記低濃度領域を形成し、上記半導体層形成エッチング工程では、上記低濃度領域の外側に配置する上記第１シリコン層形成層の一部を除去することにより、上記チャネル部に上記ソース電極及びドレイン電極に対応して配置され上記低濃度領域よりも水素含有量が高い高濃度領域を形成してもよい。 In the low concentration region forming step, the low concentration region is formed in the first silicon layer forming layer that is the first silicon layer exposed from the source electrode and the drain electrode, and in the semiconductor layer forming etching step, the low concentration region is formed. By removing a part of the first silicon layer forming layer disposed outside the region, the channel portion is disposed corresponding to the source electrode and the drain electrode and has a higher hydrogen content than the low concentration region. A concentration region may be formed.
　上記の方法によれば、低濃度領域形成工程において、ソース電極及びドレイン電極から露出する第１シリコン層形成層に低濃度領域を形成し、半導体層形成エッチング工程において、低濃度領域の外側に配置する第１シリコン層形成層の一部を除去して、チャネル部に高濃度領域を形成することになる。ここで、水素含有量が相対的に低い低濃度領域は、結晶性が相対的に高く、水素含有量が相対的に高い高濃度領域は、結晶性が相対的に低くなるので、高濃度領域が低濃度領域とソース電極及びドレイン電極との間の電界を緩和するための緩衝領域になり、オフ電流を低減させた薄膜トランジスタが具体的に製造される。 According to the above method, the low concentration region is formed in the first silicon layer forming layer exposed from the source electrode and the drain electrode in the low concentration region forming step, and is disposed outside the low concentration region in the semiconductor layer forming etching step. A part of the first silicon layer forming layer to be removed is removed to form a high concentration region in the channel portion. Here, the low concentration region having a relatively low hydrogen content has a relatively high crystallinity, and the high concentration region having a relatively high hydrogen content has a relatively low crystallinity. Becomes a buffer region for relaxing the electric field between the low concentration region and the source and drain electrodes, and a thin film transistor with reduced off-current is specifically manufactured.
　上記レーザー光の波長は、２４８ｎｍ以上且つ３５５ｎｍ以下であってもよい。 The wavelength of the laser beam may be 248 nm or more and 355 nm or less.
　上記の方法によれば、第１シリコン膜に対して照射するレーザー光の波長が２４８ｎｍ以上且つ３５５ｎｍ以下であるので、第１シリコン膜が薄く形成されても、第１シリコン膜におけるレーザー光の透過が抑制され、ゲート電極やゲート絶縁膜を損傷させることなく、高性能の薄膜トランジスタを製造することが可能になる。 According to the above method, since the wavelength of the laser beam applied to the first silicon film is not less than 248 nm and not more than 355 nm, even if the first silicon film is formed thin, the laser beam is transmitted through the first silicon film. Is suppressed, and a high-performance thin film transistor can be manufactured without damaging the gate electrode and the gate insulating film.
　上記基板は、短辺が１５００ｍｍ以上の矩形状のガラス基板であってもよい。 The substrate may be a rectangular glass substrate having a short side of 1500 mm or more.
　上記の方法によれば、基板が大型のガラス基板であるので、本発明の作用効果が有効に奏される。 According to the above method, since the substrate is a large glass substrate, the effects of the present invention are effectively exhibited.
　本発明によれば、第１シリコン層において、水素含有量が３アトミック％以下の低濃度領域を有しているので、半導体層を構成する第１シリコン層及び第２シリコン層のエッチングの選択比を可及的に高くすることができる。 According to the present invention, since the first silicon layer has a low concentration region with a hydrogen content of 3 atomic% or less, the etching selectivity of the first silicon layer and the second silicon layer constituting the semiconductor layer Can be made as high as possible.
図１は、実施形態１に係るＴＦＴ５ａの断面図である。FIG. 1 is a cross-sectional view of a TFT 5a according to the first embodiment. 図２は、ＴＦＴ５ａを製造するためのフローチャートである。FIG. 2 is a flowchart for manufacturing the TFT 5a. 図３は、実施形態１に係る低濃度領域形成工程における基板の断面図である。FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step according to the first embodiment. 図４は、実施形態１に係る水素ガスエッチング工程における基板の断面図である。FIG. 4 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the first embodiment. 図５は、実施形態２に係るＴＦＴ５ｂの断面図である。FIG. 5 is a cross-sectional view of the TFT 5b according to the second embodiment. 図６は、ＴＦＴ５ｂを製造するためのフローチャートである。FIG. 6 is a flowchart for manufacturing the TFT 5b. 図７は、実施形態２に係るＴＦＴパターン形成工程後の基板の断面図である。FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process according to the second embodiment. 図８は、実施形態２に係る低濃度領域形成工程における基板の断面図である。FIG. 8 is a cross-sectional view of the substrate in the low concentration region forming step according to the second embodiment. 図９は、実施形態２に係る水素ガスエッチング工程における基板の断面図である。FIG. 9 is a cross-sectional view of the substrate in the hydrogen gas etching process according to the second embodiment. 図１０は、一般的なボトムゲート型のＴＦＴ１０５の断面図である。FIG. 10 is a cross-sectional view of a general bottom gate type TFT 105.
　以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、本発明は、以下の各実施形態に限定されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.
　《発明の実施形態１》
　図１～図４は、本発明に係る薄膜トランジスタ（ＴＦＴ）及びその製造方法の実施形態１を示している。具体的に、図１は、本実施形態のＴＦＴ５ａの断面図である。 Embodiment 1 of the Invention
1 to 4 show a first embodiment of a thin film transistor (TFT) and a method for manufacturing the same according to the present invention. Specifically, FIG. 1 is a cross-sectional view of the TFT 5a of this embodiment.
　ＴＦＴ５ａは、図１に示すように、絶縁基板１０上に設けられたゲート電極１１と、ゲート電極１１を覆うように設けられたゲート絶縁膜１２と、ゲート絶縁膜１２上でゲート電極１１に対応する位置に島状に設けられた半導体層１３と、半導体層１３上で互いに離間するように設けられたソース電極１４ａ及びドレイン電極１４ｂとを備えている。 As shown in FIG. 1, the TFT 5 a corresponds to the gate electrode 11 provided on the insulating substrate 10, the gate insulating film 12 provided so as to cover the gate electrode 11, and the gate electrode 11 on the gate insulating film 12. The semiconductor layer 13 is provided in an island shape at a position where the source electrode 14 a and the drain electrode 14 b are provided so as to be separated from each other on the semiconductor layer 13.
　半導体層１３は、図１に示すように、第１シリコン層として設けられた下層の真性アモルファスシリコン層１３ａと、第２シリコン層として設けられた上層のリンがドープされたｎ＋アモルファスシリコン層１３ｂとを備え、ソース電極１４ａ及びドレイン電極１４ｂから露出する真性アモルファスシリコン層１３ａがチャネル部Ｃを構成している。 As shown in FIG. 1, the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13a provided as a first silicon layer and an upper phosphorus-doped n + amorphous silicon layer 13b provided as a second silicon layer. The intrinsic amorphous silicon layer 13a exposed from the source electrode 14a and the drain electrode 14b constitutes the channel portion C.
　真性アモルファスシリコン層１３ａの全体は、水素含有量が３アトミック％以下の低濃度領域Ｒａになっている。 The entire intrinsic amorphous silicon layer 13a is a low concentration region Ra having a hydrogen content of 3 atomic% or less.
　上記構成のＴＦＴ５ａは、例えば、複数の画素電極がマトリクス状に配置されたアクティブマトリクス基板の各画素電極に接続されたスイッチング素子として設けられ、そのアクティブマトリクス基板と、それに対向して配置される対向基板と、それらの両基板の間に封入される液晶層と共に、液晶表示パネルを構成するものである。 The TFT 5a having the above-described configuration is provided as a switching element connected to each pixel electrode of an active matrix substrate in which a plurality of pixel electrodes are arranged in a matrix, for example, and the active matrix substrate is opposed to the opposing one. A liquid crystal display panel is constituted with a substrate and a liquid crystal layer sealed between the two substrates.
　次に、本実施形態のＴＦＴ５ａの製造方法について、図２～図４を用いて説明する。 Next, a manufacturing method of the TFT 5a of this embodiment will be described with reference to FIGS.
　本実施形態のＴＦＴ５ａの製造方法は、図２のフローチャートに示すように、ゲート電極形成工程、ＧＩ／ｉ－Ｓｉ層形成工程、低濃度領域形成工程、ｎ＋－Ｓｉ膜成膜工程、ｎ＋－Ｓｉ層形成工程、ソースドレイン形成工程、半導体層形成エッチング工程及びレジスト剥離工程を備える。ここで、図３は、本実施形態の低濃度領域形成工程における基板の断面図であり、図４は、本実施形態の半導体層形成エッチング工程における基板の断面図である。 As shown in the flowchart of FIG. 2, the manufacturing method of the TFT 5a of this embodiment includes a gate electrode formation step, a GI / i-Si layer formation step, a low concentration region formation step, an n + -Si film formation step, an n + A Si layer forming step, a source / drain forming step, a semiconductor layer forming etching step, and a resist stripping step; Here, FIG. 3 is a cross-sectional view of the substrate in the low concentration region forming step of the present embodiment, and FIG. 4 is a cross-sectional view of the substrate in the semiconductor layer forming etching step of the present embodiment.
　＜ゲート電極形成工程（Ｓｔ１１）＞
　まず、ガラス基板（例えば、０．７ｍｍ×１５００ｍｍ×１８００ｍｍ）などの絶縁基板１０の基板全体に、スパッタリング法により、例えば、アルミニウム膜、銅膜やチタン膜などの第１の金属膜を厚さ３０００Å程度で成膜する。 <Gate electrode formation step (St11)>
First, a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate (for example, 0.7 mm × 1500 mm × 1800 mm) by a sputtering method to a thickness of 3000 mm. Film is formed to the extent.
　続いて、上記第１の金属膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第１のレジストパターンを形成する。 Subsequently, a photosensitive resin film is applied to the entire substrate on which the first metal film has been formed by spin coating, and then patterned to form a first resist pattern.
　さらに、上記第１のレジストパターンから露出する第１の金属膜をドライエッチングにより除去した後に、その第１のレジストパターンを剥離させることにより、ゲート電極１１を形成する。 Further, after removing the first metal film exposed from the first resist pattern by dry etching, the first resist pattern is peeled off to form the gate electrode 11.
　＜ＧＩ／ｉ－Ｓｉ層形成工程（Ｓｔ１２）＞
　まず、上記ゲート電極形成工程でゲート電極１１が形成された基板全体に、ＣＶＤ（Chemical Vapor Deposition）法により窒化シリコン膜や酸化シリコン膜などを厚さ４０００Å程度で成膜することにより、ゲート絶縁膜１２を形成する。 <GI / i-Si layer forming step (St12)>
First, a gate insulating film is formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm on the entire substrate on which the gate electrode 11 has been formed in the gate electrode formation step by a CVD (Chemical Vapor Deposition) method. 12 is formed.
　続いて、ゲート絶縁膜１２が形成された基板全体に、ＣＶＤ法により第１シリコン膜として真性アモルファスシリコン膜を厚さ２００Å～８００Å程度で成膜する。ここで、通常、ＣＶＤ法で成膜された真性アモルファスシリコン膜は、反応室内にシランガスや水素ガスを導入して成膜されるので、その水素含有量が１０アトミック％以上になっている。 Subsequently, an intrinsic amorphous silicon film is formed as a first silicon film with a thickness of about 200 to 800 mm on the entire substrate on which the gate insulating film 12 is formed by a CVD method. Here, since the intrinsic amorphous silicon film formed by the CVD method is generally formed by introducing silane gas or hydrogen gas into the reaction chamber, the hydrogen content is 10 atomic% or more.
　そして、上記真性アモルファスシリコン膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第２のレジストパターンを形成する。 Then, a second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film has been formed by spin coating, followed by patterning.
　さらに、上記第２のレジストパターンから露出する真性アモルファスシリコン膜をドライエッチングにより除去した後に、その第２のレジストパターンを剥離させることにより、真性アモルファスシリコン層（１３ａ）を形成する。 Further, after removing the intrinsic amorphous silicon film exposed from the second resist pattern by dry etching, the second resist pattern is peeled off to form an intrinsic amorphous silicon layer (13a).
　＜低濃度領域形成工程（Ｓｔ１３）＞
　上記ＧＩ／ｉ－Ｓｉ層形成工程で形成された真性アモルファスシリコン層（１３ａ）に対し、図３に示すように、波長２４８ｎｍ以上且つ３５５ｎｍ以下のレーザー光Ｌ（例えば、波長３０８ｎｍのエキシマレーザー光）を照射することにより、アモルファスシリコンをレーザーアニールによって結晶化させると共に、水素含有量を３アトミック％以下にして、低濃度領域Ｒａを形成する。ここで、本実施形態では、低濃度領域Ｒａを形成する方法として、レーザーアニールを例示したが、ランプアニールやオーブンアニールなどでもよく、また、例えば、Ｈ２ガス流量／ＳｉＨ４ガス流量の比を２０以上に高めて成膜し水素含有量が低くなるようにＣＶＤ条件を設定してもよい。 <Low concentration region forming step (St13)>
As shown in FIG. 3, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer (13a) formed in the GI / i-Si layer forming process. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra. Here, in this embodiment, laser annealing is exemplified as a method for forming the low concentration region Ra, but lamp annealing, oven annealing, or the like may be used. For example, the ratio of H 2 gas flow rate / SiH 4 gas flow rate may be set. The CVD conditions may be set so that the film is formed at a temperature of 20 or more and the hydrogen content is lowered.
　＜ｎ＋－Ｓｉ膜成膜工程（Ｓｔ１４）＞
　上記低濃度領域形成工程で低濃度領域Ｒａが形成された基板全体に、ＣＶＤ法により第２シリコン膜としてリンがドープされたｎ＋アモルファスシリコン膜を厚さ５００Å程度で成膜する。ここで、ｎ＋アモルファスシリコン膜は、上述した真性アモルファスシリコン膜と同様に、水素ガスを導入して成膜されるので、その水素含有量が１０アトミック％以上になっている。 <N + -Si film formation step (St14)>
An n + amorphous silicon film doped with phosphorus as a second silicon film is formed to a thickness of about 500 mm on the entire substrate on which the low concentration region Ra has been formed in the low concentration region forming step by the CVD method. Here, since the n + amorphous silicon film is formed by introducing hydrogen gas as in the case of the intrinsic amorphous silicon film described above, the hydrogen content is 10 atomic% or more.
　＜ｎ＋－Ｓｉ層形成工程（Ｓｔ１５）＞
　まず、上記ｎ＋－Ｓｉ膜成膜工程でｎ＋アモルファスシリコン膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第３のレジストパターンを形成する。 <N + -Si layer forming step (St15)>
First, a third resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the n + amorphous silicon film has been formed in the n + -Si film forming process by spin coating, followed by patterning. Form.
　続いて、上記第３のレジストパターンから露出するｎ＋アモルファスシリコン膜をドライエッチングにより除去した後に、その第３のレジストパターンを剥離させることにより、第２シリコン層形成層（半導体層形成層）として、ｎ＋アモルファスシリコン層形成層１３ｂａを形成する（図４参照）。ここで、ｎ＋アモルファスシリコン膜は、六フッ化硫黄ガスや四フッ化炭素ガスなどのフッ素系ガスと、塩化水素ガスや塩素ガスなどの塩素系ガスとを用いた反応性ドライエッチングによって、容易に除去することができる（表１参照）。 Subsequently, after removing the n + amorphous silicon film exposed from the third resist pattern by dry etching, the third resist pattern is peeled off to form a second silicon layer forming layer (semiconductor layer forming layer). , N + amorphous silicon layer forming layer 13ba is formed (see FIG. 4). Here, the n + amorphous silicon film can be easily formed by reactive dry etching using a fluorine-based gas such as sulfur hexafluoride gas or carbon tetrafluoride gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas. (See Table 1).
　＜ソースドレイン形成工程（Ｓｔ１６）＞
　まず、上記ｎ＋－Ｓｉ層形成工程でｎ＋アモルファスシリコン層形成層１３ｂａが形成された基板全体に、アルミニウム膜、銅膜やチタン膜などの第２の金属膜を厚さ３０００Å程度でスパッタリング法により成膜する。 <Source / Drain Formation Step (St16)>
First, a second metal film such as an aluminum film, a copper film, or a titanium film is sputtered to a thickness of about 3000 mm on the entire substrate on which the n + amorphous silicon layer forming layer 13ba has been formed in the n + -Si layer forming step. The film is formed by
　続いて、上記第２の金属膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第４のレジストパターンを形成する。 Subsequently, a photosensitive resin film is applied to the entire substrate on which the second metal film has been formed by spin coating, and then patterned to form a fourth resist pattern.
　さらに、上記第４のレジストパターンから露出する第２の金属膜をドライエッチングにより除去することにより、ソース電極１４ａ及びドレイン電極１４ｂを形成する（図４参照）。 Further, the second metal film exposed from the fourth resist pattern is removed by dry etching to form the source electrode 14a and the drain electrode 14b (see FIG. 4).
　＜半導体層形成エッチング工程（Ｓｔ１７）＞
　上記ソースドレイン形成工程で形成されたソース電極１４ａ及びドレイン電極１４ｂから露出するｎ＋アモルファスシリコン層形成層１３ｂａを、図４に示すように、水素ガスを主成分として用いた反応性イオンエッチングやプラズマエッチングなどのドライエッチングで発生する水素ラジカルや水素イオンによって、除去することにより、ｎ＋アモルファスシリコン層１３ｂを形成する。ここで、水素ガスによるドライエッチングにおいて、水素含有量が３アトミック％以下の真性アモルファスシリコン層１３ａは、水素含有量が少ないために、発生した水素ラジカルや水素イオンによって、ほとんど除去されないものの、水素含有量が１０アトミック％以上のｎ＋アモルファスシリコン層形成層１３ｂａでは、発生した水素ラジカルや水素イオンによって、容易に除去されるので、真性アモルファスシリコン層１３ａ及びｎ＋アモルファスシリコン層形成層１３ｂａの間で高い選択性を実現することができる。 <Semiconductor layer formation etching step (St17)>
As shown in FIG. 4, the n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is subjected to reactive ion etching or plasma using hydrogen gas as a main component. By removing with hydrogen radicals or hydrogen ions generated by dry etching such as etching, the n + amorphous silicon layer 13b is formed. Here, in the dry etching using hydrogen gas, the intrinsic amorphous silicon layer 13a having a hydrogen content of 3 atomic% or less is hardly removed by the generated hydrogen radicals or hydrogen ions because the hydrogen content is small. In the n + amorphous silicon layer forming layer 13ba whose amount is 10 atomic% or more, it is easily removed by the generated hydrogen radicals or hydrogen ions, and therefore between the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer forming layer 13ba. High selectivity can be realized.
　また、上記水素ガスによるドライエッチングの代わりに、上記ソースドレイン形成工程で形成されたソース電極１４ａ及びドレイン電極１４ｂから露出するｎ＋アモルファスシリコン層形成層１３ｂａを、図４に示すように、過酸化水素及びフッ素を含み、フッ素化合物を主成分として用いたエッチャントによって、ウエットエッチングしてもよい。ここで、フッ素化合物は、シリコンをエッチングすることが知られているが、水素含有量の多いｎ＋アモルファスシリコン層は、水素含有量の少ない真性アモルファスシリコン層１３ａに比べてエッチング速度が速くなるために、真性アモルファスシリコン層１３ａの膜厚を厚くする必要がない。さらに、フッ素化合物は、チタンメタルをエッチングすることができるため、ソースドレインメタルに単層もしくは複層配線にチタン膜を用いた場合には、ソースドレイン形成工程（Ｓｔ１６）も同時に処理できるため、工程を削減することができる、というメリットがある。 Further, instead of the dry etching with hydrogen gas, the n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b formed in the source / drain formation step is oxidized as shown in FIG. Wet etching may be performed with an etchant containing hydrogen and fluorine and using a fluorine compound as a main component. Here, the fluorine compound is known to etch silicon, but the n + amorphous silicon layer having a high hydrogen content has a higher etching rate than the intrinsic amorphous silicon layer 13a having a low hydrogen content. In addition, it is not necessary to increase the thickness of the intrinsic amorphous silicon layer 13a. Further, since the fluorine compound can etch titanium metal, the source / drain formation step (St16) can be performed at the same time when a single layer or a multilayer wiring is used for the source / drain metal. There is an advantage that can be reduced.
　＜レジスト剥離工程（Ｓｔ１８）＞
　上記半導体層形成エッチング工程でｎ＋アモルファスシリコン層１３ｂが形成された基板から第４のレジストパターンを剥離させる。 <Resist stripping step (St18)>
The fourth resist pattern is peeled off from the substrate on which the n + amorphous silicon layer 13b is formed in the semiconductor layer formation etching step.
　以上のようにして、本実施形態のＴＦＴ５ａを製造することができる。 As described above, the TFT 5a of this embodiment can be manufactured.
　以上説明したように、本実施形態のＴＦＴ５ａ及びその製造方法によれば、低濃度領域形成工程において、真性アモルファスシリコン層１３ａに水素含有量が３アトミック％以下の低濃度領域Ｒａが形成されるので、その低濃度領域Ｒａでは、従来のＴＦＴ１０５（図１０参照）の真性アモルファスシリコン層１１３ａの水素含有量（例えば、１０アトミック％程度）よりも低くなっている。ここで、本発明者らは、上述した表１に示すように、例えば、ＣＶＤ法により成膜した真性アモルファスシリコン膜の水素含有量をレーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜よりも、水素ガスを主成分として用いたドライエッチングにおいてエッチング速度が極端に遅い（例えば、１／１８程度）、また、上述した表２に示すように、例えば、ＣＶＤ法により成膜した真性アモルファスシリコン膜の水素含有量をレーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜よりも、過酸化水素及びフッ素を含むエッチャントを用いたウエットエッチングにおいてエッチング速度が遅いという独自の知見を得た。そして、これによれば、低濃度領域形成工程において、レーザーアニールによって真性アモルファスシリコン層１３ａ（低濃度領域Ｒａ）の水素含有量を３アトミック％以下に抑え、さらに、半導体層形成エッチング工程において、水素ガスを用いたドライエッチング又は過酸化水素及びフッ素を含むエッチャントを用いたウエットエッチングを行うことにより、ソース電極１４ａ及びドレイン電極１４ｂから露出するｎ＋アモルファスシリコン層形成層１３ｂａを除去する際に、真性アモルファスシリコン層１３ａ（低濃度領域Ｒａ）の除去が抑制されるので、半導体層１３を構成する真性アモルファスシリコン層１３ａ及びｎ＋アモルファスシリコン層１３ｂ（ｎ＋アモルファスシリコン層形成層１３ｂａ）のエッチング時の選択比を可及的に高くすることができる。 As described above, according to the TFT 5a of this embodiment and the manufacturing method thereof, the low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer 13a in the low concentration region forming step. In the low concentration region Ra, the hydrogen content (for example, about 10 atomic%) of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower. Here, as shown in Table 1 above, the inventors of the present invention, for example, an intrinsic amorphous silicon film in which the hydrogen content of an intrinsic amorphous silicon film formed by a CVD method is 3 atomic% or less by laser annealing, The etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component, as compared with an intrinsic amorphous silicon film or an n + amorphous silicon film formed simply by a CVD method. As shown in Table 2, for example, an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method. than or n + amorphous silicon film, peroxide And etch rate in wet etching to obtain a unique finding that slow using an etchant containing fluorine. According to this, in the low concentration region formation step, the hydrogen content of the intrinsic amorphous silicon layer 13a (low concentration region Ra) is suppressed to 3 atomic% or less by laser annealing, and in the semiconductor layer formation etching step, When the n + amorphous silicon layer forming layer 13ba exposed from the source electrode 14a and the drain electrode 14b is removed by performing dry etching using a gas or wet etching using an etchant containing hydrogen peroxide and fluorine, an intrinsic property is obtained. Since removal of the amorphous silicon layer 13a (low concentration region Ra) is suppressed, the intrinsic amorphous silicon layer 13a and the n + amorphous silicon layer 13b (n + amorphous silicon layer forming layer 13ba) constituting the semiconductor layer 13 are etched. Selectivity It can be increased retroactively.
　また、本実施形態のＴＦＴ５ａによれば、真性アモルファスシリコン層１３ａの膜厚が２００Å以上且つ８００Å以下であるので、真性アモルファスシリコン層１３ａが真性半導体層として機能させる適正な膜厚になり、ＴＦＴのオン特性及び生産性を向上させることができる。 Further, according to the TFT 5a of the present embodiment, since the film thickness of the intrinsic amorphous silicon layer 13a is not less than 200 mm and not more than 800 mm, the intrinsic amorphous silicon layer 13a has an appropriate film thickness to function as an intrinsic semiconductor layer. ON characteristics and productivity can be improved.
　また、本実施形態のＴＦＴ５ａによれば、真性アモルファスシリコン層１３ａが結晶性を有しているので、真性アモルファスシリコン層１３ａの移動度が、例えば、１ｃｍ２／Ｖｓ～１００ｃｍ２／Ｖｓ程度に高くなり、真性アモルファスシリコン層１３ａを含む半導体層１３により、液晶表示パネルや有機ＥＬ表示パネルの各画素に設けられるＴＦＴだけでなく、ゲートドライバやソースドライバなどの高機能回路を構成することができる。 Further, according to the TFT5a of this embodiment, since the intrinsic amorphous silicon layer 13a has crystallinity, the mobility of the intrinsic amorphous silicon layer 13a is, for example, as high as 1cm 2 / Vs ~ 100cm 2 / Vs Thus, the semiconductor layer 13 including the intrinsic amorphous silicon layer 13a can constitute not only a TFT provided in each pixel of a liquid crystal display panel or an organic EL display panel, but also a high function circuit such as a gate driver or a source driver.
　また、本実施形態のＴＦＴ５ａの製造方法によれば、真性アモルファスシリコン層１３ａに対して照射するレーザー光Ｌの波長が２４８ｎｍ以上且つ３５５ｎｍ以下であるので、真性アモルファスシリコン層１３ａが薄く形成されても、真性アモルファスシリコン層１３ａにおけるレーザー光Ｌの透過が抑制され、ゲート電極１１やゲート絶縁膜１２を損傷させることなく、高性能のＴＦＴを製造することができる。 In addition, according to the manufacturing method of the TFT 5a of the present embodiment, the wavelength of the laser light L applied to the intrinsic amorphous silicon layer 13a is not less than 248 nm and not more than 355 nm. Therefore, even if the intrinsic amorphous silicon layer 13a is formed thin. The transmission of the laser light L in the intrinsic amorphous silicon layer 13a is suppressed, and a high-performance TFT can be manufactured without damaging the gate electrode 11 and the gate insulating film 12.
　《発明の実施形態２》
　図５は、本実施形態２のＴＦＴ５ｂの断面図である。なお、以下の実施形態において、図１～図４と同じ部分については同じ符号を付して、その詳細な説明を省略する。 << Embodiment 2 of the Invention >>
FIG. 5 is a cross-sectional view of the TFT 5b of the second embodiment. In the following embodiments, the same parts as those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
　ＴＦＴ５ｂは、上記実施形態１のＴＦＴ５ａと同様に、図５に示すように、絶縁基板１０上に設けられたゲート電極１１と、ゲート電極１１を覆うように設けられたゲート絶縁膜１２と、ゲート絶縁膜１２上でゲート電極１１に対応する位置に島状に設けられた半導体層１３と、半導体層１３上で互いに離間するように設けられたソース電極１４ｃ及びドレイン電極１４ｄとを備えている。 Like the TFT 5a of the first embodiment, the TFT 5b includes a gate electrode 11 provided on the insulating substrate 10, a gate insulating film 12 provided so as to cover the gate electrode 11, and a gate, as shown in FIG. A semiconductor layer 13 provided in an island shape at a position corresponding to the gate electrode 11 on the insulating film 12, and a source electrode 14 c and a drain electrode 14 d provided on the semiconductor layer 13 so as to be separated from each other are provided.
　半導体層１３は、図５に示すように、第１シリコン層として設けられた下層の真性アモルファスシリコン層１３ｃと、第２シリコン層として設けられた上層のリンがドープされたｎ＋アモルファスシリコン層１３ｄとを備え、ソース電極１４ｃ及びドレイン電極１４ｄ並びにｎ＋アモルファスシリコン層１３ｄから露出する真性アモルファスシリコン層１３ｃがチャネル部Ｃを構成している。 As shown in FIG. 5, the semiconductor layer 13 includes a lower intrinsic amorphous silicon layer 13c provided as a first silicon layer, and an upper phosphorus + doped n + amorphous silicon layer 13d provided as a second silicon layer. The intrinsic amorphous silicon layer 13c exposed from the source electrode 14c, the drain electrode 14d, and the n + amorphous silicon layer 13d constitutes the channel portion C.
　真性アモルファスシリコン層１３ｃのチャネル部Ｃは、水素含有量が３アトミック％以下の低濃度領域Ｒａと、低濃度領域Ｒａの外側にソース電極１４ｃ及びドレイン電極１４ｄに対応して配置され、水素含有量が１０アトミック％程度の高濃度領域Ｒｂとを有している。 The channel portion C of the intrinsic amorphous silicon layer 13c is disposed corresponding to the source electrode 14c and the drain electrode 14d on the outer side of the low concentration region Ra having a hydrogen content of 3 atomic% or less and the low hydrogen concentration. Has a high concentration region Rb of about 10 atomic%.
　次に、本実施形態のＴＦＴ５ｂの製造方法について、図６～図９を用いて説明する。 Next, a manufacturing method of the TFT 5b of this embodiment will be described with reference to FIGS.
　本実施形態のＴＦＴ５ｂの製造方法は、図６のフローチャートに示すように、ＴＦＴパターン形成工程、低濃度領域形成工程及び水素ガスエッチング工程（半導体層形成エッチング工程）を備える。ここで、図７は、本実施形態のＴＦＴパターン形成工程後の基板の断面図であり、図８は、本実施形態の低濃度領域形成工程における基板の断面図であり、図９は、本実施形態の水素ガスエッチング工程における基板の断面図である。 The manufacturing method of the TFT 5b of this embodiment includes a TFT pattern forming step, a low concentration region forming step, and a hydrogen gas etching step (semiconductor layer forming etching step) as shown in the flowchart of FIG. Here, FIG. 7 is a cross-sectional view of the substrate after the TFT pattern forming process of the present embodiment, FIG. 8 is a cross-sectional view of the substrate in the low-concentration region forming process of the present embodiment, and FIG. It is sectional drawing of the board | substrate in the hydrogen gas etching process of embodiment.
　＜ＴＦＴパターン形成工程（Ｓｔ２１）＞
　まず、ガラス基板などの絶縁基板１０の基板全体に、スパッタリング法により、例えば、アルミニウム膜、銅膜やチタン膜などの第１の金属膜を厚さ３０００Å程度で成膜する。 <TFT pattern forming step (St21)>
First, for example, a first metal film such as an aluminum film, a copper film, or a titanium film is formed on the entire substrate of the insulating substrate 10 such as a glass substrate with a thickness of about 3000 mm by a sputtering method.
　続いて、上記第１の金属膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第１のレジストパターンを形成する。 Subsequently, a photosensitive resin film is applied to the entire substrate on which the first metal film has been formed by spin coating, and then patterned to form a first resist pattern.
　さらに、上記第１のレジストパターンから露出する第１の金属膜をドライエッチングにより除去した後に、その第１のレジストパターンを剥離させることにより、ゲート電極１１を形成する。 Further, after removing the first metal film exposed from the first resist pattern by dry etching, the first resist pattern is peeled off to form the gate electrode 11.
　その後、ゲート電極１１が形成された基板全体に、ＣＶＤ（Chemical Vapor Deposition）法により窒化シリコン膜や酸化シリコン膜などを厚さ４０００Å程度で成膜することにより、ゲート絶縁膜１２を形成する。 Thereafter, a gate insulating film 12 is formed on the entire substrate on which the gate electrode 11 has been formed by forming a silicon nitride film, a silicon oxide film, or the like with a thickness of about 4000 mm by a CVD (Chemical Vapor Deposition) method.
　続いて、ゲート絶縁膜１２が形成された基板全体に、ＣＶＤ法により、第１シリコン膜として真性アモルファスシリコン膜を厚さ２０００Å程度で成膜した後に、第２シリコン膜としてリンがドープされたｎ＋アモルファスシリコン膜を厚さ５００Å程度で成膜する。 Subsequently, an intrinsic amorphous silicon film having a thickness of about 2000 mm is formed as a first silicon film on the entire substrate on which the gate insulating film 12 is formed by CVD, and then phosphorus is doped as the second silicon film. + Amorphous silicon film is formed with a thickness of about 500 mm.
　そして、上記真性アモルファスシリコン膜及びｎ＋アモルファスシリコン膜が順に成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第２のレジストパターンを形成する。 A second resist pattern is formed by applying a photosensitive resin film to the entire substrate on which the intrinsic amorphous silicon film and the n + amorphous silicon film are sequentially formed by spin coating, followed by patterning.
　さらに、上記第２のレジストパターンから露出する真性アモルファスシリコン膜及びｎ＋アモルファスシリコン膜をドライエッチングにより除去した後に、その第２のレジストパターンを剥離させることにより、半導体層形成層を形成する。 Further, after removing the intrinsic amorphous silicon film and the n + amorphous silicon film exposed from the second resist pattern by dry etching, the second resist pattern is peeled off to form a semiconductor layer forming layer.
　その後、上記半導体層形成層が形成された基板全体に、スパッタリング法により、アルミニウム膜、銅膜やチタン膜などの第２の金属膜を厚さ３０００Å程度でスパッタリング法により成膜する。 Thereafter, a second metal film such as an aluminum film, a copper film, or a titanium film is formed by sputtering on the entire substrate on which the semiconductor layer forming layer has been formed by sputtering.
　続いて、上記第２の金属膜が成膜された基板全体にスピンコーティング法により、感光性樹脂膜を塗布した後に、パターニングすることにより、第３のレジストパターンを形成する。 Subsequently, a photosensitive resin film is applied to the entire substrate on which the second metal film is formed by spin coating, and then patterned to form a third resist pattern.
　さらに、上記第３のレジストパターンから露出する第２の金属膜をドライエッチングにより除去することにより、ソース電極１４ｃ及びドレイン電極１４ｄを形成する（図７参照）。 Further, the second metal film exposed from the third resist pattern is removed by dry etching to form the source electrode 14c and the drain electrode 14d (see FIG. 7).
　その後、ソース電極１４ｃ及びドレイン電極１４ｄから露出するｎ＋アモルファスシリコン層形成層及びその下層に配置する真性アモルファスシリコン層形成層の上層部を、六フッ化硫黄ガスや四フッ化炭素ガスなどのフッ素系ガスと、塩化水素ガスや塩素ガスなどの塩素系ガスとを用いた反応性ドライエッチングによって除去することにより、図７に示すように、ＴＦＴパターン１５を形成する。 Thereafter, the upper layer portion of the n + amorphous silicon layer forming layer exposed from the source electrode 14c and the drain electrode 14d and the intrinsic amorphous silicon layer forming layer disposed below the n + amorphous silicon layer forming layer is made of fluorine such as sulfur hexafluoride gas or carbon tetrafluoride gas. The TFT pattern 15 is formed as shown in FIG. 7 by removing by reactive dry etching using a system gas and a chlorine-based gas such as hydrogen chloride gas or chlorine gas.
　＜低濃度領域形成工程（Ｓｔ２２）＞
　上記ＴＦＴパターン形成工程で形成されたＴＦＴパターン１５の真性アモルファスシリコン層形成層１３ｃａに対し、図８に示すように、波長２４８ｎｍ以上且つ３５５ｎｍ以下のレーザー光Ｌ（例えば、波長３０８ｎｍのエキシマレーザー光）を照射することにより、アモルファスシリコンをレーザーアニールによって結晶化させると共に、水素含有量を３アトミック％以下にして、低濃度領域Ｒａを形成する。ここで、ソース電極１４ｃ及びドレイン電極１４ｄは、アルミニウム膜や銀膜などの高反射性の材料により構成されているので、その下層に配置する真性アモルファスシリコン層形成層１３ｃａには、レーザー光Ｌが照射されない。そのため、ソース電極１４ｃ及びドレイン電極１４ｄの下層に配置する真性アモルファスシリコン層形成層１３ｃａは、レーザーアニールされないので、低濃度領域Ｒａの外側に高濃度領域Ｒｂが形成される。 <Low concentration region forming step (St22)>
As shown in FIG. 8, laser light L (for example, excimer laser light having a wavelength of 308 nm) having a wavelength of 248 nm or more and 355 nm or less is applied to the intrinsic amorphous silicon layer forming layer 13ca of the TFT pattern 15 formed in the TFT pattern forming step. , The amorphous silicon is crystallized by laser annealing, and the hydrogen content is reduced to 3 atomic% or less to form the low concentration region Ra. Here, since the source electrode 14c and the drain electrode 14d are made of a highly reflective material such as an aluminum film or a silver film, the laser beam L is applied to the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d. Not irradiated. Therefore, the intrinsic amorphous silicon layer forming layer 13ca disposed below the source electrode 14c and the drain electrode 14d is not laser-annealed, so that the high concentration region Rb is formed outside the low concentration region Ra.
　＜水素ガスエッチング工程（Ｓｔ２３）＞
　上記低濃度領域形成工程で低濃度領域Ｒａが形成された基板において、ソース電極１４ａ及びドレイン電極１４ｂから露出するｎ＋アモルファスシリコン層形成層１３ｄａ及びその下層に配置する真性アモルファスシリコン層形成層１３ｃａの上層部を、例えば、コイルなどを用いた等方性の高密度プラズマエッチング装置を利用して、図９に示すように、水素ガスを主成分として用いたイオン性ドライエッチングで発生する水素プラズマＰによって、除去することにより、真性アモルファスシリコン層１３ｃ及びｎ＋アモルファスシリコン層１３ｄを形成する。ここで、水素ガスによるイオン性ドライエッチングにおいて、真性アモルファスシリコン層形成層１３ｃａの水素含有量が３アトミック％以下の低濃度領域Ｒａは、イオン性が低く、ほとんど除去されないものの、真性アモルファスシリコン層形成層１３ｃａの水素含有量が１０アトミック％程度の高濃度領域Ｒｂ、及び水素含有量が１０アトミック％程度のｎ＋アモルファスシリコン層形成層１３ｂａは、イオン性が高く、容易に除去されるので、真性アモルファスシリコン層形成層１３ｃａ及びｎ＋アモルファスシリコン層ｄａは、図９に示すように、側方に１μｍ程度除去される。 <Hydrogen gas etching process (St23)>
In the substrate on which the low concentration region Ra is formed in the low concentration region formation step, the n + amorphous silicon layer formation layer 13da exposed from the source electrode 14a and the drain electrode 14b and the intrinsic amorphous silicon layer formation layer 13ca disposed below the n + amorphous silicon layer formation layer 13ca For example, as shown in FIG. 9, a hydrogen plasma P generated by ionic dry etching using hydrogen gas as a main component is used for the upper layer portion by utilizing an isotropic high-density plasma etching apparatus using a coil or the like. Thus, the intrinsic amorphous silicon layer 13c and the n + amorphous silicon layer 13d are formed by removing. Here, in the ionic dry etching using hydrogen gas, the intrinsic amorphous silicon layer formation layer 13ca has a low hydrogen concentration of 3 atomic% or less, but the low concentration region Ra has low ionicity and is hardly removed. The high concentration region Rb having a hydrogen content of about 10 atomic% and the n + amorphous silicon layer forming layer 13ba having a hydrogen content of about 10 atomic% have high ionicity and are easily removed. As shown in FIG. 9, the amorphous silicon layer forming layer 13ca and the n + amorphous silicon layer da are removed by about 1 μm to the side.
　以上のようにして、本実施形態のＴＦＴ５ｂを製造することができる。 As described above, the TFT 5b of this embodiment can be manufactured.
　以上説明したように、本実施形態のＴＦＴ５ｂ及びその製造方法によれば、低濃度領域形成工程において、真性アモルファスシリコン層１３ｃとなる真性アモルファスシリコン層形成層１３ｃａに水素含有量が３アトミック％以下の低濃度領域Ｒａが形成されるので、その低濃度領域Ｒａでは、従来のＴＦＴ１０５（図１０参照）の真性アモルファスシリコン層１１３ａの水素含有量（例えば、１０アトミック％程度）よりも低くなっている。ここで、上記実施形態１と同様に、例えば、ＣＶＤ法により成膜した真性アモルファスシリコン膜の水素含有量をレーザーアニールによって３アトミック％以下とした真性アモルファスシリコン膜が、単にＣＶＤ法により成膜した真性アモルファスシリコン膜やｎ＋アモルファスシリコン膜よりも、水素ガスを主成分として用いたドライエッチングにおいてエッチング速度が極端に遅い（例えば、１／１８程度）という独自の知見により、低濃度領域形成工程において、例えば、レーザーアニールによって、ソース電極１４ｃ及びドレイン電極１４ｄから露出する真性アモルファスシリコン層形成層１３ｃａに水素含有量を３アトミック％以下の低濃度領域Ｒａを形成し、水素ガスエッチング工程において、水素ガスを用いたドライエッチングを行うことにより、半導体層となる半導体層形成層の一部を除去して、チャネル部Ｃに高濃度領域Ｒｂを形成する際に、真性アモルファスシリコン層形成層１３ｃａの低濃度領域Ｒａの除去が抑制され、低濃度領域Ｒａの外側に配置する真性アモルファスシリコン層形成層１３ｃａの高濃度領域Ｒｂ及びｎ＋アモルファスシリコン層形成層ｄａが除去されるので、半導体層１３ｃを構成する真性アモルファスシリコン層１３ｃ（真性アモルファスシリコン層形成層１３ｃａ）及びｎ＋アモルファスシリコン層１３ｄ（ｎ＋アモルファスシリコン層形成層１３ｄａ）のドライエッチング時の選択比を可及的に高くすることができる。 As described above, according to the TFT 5b and the manufacturing method thereof of the present embodiment, the hydrogen content in the intrinsic amorphous silicon layer forming layer 13ca to be the intrinsic amorphous silicon layer 13c is 3 atomic% or less in the low concentration region forming step. Since the low concentration region Ra is formed, the hydrogen concentration (for example, about 10 atomic%) of the intrinsic amorphous silicon layer 113a of the conventional TFT 105 (see FIG. 10) is lower in the low concentration region Ra. Here, as in the first embodiment, for example, an intrinsic amorphous silicon film in which the hydrogen content of the intrinsic amorphous silicon film formed by the CVD method is 3 atomic% or less by laser annealing is simply formed by the CVD method. In the low-concentration region forming process, the unique knowledge that the etching rate is extremely slow (for example, about 1/18) in dry etching using hydrogen gas as a main component compared to an intrinsic amorphous silicon film or an n + amorphous silicon film. For example, a low concentration region Ra having a hydrogen content of 3 atomic% or less is formed in the intrinsic amorphous silicon layer forming layer 13ca exposed from the source electrode 14c and the drain electrode 14d by laser annealing. Dry etch using By removing a part of the semiconductor layer forming layer that becomes the semiconductor layer by forming the high concentration region Rb in the channel portion C, the low concentration region Ra of the intrinsic amorphous silicon layer forming layer 13ca is removed. Is suppressed, and the high concentration region Rb and the n + amorphous silicon layer formation layer da of the intrinsic amorphous silicon layer formation layer 13ca disposed outside the low concentration region Ra are removed, so that the intrinsic amorphous silicon layer constituting the semiconductor layer 13c is removed. The selection ratio during dry etching of 13c (intrinsic amorphous silicon layer forming layer 13ca) and n + amorphous silicon layer 13d (n + amorphous silicon layer forming layer 13da) can be made as high as possible.
　また、本実施形態のＴＦＴ５ｂ及びその製造方法によれば、真性アモルファスシリコン層１３ｃにおいて、水素含有量が相対的に低い低濃度領域Ｒａは、結晶性が相対的に高く、水素含有量が相対的に高い高濃度領域Ｒｂは、結晶性が相対的に低くなるので、高濃度領域Ｒｂが低濃度領域Ｒａとソース電極１４ｃ及びドレイン電極１４ｄとの間の電界を緩和するための緩衝領域になり、オフ電流を低減させることができる。 Further, according to the TFT 5b and the manufacturing method thereof of the present embodiment, in the intrinsic amorphous silicon layer 13c, the low concentration region Ra having a relatively low hydrogen content has a relatively high crystallinity and a relatively high hydrogen content. Since the high concentration region Rb is relatively low in crystallinity, the high concentration region Rb becomes a buffer region for relaxing the electric field between the low concentration region Ra and the source electrode 14c and drain electrode 14d. The off current can be reduced.
　また、本実施形態のＴＦＴ５ｂ及びその製造方法によれば、レーザー光Ｌを照射後に発生したシリコン内の欠陥部分を水素プラズマによって終端することができるので、ＴＦＴ特性（移動度やオフ電流）を向上させることができる。 In addition, according to the TFT 5b and the manufacturing method thereof of the present embodiment, the defect portion in the silicon generated after irradiation with the laser beam L can be terminated by hydrogen plasma, so that the TFT characteristics (mobility and off-current) are improved. Can be made.
　なお、本実施形態のＳｔ２３では、水素ガスを用いたドライエッチングを行ったが、過酸化水素及びフッ素を含むエッチャントを用いたウエットエッチングを行ってもよい。 In St23 of this embodiment, dry etching using hydrogen gas is performed, but wet etching using an etchant containing hydrogen peroxide and fluorine may be performed.
　上記各実施形態では、第２シリコン層にリンがドープされたｎチャネル型のＴＦＴを例示したが、本発明は、第２シリコン層にボロンがドープされたｐチャネル型のＴＦＴにも適用することができる。 In each of the above embodiments, an n-channel TFT in which the second silicon layer is doped with phosphorus is exemplified, but the present invention is also applicable to a p-channel TFT in which the second silicon layer is doped with boron. Can do.
　以上説明したように、本発明は、ＴＦＴの特性を向上させることができるので、例えば、アクティブマトリクス駆動方式の液晶表示パネルや有機ＥＬ表示パネルについて有用である。 As described above, since the characteristics of the TFT can be improved, the present invention is useful for, for example, an active matrix liquid crystal display panel and an organic EL display panel.
Ｃ　　　　　　チャネル部
Ｌ　　　　　　レーザー光
Ｐ　　　　　　水素プラズマ
Ｒａ　　　　　低濃度領域
Ｒｂ　　　　　高濃度領域
５ａ，５ｂ　　ＴＦＴ
１０　　　　　絶縁基板
１１　　　　　ゲート電極
１２　　　　　ゲート絶縁膜
１３　　　　　半導体層
１３ａ，１３ｃ　　真性アモルファスシリコン層（第１シリコン層、第１シリコン膜）
１３ｂ，１３ｄ　　ｎ＋アモルファスシリコン層（第２シリコン層）
１３ｂａ　　　ｎ＋アモルファスシリコン層形成層（第２シリコン層形成層、半導体層形成層）
１３ｃａ　　　真性アモルファスシリコン層形成層（第１シリコン層形成層、半導体層形成層）
１３ｄａ　　　ｎ＋アモルファスシリコン層形成層（第２シリコン層形成層、半導体層形成層）
１４ａ，１４ｃ　　ソース電極
１４ｂ，１４ｄ　　ドレイン電極 C channel portion L laser beam P hydrogen plasma Ra low concentration region Rb high concentration region 5a, 5b TFT
DESCRIPTION OF SYMBOLS 10 Insulating substrate 11 Gate electrode 12 Gate insulating film 13 Semiconductor layer 13a, 13c Intrinsic amorphous silicon layer (1st silicon layer, 1st silicon film)
13b, 13dn + amorphous silicon layer (second silicon layer)
13ba n + amorphous silicon layer formation layer (second silicon layer formation layer, semiconductor layer formation layer)
13ca Intrinsic amorphous silicon layer formation layer (first silicon layer formation layer, semiconductor layer formation layer)
13 dan + amorphous silicon layer forming layer (second silicon layer forming layer, semiconductor layer forming layer)
14a, 14c Source electrode 14b, 14d Drain electrode

Claims (11)

  1. 　基板に設けられたゲート電極と、
    　上記ゲート電極を覆うように設けられたゲート絶縁膜と、
    　上記ゲート絶縁膜上に設けられ上記ゲート電極に重なるようにチャネル部が配置された第１シリコン層を有する半導体層と、
    　上記半導体層上に設けられ上記チャネル部が露出するように互いに離間して配置されたソース電極及びドレイン電極とを備え、
    　上記半導体層が上記第１シリコン層と上記ソース電極及びドレイン電極との間に不純物がドープされた第２シリコン層を有する薄膜トランジスタであって、
    　上記第１シリコン層は、水素含有量が３アトミック％以下の低濃度領域を有していることを特徴とする薄膜トランジスタ。     A gate electrode provided on the substrate;
    A gate insulating film provided to cover the gate electrode;
    A semiconductor layer having a first silicon layer provided on the gate insulating film and having a channel portion disposed so as to overlap the gate electrode;
    A source electrode and a drain electrode, which are provided on the semiconductor layer and spaced apart from each other so as to expose the channel portion;
    The semiconductor layer is a thin film transistor having a second silicon layer doped with impurities between the first silicon layer and the source and drain electrodes,
    The thin film transistor according to claim 1, wherein the first silicon layer has a low concentration region having a hydrogen content of 3 atomic% or less.
  2. 　請求項１に記載された薄膜トランジスタにおいて、
    　上記低濃度領域は、上記第１シリコン層の全体に配置されていることを特徴とする薄膜トランジスタ。     The thin film transistor according to claim 1,
    The thin film transistor according to claim 1, wherein the low concentration region is disposed on the entire first silicon layer.
  3. 　請求項２に記載された薄膜トランジスタにおいて、
    　上記第１シリコン層の膜厚は、２００Å以上且つ８００Å以下であることを特徴とする薄膜トランジスタ。     The thin film transistor according to claim 2,
    The thin film transistor, wherein the first silicon layer has a thickness of 200 to 800 mm.
  4. 　請求項１に記載された薄膜トランジスタにおいて、
    　上記第１シリコン層は、上記チャネル部において、上記低濃度領域と、該低濃度領域の外側に上記ソース電極及びドレイン電極に対応して配置され該低濃度領域よりも水素含有量が高い高濃度領域とを有していることを特徴とする薄膜トランジスタ。     The thin film transistor according to claim 1,
    The first silicon layer is disposed in the channel portion so as to correspond to the source electrode and the drain electrode on the outside of the low concentration region and the low concentration region, and has a higher hydrogen content than the low concentration region. A thin film transistor having a region.
  5. 　請求項１乃至４の何れか１つに記載された薄膜トランジスタにおいて、
    　上記第１シリコン層は、結晶性を有していることを特徴とする薄膜トランジスタ。     The thin film transistor according to any one of claims 1 to 4,
    The thin film transistor, wherein the first silicon layer has crystallinity.
  6. 　基板に設けられたゲート電極と、
    　上記ゲート電極を覆うように設けられたゲート絶縁膜と、
    　上記ゲート絶縁膜上に設けられ上記ゲート電極に重なるようにチャネル部が配置された第１シリコン層を有する半導体層と、
    　上記半導体層上に設けられ上記チャネル部が露出するように互いに離間して配置されたソース電極及びドレイン電極とを備え、
    　上記半導体層が上記第１シリコン層と上記ソース電極及びドレイン電極との間に不純物がドープされた第２シリコン層を有する薄膜トランジスタを製造する方法であって、
    　上記第１シリコン層となる第１シリコン膜に水素含有量が３アトミック％以下の低濃度領域を形成する低濃度領域形成工程と、
    　上記低濃度領域が形成された基板に対して、水素ガスを用いたドライエッチング、又は、過酸化水素及びフッ素を含むエッチャントを用いたウエットエッチングを行うことにより、上記半導体層となる半導体層形成層の一部を除去する半導体層形成エッチング工程とを備えることを特徴とする薄膜トランジスタの製造方法。     A gate electrode provided on the substrate;
    A gate insulating film provided to cover the gate electrode;
    A semiconductor layer having a first silicon layer provided on the gate insulating film and having a channel portion disposed so as to overlap the gate electrode;
    A source electrode and a drain electrode, which are provided on the semiconductor layer and spaced apart from each other so as to expose the channel portion;
    A method of manufacturing a thin film transistor, wherein the semiconductor layer has a second silicon layer doped with impurities between the first silicon layer and the source and drain electrodes,
    A low concentration region forming step of forming a low concentration region having a hydrogen content of 3 atomic% or less in the first silicon film to be the first silicon layer;
    A semiconductor layer forming layer which becomes the semiconductor layer by performing dry etching using hydrogen gas or wet etching using an etchant containing hydrogen peroxide and fluorine on the substrate on which the low concentration region is formed A method for producing a thin film transistor, comprising: a semiconductor layer forming etching step for removing a part of the semiconductor layer.
  7. 　請求項６に記載された薄膜トランジスタの製造方法において、
    　上記低濃度領域形成工程では、上記第１シリコン膜に対してレーザー光を照射することにより、上記低濃度領域を形成することを特徴とする薄膜トランジスタの製造方法。     In the manufacturing method of the thin-film transistor according to claim 6,
    In the low concentration region forming step, the low concentration region is formed by irradiating the first silicon film with a laser beam.
  8. 　請求項６又は７に記載された薄膜トランジスタの製造方法において、
    　上記低濃度領域形成工程では、上記第１シリコン膜の少なくとも上記チャネル部となる領域に上記低濃度領域を形成し、
    　上記低濃度領域が形成された第１シリコン膜上に上記第２シリコン層となる第２シリコン層形成層を形成した後に、上記ソース電極及びドレイン電極を形成するソースドレイン形成工程を有し、
    　上記半導体層形成エッチング工程では、上記ソース電極及びドレイン電極から露出する上記第２シリコン層形成層を除去して、上記チャネル部を形成することを特徴とする薄膜トランジスタの製造方法。     In the manufacturing method of the thin-film transistor described in Claim 6 or 7,
    In the low-concentration region forming step, the low-concentration region is formed in a region that becomes at least the channel portion of the first silicon film,
    A source drain forming step of forming the source electrode and the drain electrode after forming a second silicon layer forming layer to be the second silicon layer on the first silicon film in which the low concentration region is formed;
    In the semiconductor layer formation etching step, the channel portion is formed by removing the second silicon layer formation layer exposed from the source electrode and the drain electrode.
  9. 　請求項６又は７に記載された薄膜トランジスタの製造方法において、
    　上記低濃度領域形成工程では、上記ソース電極及びドレイン電極から露出する上記第１シリコン層となる第１シリコン層形成層に上記低濃度領域を形成し、
    　上記半導体層形成エッチング工程では、上記低濃度領域の外側に配置する上記第１シリコン層形成層の一部を除去することにより、上記チャネル部に上記ソース電極及びドレイン電極に対応して配置され上記低濃度領域よりも水素含有量が高い高濃度領域を形成することを特徴とする薄膜トランジスタの製造方法。     In the manufacturing method of the thin-film transistor described in Claim 6 or 7,
    In the low-concentration region forming step, the low-concentration region is formed in a first silicon layer forming layer that becomes the first silicon layer exposed from the source electrode and the drain electrode,
    In the semiconductor layer formation etching step, by removing a part of the first silicon layer formation layer disposed outside the low concentration region, the channel portion is disposed corresponding to the source electrode and the drain electrode. A method for manufacturing a thin film transistor, wherein a high concentration region having a higher hydrogen content than a low concentration region is formed.
  10. 　請求項７に記載された薄膜トランジスタの製造方法において、
    　上記レーザー光の波長は、２４８ｎｍ以上且つ３５５ｎｍ以下であることを特徴とする薄膜トランジスタの製造方法。     In the manufacturing method of the thin-film transistor described in Claim 7,
    The method of manufacturing a thin film transistor, wherein the laser beam has a wavelength of 248 nm to 355 nm.
  11. 　請求項６乃至１０の何れか１つに記載された薄膜トランジスタの製造方法において、
    　上記基板は、短辺が１５００ｍｍ以上の矩形状のガラス基板であることを特徴とする薄膜トランジスタの製造方法。     In the manufacturing method of the thin-film transistor as described in any one of Claims 6 thru | or 10,
    The method of manufacturing a thin film transistor, wherein the substrate is a rectangular glass substrate having a short side of 1500 mm or more.
PCT/JP2009/003499 2008-12-11 2009-07-24 Thin film transistor and method for manufacturing the thin film transistor WO2010067483A1 (en)

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