WO2010060237A1 - Ordinateur de réseau basé sur un circuit intégré prédiffusé programmable - Google Patents

Ordinateur de réseau basé sur un circuit intégré prédiffusé programmable Download PDF

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Publication number
WO2010060237A1
WO2010060237A1 PCT/CN2008/072912 CN2008072912W WO2010060237A1 WO 2010060237 A1 WO2010060237 A1 WO 2010060237A1 CN 2008072912 W CN2008072912 W CN 2008072912W WO 2010060237 A1 WO2010060237 A1 WO 2010060237A1
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WO
WIPO (PCT)
Prior art keywords
fpga
interface
module
fpga chip
chip
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Application number
PCT/CN2008/072912
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English (en)
Chinese (zh)
Inventor
江殷
赵煦苏
Original Assignee
北京瑞智创通系统科技有限公司
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Publication date
Application filed by 北京瑞智创通系统科技有限公司 filed Critical 北京瑞智创通系统科技有限公司
Priority to PCT/CN2008/072912 priority Critical patent/WO2010060237A1/fr
Publication of WO2010060237A1 publication Critical patent/WO2010060237A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to the field of embedded electronic chips, in particular to a network computer based on a field programmable gate array (FPGA). Background technique
  • FIG. 1 is a schematic structural view of a computer system in the prior art.
  • One is the traditional x86-based technology for reducing PCs.
  • the other category is embedded system technology using dedicated chips.
  • the x86-based reduced PC technology is based on the technology of a PC, using a small local flash to replace the hard disk, reducing the local memory configuration, and using a CPU with a reduced instruction set, and using a reduced version of the operating system.
  • Dedicated commercial PC Network computers using this architecture technology, because the hardware modules necessary for the PC system have not been reduced, only a few reductions in the configuration of the functional modules, so the complexity is not reduced. There is no reduction in manufacturing cost compared to traditional PCs. In addition, because this type of network computer must use some fixed chipset, there is no significant improvement in power consumption.
  • Embedded system technology using a dedicated chip is another architecture technology that is widely used in network computer products. Some people call it a "thin client”.
  • Traditional embedded system technologies generally use fixed chips or chipsets, such as embedded systems based on ARM (Advanced reduced instruction set computer machines) and embedded systems using PowerPC architecture. This technology using a fixed chipset is compared to x86 technology. In terms of cost and technical complexity, there is a certain reduction in scalability, but in terms of scalability, for example, if you need to add some hardware or software functional modules to a fixed architecture, this architecture with dedicated chips can be powerless. And the embedded system using A or PowerPC still consumes a lot of power. Summary of the invention
  • an embodiment of the present invention provides an FPGA-based network computer, which is characterized in that the FPGA chip includes a switching bus and a bus controller, and further includes a USB processing module, a display drawing array module, and an Ethernet module. Two or more of a digital audio module or a memory controller for transmitting data of each functional module in the FPGA chip, the bus controller being connected to the switching bus for controlling the The exchange bus transfers data.
  • a further aspect of an FPGA-based network computer further includes a power PC chip connected to the FPGA chip, the power PC chip internally comprising a plurality of hardware chip sets, respectively
  • the function of the FPGA chip of the network computer is not realized, for example, if there is no Ethernet module in the FPGA chip, the Ethernet connection is realized by the Ethernet chipset of the power PC chip.
  • the FPGA chip further includes a processor core simulated by software, and is connected to the switching bus for the FPGA.
  • Other functional modules within the chip send control logic.
  • the FPGA chip further includes a Ps/2 module simulated by software for processing data of an external device using the Ps/2 interface.
  • the network computer further comprises the following interface corresponding to each software simulation module of the FPGA chip: a USB interface, the USB interface is connected to a corresponding pin of the FPGA chip, and is used for data communication with the FP GA, the USB processing module of the FPGA chip processes data of the USB interface; and displays a drawing array interface, The display drawing array interface is connected to a corresponding pin of the FPGA chip, and is configured to output data processed by the display drawing array module of the FPGA chip to a display device external to the network computer;
  • Ethernet interface is connected to a corresponding pin of the FPGA chip, and configured to transmit data processed by an Ethernet module of the FPGA chip;
  • the digital audio interface being connected to a corresponding pin of the FPGA chip, for transmitting data processed by the digital audio module of the FPGA chip;
  • a storage controller interface where the storage controller interface is connected to a corresponding pin of the FPGA chip, and is used for data transmission between the FPGA chip and the memory.
  • the FPGA chip further includes a joint test interface module, and is connected to the switch bus, and is configured to be used in the FPGA chip. Each device was tested.
  • the FPGA chip further includes an on-chip user logic module connected to the switch bus for starting the FPGA chip.
  • the FPGA chip further includes a timer, and is connected to the switching bus, and is used for other internals of the F PGA chip.
  • the function module provides clock data.
  • the beneficial effects of the method embodiment of the present invention are that an FPGA is used to implement a plurality of functional modules of a computer. Since a plurality of corresponding hardware modules are not used, only a software is programmed on the FPGA to implement various functions, so the present invention
  • the network computer is low in manufacturing cost; and therefore, the product can be energy-saving and environmentally friendly, because when the computer is upgraded, the hardware waste is not reduced by using multiple hardware modules, and no more environmental pollution is caused, and the FGPA implementation of the embodiment of the present invention is realized.
  • Functional model of various computers DRAWINGS
  • FIG. 1 is a schematic structural view of a computer system in the prior art
  • FIG. 2 is a schematic diagram of functional modules of a first embodiment of an FPGA-based network computer according to the present invention
  • FIG. 3 is a circuit diagram of a first embodiment of a network computer based on FPGA according to the present invention
  • FIG. 4 is a schematic diagram of a Ps/2 mouse interface according to an embodiment of the present invention.
  • FIG. 5 shows a schematic diagram of the VGA interface
  • FIG. 6 is a schematic diagram of functional modules of a second embodiment of an FPGA-based network computer according to the present invention
  • FIG. 7 is a circuit diagram of a second embodiment of an FPGA-based network computer according to the present invention.
  • FIG. 8 is a schematic diagram of a network interface according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a network computer based on an FPGA. The invention will now be described in detail in conjunction with the drawings.
  • FIG. 2 is a schematic diagram of functional modules of a first embodiment of an FPGA-based network computer according to the present invention, including an FPGA chip 100, a processor core 101 implemented by using an internal logic circuit of the FPGA chip, and an internal logic circuit of the FPGA chip.
  • the memory controller 102, the switching bus controller 103 implemented by the internal logic circuit of the FPGA chip, the switching bus 104 implemented by the internal logic circuit of the FPGA chip, and the asynchronous serial transceiver 105 implemented by the internal logic circuit of the FPGA chip are utilized.
  • the timer 106 implemented by the internal logic circuit of the FPGA chip, the display graphics array (VGA: Video Graphics Array) module 107 implemented by the internal logic circuit of the FPGA chip, and the USB processing module 108 implemented by the internal logic circuit of the FPGA chip,
  • the Ethernet module 109 (ETHPHY) implemented by the internal logic circuit of the FPGA chip, and the synchronous serial interface module implemented by the internal logic circuit of the FPGA chip
  • the Ps/2 processing module 114 implemented by the internal logic circuit of the FPGA chip.
  • the foregoing implementation of various functions by the internal logic circuit of the FPGA chip refers to, according to the method for processing data by the existing hardware function module, using the editing tool of the FPGA chip, so that the FPGA chip simulates the function of the hardware, for example, can be used.
  • the hardware description language constructs the internal logic circuit of the FPGA chip on the FPGA chip, so that the FPGA chip implements the video data processing function of the hardware VGA device.
  • the processor core 101 is used to implement the functions of the soft CPU, process externally input data, and control other functional modules on the FPGA.
  • the processor core 101 can be implemented using a soft core CPU of the prior art.
  • the storage controller 102 is configured to perform data transmission control on a Synchronous Dynamic Random Access Memory (SDRAM), a Read-Only Memory (ROM), and an external Flash.
  • SDRAM Synchronous Dynamic Random Access Memory
  • ROM Read-Only Memory
  • external Flash an external Flash
  • the bus controller 103 is used to control the transfer of data on the bus.
  • the bus controller can be used
  • the HDL language simulates the control functions of a typical computer's bus controller on an FPGA chip.
  • the FPGA internal switch bus 104 is used to provide bus channels to various functional blocks within the FPGA. All functional modules are connected to the FPGA internal switching bus 104 via an NPI interface.
  • the asynchronous serial transceiver 105 is configured to manage data USB when the FPGA is being debugged.
  • the timer 106 is used to provide clocks to other functional modules.
  • the VGA module 107 is configured to process video data and communicate with an external display via a VGA interface or The video capture device performs data communication.
  • the USB processing module 108 is configured to process data of a user USB device.
  • the Ethernet module 109 is configured to receive data transmitted by the network interface, and modulate and demodulate the transmission data to implement a function of the network card.
  • the network interface is, for example, an RJ45 interface.
  • the synchronous serial interface module 110 is configured to manage data USB when the FPGA is debugging.
  • the on-chip user logic 111 is used to boot the FPGA chip.
  • the digital audio module 112 is configured to process audio data and communicate data with an external speaker or audio capture device via an audio interface.
  • the JTAG interface module 113 is configured to connect to an external JTAG debugger, and use the JTAG debugger to test each device in the FPGA chip.
  • the device described here is different from the above functional module and refers to the physical device within the FPGA chip.
  • the Ps/2 processing module 114 is configured to control the input and output of the Ps/2 interface peripheral, such as the mouse and keyboard of the Ps/2 interface.
  • FIG. 3 is a circuit diagram of a first embodiment of an FPGA-based network computer according to the present invention.
  • the FPGA chip 200 shown in FIG. 2 includes various functional modules internally implemented by software, including a controller for the memory, an asynchronous serial transceiver, a VGA module, a USB processing module, an Ethernet module, and a synchronous serial interface.
  • Module, digital audio module, JTAG interface module and Ps/2 processing module also has USB and Ps/2 interface 201 outside the FPGA chip (including USB interface pin and Ps/2 interface pin), digital audio Interface 202, Ethernet interface 203, JTAG interface 204, NAND Flash interface 205, SDRAM interface 206, VGA interface 207, SPI interface 208, UART interface 209.
  • USB and Ps/2 interface 201 the digital audio interface 202, the Ethernet interface 203, the JTAG interface 204, the non-flash interface (NAND Flash) 205, the SDRAM interface 206, the VGA interface 207, the SPI interface 208, and the UART interface 209 are both Connected to corresponding pins on the FPGA chip 200.
  • the USB and Ps/2 interface 201 is connected to the tube of the USB module of the FPGA chip 200 through a corresponding pin (USB-1-n-pin, USB-1-p pin) and Ps/2 module. Foot (KB-d pin and The MS-CK pin is connected, and the USB and Ps/2 interface 201 is connected to a device such as an external mouse, a keyboard, or the like, or a Ps/2 or USB interface.
  • the KB_d pin represents a set of pin data (KB_d) and a clock (KB_CK) pin of the Ps/2 interface keyboard, and the MS-CK pin represents a Ps/2 interface mouse.
  • the digital audio interface 202 is connected to a pin drawn from a digital audio module of the FPGA chip 200 through a corresponding pin, and audio input and output is performed through the digital audio interface 202.
  • the Ethernet interface 203 is connected to a pin drawn from an Ethernet module of the FPGA chip 200 through a corresponding pin, and is connected to the network interface through the Ethernet interface 203 to perform network data communication, for example, the network interface.
  • the JTAG interface 204 is connected to the JTAG interface module of the FPGA chip 200 through a corresponding pin, and the JTAG debugger is accessed through the JTAG interface 204 to implement various devices in the FPGA chip, such as transistors, and non- Devices such as doors are tested.
  • the NAND Flash interface 205 and the corresponding pins of the SDRAM interface 206 are connected to the memory controller of the FPGA chip 200, and the data is transmitted through the NAND Flash interface 205 and the SDRAM interface 206 and external storage devices such as Flash and SDRAM.
  • the operating system and pre-installed software in the external Flash are obtained through the NAND Flash interface 205, and the SDRAM interface 206 enables the FPGA chip to utilize the external SDRAM memory to provide a memory space for running the software.
  • the VGA interface 207 is connected to the VGA module of the FPGA chip 200 through corresponding pins, and the video data is input and output through the VGA interface 207.
  • the SPI interface 208 is connected to the synchronous serial interface module of the FPGA chip 200 through a corresponding pin, and the synchronous serial interface module of the FPGA chip 200 is communicated with external synchronous serial data through the SPI interface 208. .
  • the UART interface 209 is connected to an asynchronous serial transceiver of the FPGA chip 200 through a corresponding pin, and the asynchronous serial transceiver of the FPGA chip 200 is communicated with external asynchronous serial data through the UART interface 209. .
  • Table 1 determines the interface pins of the functional modules of the FPGA chip. Main pin description
  • ETHPHY TXD sends data signals
  • Ethernet module RXD receives data signals
  • RXCLK transmit clock signal
  • TXCLK receive clock signal
  • RXDV accepts control signals
  • MDI-TP differential transmission signal is positive
  • FIG. 4 is a schematic diagram of a Ps/2 mouse interface according to an embodiment of the present invention, wherein the pin 1 of the Ps/2 interface and the MS-D pin of the FPGA chip Ps/2 module of the first embodiment Connection for transmitting data; pin 3 of the Ps/2 interface is connected to the ground; pin 4 of the Ps/2 interface is connected to the power supply VCC; pin 5 of the Ps/2 interface is connected to the MS-CK pin of the FPGA , used to transmit clock information.
  • Figure 5 shows a schematic diagram of the VGA interface.
  • the pins 1, 2, and 3 of the VGA interface are respectively connected to the VGA red, VGA green, and VGA blue pins of the FPGA chip, and are used to transmit red, green, and The blue color data;
  • the pins 13 and 14 of the VGA interface are respectively connected with the horizontal synchronization signal (VGA-HSVNC) and the vertical synchronization signal (VGA-VSVNC) pins of the FPGA chip VGA module, and are used for transmitting horizontal synchronization and vertical synchronization signals.
  • VGA-HSVNC horizontal synchronization signal
  • VGA-VSVNC vertical synchronization signal
  • a single FPGA chip is used to simulate various hardware functions, and the connection between the FPGA chip and the external interface enables the FPGA to implement the function of the network computer, and since all functions are implemented in the FPGA chip using software, the cost is on the hardware. Very low.
  • FIG. 6 is a schematic diagram of functional modules of a second embodiment of an FPGA-based network computer according to the present invention, including a Power PC (Performance Optimized With Enhanced RISC) chip 300, an FPGA chip 301, a NAND interface 302, and an SD card reader interface 303.
  • USB interface 304 Ethernet interface 305, UART interface 306, first JTAG interface 307, digital audio interface 308, Ps/2 interface 309, VGA interface 310, video memory (VID SD) interface 311, second JTAG interface 312, network interface 313.
  • VGA interface 310 video memory (VID SD) interface 311, second JTAG interface 312, network interface 313.
  • the NAND interface 302, the SD card reader interface 303, the USB interface 304, the UART interface 306, the first JTAG interface 307, and the Ethernet interface 305 are respectively connected to the power PC chip 300, the network interface 313 and the The Ethernet interface 305 is connected, and has a corresponding hardware chipset inside the power PC chip 300 to support data control and processing of each interface; the FPGA chip 301 is connected to the power PC chip 300, and accepts the power PC.
  • the control of the chip 300; the Ps/2 interface 309, the digital audio interface 308, the VGA interface 310, the memory (VID SD) interface 311, and the second JTAG interface 312 are respectively connected to the FPGA chip 301, where the FPGA chip
  • the 301 has corresponding software function modules internally to support data control and processing of the external interfaces.
  • the power PC chip 300 Since the power PC chip 300 has a chipset supporting each functional module internally, the processing speed is relatively fast, but the disadvantage is that the cost is relatively high, and since the internal chipset is composed of hardware, the functions that the power PC chip 300 can perform are affected.
  • the FPGA chip 301 By limiting the FPGA chip 301, the FPGA chip 301 can be implemented by various functions.
  • the power PC chip 300 in this example does not have VGA video processing capability, audio data processing capability, and Ps/2.
  • the serial data processing capability, but the above functions are realized by the software function module inside the FPGA chip 301.
  • the Power PC chip 300 realizes the above functions by controlling and calling the FPGA chip 301, so the power PC chip 300 and the FPGA in this embodiment
  • the network computer formed by the chip 301 can realize the basic functions of an ordinary computer at a relatively high speed and at a low cost.
  • FIG. 7 is a circuit diagram of a second embodiment of an FPGA-based network computer according to the present invention.
  • GMII - REFCLK receive clock signal
  • FIG. 8 is a schematic diagram of a network interface according to an embodiment of the present invention, wherein the differential transmission signals of the pins 1, 2, 3, and 6 of the network interface 313 and the Ethernet interface 305 are positive MDI-TP pins, and the differential transmission signals are negative.
  • MDI—TN pin, differential receive signal positive MDI—R pin, differential receive signal negative PMDI—RN pin is connected, and LED1 and LED2 are connected to LED1 and LED2 pins of Ethernet interface 305, respectively.
  • the utility model has the beneficial effects that the function module of the plurality of computers is realized by using one FPGA, and the network computer manufacturing cost of the invention is realized because the corresponding plurality of hardware modules are not used, and only the functions of the FPGA are implemented on the software. Low; and therefore also able to achieve energy saving and environmental protection,
  • the computer is upgraded, the hardware waste is not reduced, and the environmental waste is not caused, and the FGPA of the embodiment of the present invention implements a plurality of computer functional modules, and the power consumption is low, which is equivalent to ordinary PC 1/40 (power consumption 5 watts, maximum no more than 6 watts, ordinary PC power consumption 200 watts); indirect savings of air conditioning costs over 80%, compact size, weight less than 200 grams, saving floor space and transportation Cost; adopts fanless design, no noise operation; product meets the green standard of RoHS (Restriction of Hazardous Substances), does not produce any harmful waste; operation and maintenance management is simple: low power consumption, can avoid heat generation Too much, component aging is accelerated, so the

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

Dans le domaine des ordinateurs embarqués, l'invention porte sur un ordinateur de réseau basé sur un circuit intégré prédiffusé programmable (FPGA) qui surmonte les désavantages qui sont que l'ordinateur antérieur a une consommation électrique plus élevée, gaspille davantage de matériel et n'est pas commode pour étendre la fonction du processeur. A l'intérieur de la puce FPGA se trouve un bus d'échange, un contrôleur de bus, et deux modules ou plus parmi un module de traitement USB, un module de carte vidéographique (VGA), un module Ethernet, un module audionumérique ou un contrôleur de mémoire. Le bus d'échange transmet les données de chaque module fonctionnel de la puce FPGA. Le contrôleur de bus est connecté au bus d'échange pour commander le bus d'échange afin de transmettre des données. Cette invention réduit la complexité du système et la consommation d'énergie de l'ordinateur embarqué, et confère à l'ordinateur de réseau une bonne capacité d'extension.
PCT/CN2008/072912 2008-11-03 2008-11-03 Ordinateur de réseau basé sur un circuit intégré prédiffusé programmable WO2010060237A1 (fr)

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PCT/CN2008/072912 WO2010060237A1 (fr) 2008-11-03 2008-11-03 Ordinateur de réseau basé sur un circuit intégré prédiffusé programmable

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PCT/CN2008/072912 WO2010060237A1 (fr) 2008-11-03 2008-11-03 Ordinateur de réseau basé sur un circuit intégré prédiffusé programmable

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108303935A (zh) * 2018-04-08 2018-07-20 北京强度环境研究所 一种基于多核SoC处理器的振动控制器
CN111766807A (zh) * 2020-06-23 2020-10-13 济南浪潮高新科技投资发展有限公司 一种医院病房夜班巡视机器人控制系统
CN112346645A (zh) * 2019-08-06 2021-02-09 天津光电通信技术有限公司 一种基于fpga与单板pc的多通道高速信号采集处理板卡
CN113742268A (zh) * 2021-09-14 2021-12-03 北京坤驰科技有限公司 一种基于以太网光纤的高速脉冲采集系统
CN114301854A (zh) * 2021-02-05 2022-04-08 井芯微电子技术(天津)有限公司 一种PCIe交换设备

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108303935A (zh) * 2018-04-08 2018-07-20 北京强度环境研究所 一种基于多核SoC处理器的振动控制器
CN112346645A (zh) * 2019-08-06 2021-02-09 天津光电通信技术有限公司 一种基于fpga与单板pc的多通道高速信号采集处理板卡
CN111766807A (zh) * 2020-06-23 2020-10-13 济南浪潮高新科技投资发展有限公司 一种医院病房夜班巡视机器人控制系统
CN114301854A (zh) * 2021-02-05 2022-04-08 井芯微电子技术(天津)有限公司 一种PCIe交换设备
CN114301854B (zh) * 2021-02-05 2024-02-23 井芯微电子技术(天津)有限公司 一种PCIe交换设备
CN113742268A (zh) * 2021-09-14 2021-12-03 北京坤驰科技有限公司 一种基于以太网光纤的高速脉冲采集系统
CN113742268B (zh) * 2021-09-14 2023-12-08 北京坤驰科技有限公司 一种基于以太网光纤的高速脉冲采集系统

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