WO2010058831A1 - パケットフィルタを用いたクロック同期システム、装置、方法およびそのプログラム - Google Patents
パケットフィルタを用いたクロック同期システム、装置、方法およびそのプログラム Download PDFInfo
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- 238000001914 filtration Methods 0.000 claims abstract description 30
- 238000012937 correction Methods 0.000 claims description 29
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000005259 measurement Methods 0.000 claims description 7
- 230000001360 synchronised effect Effects 0.000 description 76
- 230000007423 decrease Effects 0.000 description 28
- 238000012545 processing Methods 0.000 description 21
- 230000000694 effects Effects 0.000 description 11
- 238000012546 transfer Methods 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 6
- 238000007429 general method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0664—Clock or time synchronisation among packet nodes using timestamps unidirectional timestamps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
Definitions
- the present invention relates to a system, apparatus, method, and program for synchronizing clocks between apparatuses via a packet network, and more particularly to a clock synchronization system, apparatus, method, and program for improving clock synchronization accuracy between apparatuses. .
- TDM time division multiplexing
- IP Internet protocol
- Some traffic transferred within the network requires accurate clock synchronization between the sending node and the receiving node. For example, in order to exchange high-quality real-time data such as voice and video, it is necessary to reproduce the data at a predetermined timing, and thus an accurate clock is required.
- each base station device on the mobile network is required to have highly accurate clock synchronization of 50 parts per billion (ppb) with the wireless network control device. If the clock synchronization accuracy of the base station device exceeds this required value during service, handover between cells may fail, data may be lost, and communication quality may deteriorate.
- ppb parts per billion
- the receiving node can extract the clock information of the transmitting node via the transmission path, it was possible to realize highly accurate clock synchronization between the transmitting and receiving nodes.
- data is transferred asynchronously in a network using the IP method. Therefore, there is a fluctuation in the data arrival interval at the receiving side node, and it is difficult to extract highly accurate clock information from the received data. Therefore, the receiving side node needs to find the clock interval of the transmitting side node by some method and adjust the clock interval to the transmitting side node.
- matching the clock interval of the receiving side node with the clock interval of the transmitting side node means that the receiving side node regenerates the clock of the transmitting side node.
- a time stamp method has been proposed as a technique for realizing highly accurate clock recovery via a packet network represented by an IP network or the like.
- This time stamp method is described in Patent Document 1, for example.
- a block diagram of the time stamp method is shown in FIG. FIG. 1 shows a state in which a master node 100 that is a transmission side node transmits a packet 120 to a slave node 110 that is a reception side node via a packet network 130. Note that the section from the master node 100 to the packet network 130 and the section from the packet network 130 to the slave node 110 are both connected by a network using the TDM method.
- a time stamp method is used to perform synchronization control of the TDM flow between the master node located at the ingress edge and the slave node located at the egress edge via the packet network 130.
- the master node 100 corresponding to the transmission side node transmits the packet 120 storing the time stamp (hereinafter referred to as “TS”) to the slave node 110 corresponding to the reception side node.
- TS is a value indicating time information generated based on the clock of the master node 100 or the slave node 110.
- it is a numerical value that increases by 1 in the minimum time unit (for example, 125 usec) of the clock of the master node 100, and it can be said that the numerical value in this minimum time unit is the clock width.
- the clocks being synchronized means that the clock width of the master node is equal to the clock width of the slave node.
- the above-mentioned minimum time unit of the clock can also be regarded as the clock speed. In this case, it can be said that the clock is synchronized when the clock speed of the master node is equal to the clock speed of the slave node.
- a packet 120 is a packet group transmitted from the master node 100 at a certain interval, and packets 120-1, 120-2, 120-3, 120-4, 120- are transmitted in the order transmitted from the master node. 5
- Each packet of the packet 120 stores the TS at the master node at the time of transmission, the TS of the packet 120-1 is 1, the TS of the packet 120-2 is 2, the TS of the packet 120-3 is 3, The TS of 120-4 is 4, and the TS of the packet 120-5 is 5.
- the packet 120 arrives at the slave node 110 via the packet network 130 (see the upper part of FIG. 1).
- the slave node 110 attempts to synchronize the clock of the slave node 110 with the clock of the master node 100 by adjusting the clock width according to the interval of the packets 120 received from the master node 100. For example, consider a case where TS increases by 1 every 125 usec in the clock of the master node 100 in FIG. That is, the clock width of the master node 100 is 125 usec. However, the clock width of the slave node 110 is not necessarily 125 usec and may be different.
- the TSs of the packets 120-1 and 120-2 are 1 and 2, respectively, and the interval between both packets is 1 in TS, which is equal to 125 usec, which is the clock width of the master node 100.
- the slave node 110 recognizes 1 which is the difference between the TSs of the packet 120-1 and the packet 120-2 as the minimum time unit of the clock of the master node 100, that is, 125 usec. Therefore, even when the clock width of the slave node 110 is different from the clock width of the master node 100 (125 usec in this example), the slave node 110 synchronizes with the clock width of the master node 100 (125 usec in this example). be able to.
- a delay occurs in the reception timing at the slave node 110 due to the packet 120 passing through the packet network 130.
- the TS in the clock of the slave node when passing through the packet network 130 and arriving at the slave node 110 is 1 for the packet 120-1 and 3 for the packet 120-2.
- the packet 120-2 is delayed by 1 from the TS.
- the slave node 110 recognizes that the difference between TSs of the packet 120-1 and the packet 120-2 is 250 usec in the minimum time unit of the clock of the master node 100. Therefore, the slave node 110 adjusts the clock width so that the minimum time unit of the clock is 250 usec.
- the clock width of the master node 100 is 125 usec, whereas the clock width of the slave node 110 is 250 usec, and the clock width is different. At this time, it is said that the master node 100 and the slave node 110 are not synchronized.
- the TS method is a method in which the slave node 110 that has received the packet 120 synchronizes with the clock of the master node 100 by adjusting its own clock using the stored TS as described above. While describing the configuration of the slave node 110, the clock synchronization operation in the TS method will be described in more detail.
- the slave node 110 includes a packet receiving unit 146 and a phase locked loop (PLL) 140.
- the packet receiving unit 146 receives the packet 120 transferred from the master node 100 via the packet network 130.
- the received packet 120 is sent to the PLL 140.
- the PLL 140 generates a TS (hereinafter referred to as “generated TS”) based on the clock of the slave node 110 when receiving the packet 120 from the master node 100 and a TS (
- the difference from the “received TS” is calculated, and the PLL 140 adjusts its own clock based on the difference, thereby realizing clock synchronization.
- generated TS hereinafter, the difference from the “received TS” is calculated, and the PLL 140 adjusts its own clock based on the difference, thereby realizing clock synchronization.
- a phase comparator 141 a low pass filter (Low Pass Filter: LPF) 142 , a proportional / integration (Proportion Integration: PI) circuit 143 , a voltage controlled oscillator (Voltage)
- VCO control Oscillator
- the phase comparator 141 calculates a difference signal between the received TS and the TS generated from the clock of the slave node 110. This difference signal is input to the LPF 142.
- the LPF 142 attenuates a frequency signal higher than a specific threshold value and blocks it, and passes only a low frequency as a signal, thereby removing jitter and noise generated in the differential signal by passing through the packet network 130.
- the differential signal smoothed by the LPF 142 is input to the PI circuit 143.
- the PI circuit 143 calculates a control signal that finally converges the difference signal to zero and outputs the control signal to the VCO 144.
- the VCO 144 outputs a clock having a frequency determined by a control signal from the PI circuit 143.
- the clock width (interval) on the slave side is adjusted.
- the counter 145 generates a TS on the slave side based on the adjusted clock and passes it to the phase comparator 141.
- the slave node 110 can reproduce the clock of the master node 100 and synchronize with the master node 100 even via the packet network 130.
- the amount of delay D generated in the network is the received TS (generated TS: Ts) generated based on the clock of the slave node when the packet arrives at the slave node. It is obtained by the difference from the TS (received TS: Tm) stored in the packet. Therefore, at the time of arrival of the packet that arrives at the slave node by passing through the fluctuating network, a delay occurs between the received TS and the TS at which the packet actually arrives at the slave node, Some packets have a large delay until reaching the slave node.
- the LPF in the slave node performs a process for leveling the randomness of the generated delay amount, and a process for reducing the influence thereof.
- a packet filter function that performs packet filtering processing according to the delay amount of packets arriving at the slave node from the master node is used. This packet filter function is described in Patent Document 3, for example.
- FIG. 2 shows an example of the delay amount distribution.
- the delay amount is distributed from almost zero to several hundred microseconds.
- a filtering process is performed in which a threshold value is set for the delay amount, a TS of a packet whose delay amount is smaller than the threshold value is adopted, and a TS of a large packet is not adopted.
- FIG. 3 shows a slave node 310 having a packet filter unit.
- a packet filter unit 350 is added to the slave node 110 in FIG.
- the packet filter unit 350 receives a packet arriving from the master node from the packet receiving unit 146, and receives a received TS (hereinafter referred to as “Tm”) stored in the packet, and a slave node when the packet arrives.
- Tm received TS
- the delay amount D is obtained from the TS generated by itself (hereinafter referred to as “Ts”).
- Ts the delay amount D is smaller than the predetermined threshold Dth, the TS of the packet is adopted, and when it is larger, the TS of the packet is not adopted.
- a process of passing the TS of the packet to the PLL 140 is performed.
- FIG. 4 shows a packet timing flow when the packet filter function is used.
- a time axis 401 indicates a time axis indicating packet transmission timing to the slave node in the master node.
- a packet 405 is transmitted.
- a clock 402 (hereinafter referred to as “master clock 402”) in the master node is shown below the time axis 401.
- master clock 402 in the master node is shown below the time axis 401.
- the packet 405 is transmitted at the timing when the TS of the master clock 402 is 55. Therefore, the packet 405 stores a value of 55 as TS.
- a time axis 403 in the slave node and a clock 404 of the slave node (hereinafter referred to as “slave clock 404”) are shown below.
- the TS of the master clock 402 and the TS of the slave clock 404 are different at a certain same time.
- the TS of the master clock 402 is 70
- the TS is different such that the slave clock 404 is 67.
- the master clock 402 and the slave clock 404 have the same clock width.
- the clock in a state like the slave clock 404 is hereinafter referred to as “synchronized slave clock”.
- slave clock 404 In order for the slave clock to be in a synchronized state, it is necessary that the clock width of the slave clock and the clock width of the master clock match.
- the operation of the slave clock that is not synchronized with the master clock in the TS method will be described with reference to the clock of the slave node in a synchronized state (indicated as “slave clock 404” in FIG. 4).
- the packet 405 transmitted by the master node when the TS of the master clock 402 is 55 is transmitted at the slave node.
- the slave clock 404 arrives when TS is 55.
- a packet 407 indicates a packet that arrives when the above-described TS is 59 in the slave clock 404 due to the addition of the delay amount 4 via the packet network.
- the value of the time stamp of the clock of the slave node when the packet transmitted by the master slave arrives at the slave node is referred to as packet arrival timing.
- the delay amount D is obtained from the difference between the received TS and the generated TS, and the filtering process is executed under the condition including the threshold value Dth. It is possible to perform clock synchronization control by selectively adopting only TS of smaller packets.
- the clock synchronization control can be performed using the packet filter function by the method described with reference to FIG.
- FIG. 4 the case where the master clock 402 and the slave clock 404 are completely synchronized and the slave clock 404 is in the synchronized state has been described as an example.
- the purpose is to synchronize by applying synchronization control from the situation that is not.
- the master node clock and the slave node clock are not synchronized, there are the following problems.
- FIG. 5 shows that when the master clock 402 and the slave node clock 501 (hereinafter referred to as “slave clock 501”) are not synchronized with the timing flow shown in FIG.
- FIG. 10 is a diagram in which a timing flow in the case of being smaller than a master clock 402 is added.
- the slave node in addition to the master node time axis 401, master clock 402, slave node time axis 403, and synchronized slave clock 404 shown in FIG. 4, the slave node is not synchronized with the master node.
- a slave clock 501 is added.
- the slave clock 501 has a smaller clock width than the slave clock 404. Therefore, the slave node is not synchronized with the master node.
- the slave clock 404 is in a synchronized state, as described above, the TS of the master clock 402 and the TS of the slave clock 404 are different at a certain same time. As an example, when the TS of the master clock 402 is 70, the TS is different such that the TS of the slave clock 404 is 67.
- the TS value of the slave clock 501 not in the synchronized state is 64 at the time of the TS value 55 (illustrated as the packet 406) when the packet is received from the master node. ing.
- timestamp deviation (hereinafter referred to as“ TS deviation ”) in the present invention.
- TS deviation ⁇ the TS deviation ⁇ is ⁇ 9.
- the slave clock 601 is not synchronized with the master node by the slave node, and the slave clock 601 has a larger clock width than the slave clock 404.
- the delay amount D is not included in the slave clock 404 in the synchronized state (packet 406, TS is 55)
- TS is 49.
- the slave clock when the clocks of the master node and the slave node are not synchronized, the slave clock includes a TS deviation ⁇ with respect to the synchronized slave clock. Therefore, since the TS deviation ⁇ is also included in the generated TS (Ts) generated at the timing when the packet arrives at the slave node, the delay amount cannot be calculated appropriately on the slave node side. As a result, when performing packet filter processing, filter processing that appropriately adopts TS of packets whose delay amount exceeds a predetermined threshold cannot be performed, and as a result, the master clock and the slave clock are synchronized. There is a problem that it cannot be done.
- the object of the present invention is the above-described problem.
- a master node transmits a packet to a slave node via a packet network and performs packet filter processing on the slave node side, a packet whose delay amount exceeds a predetermined threshold value.
- a clock synchronization system, method, apparatus, and program for solving the problem that filter processing that appropriately employs TS cannot be performed and, as a result, master clock and slave clock cannot be synchronized. There is.
- the clock synchronization system of the present invention is a clock synchronization system that synchronizes the clock of the slave node with the clock of the master node.
- the master node includes packet transmission means for transmitting a packet including a time stamp to the slave node.
- the slave node includes packet reception means, packet filter means, and phase synchronization means.
- the packet receiving means receives the packet transmitted from the master node.
- the packet filter means calculates a difference between a clock time stamp of the slave node at the time of reception of the packet and a time stamp of the received packet as a delay value of the packet, and the delay value of the packet or the packet And a filtering process is performed on the packet received from the packet receiving unit based on the packet delay value and the packet delay threshold.
- the phase synchronization means outputs a clock of the slave node based on a time stamp included in the packet adopted by the packet filter means.
- the node of the present invention is a node that synchronizes the clock of its own node with the clock of the master node.
- the node includes packet reception means, packet filter means, and phase synchronization means.
- the packet receiving means receives a packet including a time stamp from the master node via a network.
- the packet filter means calculates a difference between a time stamp of a clock of the own node at the time of reception of the packet and a time stamp of the received packet as a delay value of the packet, and the delay value of the packet or the packet And a filtering process is performed on the packet received from the packet receiving unit based on the packet delay value and the packet delay threshold.
- the phase synchronization means outputs a clock of its own node based on a time stamp included in the packet adopted by the packet filter means.
- the clock synchronization method of the present invention is a clock synchronization method for synchronizing the clock of the slave node with the clock of the master node, and includes a packet reception step, a delay calculation step, a correction step, and a packet filter step.
- a packet receiving step a packet including a time stamp is received via the network.
- a delay calculating step a difference between the time stamp of the clock of the slave node at the time of receiving the packet and the time stamp of the received packet is calculated as a delay value of the packet.
- the correction step a delay value of the packet or a threshold value related to the delay of the packet is corrected.
- a filtering process is performed on the packet received from the packet receiving unit based on a delay value of the packet and a threshold value related to the delay of the packet.
- the clock of the slave node is output based on the time stamp included in the packet adopted in the packet filter step.
- the program of the present invention is a program for synchronizing the clock of the slave node with the clock of the master node, and includes a packet reception process, a packet filter process, and a phase synchronization process.
- the packet reception process executes a process of receiving a packet including a time stamp from the master node via a network.
- the packet filtering process calculates a difference between the time stamp of the slave node clock at the time of reception of the packet and the time stamp of the received packet as a delay value of the packet, and the packet delay value or the packet And a filter processing is performed based on the corrected delay value of the packet and the threshold value of the packet delay.
- the phase synchronization process executes a process of outputting a clock of the slave node based on a time stamp included in the packet adopted in the packet filter step.
- the delay amount of the packet arriving on the slave node side is accurately calculated, and the packet whose delay amount exceeds a predetermined threshold
- the packet filter process appropriately adopting the TS can be performed, and the master clock and the slave clock can be synchronized.
- FIG. 3 is an example of a detailed configuration diagram of a general packet filter unit 350.
- FIG. It is an example of the detailed block diagram of the packet filter part 912 in the case of using the 1st correction method of this invention. It is an example of the detailed block diagram of the packet filter part 912 in the case of using the 2nd correction method of this invention.
- the slave node performs TS processing based on the timing under the slave clock including the TS deviation ⁇ , not the synchronized slave clock. is there. Therefore, in the present invention, in consideration of the TS shift ⁇ of the slave clock that is not synchronized with respect to the slave clock that is synchronized, the delay of the arrival timing of the packet of the slave clock that is not synchronized with respect to the arrival timing of the packet of the slave clock that is not synchronized.
- the above-mentioned problem is solved by correcting the threshold of the amount or delay amount set in advance and matching the arrival timing of the slave clock packet with the arrival timing of the slave clock packet in the synchronized state.
- FIG. 7 shows an example where the clock width of the slave clock 501 is smaller than the clock width of the master clock 402 as in FIG. 5, and the slave node and the master node are not synchronized.
- the TS of the arrival timing of the packet 406 at the synchronized slave clock 404 is 55, and the TS of the packet 706 under the slave clock 501 that is not synchronized at the same time is 64, and the arrival timing of the packet 406 The shift is -9.
- This packet 706 indicates a packet whose arrival timing is the same as the arrival timing of the packet 406 in the slave clock 404.
- the packet filtering process can be performed with the same filter width as that of the slave clock 404.
- FIG. 8 shows an example in which the clock width of the slave node is larger than the clock width of the master node as in FIG. 6, and the slave node and the master node are not synchronized.
- the arrival timing TS of the packet 406 at the slave clock 404 in the synchronized state is 55, and the arrival timing TS of the packet 806 under the slave clock 601 that is not in the synchronized state at the same time is 49. +6 shift from the arrival timing.
- This packet 806 indicates a packet whose arrival timing is the same as the arrival timing of the packet 406 in the slave clock 404. This packet 806 indicates a packet whose arrival timing is the same as the arrival timing of the packet 406 in the slave clock 404.
- the overall configuration of the embodiment of the present invention includes a master node 900, a slave node 910, and a packet network 130.
- the master node 900 and the slave node 910 are configured as follows.
- the master node 900 includes a packet generation unit 901 and a packet transmission unit 902.
- the packet generation unit 901 generates a packet 120 in which a TS for performing clock synchronization is stored.
- the packet transmission unit 902 periodically transmits the packet 120 generated by the packet generation unit 801 to the slave node 910.
- the slave node 910 includes a packet reception unit 911, a packet filter unit 912, a PLL (Phased Locked Loop) 140, a filter control unit 914, a synchronization accuracy monitor unit 915, and a packet counter 916.
- the packet receiving unit 146 receives the packet 120 transferred from the master node 900 via the packet network 130.
- the received packet 120 is sent simultaneously to the packet filter unit 912 and the packet counter 916 (a copy of the packet 120 may be sent to one side).
- the packet filter unit 912 calculates the delay amount D from the difference between the received TS stored in the packet 120 received from the packet receiving unit 146 and the generated TS generated by the counter 145, and sets a preset threshold Dth and delay amount D.
- the TS of the received packet 120 is decided to be adopted or discarded, and the packet 120 adopting the TS is sent to the PLL 140. Further, by adjusting the delay amount D or the threshold value Dth according to the control information received from the filter control 914, more appropriate packet discard processing is performed.
- the packet filter unit 912 may be activated from the start of transmission / reception of the packet 120 with the master node 600. In order to reduce the time until stabilization, all packets are captured without being activated at first, You may start it after it stabilizes to some extent. Generally, when the number of packets taken into the PLL 140 is reduced, it takes time until stabilization. When the packet filter unit 912 is activated, packets with a delay greater than a certain value are discarded, and the number of adopted packets is reduced. However, if a packet with a large delay is captured, there is a possibility that sufficient synchronization accuracy cannot be obtained as described above.
- the packet filter unit 912 captures all the packets without being activated until a certain level of stability is obtained, and when the level is stabilized to a certain extent, the packet filter unit 912 is activated to discard a packet with a large delay, so that the synchronization accuracy is not changed. Can be shortened.
- the PLL 140 includes a phase comparator 141, a low pass filter (LPF) 142, a proportional / integration (Proportion Integration: PI) circuit 143, a voltage controlled oscillator (Voltage Control Oscillator: VCO) 144, and a counter 145.
- the configuration is the same as that of the PLL 140 included in the slave node of FIG. This configuration is merely an example. Even if the configuration is different from this, the difference between the TS generated from the clock of the slave node 910 itself and the TS received from the master node 900 is calculated, and the clock of the slave node 910 itself is adjusted based on the difference. If possible, the configuration is not limited to this configuration.
- the phase comparator 141 calculates a difference signal between the received TS stored in the packet 120 received from the packet filter unit 912 and the TS generated by the counter 145 and outputs the difference signal to the LPF 142.
- the LPF 142 leveles the differential signal, suppresses jitter and noise, and outputs the result to the PI circuit 143.
- the PI circuit 143 generates a control signal such that the leveled difference signal finally becomes zero and outputs the control signal to the VCO 144.
- the VCO 144 generates a clock having a frequency determined by the input control signal and outputs it to the counter 145. Further, the counter value of the packet counter 916 is decreased according to the generated frequency clock.
- the counter 145 generates a TS based on the clock and transfers it to the phase comparator 141 and the packet filter unit 912.
- the packet counter 916 increases the counter value by a predetermined value every time the packet 120 is received from the packet receiving unit 146. At the same time, the counter value is decreased according to the frequency determined by the VCO 144.
- the packet counter 916 may be a packet buffer. In the case of the packet buffer, when the packet 120 is received from the packet receiving unit 146, the packet 120 is accumulated in the buffer, and at the same time, the accumulated packet is output according to the frequency determined by the VCO 144.
- the synchronization accuracy monitor unit 915 includes a synchronization accuracy measurement unit 915-1 and a counter value increase / decrease information acquisition unit 915-2.
- the synchronization accuracy measuring unit 915-1 measures the synchronization accuracy between the master node 900 and the slave node 910.
- any method such as a method using a packet counter, which will be described later, or a method using a device for measuring the synchronization accuracy may be used.
- a method using a packet counter will be described as an example of a method for measuring synchronization accuracy.
- the operation of the synchronization accuracy measuring unit 915-1 in this method will be described below.
- the synchronization accuracy measuring unit 915-1 monitors the counter value of the packet counter 916. Then, the maximum counter value Counter_Max [t] in the interval t is obtained.
- the synchronization accuracy measuring unit 915-1 that has obtained the counter maximum value Counter_Max [t] calculates the difference amount Deviation [t] between the counter maximum value Counter_Max [t] and the counter reference value Counter_Ref in the interval.
- the formula at this time is as follows.
- Deviation [t] Counter_Max [t] ⁇ Counter_Ref
- This difference amount Deviation [t] represents the variation amount of the above-mentioned counter maximum value.
- the counter reference value Counter_Ref is a value indicating a counter value at the start of measurement, a predetermined counter value, or both.
- the counter value increase / decrease information acquisition unit 915-2 monitors the increase / decrease status of the counter value of the packet counter 916. Thereafter, the synchronization accuracy information and the counter value increase / decrease information obtained by the synchronization accuracy measuring unit 915-1 and the counter value increase / decrease information acquiring unit 915-2 are notified to the filter control unit 914.
- the filter control unit 914 corrects the threshold value Dth of the packet filter unit 912 or the delay amount D calculated by the packet filter unit 912 based on the synchronization accuracy information received from the synchronization accuracy monitor unit 915 and the increase / decrease information of the packet counter 916.
- the shift ⁇ is calculated, and the result is notified to the packet filter unit 912. A method for calculating the TS deviation ⁇ will be described below.
- the arrival of the packet at the slave clock that is not synchronized with respect to the arrival timing of the packet at the slave clock that is synchronized is corrected.
- the packet TS filtering process is performed at the same timing as the arrival timing of the packet in the synchronized slave clock by matching the arrival timing of the packet in the slave clock with the arrival timing of the synchronized slave clock. Yes.
- step S11 the filter control unit 914 receives synchronization accuracy information between the master / slave nodes from the synchronization accuracy monitoring unit 915 at predetermined intervals.
- the increase / decrease information of the counter value of the packet counter 916 is received.
- the acquisition method of the synchronization accuracy information in the synchronization accuracy measurement unit 915-1 of the synchronization accuracy monitor unit 915 is not particularly limited as described above.
- An example of a method for acquiring the increment / decrement information of the counter value in the counter value increase / decrease information acquisition unit 915-2 will be described later.
- the filter control unit 914 first receives the synchronization accuracy and counter value increase / decrease information (step S11). Subsequently, the filter control unit 914 calculates a TS deviation ⁇ from the synchronization accuracy received in step S12.
- the synchronization accuracy obtained by the synchronization accuracy measuring unit 915-1 is Xppb
- the preset time stamp value per 1 sec is L (TS) in the clock of the master node, and the synchronization is determined in advance. If the interval for calculating the accuracy is Y sec, a deviation occurs at a rate of X ppb with respect to L ⁇ Y (TS). Therefore, the TS deviation can be expressed by the following equation.
- step S12 the filter control unit 914 that has calculated the TS deviation ⁇ determines the sign of the TS deviation ⁇ as shown in (1) and (2) below from the increment / decrement information of the counter value received in step S11. (Step S13). Details of the following (1) and (2) will be described later.
- the filter control unit 914 that has determined the sign of the TS deviation ⁇ in step S13 finally transmits the TS deviation amount + ⁇ or ⁇ to the packet filter unit 912 in step S14.
- the packet filter unit 912 will be described.
- the packet filter unit 350 as shown in FIG. 3 executes packet filtering under the condition of 0 ⁇ D ⁇ Dth.
- the packet filter unit 912 of the present invention corrects the TS of the packet received from the master node by using the TS deviation ⁇ received from the filter control unit 914.
- the present invention proposes two methods, a method of correcting the delay amount D and a method of correcting the delay threshold value Dth. In the present embodiment, a method for correcting the delay amount D will be described.
- the correction method in the present embodiment is a method for correcting the delay amount D.
- a flowchart of this method is shown in FIG.
- step S21 the packet filter unit 912 obtains a delay D considering the TS deviation by adding a TS deviation ⁇ to the generated TS (Ts).
- D (Ts + ⁇ ) ⁇ Tm
- the packet filter unit 912 determines whether or not the delay amount D obtained in step S21 is not less than 0 and not more than the threshold value Dth (step S22).
- step S22 if the delay amount D is not less than 0 and not more than the threshold value (Yes in step S22), the packet filter unit 912 proceeds to step S23 and performs a process of adopting the TS of the packet. On the other hand, if the delay amount D does not satisfy the condition of step S22 (No in step S22), the packet filter unit 912 proceeds to step S24 and performs a process of not adopting the TS of the packet.
- the correction method in the present embodiment is a method of correcting the delay amount D.
- a packet TS is adopted when the following condition is satisfied. 0 ⁇ (Ts + ⁇ ) ⁇ Tm ⁇ Dth
- a configuration of the packet filter unit 912 for realizing the correction method will be described.
- the packet filter unit 350 includes a subtractor 1101 and a comparator 1100.
- the subtractor 1101 the difference between the generated TS (Ts) input from the counter 145 and the received TS (Tm) input from the master node 100 is calculated and input to the comparator 1100.
- Comparator 1100 performs comparison calculation according to the following filter conditions (1) to (3) consisting of threshold value Dth and difference information Ts ⁇ Tm set by a setting interface (hereinafter referred to as “setting IF”).
- the filtering process is performed in accordance with the filter condition corresponding to the TS of the packet.
- the setting IF refers to an interface for performing various settings of the slave node such as an interval for calculating synchronization accuracy and a threshold Dth on a GUI (Graphical User Interface), for example.
- the packet TS is adopted and transferred to the PLL 140.
- FIG. 12 shows the configuration of the packet filter unit 912 of the correction method.
- the packet filter unit 912 includes a subtractor 1101, a comparator 1100, and an adder 1200.
- the difference from the packet filter unit 350 is that the adder 1200 adds the TS deviation ⁇ received from the filter control unit 914 to the generated TS (Ts).
- Ts the generated TS
- the addition information (Ts + ⁇ ) is input to the subtractor 1101, and the difference between the addition information (Ts + ⁇ ) and the received TS (Tm) input from the master node 100 is calculated and input to the comparator 1100.
- the comparator 1100 performs comparison calculation according to the following filter conditions (1) to (3) consisting of the threshold value Dth set by the setting IF and the difference information (Ts + ⁇ ) ⁇ Tm, and the TS of the packet follows the corresponding filter condition And filter processing.
- the counter value increase / decrease information acquisition method of the packet counter 916 in the counter value increase / decrease information acquisition unit 915-2 will be described with two examples. Note that, as described above, the acquisition method described below is an example, and any method may be used for acquiring the increase / decrease information of the counter value.
- the simplest method is a method of acquiring the counter value of the packet counter 916 at the timing of acquiring the synchronization accuracy information in the synchronization accuracy monitor unit 915 and comparing it with the previously acquired counter value.
- a method may be used in which an average value of counter values during an interval of timing for acquiring synchronization accuracy information is calculated and compared with the previous average value.
- Counter value increase / decrease information acquisition method second method> If the first method is used as the counter value increase / decrease information acquisition method of the counter value increase / decrease information acquisition unit 915-1 in FIG. 9, the influence of the delay added when the packet 120 is transferred through the packet network 130. Therefore, there arises a problem that the increase or decrease in the counter value may not accurately represent the difference in clock width. Therefore, a method that is less susceptible to delay will be described below, including the problems of the first method.
- FIG. 14 shows the counter value of the packet counter 916 when the clock of the slave node is accurately synchronized with the clock of the master node and the amount of delay added to the packet is always 0 in the packet network. Yes.
- the horizontal axis direction is the elapsed time, and the vertical axis direction is the counter value.
- FIG. 15 shows the counter value when the slave clock and the master clock are accurately synchronized but there is a delay added to the packet in the packet network.
- FIGS. 16 and 17 show counter values when the slave clock and the master clock are not synchronized and there is a delay added to the packet in the packet network.
- FIG. 16 as an example where the slave clock and the master clock are not synchronized, a case where the clock width of the slave clock is smaller than the clock width of the master clock is shown.
- FIG. 17 shows a case where the clock width of the slave clock is larger than the clock width of the master clock.
- the maximum value of the counter value is a constant value.
- the counter value When the packet arrives at the packet counter 916, the counter value increases by a predetermined value. On the other hand, the counter value is subtracted according to the speed at which the VCO 144 outputs a clock. In this example, a predetermined counter value for one packet is subtracted according to the interval at which the packets arrive. In the example of FIG. 14, since the slave clock and the master clock are synchronized, the counter value is repeatedly increased and decreased at regular intervals of the packet arrival interval, and the maximum value of the counter when increased and the minimum value of the counter when decreased The value is constant.
- FIG. 15 shows a case where the slave clock and the master clock are synchronized and a delay is added in the packet network. Since the delay is added, the arrival of the packet is delayed, and the subtraction amount of the counter value is increased by the delay amount, and the lower limit value of the counter value is smaller than the example of FIG. Therefore, the counter value at the time of packet arrival is not constant as in the example of FIG. 14, and there are places where it is smaller than the others. However, when a packet without delay arrives, the counter value reaches the value that should be originally reached (the maximum value of the counter). If it is considered that a packet without a delay is received during an interval (for example, 10 seconds), the maximum value of the counter value is constant during the interval.
- an interval for example, 10 seconds
- the slave clock and the master clock are synchronized, for example, at a certain interval (for example, a time when one non-delayed packet is expected to arrive).
- a certain interval for example, a time when one non-delayed packet is expected to arrive.
- the counter value fluctuates depending on the delay of the received packet at the timing of the boundary of the interval for acquiring the synchronization accuracy information. Therefore, regarding the amount of change in the counter value compared to the time when the previous synchronization accuracy measurement was performed, the effect of the difference due to the delay amount is greater than the difference due to the clock width difference (speed difference) between the master clock and the slave clock. There is a big possibility. Therefore, the difference (speed difference) between the clock widths of the master clock and the slave clock may not be reflected in the fluctuation of the counter value.
- an average value of counter values in a certain interval can be adopted and a method can be used that uses only the received packet at the boundary timing. According to the method, although the influence of the delay amount can be reduced compared with the above-described method, for example, if the delay amount tends to be large in a certain interval, the average value becomes lower as a whole. The amount of delay may be affected.
- FIGS. 16 and 17 are cases in which the slave clock and the master clock are not synchronized.
- FIG. 16 shows a case where the clock width of the slave clock is smaller than the clock width of the master clock. Similar to the example of FIG. 15, there is a portion where the counter value does not reach the maximum value when the packet arrives due to delay of packet arrival due to the delay. However, the maximum value is reached when a packet without delay arrives. The difference from FIG. 15 is that the counter maximum value for each interval fluctuates.
- the clock width of the slave clock is smaller than the clock width of the master clock. This is synonymous with the fact that the output speed of the slave clock is slower than the output speed of the master clock. Therefore, since the subtraction speed of the packet counter existing in the slave node is slower than the increase speed, the counter value gradually increases. Therefore, the maximum value of the counter value for each interval increases with time.
- FIG. 17 shows a case where the clock width of the slave clock is larger than the clock width of the master clock. This is synonymous with the speed of the slave clock being higher than the speed of the master clock. Therefore, regarding the fluctuation of the counter maximum value for each interval, which is the difference from FIG. 15, the counter value gradually decreases because the subtraction speed of the packet counter is faster than the increase speed. Therefore, the maximum value of the counter value for each interval decreases with time.
- the maximum counter value is monitored, and it can be seen from the fluctuation of the maximum value for each interval whether the slave clock and master clock are synchronized. That is, it can be seen that if the counter maximum value is constant, it is synchronized, and if it is fluctuated, it is not synchronized. If the counter maximum value is increasing, the slave clock width is smaller than the master clock, and if the counter maximum value is decreasing, the slave clock width is the master clock clock. It can be seen that it is larger than the width. When this method is used, the influence of delay can be eliminated, so that the situation of the speed difference can be grasped more accurately.
- the synchronization accuracy monitoring unit 915 measures the maximum counter value of the packet counter 916 at every interval, and notifies the filter control unit 914 of the increase / decrease information of the maximum counter value.
- the influence of delay can be eliminated and the TS deviation between the master clock and the slave clock can be grasped more accurately.
- the filter control unit calculates the TS deviation by using the synchronization accuracy information acquired by the synchronization accuracy monitor unit and the increase / decrease information of the counter value of the packet counter.
- the packet filter unit corrects the arrival timing of the slave clock to the arrival timing of the synchronized slave clock by correcting the delay amount D by using the TS deviation.
- the slave node processes the generated TS and received TS, calculates the delay amount of the packet that arrived on the slave node side, and appropriately selects the TS of the packet according to the set threshold Can be hired.
- the synchronization accuracy can be improved by adopting only the TS of the packet with a small delay amount into the clock synchronization circuit without adopting the TS of the packet with a large delay amount.
- the counter value increase / decrease information acquisition unit by using the second method of the counter value increase / decrease information acquisition method described above, it is possible to eliminate the influence of delay, and more accurately between the master clock and the slave clock. There is an effect that TS deviation can be grasped.
- the packet filter unit 912 further obtains a delay amount D considering the TS deviation by subtracting a value obtained by subtracting the TS deviation ⁇ from the received TS (Tm) from the generated TS (Ts).
- D Ts ⁇ (Tm ⁇ )
- the packet filter unit 912 determines whether or not the delay amount D obtained in step S31 is not less than 0 and not more than the threshold value Dth (step S32).
- step S32 if the delay amount D is greater than or equal to 0 and less than or equal to the threshold (Yes in step S32), the packet filter unit 912 proceeds to step S33 and performs a process of adopting the TS of the packet. On the other hand, if the delay amount D does not satisfy the condition of step S32 (No in step S32), the packet filter unit 912 proceeds to step S34 and performs a process of not adopting the TS of the packet.
- the TS of the packet 606 is adopted according to step S33.
- a method of correcting the delay amount D different from that in the first embodiment is used.
- a packet TS is adopted when the following condition is satisfied.
- the configuration of the packet filter unit 912 for realizing the above correction method will be described with reference to FIG.
- the packet filter unit 912 includes subtracters 1101 and 1102 and a comparator 1100.
- the difference from the packet filter unit 350 is that the subtractor 1101 calculates the difference between the TS deviation ⁇ received from the filter control unit 914 and the received TS, and the subtractor 1102 subtracts the difference obtained from the generated TS. It is. By this process, the generated TS is corrected.
- the subtraction information (Tm ⁇ ) is input to the subtractor 1101, and the difference between the subtraction information (Tm ⁇ ) and the generated TS (Ts) input from the master node 100 is calculated and input to the comparator 1100.
- the comparator 1100 performs a comparison calculation according to the following filter conditions (1) to (3) including the threshold value Dth set by the setting IF and the difference information Ts ⁇ (Tm ⁇ ), and the filter to which the TS of the packet corresponds Filtering is performed according to the conditions.
- the filter control unit calculates the TS deviation using the synchronization accuracy information acquired by the synchronization accuracy monitor unit and the increase / decrease information of the counter value of the packet counter.
- the packet filter unit corrects the arrival timing of the slave clock to the arrival timing of the synchronized slave clock by correcting the delay amount D by using the TS deviation.
- the slave node processes the generated TS and received TS, calculates the delay amount of the packet that arrived on the slave node side, and appropriately selects the TS of the packet according to the set threshold Can be hired.
- the synchronization accuracy can be improved by adopting only the TS of the packet with a small delay amount into the clock synchronization circuit without adopting the TS of the packet with a large delay amount.
- the correction method in the present embodiment is a method for correcting the threshold value Dth in the packet filter unit. By subtracting the TS deviation ⁇ from the threshold Dth, the threshold Dth considering the TS deviation can be obtained.
- the packet filter unit 912 corrects the delay amount threshold value Dth.
- a packet TS is adopted when the following condition is satisfied. ⁇ ⁇ Ts ⁇ Tm ⁇ Dth ⁇
- FIG. 13 shows the configuration of the packet filter unit 912 of the present embodiment.
- the packet filter unit 912 includes a subtractor 1101, a comparator 1100, and a subtracter 1300.
- the difference from the general packet filter unit 350 is that the subtractor 1300 subtracts the TS deviation ⁇ received from the filter control unit 914 from the threshold value Dth. This operation indirectly corrects the generated TS.
- the generated TS (Ts) received from the counter 145 and the received TS (Tm) received from the packet receiving unit 911 are input to the subtractor 1101, and a difference Ts ⁇ Tm is calculated and input to the comparator 1100.
- the threshold value Dth set by the setting IF and the TS deviation ⁇ input from the filter control unit 914 are input to the subtractor 1200, and the difference Dth ⁇ is calculated and input to the comparator 1100.
- the comparator 1100 performs a comparison calculation according to the following filter conditions (1) to (3) consisting of the difference information Dth ⁇ relating to the threshold Dth and the difference information Ts ⁇ Tm relating to TS, and the filter condition to which the TS of the packet corresponds.
- the filter process is performed according to the above.
- the filter control unit calculates the TS deviation using the synchronization accuracy information acquired by the synchronization accuracy monitor unit and the increase / decrease information of the counter value of the packet counter.
- the packet filter unit corrects the arrival timing of the slave clock to the arrival timing of the synchronized slave clock by correcting the delay amount D by using the TS deviation.
- the slave node processes the generated TS and received TS, calculates the delay amount of the packet that arrived on the slave node side, and appropriately selects the TS of the packet according to the set threshold Can be hired.
- the synchronization accuracy can be improved by adopting only the TS of the packet with a small delay amount into the clock synchronization circuit without adopting the TS of the packet with a large delay amount.
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Abstract
Description
110、310 スレーブノード
120(120-1、2、3、4、5)、405、406、407、506、606、706、806 パケット
130 パケットネットワーク
140 PLL
141 位相比較器
142 LPF
143 PI回路
144 VCO
145 カウンタ
146 パケット受信部
350、912 パケットフィルタ部
401 マスタノードの時間軸
402 マスタクロック
403 スレーブノードの時間軸
404、501、601 スレーブクロック
901 パケット生成部
902 パケット送信部
914 フィルタ制御部
915 同期精度モニタ部
916 パケットカウンタ
1100 比較器
1101、1102、1300 減算器
1200 加算器
以下、本発明の第一の実施の形態について説明する。
<実施の形態の動作概要>
上述したように、マスタノードのクロックとスレーブノードのクロックが同期していない場合は、スレーブノードのクロックは同期している状態のスレーブクロックに対してTSずれΔを含んでしまう。そのため、スレーブノードにパケットが到着したタイミングで生成される生成TS(Ts)にもTSずれΔが含まれるので、スレーブノード側で遅延量を適切に算出することができない。その結果として、パケットフィルタ処理を行う際、遅延量が所定の閾値を超過するパケットのTSを適切に採用するというフィルタ処理を行うことができないという課題があった。この課題を解決するための本発明の基本的な考え方について、図7及び図8を用いて説明する。
図9の上部分を参照すると、本発明の実施の形態の全体構成は、マスタノード900とスレーブノード910とパケットネットワーク130とからなる。マスタノード900、スレーブノード910は以下のように構成される。
マスタノード900は、パケット生成部901と、パケット送信部902とを備える。パケット生成部901は、クロック同期を行うためのTSが格納されたパケット120を生成する。パケット送信部902は、パケット生成部801で生成されたパケット120をスレーブノード910に対して、定期的に送信する。
スレーブノード910は、パケット受信部911と、パケットフィルタ部912と、PLL(Phased Locked Loop)140と、フィルタ制御部914と、同期精度モニタ部915と、パケットカウンタ916とを備える。
この差分量Deviation[t]は、上述のカウンタ最大値の変動量を表す。なお、カウンタ基準値Counter_Refとは、測定開始時のカウンタ値、予め決められたカウンタ値またはその双方を示す値である。
前述したように、本発明では、同期状態のスレーブクロックに対する、同期状態でないスレーブクロックのTSずれΔを考慮して、同期状態のスレーブクロックにおけるパケットの到着タイミングに対する同期状態でないスレーブクロックにおけるパケットの到着タイミングの遅延量、もしくは、あらかじめ設定された遅延量の閾値を補正する。その後、スレーブクロックにおけるパケットの到着タイミングを同期状態のスレーブクロックの到着タイミングに合わせることにより、同期状態のスレーブクロックにおけるパケットの到着タイミングと同一のタイミングでパケットのTSのフィルタ処理を行うことを特徴としている。これを実現するために、図9の各部の中で特にパケットフィルタ部912とフィルタ制御部914と同期精度モニタ部915の動作がポイントとなる。以降では、フィルタ制御部914の動作を中心に各部の動作を説明する。
D = (Ts + Δ) - Tm
D = (69 - 9) - 55 = 5となる。そして、ステップS22の条件、0≦D≦閾値Dth=8を満たすため、ステップS23に従いパケット506のTSは採用となる。一般的な方法では、D=69-55=14となり、閾値Dth=8よりも大きくなるため、ステップS24に従いパケット506のTSは採用されなかった。これより、本実施の形態における補正により適切にフィルタ処理を行うことができることが分かる。
D = (52 + 6) - 55 = 3となる。そして、ステップS22の条件、0≦D≦閾値Dth=8を満たすため、ステップS23に従いパケット606のTSは採用となる。一般的な方法では、D=52-55=-3となり、閾値0よりも小さくなるため、ステップS24に従いパケット606のTSは採用されなかった。これより、本実施の形態における補正により適切にフィルタ処理を行うことができることが分かる。
上記補正方法を実現するためのパケットフィルタ部912の構成について説明する。
(1) 0 ≦ Ts - Tm ≦ Dth
→パケットのTSを採用し、PLL140に転送する。
(2) Ts - Tm < 0
→パケットのTSは採用しない。
(3)
Dth < Ts - Tm
→パケットのTSは採用しない。
(1) 0 ≦ (Ts + Δ) - Tm≦Dth
→パケットのTSを採用、PLL140に転送する。
(2)
(Ts + Δ) - Tm < 0
→パケットのTSは採用しない。
(3)
Dth < (Ts + Δ) - Tm
→パケットのTSは採用しない。
最も簡単な方法は、同期精度モニタ部915において同期精度情報を取得するタイミングにおけるパケットカウンタ916のカウンタ値を取得し、前回取得したカウンタ値と比較する方法である。また、この応用例として、同期精度情報を取得するタイミングのインターバルの間におけるカウンタ値の平均値を計算しておき、前回の平均値と比較するという方法をとっても良い。これらの方法を用いてカウンタ値の増減情報を得ることにより、マスタ側のクロックとスレーブ側のクロックの幅の大小の情報を得ることが可能である。なお、マスタクロックとスレーブクロックのクロック幅の大小関係は、マスタクロックとスレーブクロックのクロックの速度の大小関係と捉えることもできる。その場合は、クロック幅の差はクロックの速度差といえる。
図9のカウンタ値増減情報取得部915-1のカウンタ値増減情報取得の方法として、上記の第一の方法を用いると、パケット120がパケットネットワーク130を転送される際に付加される遅延の影響により、カウンタ値の増減がクロック幅の差を正確に表さない場合があるという問題が生じる。そのため、遅延の影響を受けにくい方法について、上記の第一の方法の問題点を含めて、以下に説明する。
以上説明したように、本実施の形態によれば、同期精度モニタ部が取得する同期精度情報ならびにパケットカウンタのカウンタ値の増減情報を利用して、フィルタ制御部がTSずれを計算する。パケットフィルタ部はTSずれを利用して、遅延量Dを補正することにより、スレーブクロックの到着タイミングを同期状態のスレーブクロックの到着タイミングに補正する。この補正したタイミングの下で、スレーブノードが生成TS、受信TSの処理を行うことにより、スレーブノード側で到着したパケットの遅延量を算出し、設定した閾値に応じて適切にパケットのTSの選択的採用を行うことが可能になる。その結果、遅延量の大きいパケットのTSを採用せず、遅延量の小さいパケットのTSのみをクロック同期回路に取り込むことにより、同期精度を向上できるという効果がある。
以下、本発明の第二の実施の形態について説明する。本実施の形態の基本的な構成及び動作は第一の実施の形態とほぼ同様であり、相違点はパケットフィルタ部912における遅延量Dの補正方法にある。以下、その遅延量Dの補正方法について説明する。この補正方法のフローチャートを図19に示す。
D = Ts - (Tm - Δ)
D = 69 - (55 - (-9)) = 69 - 64 = 5となる。そして、ステップS32の条件、0≦D≦閾値Dth=8を満たすため、ステップS33に従いパケット506のTSは採用となる。一般的な方法では、D=69-55=14となり、閾値Dth=8よりも大きくなるため、ステップS34に従いパケット506のTSは採用されなかった。これより、本実施の形態における補正により適切にフィルタ処理を行うことができることが分かる。
D = 52 - (55 - 6) = 52 - 49 = 3
となり、ステップS32の条件、0≦D≦閾値Dth=8を満たすため、ステップS33に従いパケット606のTSは採用となる。一般的な方法では、D=52-55=-3となり、閾値0よりも小さくなるため、ステップS34に従いパケット606のTSは採用されなかった。これより、本実施の形態における補正により適切にフィルタ処理を行うことができることが分かる。
上記の補正方法を実現するためのパケットフィルタ部912の構成について図12を用いて説明する。パケットフィルタ部912は減算器1101、1102と比較器1100とから構成される。パケットフィルタ部350との差分は、減算器1101において、フィルタ制御部914から受信するTSずれΔと受信TSとの差分を計算し、減算器1102で、生成TSから得られた差分を減算する点である。この処理により、生成TSの補正が行われている。減算情報(Tm-Δ)は減算器1101に入力され、減算情報(Tm-Δ)とマスタノード100から入力される生成TS(Ts)の差分が計算され、比較器1100に入力される。比較器1100では、設定IFより設定された閾値Dthと差分情報Ts-(Tm-Δ)とからなる以下のフィルタ条件(1)~(3)に従い比較計算を行い、パケットのTSが該当するフィルタ条件に従い、フィルタ処理を行う。
(1)
0 ≦ Ts - (Tm - Δ)≦Dth
→パケットのTSを採用、PLL140に転送する。
(2)
Ts - (Tm - Δ) < 0
→パケットのTSは採用しない。
(3)
Dth < Ts - (Tm - Δ)
→パケットのTSは採用しない。
以上説明した本実施の形態によれば、第一の実施の形態と同等の効果が得られる。本実施の形態によれば、同期精度モニタ部が取得する同期精度情報ならびにパケットカウンタのカウンタ値の増減情報を利用して、フィルタ制御部がTSずれを計算する。パケットフィルタ部はTSずれを利用して、遅延量Dを補正することにより、スレーブクロックの到着タイミングを同期状態のスレーブクロックの到着タイミングに補正する。この補正したタイミングの下で、スレーブノードが生成TS、受信TSの処理を行うことにより、スレーブノード側で到着したパケットの遅延量を算出し、設定した閾値に応じて適切にパケットのTSの選択的採用を行うことが可能になる。その結果、遅延量の大きいパケットのTSを採用せず、遅延量の小さいパケットのTSのみをクロック同期回路に取り込むことにより、同期精度を向上できるという効果がある。
以下、本発明の第三の実施の形態について説明する。本実施の形態の基本的な構成及び動作は第一の実施の形態及び第二の実施の形態とほぼ同様である。相違点はパケットフィルタ部において遅延量Dを補正するのではなく、遅延量の閾値Dthを補正するという点にある。
その結果、9≦D=69-55=14≦17を満たすため、パケット506のTSは採用となる。一般的な方法では、D=69-55=14となり、閾値Dth=8よりも大きくなるため、TSが採用されていなかったことから、本実施の形態における補正により適切にフィルタ処理を行うことができている。
その結果、-6≦D=52-55=-3≦2を満たすため、パケット606のTSは採用となる。一般的な方法では、D=52-55=-3となり、閾値0よりも小さくなるため、TSが採用されていなかったことから、本実施の形態における補正により適切にフィルタ処理を行うことができている。
-Δ≦Ts - Tm≦Dth -Δ
(1)
-Δ≦Ts - Tm ≦Dth -Δ
→パケットのTSを採用、PLL140に転送する。
(2)
Ts - Tm < -Δ
→パケットのTSは採用しない。
(3)
Dth -Δ< Ts - Tm
→パケットのTSは採用しない。
以上説明した本実施の形態によれば、第一の実施の形態及び第二の実施の形態と同等の効果が得られる。本実施の形態によれば、同期精度モニタ部が取得する同期精度情報ならびにパケットカウンタのカウンタ値の増減情報を利用して、フィルタ制御部がTSずれを計算する。パケットフィルタ部はTSずれを利用して、遅延量Dを補正することにより、スレーブクロックの到着タイミングを同期状態のスレーブクロックの到着タイミングに補正する。この補正したタイミングの下で、スレーブノードが生成TS、受信TSの処理を行うことにより、スレーブノード側で到着したパケットの遅延量を算出し、設定した閾値に応じて適切にパケットのTSの選択的採用を行うことが可能になる。その結果、遅延量の大きいパケットのTSを採用せず、遅延量の小さいパケットのTSのみをクロック同期回路に取り込むことにより、同期精度を向上できるという効果がある。
Claims (15)
- スレーブノードのクロックをマスタノードのクロックに同期させるクロック同期システムであって、
前記マスタノードは、タイムスタンプを含むパケットをスレーブノードに対して送信するパケット送信手段を備え、
前記スレーブノードは、前記マスタノードから送信された前記パケットを受信するパケット受信手段と、
前記パケットの受信時におけるスレーブノードのクロックのタイムスタンプと受信した前記パケットのタイムスタンプとの差分を前記パケットの遅延の値として算出し、前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正し、且つ、前記パケット受信手段から受信した前記パケットに対して、前記パケットの遅延の値及び前記パケットの遅延に関する閾値に基づいてフィルタ処理を行うパケットフィルタ手段と、
前記パケットフィルタ手段において採用された前記パケットに含まれるタイムスタンプに基づいてスレーブノードのクロックを出力する位相同期手段と、
を備えることを特徴とするクロック同期システム。 - 前記スレーブノードは、
前記マスタノードと前記スレーブノード間の同期精度を計測する同期精度計測手段と、
前記同期精度と、あらかじめ設定された同期精度計測間隔と、あらかじめ設定された前記マスタノードのクロックにおいて単位時間あたりに進むタイムスタンプとを積算することでタイムスタンプずれを算出するフィルタ制御手段と、
を備えることを特徴とする請求項1記載のクロック同期システム。 - 前記パケットフィルタ手段は、
前記タイムスタンプずれに基づいて前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正することを特徴とする請求項2記載のクロック同期システム。 - 前記パケットフィルタ手段は、
前記パケット受信手段が前記マスタノードからのパケットの受信時におけるスレーブノードのクロックのタイムスタンプに対して、前記タイムスタンプずれを加算することで、前記スレーブノードのクロックのタイムスタンプを補正し、前記補正したスレーブノードのクロックのタイムスタンプと前記受信したパケットに格納されているタイムスタンプとの差分を遅延として、フィルタ処理を行うことを特徴とする請求項2または3に記載のクロック同期システム。 - 前記パケットフィルタ手段は、
前記パケットの遅延に関する閾値から、前記タイムスタンプずれを減算して前記パケットの遅延に関する閾値を補正し、前記補正したパケットの遅延に関する閾値を用いてフィルタ処理を行うことを特徴とする請求項2または3に記載のクロック同期システム。 - 前記パケットフィルタ手段は、
前記パケット受信手段で受信したパケットの中で前記パケットの遅延に関する閾値を超過した遅延を含むパケットのタイムスタンプを採用せず、前記パケットの遅延に関する閾値以下の遅延を含むパケットのタイムスタンプを採用することを特徴とする請求項1乃至5の何れか1項に記載のクロック同期システム。 - 自ノードのクロックをマスタノードのクロックに同期させるノードであって、
前記マスタノードからネットワークを介してタイムスタンプを含むパケットを受信するパケット受信手段と、
前記パケットの受信時における自ノードのクロックのタイムスタンプと受信した前記パケットのタイムスタンプとの差分を前記パケットの遅延の値として算出し、前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正し、且つ、前記パケット受信手段から受信した前記パケットに対して、前記パケットの遅延の値及び前記パケットの遅延に関する閾値に基づいてフィルタ処理を行うパケットフィルタ手段と、
前記パケットフィルタ手段において採用された前記パケットに含まれるタイムスタンプに基づいて自ノードのクロックを出力する位相同期手段と、
を備えることを特徴とするノード。 - 前記ノードは、
前記マスタノードと自ノード間の同期精度を計測する同期精度計測手段と、
前記同期精度と、あらかじめ設定した同期精度計測間隔と、あらかじめ設定された前記マスタノードのクロックにおいて単位時間あたりに進むタイムスタンプとを積算することでタイムスタンプずれを算出するフィルタ制御手段と、
を備えることを特徴とする請求項7記載のノード。 - 前記パケットフィルタ手段は、
前記タイムスタンプずれに基づいて前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正することを特徴とする請求項8記載のノード。 - 前記パケットフィルタ手段は、
前記パケット受信手段が前記マスタノードからのパケット受信時における自ノードのクロックのタイムスタンプに対して、前記タイムスタンプずれを加算することで、自ノードのクロックのタイムスタンプを補正し、前記補正した自ノードのクロックのタイムスタンプと前記受信したパケットに格納されているタイムスタンプとの差分を遅延として、フィルタ処理を行うことを特徴とする請求項8または9に記載のノード。 - 前記パケットフィルタ手段は、
前記パケットの遅延に関する閾値から、前記タイムスタンプずれを減算して前記パケットの遅延に関する閾値を補正し、前記補正したパケットの遅延に関する閾値を用いてフィルタ処理を行うことを特徴とする請求項8または9に記載のノード。 - 前記パケットフィルタ手段は、前記パケット受信手段で受信したパケットの中で前記パケットの遅延に関する閾値を超過した遅延を含むパケットのタイムスタンプを採用せず、前記パケットの遅延に関する閾値以下の遅延を含むパケットのタイムスタンプを採用することを特徴とする請求項7乃至11の何れか1項に記載のノード。
- スレーブノードのクロックをマスタノードのクロックに同期させるクロック同期方法であって、
ネットワークを介してタイムスタンプを含むパケットを受信し、
前記パケットの受信時における前記スレーブノードのクロックのタイムスタンプと受信した前記パケットのタイムスタンプとの差分を前記パケットの遅延の値として算出し、
前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正し、
前記パケット受信手段から受信した前記パケットに対して、前記パケットの遅延の値及び前記パケットの遅延に関する閾値に基づいてフィルタ処理をし、
前記パケットフィルタステップにおいて採用された前記パケットに含まれるタイムスタンプに基づいてスレーブノードのクロックを出力する、
ことを特徴とするクロック同期方法。 - 前記マスタノードと前記スレーブノード間の同期精度を計測するし、
前記同期精度と、あらかじめ設定された同期精度計測間隔と、あらかじめ設定された前期マスタノードのクロックにおいて単位時間あたりに進むタイムスタンプ値とを積算することでタイムスタンプずれを算出する、
ことを特徴とする請求項13記載のクロック同期方法。 - スレーブノードのクロックをマスタノードのクロックに同期させるプログラムであって、
前記マスタノードからネットワークを介してタイムスタンプを含むパケットを受信するパケット受信処理と、
前記パケットの受信時におけるスレーブノードのクロックのタイムスタンプと受信した前記パケットのタイムスタンプとの差分を前記パケットの遅延の値として算出し、前記パケットの遅延の値または前記パケットの遅延に関する閾値を補正して、補正した前記パケットの遅延の値及び前記パケットの遅延に関する閾値に基づいてフィルタ処理を行うパケットフィルタ処理と、
前記パケットフィルタステップにおいて採用された前記パケットに含まれるタイムスタンプに基づいてスレーブノードのクロックを出力させる位相同期処理と、
を実行させることを特徴とするプログラム。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104067555A (zh) * | 2012-01-30 | 2014-09-24 | 索尼公司 | 同步处理设备、同步处理方法和程序 |
US11038608B2 (en) * | 2016-11-04 | 2021-06-15 | Huawei Technologies Co., Ltd. | Frequency synchronization method and slave clock |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8358729B2 (en) * | 2008-08-22 | 2013-01-22 | Finisar Corporation | Baseband phase-locked loop |
JP5130313B2 (ja) * | 2010-04-02 | 2013-01-30 | 株式会社日立製作所 | 管理システム及び計算機システムの管理方法 |
WO2013170359A1 (en) * | 2012-05-16 | 2013-11-21 | Microsemi Semiconductor Ulc | Method of adjusting a local clock in asynchronous packet networks |
US9124380B2 (en) * | 2012-12-03 | 2015-09-01 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Packet delay distribution rate filtering |
US9760114B1 (en) * | 2014-01-03 | 2017-09-12 | Juniper Networks, Inc. | Systems and methods for improving clock synchronization between master and slave devices |
US9769695B2 (en) * | 2014-11-04 | 2017-09-19 | Cisco Technology, Inc. | Adaptive quality of service for wide area network transport |
US9891966B2 (en) | 2015-02-10 | 2018-02-13 | Red Hat, Inc. | Idempotent mode of executing commands triggered by complex event processing |
US10423468B2 (en) * | 2015-02-10 | 2019-09-24 | Red Hat, Inc. | Complex event processing using pseudo-clock |
US9814007B2 (en) | 2015-09-25 | 2017-11-07 | Intel Corporation | Synchronizing time among two or more devices |
US10541944B1 (en) * | 2017-07-24 | 2020-01-21 | Rockwell Collins, Inc. | High integrity AFDX switches |
WO2020024199A1 (en) * | 2018-08-02 | 2020-02-06 | Texas Instruments Incorporated | High speed flexled digital interface |
US10769038B2 (en) * | 2018-08-23 | 2020-09-08 | Arm Limited | Counter circuitry and methods including a master counter providing initialization data and fault detection data and wherein a threshold count difference of a fault detection count is dependent upon the fault detection data |
JP2021190868A (ja) * | 2020-05-29 | 2021-12-13 | キヤノン株式会社 | 映像同期装置、映像同期装置の制御方法及びプログラム |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000244473A (ja) * | 1999-02-24 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Pll回路 |
JP2000278275A (ja) * | 1999-03-23 | 2000-10-06 | Yamaha Corp | パケット転送装置 |
WO2001050674A1 (en) * | 1999-12-30 | 2001-07-12 | Nokia Networks Oy | Synchronization in packet-switched telecommunications system |
JP2001244809A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Pll回路 |
JP2006518557A (ja) * | 2003-02-20 | 2006-08-10 | ザ−リンク・セミコンダクタ−・インコ−ポレイテッド | パケットネットワークにおけるクロックドメインの調整 |
JP2007134873A (ja) * | 2005-11-09 | 2007-05-31 | National Institute Of Information & Communication Technology | 高精度時刻同期処理装置およびそのプログラム,ならびにネットワーク混雑度警告装置およびそのプログラム |
WO2009035091A1 (ja) * | 2007-09-14 | 2009-03-19 | Nec Corporation | クロック同期システム、その方法及びそのプログラム |
WO2009034984A1 (ja) * | 2007-09-14 | 2009-03-19 | Nec Corporation | パケットネットワークにおけるクロック同期システム、その方法及びそのプログラム |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3463460B2 (ja) * | 1996-05-20 | 2003-11-05 | ヤマハ株式会社 | データ伝送方式 |
US6199169B1 (en) * | 1998-03-31 | 2001-03-06 | Compaq Computer Corporation | System and method for synchronizing time across a computer cluster |
EP1312179B1 (en) * | 2000-08-17 | 2012-12-05 | Broadcom Corporation | Method and system for transmitting isochronous voice in a wireless network |
JP2004248123A (ja) | 2003-02-17 | 2004-09-02 | Matsushita Electric Ind Co Ltd | Pll回路 |
GB2399263A (en) | 2003-03-07 | 2004-09-08 | Zarlink Semiconductor Ltd | Clock synchronisation over a packet network |
JP2007104347A (ja) | 2005-10-05 | 2007-04-19 | Matsushita Electric Ind Co Ltd | 音声伝送システムにおけるクロック同期システム及び方法 |
JP4650248B2 (ja) | 2005-12-09 | 2011-03-16 | 株式会社デンソー | 車両用ネットワークシステム及びネットワークノード |
US20070147435A1 (en) | 2005-12-23 | 2007-06-28 | Bruce Hamilton | Removing delay fluctuation in network time synchronization |
-
2009
- 2009-11-20 JP JP2010539256A patent/JP5440880B2/ja not_active Expired - Fee Related
- 2009-11-20 US US13/129,755 patent/US8731036B2/en not_active Expired - Fee Related
- 2009-11-20 WO PCT/JP2009/069684 patent/WO2010058831A1/ja active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000244473A (ja) * | 1999-02-24 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Pll回路 |
JP2000278275A (ja) * | 1999-03-23 | 2000-10-06 | Yamaha Corp | パケット転送装置 |
WO2001050674A1 (en) * | 1999-12-30 | 2001-07-12 | Nokia Networks Oy | Synchronization in packet-switched telecommunications system |
JP2001244809A (ja) * | 2000-02-28 | 2001-09-07 | Matsushita Electric Ind Co Ltd | Pll回路 |
JP2006518557A (ja) * | 2003-02-20 | 2006-08-10 | ザ−リンク・セミコンダクタ−・インコ−ポレイテッド | パケットネットワークにおけるクロックドメインの調整 |
JP2007134873A (ja) * | 2005-11-09 | 2007-05-31 | National Institute Of Information & Communication Technology | 高精度時刻同期処理装置およびそのプログラム,ならびにネットワーク混雑度警告装置およびそのプログラム |
WO2009035091A1 (ja) * | 2007-09-14 | 2009-03-19 | Nec Corporation | クロック同期システム、その方法及びそのプログラム |
WO2009034984A1 (ja) * | 2007-09-14 | 2009-03-19 | Nec Corporation | パケットネットワークにおけるクロック同期システム、その方法及びそのプログラム |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104067555A (zh) * | 2012-01-30 | 2014-09-24 | 索尼公司 | 同步处理设备、同步处理方法和程序 |
US11038608B2 (en) * | 2016-11-04 | 2021-06-15 | Huawei Technologies Co., Ltd. | Frequency synchronization method and slave clock |
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