WO2010056003A2 - 메모리 뱅크로의 접근을 제어하는 고체 상태 디스크를 위한 컨트롤러 - Google Patents
메모리 뱅크로의 접근을 제어하는 고체 상태 디스크를 위한 컨트롤러 Download PDFInfo
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- WO2010056003A2 WO2010056003A2 PCT/KR2009/006337 KR2009006337W WO2010056003A2 WO 2010056003 A2 WO2010056003 A2 WO 2010056003A2 KR 2009006337 W KR2009006337 W KR 2009006337W WO 2010056003 A2 WO2010056003 A2 WO 2010056003A2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
Definitions
- Embodiments of the present invention relate to a controller for a solid state disk, and more particularly to a technique for efficiently selecting memory banks to be read or written in a solid state disk having a plurality of memory banks.
- Solid state disks use flash memory, synchronous dynamic random access memory (SDRAM), and the like, rather than hard disk drives.
- solid state disks do not require a mechanical drive such as a motor used for a hard disk drive, and therefore can operate with little heat and noise.
- solid state disks are resistant to external shocks and can achieve higher data rates compared to hard disk drives.
- the solid state disk includes a plurality of memory banks, and the controller must select at least one of the plurality of memory banks to perform a read or write operation.
- a typical solid state disk selects at least one of a plurality of memory banks using firmware that includes a wear leveling algorithm that allows the plurality of memory banks to wear almost evenly.
- various operations such as a time delay may be required due to calculation of a central processing unit.
- a four-channel solid state disk includes four channels, with a plurality of memory banks connected to each of the four channels.
- the controller for a solid state disk manages the indices of the idle banks separately through a storage module (for example, a register) that is a hardware medium to select a memory bank, thereby delaying the use of firmware.
- a storage module for example, a register
- controller for the solid state disk selects at least one idle bank in consideration of the state of the channel, thereby performing a read operation or a write operation without waiting due to the busy of the channel. .
- controller for the solid state disk applies a wear leveling (wear leveling) by using a round-robin method.
- controller for a solid state disk easily selects any one of a plurality of idle banks by using a pointer.
- a controller for a solid state disk is a storage module for storing an index of at least one idle bank of a plurality of memory banks and the at least one idle bank using the stored index. It includes a control module for controlling access to the.
- control module may control access to the at least one idle bank in consideration of a state of a channel corresponding to each of the at least one idle bank.
- the control module may indicate one of the stored indexes of the at least one idle bank with a pointer and control access to the idle bank corresponding to the indicated index.
- an access result for the at least one idle bank is provided to a flash translation layer (FTL), and the flash translation layer is based on a result of access to the at least one idle bank.
- FTL flash translation layer
- a logical sector may be constructed.
- control method for a solid-state disk comprises the steps of storing an index of at least one idle bank of a plurality of memory banks in a pre-prepared register, at least one from the pre-prepared register Detecting an index of and controlling access to the at least one idle bank using the detected at least one index.
- the controller for a solid state disk can reduce the delay caused by the use of firmware by separately managing the index of the idle bank through a storage module which is a hardware medium to select a memory bank.
- controller for a solid state disk selects at least one idle bank in consideration of the state of the channel, thereby performing a read operation or a write operation without waiting due to the busy of the channel. Can be.
- controller for the solid state disk can apply wear leveling by using a round-robin method.
- controller for a solid state disk can easily select any one of a plurality of idle banks by using a pointer.
- controller for the solid state disk provides the information on the selected idle bank to the Flash Translation Layer (FTL), so that the flash translation layer is more efficiently physical sector (physical sector) ) And map between logical sectors.
- FTL Flash Translation Layer
- FIG. 1 is a view showing a solid state disk according to an embodiment of the present invention.
- FIG. 2 is a block diagram illustrating a controller for a solid state disk according to an embodiment of the present invention.
- FIG. 3 is a diagram illustrating a plurality of memory blocks connected to each of a plurality of channels according to an embodiment of the present invention.
- FIG. 4 is a diagram illustrating a table managed by a storage module according to an embodiment of the present invention.
- FIG. 5 is a flowchart illustrating a control method for a solid state disk according to an embodiment of the present invention.
- FIG. 1 is a view showing a solid state disk according to an embodiment of the present invention.
- a solid state disk includes a host interface 120, a controller 130, a buffer 140, and a plurality of memory banks 151, 152, 153, and 154.
- the host interface 120 transmits / receives various signals such as control signals, address information, and data through a bus with an external host 110.
- the host interface 120 appropriately converts various signals transmitted / received with the external host 110 into internal signals and provides them to the controller 130.
- the controller 130 controls a read operation or a write operation on the plurality of memory banks 151, 152, 153, and 154 in response to an internal signal of the host interface 120.
- each of the plurality of memory banks 151, 152, 153, and 154 may be provided with a flash memory, and the plurality of memory banks 151, 152, 153, and 154 may be independent of each other.
- the buffer 140 stores frequently used data. That is, the controller 130 may store frequently used data in the buffer 140 to reduce the time required for the read operation or the write operation.
- the plurality of channels (channels A, B, C, D) operate independently of each other.
- the solid state disk may perform a read operation or a write operation in parallel by using a plurality of channels (channels A, B, C, and D) operated independently of each other.
- the controller 130 may include memory banks 0, 4, 8, 12 connected to channel A, memory banks 1, 5, 9, 13 connected to channel B, memory banks 2, 6, 10, 14 connected to channel C, and channels. Read or write operations can be controlled independently for memory banks 3, 7, 11, and 15 connected to D.
- memory banks 0, 1, 2, 3, 4, 5, and 6 all have idle states, channels A and B are busy and channels C are idle.
- the controller 130 in order to perform a read operation or a write operation on at least one of the memory banks 0, 1, 4, and 5 connected to the channel A or the channel B, it is necessary to wait until the states of the channels A and B become idle. This wait may be a cause of degrading the overall performance of the solid state disk.
- the controller 130 recognizes that the state of the channel C is idle, and the controller 130 selects the memory banks 2 or 6 connected to the channel C among the memory banks 0, 1, 2, 3, 4, 5, and 6.
- a read operation or a write operation may be performed on at least one of the selected memory banks 2 and 6. This will be described in detail with reference to FIGS. 2 to 6.
- FIG. 2 is a block diagram illustrating a controller for a solid state disk according to an embodiment of the present invention.
- a controller 130 for a solid state disk includes a storage module 210 and a control module 220.
- the control module 220 controls a read operation or a write operation on a plurality of memory banks (not shown) through channels A, B, C, and D.
- channels A, B, C, and D are shown in FIG. 2, it should be noted that the present invention can be well applied to various cases in which two or more channels exist.
- the storage module 210 stores and manages indices of idle banks among the plurality of memory banks.
- the storage module 210 can list the indices of idle banks using a register.
- the indices of the idle banks stored in the storage module 210 may be properly updated in response to their state changing to busy.
- control module 220 controls access to the selected idle bank using the indices of the idle banks stored in the storage module 210. That is, the control module 220 selects an idle bank that is a target of a read operation or a write operation based on the stored indices, and controls access to the selected idle bank.
- control module 220 may select at least one idle bank in consideration of the state of a channel connected to each of the idle banks in order to reduce the aforementioned waiting time.
- control module 220 may preferentially select an idle bank connected to channel B among several idle banks.
- control module 220 may use a round-robin scheme for wear leveling that allows a plurality of memory banks to be used evenly. For example, the control module 220 may sequentially select each of the memory banks connected to one channel so that the plurality of memory banks may be evenly used.
- the information about the selected idle bank (access result) may be provided to a flash translation layer (FTL).
- the flash translation layer may configure or update a map between a physical sector and a logical sector based on the information about the selected idle bank (access result).
- FIG. 3 is a diagram illustrating a plurality of memory blocks connected to each of a plurality of channels according to an embodiment of the present invention.
- the controller may initially select memory bank 0 and sequentially select memory banks 1, 2, and 3.
- the controller may select the memory bank 5 connected to the channel B having the idle state instead of the memory bank 4. .
- the controller according to an embodiment of the present invention improves the performance of the solid state disk by selecting memory bank 5 connected to the channel B having the idle state immediately without waiting for the state of the channel A to become idle from idle. You can.
- the controller may select one of the memory banks 6 and 14. Furthermore, the controller may select a higher priority in consideration of the cyclic order method among the memory banks 6 and 14.
- FIG. 4 is a diagram illustrating a table managed by a storage module according to an embodiment of the present invention.
- a storage module manages a table 410 that stores indices of idle banks which are memory banks or memory banks having an idle state. Numbers 1, 2, 3, ..., 7 described in table 410 represent indices of memory banks or idle banks.
- the pointer 420 indicates any one of the plurality of indices stored in the table 410. At this time, the controller selects an idle bank corresponding to the indicated index and performs a read operation or a write operation on the selected idle bank.
- the table 410 may be updated, and in another way, the pointer 420 may be indicative of the index that was indicated immediately before. You can point to another index.
- the pointer 420 may change the indexes sequentially indicated by using a cyclic order method. That is, the pointer 420 may indicate the k-th index immediately before and then indicate the current k + 1-th index.
- the pointer 420 may indicate the index of the idle bank in consideration of the state of the channel. For example, when the state of channel A is busy, the pointer 420 may indicate index 3 immediately before skipping index 4 and newly indicate index 5.
- the controller may quickly select an idle bank that is a target of a read operation or a write operation by using a pointer 420 indicating one index in consideration of a channel state.
- FIG. 5 is a flowchart illustrating a control method for a solid state disk according to an embodiment of the present invention.
- an index of at least one idle bank among a plurality of memory banks is stored in a register prepared in advance (S510).
- control method for the solid state disk checks the channel corresponding to the idle bank having the k-th index (S520).
- control method for the solid state disk determines whether the state of the inspected channel is busy (S530).
- k is increased to k + 1 (S540), the idle bank having the k + 1 th index The corresponding channel is inspected (S520).
- the control method for the solid state disk selects the idle bank having the k-th index as the memory bank to be read or write. (S550).
- control method for the solid state disk controls the access for the read operation or the write operation based on the signals received from the external host for the selected idle bank (S560).
- control method for the solid state disk provides the access result to the flash translation layer (S570).
- the flash translation layer constructs or updates a map between the physical sector and the logical sector using the access result.
- the control method for a solid state disk may be implemented in the form of program instructions that can be executed by various computer means and recorded on a computer readable medium.
- the computer readable medium may include program instructions, data files, data structures, etc. alone or in combination.
- Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks.
- Magneto-optical media and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like.
- program instructions include machine code, such as produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like.
- the hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.
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Abstract
Description
Claims (19)
- 복수의 메모리 뱅크들 중 적어도 하나의 아이들(idle) 뱅크의 인덱스를 저장하는 저장 모듈; 및상기 저장된 인덱스를 이용하여 상기 적어도 하나의 아이들 뱅크에 대한 접근을 제어하는 제어 모듈을 포함하는 것을 특징으로 하는 고체 상태 디스크(solid state disk)를 위한 컨트롤러.
- 제1항에 있어서,상기 제어 모듈은상기 적어도 하나의 아이들 뱅크 각각에 대응하는 채널의 상태를 고려하여 상기 적어도 하나의 아이들 뱅크에 대한 접근을 제어하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 제어 모듈은상기 적어도 하나의 아이들 뱅크 중 아이들 상태를 갖는 채널에 대응하는 아이들 뱅크에 접근 우선권을 부여하는 것을 특징으로 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 제어 모듈은소모 레벨링(wear leveling)을 위하여 순환 순서(round-robin) 방식에 따라 상기 적어도 하나의 아이들 뱅크에 대한 접근을 제어하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 제어 모듈은상기 저장된 적어도 하나의 아이들(idle) 뱅크의 인덱스 중 포인터로 어느 하나를 지시하고, 상기 지시된 인덱스에 대응하는 아이들 뱅크에 대한 접근을 제어하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제5항에 있어서,상기 포인터는 상기 적어도 하나의 아이들 뱅크 각각에 대응하는 채널의 상태를 고려하여 상기 저장된 적어도 하나의 아이들(idle) 뱅크의 인덱스 중 어느 하나를 지시하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제5항에 있어서,상기 포인터는소모 레벨링(wear leveling)을 위하여 순환 순서(round-robin) 방식에 따라 상기 저장된 적어도 하나의 아이들(idle) 뱅크의 인덱스 중 어느 하나를 지시하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 적어도 하나의 아이들 뱅크에 대한 접근 결과는 플래시 변환 계층(Flash Translation Layer, FTL)으로 제공되고, 상기 플래시 변환 계층은 상기 적어도 하나의 아이들 뱅크에 대한 접근 결과를 기초로 물리 섹터(physical sector) 및 논리 섹터(logical sector) 사이의 맵을 구성하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 저장 모듈은상기 적어도 하나의 아이들 뱅크의 상태가 비지(busy)로 변경됨에 응답하여 상기 저장된 적어도 하나의 아이들(idle) 뱅크의 인덱스를 업데이트하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 저장 모듈은레지스터를 이용하여 상기 적어도 하나의 아이들 뱅크의 인덱스를 저장하는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 복수의 메모리 뱅크들 각각에는 플래시 메모리가 설치되는 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 제1항에 있어서,상기 복수의 메모리 뱅크들 각각은 복수의 채널들 중 어느 하나와 연결되고, 상기 복수의 채널들은 서로 독립적인 것을 특징으로 하는 고체 상태 디스크를 위한 컨트롤러.
- 미리 준비된 레지스터에 복수의 메모리 뱅크들 중 적어도 하나의 아이들(idle) 뱅크의 인덱스를 저장하는 단계;상기 미리 준비된 레지스터로부터 적어도 하나의 인덱스를 검출하는 단계; 및상기 검출된 적어도 하나의 인덱스를 이용하여 상기 적어도 하나의 아이들 뱅크에 대한 접근을 제어하는 단계를 포함하는 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항에 있어서,상기 적어도 하나의 인덱스를 검출하는 단계는상기 적어도 하나의 아이들 뱅크 각각에 대응하는 채널의 상태를 고려하여 상기 적어도 하나의 인덱스를 검출하는 단계인 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항에 있어서,상기 적어도 하나의 아이들 뱅크 중 아이들 상태를 갖는 채널에 대응하는 아이들 뱅크에 접근 우선권을 부여하는 단계를 더 포함하고,상기 적어도 하나의 인덱스를 검출하는 단계는상기 부여된 접근 우선권을 고려하여 상기 적어도 하나의 인덱스를 검출하는 단계인 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항에 있어서,상기 적어도 하나의 인덱스를 검출하는 단계는소모 레벨링(wear leveling)을 위하여 순환 순서(round-robin) 방식에 따라 상기 적어도 하나의 인덱스를 검출하는 단계인 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항에 있어서,플래시 변환 계층(Flash Translation Layer, FTL)으로 상기 적어도 하나의 아이들 뱅크에 대한 접근 결과를 제공하는 단계를 더 포함하고,상기 플래시 변환 계층은 상기 적어도 하나의 아이들 뱅크에 대한 접근 결과를 기초로 물리 섹터(physical sector) 및 논리 섹터(logical sector) 사이의 맵을 구성하는 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항에 있어서,상기 적어도 하나의 아이들(idle) 뱅크의 인덱스를 저장하는 단계는상기 적어도 하나의 아이들 뱅크의 상태가 비지(busy)로 변경됨에 응답하여 상기 저장된 적어도 하나의 아이들(idle) 뱅크의 인덱스를 업데이트하는 단계를 포함하는 것을 특징으로 하는 고체 상태 디스크를 위한 제어 방법.
- 제13항 내지 18항 중 어느 한 항의 방법을 수행하기 위한 프로그램이 기록된 컴퓨터로 판독 가능한 기록 매체.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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US13/128,981 US8601200B2 (en) | 2008-11-13 | 2009-10-30 | Controller for solid state disk which controls access to memory bank |
JP2011536235A JP2012508921A (ja) | 2008-11-13 | 2009-10-30 | メモリバンクにおけるアクセスを制御するssdコントローラ |
CN2009801544626A CN102272848A (zh) | 2008-11-13 | 2009-10-30 | 控制内存条存取的固态硬盘控制器 |
EP09826235A EP2367175A4 (en) | 2008-11-13 | 2009-10-30 | CONTROL FOR SOLID STATE DISKS CONTROLLING ACCESS TO MEMORY BANK |
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KR10-2008-0112575 | 2008-11-13 | ||
KR1020080112575A KR101014149B1 (ko) | 2008-11-13 | 2008-11-13 | 메모리 뱅크로의 접근을 제어하는 고체 상태 디스크를 위한컨트롤러 |
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WO2010056003A2 true WO2010056003A2 (ko) | 2010-05-20 |
WO2010056003A3 WO2010056003A3 (ko) | 2010-08-05 |
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US (1) | US8601200B2 (ko) |
EP (1) | EP2367175A4 (ko) |
JP (1) | JP2012508921A (ko) |
KR (1) | KR101014149B1 (ko) |
CN (1) | CN102272848A (ko) |
WO (1) | WO2010056003A2 (ko) |
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US9471484B2 (en) | 2012-09-19 | 2016-10-18 | Novachips Canada Inc. | Flash memory controller having dual mode pin-out |
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TWI556100B (zh) * | 2015-10-26 | 2016-11-01 | 點序科技股份有限公司 | 快閃記憶體裝置及其交錯存取方法 |
CN105259989B (zh) * | 2015-11-18 | 2019-01-29 | 合肥宝龙达信息技术有限公司 | 一种笔记本板载内存兼容多源的方法 |
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- 2009-10-30 CN CN2009801544626A patent/CN102272848A/zh active Pending
- 2009-10-30 JP JP2011536235A patent/JP2012508921A/ja active Pending
- 2009-10-30 US US13/128,981 patent/US8601200B2/en active Active
- 2009-10-30 WO PCT/KR2009/006337 patent/WO2010056003A2/ko active Application Filing
- 2009-10-30 EP EP09826235A patent/EP2367175A4/en not_active Withdrawn
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None |
See also references of EP2367175A4 |
Also Published As
Publication number | Publication date |
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KR20100053782A (ko) | 2010-05-24 |
US8601200B2 (en) | 2013-12-03 |
KR101014149B1 (ko) | 2011-02-14 |
EP2367175A2 (en) | 2011-09-21 |
EP2367175A4 (en) | 2012-11-28 |
JP2012508921A (ja) | 2012-04-12 |
US20110276740A1 (en) | 2011-11-10 |
WO2010056003A3 (ko) | 2010-08-05 |
CN102272848A (zh) | 2011-12-07 |
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