WO2010039871A1 - Réseau reconfigurable d’automates magnétiques (rama) et procédés associés - Google Patents

Réseau reconfigurable d’automates magnétiques (rama) et procédés associés Download PDF

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Publication number
WO2010039871A1
WO2010039871A1 PCT/US2009/059084 US2009059084W WO2010039871A1 WO 2010039871 A1 WO2010039871 A1 WO 2010039871A1 US 2009059084 W US2009059084 W US 2009059084W WO 2010039871 A1 WO2010039871 A1 WO 2010039871A1
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Prior art keywords
nanopillars
nanopillar
array
layer
magnetic field
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PCT/US2009/059084
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English (en)
Inventor
Stuart A. Wolf
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University Of Virginia Patent Foundation
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Publication of WO2010039871A1 publication Critical patent/WO2010039871A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Definitions

  • RAMA Reconfigurable Array Magnetic Automata
  • CMOS Complementary metal-oxide-semiconductor
  • An aspect of an embodiment provides, but not limited thereto, a method of constructing magnetic automata and related structures through the development of a self- assembled thin film array of magnetic nano-pillars. For instance, it provides the ability to configure patterns electrically on a device without all requirements of producing a complicated pattern on a semiconductor chip. This relieves the requirement for using very expensive lithographic tools in the fabrication of these structures.
  • An aspect of an embodiment provides an architecture made from a self assembled thin film array of magnetic nano-pillars in a cross bar array that not only performs logic operations but also stores information. This technology goes significantly beyond these early ideas where complicated arrays had to be fashioned lithographically.
  • the magnetic bits may be regular arrays that are amenable to various self assembly schemes and each magnetic pillar can be individually addressed and controlled using electric fields (i.e., rather than charge currents or passing currents, for instance).
  • the magnetism in the dots can be gated and clocked electrically without having to strongly varying magnetic fields or large electrical currents, thereby allows these circuits to operate at very low power and to scale to dimensions not feasible with CMOS .
  • An aspect of an embodiment provides the ability to overcome ultimate CMOS limitations by using a Reconfigurable Array Magnetic Automata (RAMA) for performing logic operation and storing information.
  • RAMA Reconfigurable Array Magnetic Automata
  • An embodiment for a method of constructing a thin film array of nano-pillars may involve in-part brute force lithography. (See examples of lithography as is established in U.S. Patents Nos. 6,178,112 and 7,119,410.)
  • the memory cell allows for, but not limited thereto, the memory cell to be much smaller than the existing prior art.
  • the pillars 5 may range in diameter size (edge to edge of the pillars) from between about 3 nm to about 25 nm.
  • the pillars 5 may be less than about 15 nm at the limits of CMOS. It should be appreciated that the pillar diameter may be less than about 3 nm or greater than about 25 nm.
  • the spacing between the pillars 5 may be of the same order as the pillar diameter (but not necessarily). For example, if the pillars have a diameter of about 10 nm then the pillars may be separated by about IOnm. It should be appreciated that the pillar spacing may be less than about 3 nm or greater than about 25 nm; range between from about 3 nm to about 25 nm. The spacing will determine, among other things, the coupling between the pillars (ferromagnetic or antiferromagentic). In an embodiment, the width of the wires above and wires below the pillars may be slightly larger than the diameters of the pillars (but not necessarily).
  • pillars having a diameter of about 10 nm may have wires of about 14 nm wide and they would be separated by about 6nm. It should be appreciated that other ratios of comparative sizes involving diameters, widths and separations may be selected as desired or required and shall be considered within the context of the invention.
  • diameters of the pillars, separation between the pillars, and width of the wires may have various widths, lengths, distances, sizes, contours, and shapes as desired or required and is considered to be within the context of the embodiments. Moreover, their relative widths, lengths, distances, sizes, contours, and shapes of any of the elements relative to any adjacent, proximal or related elements may vary as well.
  • wafers, substrates, various layers discussed herein, connections, vias, conductors, and junctions may have various widths, lengths, distances, sizes, contours, and shapes as desired or required and is considered to be within the context of the invention.
  • the reconf ⁇ gurable magnetic automata is constructed by combining three layers. It should be appreciated that more layers may be added if desired or required.
  • the top layer may comprise wires or conducting material running at least substantially parallel to one another separated by an insulating material, all of which run at least substantially horizontally.
  • the middle layer may include a random array of up and down polarized ferromagnetic (FM) pillars embedded in a ferroelectric (FE) or piezoelectric (PE) matrix.
  • the nanopillars may be covered with either a novel oxide that exhibits very large changes of dielectric constant with application of magnetic field or an insulator that can act as a tunnel barrier.
  • the third and bottom layer may comprise of wires or conductors also running in a horizontal direction, but at least substantially perpendicular to the wires and conductors of the top layer. In between these wires or conductors on the third layer is an insulating material.
  • a substrate is contained under this third and bottom layer.
  • the substrate may be employed on the top layer instead of the bottom layer or in addition to the bottom layer; thus, the structure may be fabricated using a flip-chip approach, for example, that would bond two substrates together. Any vias, junctions, leads, connections, transistors or circuits may be employed to communicate among all these various components or elements as desired or required and is considered to be within the context of the invention.
  • constructing nano-pillar structures uses an advanced and novel method known as block co-polymer patterning. It can also be constructed using lithographic techniques such as e-bean lithography, polymeric self assembly, or damaged template growth.
  • lithographic techniques such as e-bean lithography, polymeric self assembly, or damaged template growth.
  • Diblock copolymer based self assembled nanomagnetoelectric Appl. Phys. Letters 93, 173507 (2008); and I. Bita, Joel K.W. Yang, Y. S. Jung, C. A. Ross, E. L. Thomas, K. K.
  • Various embodiments may use methods for writing bits to the nano-pillar memory cell, which take advantage of the antiferromagnetic coupling of the nanopillars. Furthermore, various additional methods can be used to read the memory cells constructed from the magnetic nanopillars. The output bits can be read out magnetoresitively as well as capacitively.
  • An aspect of an embodiment provides a thin film array of magnetic nano-pillars as disclosed herein that may be used in, but not limited thereto, microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits both embedded with the logic circuits or stand alone.
  • An aspect of an embodiment provides a thin film array of magnetic nano-pillars as disclosed herein that may be used in, but not limited thereto, for a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for many and various types of communication.
  • An aspect of an embodiment of the present invention includes the thin film array of magnetic nano-pillars as disclosed herein as a medium, device or system, the associated method of fabricating the same, the system, processor or computer for use therewith, and the apparatus or equipment utilized for fabricating the same.
  • An aspect of an embodiment provides self assembly techniques (for example, defect templated growth or patterning by block co-polymers) to prepare ordered arrays of the various structures discussed herein, including multilayered structures with perpendicular anisotropy in the unstrained condition, in which the ferromagnetic nanopillars may be arranged so that they couple antiferromagnetically. For instance, a magnetic rotation is caused by the piezoelectric strain coupling or ferroelectric strain coupling from the surrounding matrix of the nanopillars.
  • An aspect of an embodiment or partial embodiment comprises, but not limited thereto, a non-volatile reconfigurable array of modifiable automata (RAMA) device.
  • the device may comprise: an array of nanopillars functionally addressable by conducting elements that provide a control electric field to the nanopillars; and whereby the array of nanopillars may comprise at least one material whose properties can be controlled by the control electric field.
  • the nanopillar properties may be the direction of magnetization of the material of at least one of the nanopillars of the nanopillar array.
  • the nanopillar properties may be the direction of polarization of the material of at least one of the nanopillars of the nanopillar array.
  • An aspect of an embodiment or partial embodiment comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time.
  • the nanopillar may be a ferromagnetic (FM) material.
  • the device may comprise a layer for the array of nanopillars located above or below the array of nanopillars.
  • the nanopillar layer may comprise a colossal magnetocapacative (CMC) material.
  • CMC colossal magnetocapacative
  • the device may be configured whereby if a global magnetic field is applied to the array of nanopillars (for example, in a direction at least substantially parallel to the nanopillars), then the magnetic field on the CMC material of the nanopillar layering is subject to the sum of the fields produced by the magnetic moments of the nanopillars and the applied global magnetic field, and wherein the capacitance of the dielectric constant of the CMC material is capable of being read.
  • An aspect of an embodiment or partial embodiment comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time.
  • the nanopillar may comprise a ferromagnetic (FM) material.
  • the device may have a layer for the array of nanopillars located above or below the array of nanopillars, and the nanopillar layer may comprises a magnetoresistive oxide material.
  • the device may be configured whereby if a global magnetic field is applied to the array of nanopillars (for example, in a direction at least substantially parallel to the nanopillars) and a current is passed through the nanopillars and the nanopillar layer, then the resistance on the magnetoresistive oxide material of the nanopillar layering changes, and wherein the resistance of the magnetoresistive oxide material is capable of being read.
  • An aspect of an embodiment or partial embodiment comprises, but not limited thereto, a device comprising a non- volatile array of magnetic nanopillars, wherein the nanopillars may have been previously written at some prior time.
  • the nanopillar may comprise a ferroelectric (FE) material.
  • the device may comprise: a layer for the array of nanopillars located above or below the array of nanopillars.
  • the nanopillar layer may comprise a paraelectric material.
  • the device may be configured whereby if an electric field is applied to the nanopillars, then the electric field on the paraelectric material of the nanopillar layering is sensitive to the total electric field due to the ferroelectric (FE) material of the nanopillars and the applied electric field, and wherein the capacitance of the dielectric constant of the paraelectric material is capable of being read.
  • FE ferroelectric
  • Figure 2 provides an enlarged cross-section of an exploded schematic view of a partial segment of the array shown in Figure 1.
  • Figure 3(A) provide a schematic cross-section perspective view of a nanopillar pair with no applied electric field.
  • Figure 3(B) provides a schematic cross-section perspective view of a nanopillar with an applied electric field.
  • Figure 4(A) is a schematic view of a bit formed by four nanopillars of an embodiment providing a "0" or unwritten state.
  • Figure 4(B) is a schematic plan view of a bit formed by four nanopillars of an embodiment providing 1" bit or written state.
  • Figure 5(A) provides a schematic plan view of an example of an array configured as a "NOR" gate of an embodiment.
  • Figure 5(B) provides a schematic plan view of an example of an array configured as a "NOT" gate of an embodiment.
  • Figures 6(A)-(B) provides a schematic perspective view illustrating the writing function to a portion of an array of an embodiment.
  • Figure 7 provides a schematic perspective view illustrating the reading function (reading capacitively) of a portion of an array of an embodiment.
  • Figure 8 provides a schematic plan view of an array 25 (partial array as shown) with groupings of nine nano pillars in their respective bit.
  • Figure 9(A) provides an exploded schematic perspective view of an array of an exemplary embodiment of the RAMA system.
  • Figures 9(B)-(C) provide schematic perspective view of examples of coils associated with the RAMA system of Figure 9(A) .
  • Figure 10 provides a cross-section of an exploded schematic view of a partial segment of an array an embodiment.
  • Figure 11 provides a cross-section of an exploded schematic view of a partial segment of an array an embodiment.
  • Figure 1 provides an exploded schematic perspective view of an array 25 with a top layer 1 (or may be multiple layers as desired or required) including wires 2 that are made of conducting material running at least substantially parallel to each other, in a lateral direction (as shown) or longitudinal direction, whichever direction is perpendicular to the bottom wires or conducters 8 of the bottom layer 7 (or may be multiple layers as desired or required) of the array 25.
  • the bottom wires or conductors 8 are running longitudinally and the top wires or conductors 2 are running laterally (however, it should be appreciated that they may be running longitudinally if bottom conductors 8 are running laterally).
  • each of the top wires or conductors 2 is to be an insulator 3 (or multiple layers) running along the wires or conductors.
  • In between each of the bottom wires or conductors 8 is to be an insulator 9 running along the wires or conductors. It should be appreciated that lateral and longitudinal directions are intended for illustrative purposes and actual alignments may vary.
  • FIG 2 there is illustrated an enlarged cross-section of an exploded schematic view of a partial segment of the array 25 shown in Figure 1 that represents an exemplary embodiment.
  • This cross-section view represents the array 25 having a top layer 1, middle layer 4, and bottom layer 7 — and its associated components (as will be discussed herein) sliced longitudinally 11 (as referenced in Figure 1).
  • middle simply means interposed or between the layers. It does not necessarily mean it must be at an exact center, i.e., at equal distances.
  • the middle layer 4 may contain a random array of nanopillar structures 5 which may be embedded in a ferroelectric (FE) or piezoelectric (PE) matrix 6 such as BiFeO3, SrTiO 3 , SrBaTiO 3 PZT, PZN, etc.
  • FE ferroelectric
  • PE piezoelectric
  • the random array of up and down polarized ferromagnetic (FM) pillars (such as CoFeO4, FE3O4 or other strongly ferromagnetic oxide that is ferromagnetic to temperatures well above ambient temperature) embedded in a ferroelectric (FE) or piezoelectric (PE) matrix (such as BiFeO 3 ) can have their magnetizations rotated from being perpendicular to either top or bottom surface of the nanopillar 5 to being in the plane of the magnetic memory cell with any application of a modest electric field.
  • an aspect of an embodiment may have pairs of nanopillars that are coupled antiferromagnetically. For instance, but not limited thereto, an embodiment is capable of pairing the nanopillars into groups of four to create a bit (other pairings of nanopillars and numbers in a group may vary as desired or required for operational and manufacturing purposes).
  • the bottom layer 7 may include a set of bottom wires or conductors 8 running horizontally in a direction either laterally or longitudinally, as defined above, in a direction perpendicular to those of the wires or conductors 2 of the top layer 1. In between the wires 8 is an insulator 9 which runs across the length of the wires and serves as a shield between the wires 8.
  • the bottom layer 7 may be similar to the top layer 1 except that the bottom wires or conductors 8 run in a direction perpendicular to the top wires or conductors 2.
  • the bottom layer 7 may include the addition of a substrate 10 located under the bottom wires or conductors 8 and insulators 9.
  • a nanopillar layer may 11 be disposed on or in communication with (directly or indirectly) the nanopillar structures 5.
  • the nanopillar layer 11, for example, may be made from one of many material choices as discussed herein, or other material as desired or required.
  • a nanopillar structure 5 may be made up of more than one material.
  • the nanopillar layer 11 may be made with a novel oxide that exhibits very large changes of dielectric constant with the field or exhibits large changes in capacitance.
  • This material is labeled in Figure 2 as a colossal magnetocapacitive (CMC) material, such as LaPrCaMnO 3 , LaSrMnO 3 or other manganite because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field.
  • CMC colossal magnetocapacitive
  • the other possible material that can make up the nanopillar layer 11 above (or below) the nanopillar 5 is an insulator that can act as a tunnel barrier. In either approach (CMC or insulator as a tunnel barrier), these ferromagnetic nanopillars 5 are arranged so that they couple antiferromagnetically.
  • the nanopillar structure 5 may be ferromagnetic layer (FM), or other material as desired or required. For instance, it is possible to use other ferromagnetic compounds that have perpendicular anisotropy.
  • FM ferromagnetic layer
  • the CMC layer or segment is deposited solely over or in communication solely with the nanopillars itself, however it should be appreciated that it may be deposited over or in communication with the entire matrix , or some combination or variation thereof.
  • Figures 3(A) and 3(B) illustrate a schematic perspective view of the various exemplary positions of the magnetic field in the ferromagnetic nanopillars 5.
  • the magnetic field 12, 13 (referenced as M) of each pair of nanopillars 5 is opposite with one another or antiferromagnetic.
  • One magnetic field will be pointed in the "up” direction 12 while one will be pointed in the “down” direction 13.
  • the "up” direction, in terms of Figure 1 is the direction perpendicular (i.e., vertical) from the middle layer 4 and pointing towards the top layer 1.
  • the "down” direction in terms of Figure 1 is pointing in a direction perpendicular (i.e., vertical) to the middle layer 4 and towards the bottom layer 8, directly opposite of the direction of "up”.
  • Figure 3(B) when an electric field is applied to a nanopillar 5, the magnetic field 14 in the nanopillar 5 is pointed the direction of "in-plane” with the middle layer (i.e., horizontal).
  • the direction of "in-plane” is to be defined as parallel to that of the middle layer 4, in a direction perpendicular to that of "up” or "down”.
  • the top left and bottom right corner nanopillars of the four nanopillar square are to be magnetized in the "down" direction 13 while the top right and bottom left corner nanopillars are in the "up” direction 12.
  • an aspect of an embodiment may be applied so that the ferromagnetic nanopillars 5 couple antiferromagntically. This would be done through their dipolar exchange. Doing this creates two stable configurations of the array 25 in which each adjacent nanonpillar is oppositely magnetized for each configuration as desired or required.
  • a bit would consist of four nanopillars in a square (or other geometric configuration as desired or required) to provide a symmetrical arrangement with two corners to be polarized up and down, as for example shown in Figure 4.
  • the two states of the bit could be represented by the state of the left uppermost corner which could be up or down and the other adjacent nanopillars (and their associated antiferromagentic coupling (i.e., state)) would adjust accordingly due to their antiferromagnetic nature.
  • Any pattern of such bits could be formed in the array by applying electric fields to any nanopillars that need to be removed from those active in the gates. This removal would correspond to the magnetizations being shifted to being "in-plane" from being either "up” or "down”.
  • an array 25 (partial array as shown) with groupings of nine nano pillars 5 in a respective bit 41 may be realized in two types of bits.
  • the center pillar is not used and is always deactivated for both arrangements.
  • the arrangement of nanopillars in between, the corner pillars are at 45 degrees to the first arrangement.
  • crossovers in the same plane can be realized.
  • the logic or memory of the two types of bits can be obtained or accessed by propagating the bits in two different directions as shown, for example, by the arrows designated as "PD.”
  • PD the arrows designated as "PD.”
  • additional wires and control circuitry may be required.
  • columns and rows of nanopillars 5 may be provided between adjacent bits 41 to provide the required symmetrical spacing of the bits so the appropriate coupling is maintained throughout the array.
  • each nano-pillar can be a bit. It is envisioned within the context of the invention a structure with an additional gate between the pillars that can be used to control the interaction between the bits. The interaction between the bits can be made either ferromagnetic or antiferromagnetic depending on the electric field on this additional gate. In this case each pillar can be a bit. Such an approach would involve controlling the dipolar exchange between the bits. Making this embodiment of the array will be more difficult and it would have to be clocked, it would not operate autonomously or semiautonomously. Writing
  • writing can be done by first applying an electric field (for example the bias as indicated by "+” and “-” symbols) to put the magnetization, and hence the magnetic field 14 in the nanopillar to the "in-plane" direction (i.e., horizontal). More specifically, the electric field acts on the interface between the FM nanopillars 5 and the PE or FE matrix 6. This is a reason why the width of the conducting lines 2, 8 may be somewhat larger than the diameter of the nanopillars 5 so that the electric field extends a short distance into the matrix 6. In turn, this provides the strain which causes the magnetization of the nanopillars to rotate in- plane.
  • an electric field for example the bias as indicated by "+” and "-” symbols
  • a small magnetic bias field 19 is applied in a direction either up or down to accomplish the desired writing. If a 0 bit is a desired then the magnetic bias field is in the up direction and if a 1 bit is desired then the magnetic bias field 19 is in the down direction (i.e., apply the small magnetic bias field 19 in the direction that the writing is desired).
  • the electric field is then removed (as shown in Figure 6(B) and the input is written to the magnetic nanopillar 5 as was determined by the aforementioned magnetic bias field (i.e., remove the electric field and the input has been written). As shown in Figure 6(B), the nanopillar magnetic field is polarized in the "up" direction 12.
  • Another method for writing to the logic array is to deactivate all of the elements (i.e., nanopillars) that form the "input" bits and to apply a small magnetic bias field in the "up” direction. After the small magnetic bias field is applied in the "up” direction, the inputs that need to be in the "up” direction are selectively activated. Moreover, a similar procedure is used to write the "down" bits. After these are correctly selected, there are several options for the information to be propagated.
  • the electric field that forms the gates can be sequentially controlled (clocked) to propagate the information through the gates to do the appropriate logic functions or sections (or intended memory or storage) of the array can be controlled simultaneously, but the size of these sections must be such that the information will be certain to propagate in the forward direction (semi-autonomous operation).
  • clocking the array embodiment approach provides the appropriate directionality and the array can be operated at significantly higher speed than if run autonomously or semi- autonomously.
  • Figure 7 illustrates that an exemplary approach of reading the bits from the array is to do so capacitively.
  • the nanopillar 5, i.e., ferromagnetic layer (FM) is in communication with the nanopillar layer 11, e.g., a strongly magnetocapacitive material (such as CMC), and there is a large magnetic field on this CMC material from the ferromagnetic (FM) material (i.e., from the nanopillar itself).
  • a global magnetic field 29 is then applied to the array in the "up" direction 12 (specifically shown).
  • the magnetic field in the magnetocapacitive material 11 (e.g., CMC material) will be the sum of the magnetic fields if the moment is in the "up" direction 12 (as illustrated) and the difference of the magnetic fields if the moment is in the "down" direction (not specifically illustrated, but referred to a reference number 13 earlier).
  • the capacitance in the CMC is measured using the applied global magnetic field 20 and therefore either adding to or subtracting from the magnetic field produced by the magnetic moment of the FM material.
  • the left upper most nanopillar 18 (such as an input bit) as a form of a readout, the capacitance of the nanopillar across the crossbar array will depend on the direction of the magnetization in the nanopillar.
  • This process of reading in the reading phase as, referenced as 21 (e.g., by measuring the capacitance) and the process of writing in the writing phase, as referenced as 20 (by applying the magnetic bias field 19 in the desired or resultant up or down direction, as discussed earlier in Figure 6) can therefore be done with very small magnetic fields (29, 19, respectively).
  • Another method for reading from the logic array can be done magnetoresistively in two ways (not specifically shown in Figure 7).
  • One way of reading magnetoresistively is to use a tunnel junction whose resistance depends on the relative orientation of the nano pillar and the top interconnect which is now made of a magnetic film whose magnetization direction is pinned by an exchange bias layer.
  • the second magnetoresistive method of reading the magnetic logic array is to replace the magnetocapacitive (CMC) 11 layer with a magnetoresistive oxide such as LaSrMnO whose resistance depends strongly on the magnetic field.
  • the reading is done in a manner similar to the magnetocapcitive reading, but through the use of resistance instead of with capacitance as the sensing element.
  • a small global magnetic field is applied in the "up" direction and the total magnetic field seen by the magnetoresistive layer is the sum or difference between the magnetic field of the nanopillar and the applied magnetic field.
  • the sum or difference of the magnetic fields determines the resistance of the magentoresistive layer (i.e., the nanopillar layer) and therefore the output.
  • a gate pattern could be imposed on an array (such as any array discussed herein) in order to create a logic array such as a NOR gate 17.
  • the gate operation would be initiated by applying an electric field to the uppermost left corner of the input bit 18, which would rotate its magnetization to the "in-plane" direction.
  • a bias magnetic field such as a very small magnetic field from a small wire loop above the array, can be applied either “up” or “down” as the electric field is removed from the corner nanopillar of the input bit 18, resulting in this bit 18 being written and the gate operating as programmed.
  • the input bit 18 constitutes an unwritten or a zero bit (white).
  • an output bit 31 may be created using the aforementioned methodology used for the input bit. As illustrated the out bit 31 constitutes a written or one bit (black).
  • a gate pattern could be imposed on an array (such as any array discussed herein) in order to create a logic array such as a NOT gate 37.
  • the gate operation would be initiated by applying an electric field to the uppermost left corner of the input bit 38, which would rotate its magnetization to the "in-plane” direction.
  • a bias magnetic field such as a very small magnetic field from a small wire loop above the array, can be applied either “up” or “down” as the electric field is removed from the corner nanopillar of the input bit 38, resulting in this bit 38 being written and the gate operating as programmed.
  • the input bit 38 constitutes an unwritten or a zero bit (white).
  • an output bit 39 may be created using the aforementioned methodology used for the input bit.
  • the out bit 39 constitutes a written or one bit (black).
  • logic gates are considered part of the present application, such as NAND, OR, XOR, XNOR or AND gates, as well as 2-bit adder, and may, of course, be employed within the context of the invention.
  • the gates are written by applying the electric field to those nanopillars in a region that are not part of the gate pattern thus deactivating them.
  • the bits that are not deactivated form the gate array that can perform the logic functions either autonomously or clocked.
  • the pillar size and spacing between the pillars (edge to edge) in an embodiment may be about 5 nm to about 10 nm. Also, it should be appreciated that the pillar size and spacing may be in the range between from about 3 nm to about 25 nm; or less than about 3 nm or greater than about 25 nm.
  • a method is to use block co-polymer patterning.
  • Another method of creating the middle layer of the array is to use electron beam (or e-beam) lithography. This method is a form of maskless lithography in that no mask is required to generate the final pattern.
  • the final pattern for the middle section may be created directly from a digital representation on a computer by controlling an electron beam as it scans across the piezo or electro matrix.
  • Another method of manufacturing the middle layer of the array include using polymer self assembly. This method creates the materials that form the array by embedding them in the polymer and allowing them to precipitate out in a regulated or regular pattern.
  • FIG. 10 provides a cross-section of an exploded schematic view of a partial segment of an array pertaining to an embodiment that may use a ferroelectric (FE) material for the nanopillar 5 (rather than a FM material) and a paraelectric material as the nanopillar array layering 11 (rather than the CMC material).
  • FE ferroelectric
  • the ferroelectric (FE) material of the nanopillar 5, such as for example, BiFeO 3 , SrBaTiO 3 PZT, PZN, or any combination thereof, can be deposited so that the polarization could be either up or down and the paraelectric material (for example, BaSrTiO 3 or SrTiO 3 ) of the nanopillar layering 11 would respond to an electric field during reading in a manner similar to the way the CMC material responds to the global magnetic fields of some of the other embodiments.
  • the paraelectric material for example, BaSrTiO 3 or SrTiO 3
  • the nanopillars 5 would be located in a matrix 6, which makes up part of the middle layer 4.
  • the matrix may be comprised of FE or PE material, but this is not a requirement as it is for the ferromagnetic (FM) pillars.
  • FM ferromagnetic
  • the presence of the FE or PE matrix may facilitate the writing of these pillars (bits) using the electric field.
  • a lower substrate 10 or an upper substrate (not shown), or both a lower substrate 10 and an upper substrate may be in communication therewith.
  • FIG 11 provides a cross-section of an exploded schematic view of a partial segment of an array pertaining to an embodiment that may use a ferromagnetic (FM) material for the nanopillar 5 and a magnetoresistive oxide material (rather than the CMC material as in some of the other embodiments) as the nanopillar array layer 11.
  • the magnetoresistive oxide material is utilized whereby its resistance depends on the magnetic field.
  • the ferromagnetic (FM) material of the nanopillar 5 can be deposited on the bottom layer 7, for example (although not shown, may be deposited on the top layer 1).
  • the nanopillars 5 would be located among a matrix 6, having FE or PE material, which makes up part of the middle layer 4.
  • a lower substrate 10 or an upper substrate (not shown), or both a lower substrate 10 and an upper substrate may be in communication therewith.
  • an electric field is applied to the nanopillars and nanopillar layer to put the magnetization and hence the magnetic field in the nanopillar to the "in-plane" direction (i.e., horizontal).
  • a small magnetic bias field is applied in a direction either up or down to accomplish the desired writing.
  • the magnetoresistive oxide has to be conductive enough so that it can sustain a current whereby resistance can be measured, yet be a poor enough conductor so that both an electric field and a small current can exist simultaneously.
  • one practice may be to have an additional gate between the nanopillars to provide the electric field if using the same gate for field and current.
  • a global magnetic field (not shown in Figure 11) is applied and the magnetic field at the magnetoresistive oxide nanopillar layer 11 is either the sum or difference of these magnetic fields (i.e., magnetic fields of the FM material of the nanopillars and the applied global magnetic fields), and thereby the resistance of the magnetoresistive oxide material of the nanopillar layer 11 changes with the magnetic field.
  • a current passes through the nanopillars and the nanopillar layer enough so that the resistance can be read by the upper wires 2 and lower wires 8. Therefore the wires are capable of applying the current and reading out the resistance.
  • Two substrates 110, 151 are provided and are coated with an insulator layer 103, 109 such as silicon oxide layer of about 100 nm thick (other thicknesses and materials, such as silicon nitride, may be used as desired or required). For example the thickness may be between about 20 nm to about 100 nm; or it may be less than 20 nm or greater than 100 nm.
  • These wafers 110, 151 have embedded in them the transistors 161 and circuits 163 that will provide the voltage to wires that will be embedded in the insulating layer 103, 109.
  • the transistors 161 and circuits 163, such as control circuits will be distributed across the wafers 110, 151 (substrates) and each will be connected to one of the wires in the array at some point using a via (not shown) in the insulator layer 103, 109 of the wafer (substrate) 110, 151.
  • the wires 102, 108 may be embedded in the insulating layer 103, 109 by utilizing a nanoimprint process (or other process approach as desired or required) that exposes the appropriate highly regular wire array on a photoresist mask and deep grooves are formed in the insulator layer 103, 109 using a reactive ion etch specially configured for etching large aspect ratio structures in Si and SiO 2.
  • metal wires 102, 108 i.e., conductors
  • These types of processes may further be used other applications for either or both of the wafers 110, 151.
  • these processes may be applied so that each wafer 110, 151 has embedded in them transistors 161 connected to the wires 102, 108 as well as embedded circuits 163, such as control circuits embedded in them and in communication with the transistors and wires.
  • a piezoelectric (PE) or ferroelectric (FE) matrix 106 is deposited on one of the wafers.
  • That particular wafer may further be processed using a polymeric self assembly approach to deposit the array 125 of magnetic nanopillars 105 embedded in a piezoelectric (PE) or ferroelectric (FE) matrix.
  • PE piezoelectric
  • FE ferroelectric
  • An aspect of this process is to insure that the nanopillars are formed over the wires 102, 108 (that exist in the other two wafers 110, 151) in a highly aligned manner.
  • a layer of a colossal magnetocapacitive (CMC) material 111 is deposited uniformly on top of the nanopillar array 125. As illustrated the CMC is deposited over the entire matrix, however it should be appreciated that it may be deposited solely over the nanopillars itself or some combination or variation thereof.
  • CMC colossal magnetocapacitive
  • the two wafers (of which one will have the array of nanopillars) are flipped chipped together making sure that the wires on the flipped chip wafer run at least substantially perpendicular to the wires in the other wafer and the wires must be aligned with the nanopillars.
  • This sandwich structure will form the RAMA system 151.
  • connections to the RAMA system 151 can be made with contacts 165, such as leads, originating on the periphery of the wafers 110, 151 on the back side (or designated area as desired or required) using vias (not shown) connected to the circuits 163 and/or transistors 161 that will be used to control the RAMA system 151.
  • a magnetic field source 167 such as provided by helical coils (or other devices as desired or required) can be located on the back surface of the respective substrates.
  • the RAMA system 171 may be utilized for and as a part of, and in communication with (by way of the contacts or leads, for example) at least one of the following, but not limited thereto: microprocessors, microcontrollers, static RAM, and other digital logic circuits and memory circuits both embedded with the logic circuits or stand alone.
  • the RAMA system 171 may be utilized for and as a part of, and in communication with (by way of the contacts or leads, for example) with at least one of the following, but not limited thereto: a wide variety of analog circuits such as image sensors, data converters, and highly integrated transceivers for may types of communication. Any possible wireless communication may be applied to or with any of the aforementioned elements discussed herein (rather than hardwire or circuitry).
  • any activity can be repeated, any activity can be performed by multiple entities, and/or any element can be duplicated. Further, any activity or element can be excluded, the sequence of activities can vary, and/or the interrelationship of elements can vary. Unless clearly specified to the contrary, there is no requirement for any particular described or illustrated activity or element, any particular sequence or such activities, any particular size, speed, material, dimension or frequency, or any particularly interrelationship of such elements. Accordingly, the descriptions and drawings are to be regarded as illustrative in nature, and not as restrictive. Moreover, when any number or range is described herein, unless clearly stated otherwise, that number or range is approximate. When any range is described herein, unless clearly stated otherwise, that range includes all values therein and all sub ranges therein.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
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  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention a pour objet un procédé et un appareil de construction d’automates magnétiques et de structures associées via le développement d’un réseau de films minces auto-assemblés de nano-colonnes magnétiques. Le procédé et l’appareil permettent de configurer électriquement des motifs sur un dispositif, sans toutes les contraintes liées la production d’un motif compliqué sur une puce de semi-conducteur. Ceci réduit, par exemple, la contrainte impliquant l’utilisation d’outils lithographiques très onéreux dans la fabrication de ces structures. La présente invention a pour objet une architecture fabriquée à partir d’un réseau de films minces auto-assemblés de nano-colonnes magnétiques dans un réseau de barres transversales qui réalise non seulement des opérations logiques mais stocke également des informations.
PCT/US2009/059084 2008-09-30 2009-09-30 Réseau reconfigurable d’automates magnétiques (rama) et procédés associés WO2010039871A1 (fr)

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WO2012054040A1 (fr) * 2010-10-21 2012-04-26 Hewlett-Packard Development Company, L.P. Formation de nanopiliers coiffés
CN109628890A (zh) * 2019-01-10 2019-04-16 河北大学 一种钌酸锶/镧锶锰氧过渡金属氧化物异质结及其制备方法

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US6272036B1 (en) * 1999-12-20 2001-08-07 The University Of Chicago Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage
US20040127130A1 (en) * 2002-12-28 2004-07-01 Yi Gyu Chul Magnetic material-nanomaterial heterostructural nanorod
WO2006022859A2 (fr) * 2004-03-22 2006-03-02 The Ohio State University Dispositif spintronique possedant une couche d'espacement a nanotubes de carbone et procede de fabrication correspondant
US20070081276A1 (en) * 2002-03-28 2007-04-12 Kabushiki Kaisha Toshiba Magnetoresistance effect element, magnetic head, magnetic reproducing apparatus, and magnetic memory
US7227773B1 (en) * 2002-10-09 2007-06-05 Grandis, Inc. Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element
US20080230826A1 (en) * 2007-03-12 2008-09-25 The Board of Regents of the Nevada System of Higher Education on behalf of the University of Construction of flash memory chips and circuits from ordered nanoparticles

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Publication number Priority date Publication date Assignee Title
US6272036B1 (en) * 1999-12-20 2001-08-07 The University Of Chicago Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage
US20070081276A1 (en) * 2002-03-28 2007-04-12 Kabushiki Kaisha Toshiba Magnetoresistance effect element, magnetic head, magnetic reproducing apparatus, and magnetic memory
US7227773B1 (en) * 2002-10-09 2007-06-05 Grandis, Inc. Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element
US20040127130A1 (en) * 2002-12-28 2004-07-01 Yi Gyu Chul Magnetic material-nanomaterial heterostructural nanorod
WO2006022859A2 (fr) * 2004-03-22 2006-03-02 The Ohio State University Dispositif spintronique possedant une couche d'espacement a nanotubes de carbone et procede de fabrication correspondant
US20080230826A1 (en) * 2007-03-12 2008-09-25 The Board of Regents of the Nevada System of Higher Education on behalf of the University of Construction of flash memory chips and circuits from ordered nanoparticles

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012054040A1 (fr) * 2010-10-21 2012-04-26 Hewlett-Packard Development Company, L.P. Formation de nanopiliers coiffés
CN103153842A (zh) * 2010-10-21 2013-06-12 惠普发展公司，有限责任合伙企业 形成带帽纳米柱
CN109628890A (zh) * 2019-01-10 2019-04-16 河北大学 一种钌酸锶/镧锶锰氧过渡金属氧化物异质结及其制备方法
CN109628890B (zh) * 2019-01-10 2020-12-29 河北大学 一种钌酸锶/镧锶锰氧过渡金属氧化物异质结及其制备方法

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