WO2010035316A1 - Dispositif de commande de mémoire et procédé de commande de mémoire - Google Patents

Dispositif de commande de mémoire et procédé de commande de mémoire Download PDF

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Publication number
WO2010035316A1
WO2010035316A1 PCT/JP2008/067210 JP2008067210W WO2010035316A1 WO 2010035316 A1 WO2010035316 A1 WO 2010035316A1 JP 2008067210 W JP2008067210 W JP 2008067210W WO 2010035316 A1 WO2010035316 A1 WO 2010035316A1
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Prior art keywords
memory
data
read
address
control device
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PCT/JP2008/067210
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English (en)
Japanese (ja)
Inventor
恵治 嶋谷
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富士通株式会社
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Priority to PCT/JP2008/067210 priority Critical patent/WO2010035316A1/fr
Publication of WO2010035316A1 publication Critical patent/WO2010035316A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

Definitions

  • the present invention relates to a memory control device and a memory control method for controlling memory access to a plurality of memory banks.
  • CPU Central Processing Unit
  • PA physical address
  • the memory control device converts the physical address into a memory address and determines an access destination.
  • the present invention has been made in order to solve the above-described problems related to the prior art, and provides a memory control device and a memory control method having the same reliability as the mirror mode and the same transmission speed as the non-mirror mode.
  • the purpose is to provide.
  • the disclosed apparatus and method write data of the same contents to both the first memory bank and the second memory bank and accept a read request.
  • the data specified by the read request is divided into the first half and the second half, and one memory bank is used for normal read of the first half data and preliminary read of the second half data, and the other memory bank is used for normal read of the second half data and preliminary read of the second half data.
  • the preliminary reading is executed when there is an unrecoverable error in the result of normal reading.
  • FIG. 1 is a conceptual diagram illustrating the concept of the memory control method according to the present embodiment.
  • FIG. 2 is a schematic configuration diagram illustrating a schematic configuration of the computer apparatus according to the present embodiment.
  • FIG. 3 is a configuration diagram illustrating the configuration of the write control unit 21.
  • FIG. 4 is a configuration diagram illustrating the configuration of the read control unit 22.
  • FIG. 5 is an explanatory diagram for explaining a basic operation of a conventional memory control device (MAC).
  • FIG. 6 is an explanatory diagram for explaining the operation in the conventional non-mirror mode.
  • FIG. 7 is an explanatory diagram for explaining the operation in the conventional mirror mode.
  • FIG. 8 is an explanatory diagram for explaining the operation of improving the reliability in the conventional mirror mode.
  • FIG. MAC memory control device
  • FIG. 9 is an explanatory diagram for explaining the memory control operation according to the present embodiment.
  • FIG. 10 is an explanatory diagram illustrating the reliability improvement operation in the memory control according to the present embodiment.
  • FIG. 11 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 9 is performed.
  • FIG. 12 is a diagram illustrating a first modification of address assignment.
  • FIG. 13 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 12 is performed.
  • FIG. 14 is a diagram illustrating a second modification of address assignment.
  • FIG. 15 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 14 is performed.
  • FIG. 16 is a flowchart for explaining data read processing of the first 64 bytes.
  • FIG. 17 is a flowchart for explaining read processing of data of the latter half 64 bytes.
  • FIG. 18 is a flowchart for explaining the processing operation of the data selection units 22d0 and 22d1.
  • FIG. 1 is a conceptual diagram illustrating the concept of the memory control method according to the present embodiment.
  • the same contents are duplicated and written at the time of writing, and the data read from different addresses are combined and transmitted at the time of reading.
  • the same physical address is assigned to the same DIMM address for the two memory banks B0 and B1, each of which is a set of a plurality of DIMMs (Dual Inline Memory Modules).
  • the same data is written in 4-7. Since the transfer amount per cycle of the memory banks B0 and B1 is 64 bytes, the transmission rate at the time of writing is 64 bytes / cycle.
  • the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are read and combined and transmitted. Since the same contents are written to the same addresses in the memory banks B0 and B1 at the time of writing, the contents obtained by combining the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are combined into the memory bank B0. The same contents as the DIMM addresses 0 to 7 and the DIMM addresses 0 to 7 of the memory bank B1.
  • FIG. 1 illustrates a case where both of the DIMM addresses 0 to 3 of the memory bank B0 and the DIMM addresses 4 to 7 of the memory bank B1 are in error, but the DIMM addresses 0 to 3 of the memory bank B0 and the memory addresses of the memory bank B1 If any one of the DIMM addresses 4 to 7 is an error, only the error may be read from the other memory bank.
  • the transmission speed at the time of reading can be set to 128 bytes / cycle.
  • FIG. 2 is a schematic configuration diagram illustrating a schematic configuration of the computer apparatus according to the present embodiment.
  • the computer apparatus 1 shown in FIG. 2 includes a system controller (SC) 13, an arithmetic processing unit (CPU: Central Processing Unit) 11, a memory control unit (MAC: Memory Access controller) 12, and an interface unit 14.
  • the memory control device 12 is further connected to memory banks B0 and B1.
  • the arithmetic processing unit 11 is a device that executes various arithmetic processes.
  • the arithmetic processing executed by the arithmetic processing unit 11 includes writing data to the memory banks B0 and B1, which are main storage devices, and reading data from the memory banks B0 and B1.
  • the arithmetic processing unit 11 issues a physical address (PA) and designates an access destination when performing memory access to the memory banks B0 and B1.
  • PA physical address
  • the interface device 14 is a device for connecting to various devices (not shown) such as an auxiliary storage device and a network communication device.
  • the system control device 13 is a bridge that connects the arithmetic processing device 11, the memory control device 12, and the interface device 14.
  • the memory bank B0 has two memory modules M01 and M02, and the memory bank B1 has two memory modules M11 and M12. Each of the memory modules M01, M02, M11, and M12 is a DIMM.
  • the memory control device 12 includes therein a write control unit 21 that controls writing to the memory banks B0 and B1, and a read control unit 22 that controls reading from the memory banks B0 and B1.
  • FIG. 3 is a configuration diagram illustrating the configuration of the write control unit 21. As shown in FIG. 3, the write control unit 21 includes an address conversion unit 21a and an error detection information generation unit 21b therein.
  • the address conversion unit 21a converts the physical address (PA) issued by the arithmetic processing unit 11 into DA that is an address in the DIMM. In this conversion, the address conversion unit 21a creates an address for the memory bank B0 and an address for the memory bank B1, respectively.
  • the physical address PA is aligned in units of 64 bytes.
  • the error detection information generation unit 21b receives 64 bytes of data from the arithmetic processing unit 11 via the system control unit 13.
  • the error detection information generation unit 21b divides the 64-byte data into four 16-byte data, and calculates an error check code (ECC) that is error detection information every 16 bytes. Then, the error detection information generation unit 21b transmits (data 16 bytes + error check code 2 bytes) ⁇ 4 data to the memory modules in the memory bank B0 and the memory bank B1.
  • ECC error check code
  • FIG. 4 is a configuration diagram illustrating the configuration of the read control unit 22.
  • the read control unit 22 includes address conversion units 22a0 and 22a1, address selection units 22b0 and 22b1, reread confirmation units 22c0 and 22c1, data selection units 22d0 and 22d1, and a data transmission unit 22e.
  • the physical address PA issued when the arithmetic processing unit 11 issues a read request is aligned (aligned) in units of 128 bytes.
  • the read control unit 22 reads the physical address of 128 bytes from the memory bank by dividing the physical address into the first half 64 bytes and the second half 64 bytes.
  • the address conversion unit 22a0 is a processing unit responsible for address conversion of the first half 64 bytes.
  • the address conversion unit 22a0 designates the address of the memory bank B0 as the normal read address, and designates the address of the memory bank B1 as the reread address.
  • the address conversion unit 22a0 calculates the memory address DA by setting the value of the sixth bit of the physical address PA to “0”.
  • the address conversion unit 22a1 is a processing unit responsible for address conversion of the second half 64 bytes.
  • the address conversion unit 22a1 designates the address of the memory bank B1 as the normal read address, and designates the address of the memory bank B0 as the reread address. Further, the address conversion unit 22a1 calculates the memory address DA by setting the value of the sixth bit of the physical address PA to “1”.
  • the address selection unit 22b0 is a processing unit that reads from the memory bank B0. First, when the memory address DA is sent from the address conversion units 22a0 and 22a1, the address selection unit 22b0 selects the normal read address sent from the address conversion unit 22a0 and reads from the memory module in the memory bank B0. . Thereafter, when there is a reread request from the reread confirmation unit 22c1, the reread address is selected and read again from the memory module in the memory bank B0.
  • the address selection unit 22b1 is a processing unit that reads from the memory bank B1. First, when the memory address DA is sent from the address conversion units 22a0 and 22a1, the address selection unit 22b1 selects the normal read address sent from the address conversion unit 22a1 and reads from the memory module in the memory bank B1. . Thereafter, when there is a reread request from the reread confirmation unit 22c0, the reread address is selected and read again from the memory module in the memory bank B0.
  • the read confirmation unit 22c0 is a reread determination unit that determines the necessity of rereading based on the result of the normal read of the first 64 bytes, and makes a reread request to the address selection unit 22b1 when rereading is necessary. From the memory module, a set of data and an error check code (data 16 bytes + error check code 2 bytes) is output four times. The reread confirmation unit 22c0 checks each error check code against the normal read data, and determines that rereading is necessary if there is an uncorrectable error (UE) in any one of the four. .
  • UE uncorrectable error
  • the read confirmation unit 22c1 is a reread determination unit that determines the necessity of rereading based on the result of the normal read of the second half 64 bytes and makes a reread request to the address selection unit 22b0 when rereading is necessary. From the memory module, a set of data and an error check code (data 16 bytes + error check code 2 bytes) is output four times. The reread confirmation unit 22c1 checks each error check code with respect to the normal read data, and determines that rereading is necessary if any one of the four errors (UE) cannot be corrected.
  • the data selection unit 22d0 checks the ECC of normal read data of 64 bytes in the first half, and if there is no error or a correctable error (CE), selects the normal read data. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e.
  • CE correctable error
  • the data selection unit 22d0 checks the error check code of the data reread from the memory bank B1. As a result of this check, if the reread data is no error or CE, the reread data is selected. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e. If the reread data is also a UE, “Marked UE” is sent to the data sending unit 22e.
  • the data selection unit 22d1 checks the ECC of the normal read data of the latter half 64 bytes, and selects normal read data if there is no error or a correctable error (CE). If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e.
  • CE correctable error
  • the data selection unit 22d1 checks the error check code of the data reread from the memory bank B0. As a result of this check, if the reread data is no error or CE, the reread data is selected. If there is no error, the data is corrected if it is CE, and the data is corrected and sent to the data sending unit 22e. If the reread data is also a UE, “Marked UE” is sent to the data sending unit 22e.
  • the data transmission unit 22e combines the data of the first half 64 bytes sent from the data selection unit 22d1 with the data of the first half 64 bytes sent from the data selection unit 22d0, and outputs the data to the system controller 13 as 128 bytes data.
  • the designated 128-byte data is divided into the first half and the second half, and the data is read out from different memory banks and combined, whereby the data can be read out in 128 bytes.
  • FIG. 5 is an explanatory diagram for explaining a basic operation of a conventional memory control device (MAC).
  • the physical address (PA) indicates a place to write / read when the arithmetic processing unit accesses the memory, and is 1 byte per address.
  • the memory controller converts the physical address into a DIMM address, and the corresponding DIMM of the DIMM connected to the memory controller Write data to address.
  • Two memory banks B0 and B1 are connected to one memory control device, and two DIMMs are connected to each of the memory banks B0 and B1.
  • the two memory banks B0 and B1 operate independently of each other, and can simultaneously perform operations such as writing to and reading from each connected DIMM.
  • the data to be written to / read from the DIMM uses the error correction code of the data part 16 bytes + ECC part 2 bytes, and can correct a 1-bit error and detect a 2-bit error.
  • the operation mode of the memory control device includes the mirror mode and the non-mirror mode as described above.
  • the non-mirror mode is a capacity and speed priority mode.
  • FIG. 6 is an explanatory diagram for explaining the operation in the conventional non-mirror mode.
  • PA0 to 63 are assigned to DA0 to DA3 of memory bank B0, and PA64 to 127 are assigned to DA0 to 3 of memory bank B1. Further, PA128 to 191 are assigned to DA4 to 7 of memory bank B0, and PA192 to 255 are assigned to DA4 to 7 of memory bank B1.
  • PA0 to 63 are written to DA0 to 3 of memory bank B0, and PA64 to 127 are written to DA0 to 3 of memory bank B1.
  • PA0 to 63 are read from DA0 to DA3 of memory bank B0, and PA64 to 127 are read from DA0 to DA3 of memory bank B1.
  • the mirror mode is a mode in which the reliability of data is improved instead at the expense of capacity and speed.
  • FIG. 7 is an explanatory diagram for explaining the operation in the conventional mirror mode.
  • the same physical address is assigned to the two memory banks B0 and B1, and the same data is written twice at the time of writing.
  • data of the same physical address is simultaneously read from the two memory banks B0 and B1, and ECC check and data compare are performed.
  • ECC check and the data conveyor even if an uncorrectable error occurs in one of the memory banks, the data is not damaged.
  • the same physical address is assigned to the memory bank B0 and the memory bank B1.
  • the data from the system control device is written twice in the memory banks B0 and B1. Therefore, the data transfer amount between the system control device and the memory control device per cycle is 64 bytes.
  • data of the same physical address is simultaneously read from the memory banks B0 and B1, data to be transmitted is determined by ECC check and data compare, and sent to the system controller. Therefore, the data transfer amount between the system control device and the memory control device per cycle is 64 bytes.
  • PA0 to 63 are assigned to DA0 to 3 of memory bank B0 and memory bank B1
  • PA64 to 127 are assigned to DA4 to 7 of memory bank B0 and memory bank B1.
  • PA0 to 63 when a write request specifying physical addresses PA0 to 63 is received from the system controller, PA0 to 63 are written to both DA0 to DA3 of memory bank B0 and DA0 to DA3 of memory bank B1.
  • PA0 to 63 When a read request specifying physical addresses PA0 to 63 is received from the system controller, PA0 to 63 are read from both DA0 to DA3 of memory bank B0 and DA0 to DA3 of memory bank B1, and ECC check, Reliability is improved by performing data comparison.
  • FIG. 8 is an explanatory diagram for explaining the operation of improving the reliability in the conventional mirror mode. As shown in FIG. 8, if the data read from the memory bank B0 and the data read from the memory bank 1 are both error-free (ECC check OK) and the data comparison results match (data conveyor ⁇ ), the data can be obtained. It is assumed that the obtained data is normal.
  • ECC check OK error-free
  • data conveyor ⁇ data conveyor ⁇
  • ECC check UE One of the data read from the memory bank B0 and the data read from the memory bank 1 is an uncorrectable error (ECC check UE), and the other is no error (ECC check OK) or correctable error (CE).
  • ECC check OK no error
  • CE correctable error
  • the data conveyor is not performed, and it is assumed that the data obtained without error (ECC check OK) or the data obtained by correcting the error is normal.
  • one of the data read from the memory bank B0 and the data read from the memory bank 1 is a correctable error (CE), and the other is no error (ECC check OK) or a correctable error (CE). Then, after correcting the error, the data are compared, and if the data comparison results do not match (data conveyor ⁇ ), “Marked UE” is output.
  • data of the same physical address is written to the memory banks B0 and B1 at the time of writing, and data of physical addresses different from each other are read at the memory banks B0 and B1 at the time of reading. If the read data is an error that cannot be corrected, the data of the same physical address is written somewhere in the other memory bank. Do. By doing so, even if the data read from one of the memory banks is an error that cannot be corrected, the data is not lost and normal data can be obtained. If an uncorrectable error does not occur, the transfer speed at the time of reading is the same as in the non-mirror mode.
  • FIG. 9 is an explanatory diagram for explaining the memory control operation according to the present embodiment.
  • the first half of the DIMM address is assigned different physical addresses by 64 bytes alternately in the memory bank B0 and the memory bank B1 as in the non-mirror mode.
  • the second half of the DIMM address is assigned the same physical address as the first half of the paired memory bank.
  • the data from the system control device is written twice in the two memory banks B0 and B1.
  • the DA for writing data is different between the memory bank B0 and the memory bank B1.
  • the data transfer amount between the system controller and the memory controller per cycle is 64 bytes, which is the same as in the conventional mirror mode.
  • the memory bank to be read is changed every time the physical address PA is +64, and the memory banks B0 and B1 are operated in parallel at the same time. Retrieve the data.
  • UE uncorrectable error
  • FIG. 10 is an explanatory diagram for explaining the reliability improving operation in the memory control according to the present embodiment.
  • the ECC check result in the first read indicates no error (OK)
  • reread is not performed and the obtained data is used as normal data as it is.
  • CE correctable error
  • the lead is executed again (reread).
  • the reread ECC check result indicates no error (OK)
  • the data obtained by the reread is set as normal data.
  • the ECC check result in reread is a correctable error (CE)
  • the data obtained by reread is corrected to normal data.
  • “Marked UE” is output.
  • the data transfer amount of one cycle between the system controller and the memory controller is the conventional non-mirror mode. It will be 128 bytes as well as the hour.
  • FIG. 11 is an explanatory diagram for explaining the address conversion when the address allocation shown in FIG. 9 is performed.
  • the capacity per memory bank is 1 Kbyte
  • the value of the fourth bit of PA becomes the value of the 0th bit of DA
  • the value of the fifth bit of PA becomes the value of the first bit of DA.
  • the 6th bit value of PA is the 5th bit value of DA
  • the 7th to 9th bit values of PA are the 2nd to 4th bit values of DA, respectively.
  • the value of the fourth bit of PA becomes the value of the 0th bit of DA
  • the value of the fifth bit of PA becomes the first bit of DA. Value.
  • the 6th bit value of PA is inverted to the 5th bit value of DA
  • the 7th to 9th bit values of PA are set to the 2nd to 4th bit values of DA, respectively.
  • FIG. 12 shows a first modification of address allocation
  • FIG. 13 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 12 is performed.
  • the memory bank B0 is the same as the mirror mode. That is, PA0 to 63 are assigned to DA0 to DA3, and PA64 to 127 are assigned to DA4 to DA7. Similarly, PAs 128 to 191 are assigned to DAs 8 to 11, and PAs 192 to 255 are assigned to DAs 12 to 15.
  • PAs 64 to 127 are assigned to DA0 to DA3
  • PAs 0 to 63 are assigned to DA4 to 7.
  • PAs 192 to 255 are assigned to DAs 8 to 11
  • PAs 128 to 191 are assigned to DAs 12 to 15.
  • the value of the fourth bit of PA becomes the value of the 0th bit of DA
  • the value of the fifth bit becomes the value of the first bit of DA.
  • the 6th to 9th bit values of PA are the 2nd to 5th bit values of DA, respectively.
  • the value of the fourth bit of PA becomes the value of the 0th bit of DA
  • the value of the fifth bit of PA becomes the first bit of DA. Value.
  • the 6th bit value of PA is inverted to the 2nd bit value of DA
  • the 7th to 9th bit values of PA are set to the 3rd to 5th bit values of DA, respectively.
  • the memory banks B0 and B1 read a portion where DA is a multiple of 8, and if it is UE, read the portion where DA is +4 in the other memory bank. That is, first, the portion surrounded by the solid line in FIG. 12 is read, and if the error cannot be corrected, the portion surrounded by the broken line is read.
  • the transmission data at the time of reading is the same as the example shown in FIG.
  • FIG. 14 is a second modification of address allocation
  • FIG. 15 is an explanatory diagram for explaining address conversion when the address allocation shown in FIG. 14 is performed.
  • the address assignment shown in FIG. 14 is the same as in the conventional mirror mode.
  • PA0 to 63 are assigned to DA0 to DA3 of memory bank B0 and memory bank B1
  • PA64 to DA4 to 7 of memory bank B0 and memory bank B1 are assigned.
  • 127 is assigned.
  • PA128 to 191 are assigned to DA8 to 11 of memory bank B0 and memory bank B1
  • PA192 to 255 are assigned to DA12 to 15 of memory bank B0 and memory bank B1.
  • the address conversion in this case is the same in the memory bank B0 and the memory bank B1
  • the value of the fourth bit of the physical address PA becomes the value of the 0th bit of DA
  • the PA 5 The value of the bit is the value of the first bit of DA.
  • the 6th to 9th bit values of PA are the 2nd to 5th bit values of DA, respectively.
  • the memory bank to be read is changed every time PA is +64 (DA is +4). If the read result is UE, the same DA location in the other memory bank is read. That is, first, the portion surrounded by the solid line in FIG. 14 is read, and if the error cannot be corrected, the portion surrounded by the broken line is read. As a result, the transmission data at the time of reading is the same as the example shown in FIG.
  • FIG. 16 is a flowchart for explaining data read processing of the first 64 bytes.
  • the address conversion unit 22a0 obtains the DA for normal reading from the physical address PA aligned in 128 bytes using address conversion for the memory bank B0 (PA ⁇ DA conversion).
  • Reread DA is obtained by using address conversion for B1 (PA ⁇ DA conversion).
  • the sixth bit of PA is set to 0 (S101).
  • the address selector 22b0 reads data from the normal read DA (S102), and sends the normal read data obtained by the read to the data selector 22d0 (S103).
  • the reread confirmation unit 22c0 checks the ECC of the normal read data (S104), and if there is no unrecoverable error (S104, no UE), the process is terminated as it is. However, if there is an uncorrectable error (S104, with UE), a reread request is transmitted to the address selection unit 22b1 (S105).
  • the address selection unit 22b1 that has received the reread request reads data from the reread DA (S106), sends the reread data obtained by the read to the data selection unit 22d0 (S107), and ends the processing.
  • FIG. 17 is a flowchart for explaining the data read process of the second half 64 bytes.
  • the address conversion unit 22a1 obtains the DA for normal reading from the physical address PA aligned in 128 bytes by using address conversion for the memory bank B1 (PA ⁇ DA conversion), and the memory bank Reread DA is obtained by using address conversion for B0 (PA ⁇ DA conversion).
  • the sixth bit of PA is set to 1 (S201).
  • the address selector 22b1 reads data from the normal read DA (S202), and sends the normal read data obtained by the read to the data selector 22d1 (S203).
  • the reread confirmation unit 22c1 checks the ECC of the normal read data (S204), and if there is no unrecoverable error (S204, no UE), the process is terminated as it is. However, if there is an uncorrectable error (S204, with UE), a reread request is transmitted to the address selection unit 22b0 (S205).
  • the address selection unit 22b0 that has received the reread request reads data from the reread DA (S206), sends the reread data obtained by the read to the data selection unit 22d1 (S207), and ends the processing.
  • FIG. 18 is a flowchart for explaining the processing operation of the data selection units 22d0 and 22d1.
  • the data selectors 22d0 and 22d1 perform this process for each data 16 bytes.
  • the data selection units 22d0 and 22d1 first check the ECC of the normal read data (S301). As a result, if there is no error (OK) or the error can be corrected even if there is an error (S301, OK or CE), the process proceeds to step S304. If it is CE (S304, Yes), the data is corrected (S305), and the data is sent to the data sending unit 22e (S306). If it is not CE and there is no error (S304, No), the data is sent as it is to the data sending unit 22e (S306).
  • the data selection units 22d0 and 22d1 check the ECC of the reread data (S302). As a result, if there is no error (OK) or if the error can be corrected (S302, OK or CE), the process proceeds to step S307. If it is CE (S307, Yes), data correction is performed (S308), and then the data is sent to the data sending unit 22e (S309). If it is not CE and there is no error (S307, No), the data is sent as it is to the data sending unit 22e (S309).
  • the data selection units 22d0 and 22d1 send “Marked UE” to the data transmission unit 22e (S303).
  • the data of the same physical address is written to the memory banks B0 and B1 at the time of writing, and the data of different physical addresses are read at the memory banks B0 and B1 at the time of reading.
  • the read data is an error that cannot be corrected
  • the data of the same physical address is written somewhere in the other memory bank. Do. By doing so, even if the data read from one of the memory banks is an error that cannot be corrected, the data is not lost and normal data can be obtained.
  • the transfer speed at the time of reading is the same as that in the non-mirror mode, so that the memory control device having the same reliability as the mirror mode and the same transmission speed as the non-mirror mode A memory control method can be obtained.

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Les données de la même adresse physique sont écrites dans des banques de mémoire (B0, B1) à l'instant d'écriture et les données de différentes adresses physiques sont lues dans les banques de mémoire (B0, B1) à l'instant de lecture, lesquelles sont délivrées en combinaison. Si les données lues dans la banque de mémoire (B0) comportent une erreur qui ne peut pas être corrigée, les données sont lues de nouveau à l'emplacement où les données de la même adresse physique de la banque de mémoire (B1) sont écrites. Si les données lues dans la banque de mémoire (B1) comportent une erreur qui ne peut pas être corrigée, les données sont lues de nouveau à l'emplacement où les données de la même adresse physique de la banque de mémoire (B0) sont écrites.
PCT/JP2008/067210 2008-09-24 2008-09-24 Dispositif de commande de mémoire et procédé de commande de mémoire WO2010035316A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2738677A1 (fr) * 2011-08-23 2014-06-04 Huawei Technologies Co., Ltd. Procédé et dispositif de détection de fiabilité de données
GB2519849A (en) * 2013-08-29 2015-05-06 Quixant Plc Memory controller, memory arrangement and memory access method

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JP2006505864A (ja) * 2002-11-08 2006-02-16 インテル コーポレイション インタリーブミラーメモリシステム
JP2008158804A (ja) * 2006-12-22 2008-07-10 Nec Corp メモリコントローラ、コンピュータ、データ読み出し方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006505864A (ja) * 2002-11-08 2006-02-16 インテル コーポレイション インタリーブミラーメモリシステム
JP2008158804A (ja) * 2006-12-22 2008-07-10 Nec Corp メモリコントローラ、コンピュータ、データ読み出し方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2738677A1 (fr) * 2011-08-23 2014-06-04 Huawei Technologies Co., Ltd. Procédé et dispositif de détection de fiabilité de données
EP2738677A4 (fr) * 2011-08-23 2014-07-23 Huawei Tech Co Ltd Procédé et dispositif de détection de fiabilité de données
JP2014529793A (ja) * 2011-08-23 2014-11-13 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． データ信頼性を検出するための方法及び装置
AU2011361394B2 (en) * 2011-08-23 2015-07-09 Huawei Technologies Co., Ltd. Method and device for detecting data reliability
US9195543B2 (en) 2011-08-23 2015-11-24 Huawei Technologies Co., Ltd. Method and device for detecting data reliability
GB2519849A (en) * 2013-08-29 2015-05-06 Quixant Plc Memory controller, memory arrangement and memory access method
GB2519849B (en) * 2013-08-29 2017-02-08 Quixant Plc Memory controller, memory arrangement and memory access method

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