WO2010029634A1 - Elément à variation de résistance, et dispositif de reproduction/d'enregistrement d’informations - Google Patents

Elément à variation de résistance, et dispositif de reproduction/d'enregistrement d’informations Download PDF

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Publication number
WO2010029634A1
WO2010029634A1 PCT/JP2008/066471 JP2008066471W WO2010029634A1 WO 2010029634 A1 WO2010029634 A1 WO 2010029634A1 JP 2008066471 W JP2008066471 W JP 2008066471W WO 2010029634 A1 WO2010029634 A1 WO 2010029634A1
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Prior art keywords
layer
resistance change
resistance
variable resistance
voltage
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PCT/JP2008/066471
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English (en)
Japanese (ja)
Inventor
司 中居
隆之 塚本
親義 鎌田
伸也 青木
隆大 平井
光一 久保
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株式会社 東芝
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Priority to PCT/JP2008/066471 priority Critical patent/WO2010029634A1/fr
Publication of WO2010029634A1 publication Critical patent/WO2010029634A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B9/00—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor
    • G11B9/04—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using record carriers having variable electric resistance; Record carriers therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/565—Multilevel memory comprising elements in triple well structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/17—Memory cell being a nanowire transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/35—Material including carbon, e.g. graphite, grapheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a resistance change element and an information recording / reproducing apparatus.
  • NAND flash memory and small HDD hard disk drive
  • Non-Patent Documents 1 and 2 a memory using a resistance change material having a low resistance state and a high resistance state has been proposed (for example, Non-Patent Documents 1 and 2).
  • a voltage pulse can be applied to the variable resistance material to repeatedly change between a low resistance state and a high resistance state, and these two states correspond to binary data “0” and “1”.
  • To record data a memory using a resistance change material having a low resistance state and a high resistance state.
  • Such an information recording / reproducing apparatus is expected to enable multi-value recording and further increase the recording density.
  • P Bachtold G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis and E. Eleftheriou, in Technical Digest, IEDM03 pp.763-766
  • variable resistance element and an information recording / reproducing apparatus capable of multi-value recording are provided.
  • a first resistance change layer that exhibits a plurality of states having different electrical resistivity depending on at least one of an applied voltage and an energized current is stacked on the first resistance change layer.
  • a second variable resistance layer having a composition different from that of the first variable resistance layer and exhibiting a plurality of states having different electrical resistivity depending on at least one of an applied voltage and an applied current.
  • a variable resistance portion; and an electrode layer that performs at least one of voltage application and current flow perpendicular to the film surface of the variable resistance portion, and includes a plurality of different states in the first variable resistance layer. At least one of the transition voltage and current and at least one of the transition voltage and current between the plurality of different states in the second resistance change layer are different from each other.
  • the variable resistance element is provided, wherein.
  • an information recording / reproducing apparatus comprising: a drive unit that records information by causing the resistance change unit to transition between a plurality of resistance states.
  • 1 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a first embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of the information recording / reproducing apparatus to which the variable resistance element according to the first embodiment of the present invention is applied. It is a schematic diagram which illustrates the characteristic of the variable resistance element which concerns on the 1st Embodiment of this invention. It is a schematic diagram which illustrates the characteristic of the variable resistance element which concerns on the 1st Embodiment of this invention. It is another graph which illustrates the characteristic of the resistance change element concerning a 1st embodiment of the present invention. It is another schematic diagram which illustrates the characteristic of the variable resistance element which concerns on the 1st Embodiment of this invention.
  • FIG. 5 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a second embodiment of the invention.
  • FIG. 6 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a third embodiment of the invention. It is a typical sectional view which illustrates the composition of another variable resistance element concerning a 3rd embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a fourth embodiment of the invention.
  • FIG. 10 is a schematic cross-sectional view illustrating the configuration of another resistance change element according to the fourth embodiment of the invention.
  • FIG. 9 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a fifth embodiment of the invention.
  • FIG. 10 is a schematic cross-sectional view illustrating the configuration of another variable resistance element according to the fifth embodiment of the invention. It is a typical sectional view which illustrates the composition of the resistance change element concerning a 6th embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to a seventh embodiment of the invention. It is a schematic diagram illustrating the configuration and operation of a part of the resistance change element according to the embodiment of the invention. It is a typical sectional view which illustrates a part of composition and operation of a variable resistance element concerning an embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to an embodiment of the invention. It is a typical perspective view which illustrates the structure of the information recording / reproducing apparatus which concerns on the 8th Embodiment of this invention.
  • FIG. 20 is a schematic plan view illustrating the configuration of a part of an information recording / reproducing apparatus according to an eighth embodiment of the invention. It is a schematic diagram which illustrates operation
  • FIG. 1 It is a schematic diagram which illustrates reproduction
  • FIG. 25 is a schematic perspective view illustrating the configuration of another information recording / reproducing apparatus according to the ninth embodiment of the invention.
  • FIG. 25 is a schematic perspective view illustrating the configuration of another information recording / reproducing apparatus according to the ninth embodiment of the invention. It is a typical sectional view which illustrates the composition of the principal part of the information recording / reproducing apparatus concerning a 10th embodiment of the present invention.
  • FIG. 20 is a schematic cross-sectional view illustrating the operation of an information recording / reproducing apparatus according to a tenth embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of another information recording / reproducing apparatus which concerns on the 10th Embodiment of this invention.
  • FIG. 10 It is a schematic diagram which illustrates the structure of the principal part of another information recording / reproducing apparatus which concerns on the 10th Embodiment of this invention. It is a typical sectional view which illustrates the principal part of another information recording and reproducing device concerning a 10th embodiment of the present invention. It is a typical sectional view which illustrates the principal part of the information recording / reproducing apparatus of the modification concerning the 10th embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view illustrating the configuration of a variable resistance element according to the first embodiment of the invention.
  • the resistance change element 310 according to the first embodiment of the present invention includes a first resistance change layer (first memory layer) 12 ⁇ / b> A ⁇ b> 1, a second resistance change layer ( (Second recording layer) 12A2 and upper electrode 13A are sequentially stacked. That is, the resistance change portion (recording portion) 12 includes a first recording layer 12A1 and a second resistance change layer 12A2.
  • the nonvolatile memory element 310 can be applied to, for example, a nonvolatile memory such as a cross point type, a probe memory type, and various flash memory types.
  • a configuration of the nonvolatile memory element 310 when the nonvolatile memory element 310 is used in a cross-point nonvolatile memory device will be described.
  • FIG. 2 is a schematic view illustrating the configuration of the main part of an information recording / reproducing apparatus to which the variable resistance element according to the first embodiment of the invention is applied.
  • the memory cell 33 and the rectifying element 34 are used in the cross-point type information recording / reproducing apparatus 210. Is provided.
  • the upper and lower arrangement relationship between the word line WL i and the bit line BL j is arbitrary.
  • the arrangement relationship between the memory cell 33 and the rectifying element 34 between the word line WL i and the bit line BL j is also arbitrary. That is, in the specific example illustrated in FIG. 2, the memory cell 33 is disposed on the bit line BL j side with respect to the rectifying element 34, but the memory cell 33 is disposed on the word line WL i side with respect to the rectifying element 34. May be.
  • the memory cell 33 includes a resistance change element 310.
  • the resistance change element 310 includes a lower electrode 11, an upper electrode 13A, and a recording layer 12 provided between the lower electrode 11 and the upper electrode 13A.
  • the upper electrode 13A and the lower electrode 11 are convenient names and can be interchanged.
  • the memory cell 33 can include a protective layer 33B and a heater layer 35 provided between the resistance change element 310 and the protection layer 33B.
  • the protective layer 33B is provided on the bit line BL j side of the variable resistance element 310, but the protective layer 33B may be provided on the word line WL i side of the variable resistance element 310. Alternatively, it may be provided between the rectifying element 34 and the word line WL i .
  • the heater layer 35 and the protective layer 33B are provided as necessary and can be omitted.
  • a plurality of these word lines WL i , rectifying elements 34, memory cells 33, and bit lines BL j are provided, and an insulating layer is provided between them to be insulated from each other.
  • At least one of the lower electrode 11 and the upper electrode 13A of the resistance change element 310 is adjacent to the resistance change element 310, for example, the word line WL i , the rectifier element 34, the heater layer 35, the protective layer 33B, and the bit line BL j. It may be combined with at least one of the above. In this case, a layer that is also used as at least one of the lower electrode 11 and the upper electrode 13A is regarded as at least one of the lower electrode 11 and the upper electrode 13A.
  • either the lower electrode 11 or the upper electrode 13A can be omitted depending on the application to which the variable resistance element 310 is applied. Below, in order to demonstrate easily, it demonstrates as a case where both the lower electrode 11 and the upper electrode 13A are provided.
  • the lower electrode 11 and the upper electrode 13A have convenient names and can be interchanged. Further, in the positional relationship between the lower electrode 11 and the upper electrode 13A, the first variable resistance layer 12A1 and the second resistance change layer 12A2 can be interchanged with each other.
  • Each of the first resistance change layer 12A1 and the second resistance change layer 12A2 is a layer whose resistance changes, that is, a resistance change layer. That is, the resistance of the first resistance change layer 12A1 changes depending on at least one of the voltage applied to the first resistance change layer 12A1 and the current passed through the first resistance change layer 12A1.
  • the resistance of the second resistance change layer 12A2 changes depending on at least one of a voltage applied to the second resistance change layer 12A2 and a current passed through the second resistance change layer 12A2.
  • the first variable resistance layer 12A1 and the second variable resistance layer 12A2 have different electrical characteristics. That is, at least one of the voltage and current at which the resistance changes in the first resistance change layer 12A1, and at least one of the voltage and current at which the resistance changes in the second resistance change layer 12A2 are different from each other.
  • the difference in characteristics can be changed depending on the material and thickness used for the first resistance change layer 12A1 and the second resistance change layer 12A2.
  • FIG. 3 is a schematic view illustrating characteristics of the variable resistance element according to the first embodiment of the invention. That is, this figure is a schematic graph illustrating the current-voltage characteristics of the variable resistance element 310 according to this embodiment, and the horizontal axis represents the current flowing between the lower electrode 11 and the upper electrode 13A, that is, the resistance.
  • the current I flowing through the changing unit 12 and the vertical axis represents the voltage applied to the lower electrode 11 and the upper electrode 13 ⁇ / b> A, that is, the voltage V applied to the resistance changing unit 12.
  • the resistance change element 310 has, for example, five different regions, that is, regions R1 to R5 in the current-voltage characteristics.
  • the region R1 is, for example, a region where both the first resistance change layer 12A1 and the second resistance change layer 12A2 are in a high resistance state.
  • the region R2 is, for example, a region where the first resistance change layer 12A1 is in a low resistance state and the second resistance change layer 12A2 is in a high resistance state.
  • the region R3 is, for example, a region where the first resistance change layer 12A1 and the second resistance change layer 12A2 are in a low resistance state.
  • the region R4 is a region in which the first resistance change layer 12A1 is again in the high resistance state (reset state) and the second resistance change layer 12A2 is in the low resistance state.
  • the region R5 is a region where both the first resistance change layer 12A1 and the second resistance change layer 12A2 are again in the high resistance state (reset state).
  • the recording unit 12 By stacking the first variable resistance layer 12A1 and the second variable resistance layer 12A2 having different characteristics as described above, the recording unit 12 exhibits three or more different resistance states, that is, three or more values. Can do.
  • the resistance change element 310 according to the present embodiment, a resistance change element capable of multi-value recording is provided.
  • the resistance change unit 12 includes two resistance change layers (the first resistance change layer 12A1 and the second resistance change layer 12A2). It may have a layer.
  • the recording unit 12 When not using the reset state, the recording unit 12 has two resistance change layers, and when there is no intermediate state in the resistance change state, two levels of information per resistance change layer. Are recorded, it is possible to record and reproduce a total of four levels of 2 levels ⁇ 2 levels. On the other hand, if the above-described reset state is used, at least 3 levels ⁇ 3 levels of 9 levels in total can be recorded and reproduced. If a material having an intermediate state in the resistance change state of the resistance change layer is used, the amount of information that can be recorded can be further increased.
  • FIG. 4 is a schematic view illustrating characteristics of the variable resistance element according to the first embodiment of the invention.
  • this figure is a schematic graph illustrating the characteristics of the resistance change layer (each of the first resistance change layer 12A1 and the second resistance change layer 12A2).
  • 2A illustrates the current-voltage characteristics of the resistance change layer
  • FIG. 2B illustrates the current-resistance characteristics of the resistance change layer.
  • the resistance change layer has a relatively high resistance state (high resistance state HR) and a relatively low resistance state according to applied current and voltage ( It exhibits two states, a low resistance state LR).
  • high resistance state HR high resistance state
  • low resistance state LR low resistance state LR
  • the initial state it is in a high resistance state HR, and when a current or voltage to be applied is increased, at a certain point (hereinafter referred to as a set point), a low resistance state LR (hereinafter referred to as a set state) is obtained.
  • a reset point the state returns to the high resistance state HR (hereinafter referred to as a reset state).
  • the high resistance state HR is described as a reset state
  • the low resistance state LR is described as a reset state.
  • this definition is intended to simplify the following description. Depending on the selection of materials and the manufacturing method, this definition may be reversed, that is, the low resistance state LR becomes the reset (initial) state, and the high
  • the resistance state HR can also be defined as a set state.
  • the current and voltage at the set point are referred to as set current Is and set voltage Vs, respectively, and the current and voltage at the reset point are referred to as reset current Ir and reset voltage Vr, respectively.
  • the resistance value in the set state is referred to as a set resistor Rs, and the resistance value in the reset state is referred to as a reset resistor Rr.
  • the set current Is, the set voltage Vs, the reset current Ir, the reset voltage Vr, the set resistance Rs, and the reset resistance Rr of the resistance change layer differ depending on the material, cross-sectional area, film thickness, and the like of the resistance change element used as the resistance change layer.
  • variable resistance element when using the variable resistance element according to the present embodiment, a bipolar operation is also possible in which a reset state is applied by applying a voltage having a polarity opposite to the set voltage Vs.
  • the description is limited to the unipolar operation in which the polarity of the applied current or voltage is constant, and the current or voltage represents an absolute value.
  • the resistance change layer becomes low.
  • the resistance value state LR is maintained in the set state.
  • the resistance change layer Holds the reset state of the high resistance value state HR. Furthermore, by setting the current and voltage applied to the resistance change layer to be lower than the set current Is and the set voltage Vs, the resistance of the resistance layer can be detected without changing the state of the resistance change layer. Can be read.
  • the resistance change layer can perform writing by setting the applied current and voltage to be equal to or higher than the set current Is and the set voltage Vs and lower than the reset current Ir and the reset voltage Vr.
  • the erasing can be performed by setting the current and voltage to the reset current Ir and the reset voltage Vr or higher.
  • the applied current and voltage by setting the applied current and voltage to be less than the set current Is and the set voltage Vs, it functions as a nonvolatile memory cell that can read the state as a resistor.
  • the first resistance change layer 12A1 and the second resistance change layer 12A2 each function as a 1-bit memory cell.
  • the amount of information that can be recorded can be further increased. Note that writing and erasing can also be performed by current pulses or voltage pulses.
  • the resistance change unit 12 of the resistance change element 310 has a structure in which the first resistance change layer 12A1 and the second resistance change layer 12A2 that perform such operations are stacked.
  • At least one of the set current Is, the set voltage Vs, the reset current Ir, and the reset voltage Vr is different.
  • FIG. 5 is another graph illustrating the characteristics of the variable resistance element according to the first embodiment of the invention. That is, FIG. 5A illustrates the current-voltage characteristics of the first resistance change layer 12A1, the second resistance change layer 12A2, and the resistance change unit 12, and FIG. The current-voltage characteristics of the layer 12A1, the second resistance change layer 12A2, and the resistance change unit 12 are illustrated.
  • the solid line corresponds to the recording unit 12
  • the alternate long and short dash line corresponds to the first resistance change layer 12A1
  • the broken line corresponds to the second resistance change layer 12A2.
  • the characteristics of these variable resistance layers are approximated linearly and conceptually illustrated.
  • subscript 1 is attached to the characteristics of the first variable resistance layer 12A1 single layer
  • subscript 2 is attached to the characteristics of the second variable resistance layer 12A2 single layer. These characteristics are shown without subscripts.
  • both the first resistance change layer 12A1 and the second resistance change layer 12A2 are in a reset state. Now, increasing the current I to be applied to the recording unit 12, a set current Is 1 of the first variable resistance layer 12A1, the first variable resistance layer 12A1 is changed to the set state. At this time, the first resistance change layer 12A2 remains in the reset state and does not change.
  • the second variable resistance layer 12A2 With further increasing the current, the set current Is 2 of the second variable resistance layer 12A2, the second variable resistance layer 12A2 is changed to the set state. At this time, the first resistance change layer 12A1 remains unchanged in the set state.
  • the first resistance variable layer 12A1 in the reset current Ir 1 of the first variable resistance layer 12A1 is changed to the reset state.
  • the second resistance change layer 12A2 remains in the set state and does not change.
  • the reset current Ir 2 of the second variable resistance layer 12A2 With further increasing the current, the reset current Ir 2 of the second variable resistance layer 12A2, the second variable resistance layer 12A2, changes to the reset state. At this time, the first resistance change layer 12A1 remains unchanged in the reset state.
  • the resistance change unit 12 takes four states corresponding to four combinations of the set state and the reset state of the first resistance change layer 12A1 and the second resistance change layer 12A2 by the increase of the current I to be energized.
  • the resistance change portion 12 by energizing the lower current I than Is 1, can be read without resistance changing the respective states of the first variable resistance layer 12A1 and the second variable resistance layer 12A2. Therefore, the resistance change unit 12 functions as a non-volatile memory cell having four values.
  • the resistance change unit 12 including the first resistance change layer 12A1 and the second resistance change layer 12A2 is changed to the first resistance change layer.
  • the state of 12A1 is the least significant bit (LSB) and the state of the second resistance change layer 12A2 is the most significant bit (MSB)
  • MSB most significant bit
  • the state has 2 states “0”, “1”, “2”, “3”. It functions as a bit memory cell.
  • the amount of information that can be recorded can be further increased.
  • the first resistance change layer 12 ⁇ / b> A ⁇ b> 1 and the second resistance change layer 12 ⁇ / b> A ⁇ b> 2 are each subjected to a voltage proportionally distributed to the respective resistances.
  • the voltage at which the state changes is different from the set voltage and the reset voltage of the first resistance change layer 12A1 and the second resistance change layer 12A2 illustrated in FIG.
  • the resistance value changes in the current-voltage characteristics of the recording unit 12 as illustrated in FIG. There are four voltage values.
  • the voltage transition between each other different states of the first variable resistance layer 12A1 includes a set voltage Vs 1 and the reset voltage Vr 1 above.
  • the voltage transition between each other different states in the second variable resistance layer 12A2 includes a set voltage Vs 2 and the reset voltage Vr 2 above.
  • the set voltage Vs 1 and the reset voltage Vr 1 are different from the set voltage Vs 2 and the reset voltage Vr 2 .
  • FIG. 6 is another schematic view illustrating the characteristics of the variable resistance element according to the first embodiment of the invention. That is, this figure illustrates the current-voltage characteristics of the variable resistance element according to the present embodiment, the horizontal axis is the voltage applied to the resistance change unit 12, and the vertical axis is the current flowing through the resistance change unit 12. Indicates. In this figure, the initial state and the reset state are illustrated as a low resistance state, and the set state is illustrated as a high resistance state.
  • each voltage at which the resistance of the resistance change unit 12 changes is set as a threshold voltage Vsh, and the first threshold voltage Vsh 1 , the second threshold voltage Vsh 2 ,.
  • the Mth threshold voltage is Vsh M.
  • V ⁇ Vsh 1 state is held or read.
  • Vsh 1 ⁇ V ⁇ Vsh 2
  • state is “1”.
  • Vsh 2 ⁇ V ⁇ Vsh 3
  • Vsh 3 state “2”
  • Vsh 3 ⁇ V ⁇ Vsh 4
  • Vsh 4 state “3”
  • writing, erasing, and reading can be performed by either a current pulse or a voltage pulse.
  • the first resistance change layer 12A1 and the second resistance change layer 12A2 are applied only to the first variable resistance layer 12A2.
  • the second resistance change layer 12A2 also changes from the high resistance state HR to the low resistance state LR at the same time. If you happen to occur.
  • the voltage of the second resistance change layer 12A2 is preferably lower than the voltage at which the second resistance change layer 12A2 shifts from the high resistance state HR to the low resistance state LR.
  • the high resistance state HR and the low resistance state LR of each of the first and second resistance change layers 12A1 and 12A2 are used. It can be performed by applying a voltage higher than the voltage that shifts to the first and second resistance change layers 12A1 and 12A2. Actually, it is only necessary to apply the total voltage of the voltage that shifts from the high resistance state HR to the low resistance state LR of each of the first and second resistance change layers 12A1 and 12A2, and this operation can be performed collectively. it can.
  • the set voltage and reset voltage (Vs 1 , Vr 1 ) of the first resistance change layer 12A1 and the set voltage and reset voltage (Vs 2 , Vr 2 ) of the second resistance change layer 12A2 are mainly changed in resistance.
  • the slope of the current-voltage characteristic in the first resistance change layer 12A1 and the second resistance change layer 12A2, that is, the electrical resistance between on and off, is the layer thickness in the first resistance change layer 12A1 and the second resistance change layer 12A2.
  • it is determined by the film thickness and the area perpendicular to the direction of current flow in these layers. Therefore, by controlling the layer thickness of the first resistance change layer 12A and the second resistance change layer and the area perpendicular to the stacking direction, a plurality of resistances (Rs 1 , Rr) of the first resistance change layer 12A1 are controlled. 1 ) and a plurality of resistances (Rs 2 , Rr 2 ) of the second resistance change layer 12A2 can be set to desired values.
  • variable resistance element 310 since the variable resistance element 310 has a plurality of variable resistance layers, the electrical resistance as the variable resistance element 310 should be higher than when one variable resistance layer is used. Can do. If the resistance is high and the same voltage is applied, the current value can be kept low. Therefore, the variable resistance element 310 according to the present embodiment leads to low power consumption of an information recording / reproducing apparatus using the variable resistance element 310. As described above, the variable resistance element according to the present embodiment can perform multi-value recording, and at the same time, can reduce power consumption of an information recording / reproducing apparatus using the resistance change element.
  • the resistance change unit 12 includes a plurality of resistance change layers (for example, the first resistance change layer 12A1 and the second resistance change layer 12A2) having different compositions.
  • the threshold voltages are the set voltage and reset voltage of the respective resistance change layers. This is because at least one of them is different.
  • each of the first to fourth threshold voltages Vsh 1 to Vsh 4 illustrated in FIG. 6 includes the set voltage Vs 1 and the reset voltage Vr 1 of the first resistance change layer 12A1 illustrated in FIG. Although the set voltage Vs 2 and the reset voltage Vr 2 of the two-resistance change layer 12A2 do not coincide with each other, the set voltage Vs 1 and the reset voltage Vr 1 , and the set voltage Vs 2 and the reset voltage Vr 2 are different from each other. Is done.
  • a resistance change element capable of multi-value recording can be provided.
  • the example is described in which the set voltage Vs 1 and reset voltage Vr 1 of the first resistance change layer 12A1 are different from the set voltage Vs 2 and reset voltage Vr 2 of the second resistance change layer 12A2.
  • the present invention is not limited to this, and at least one of the set voltage Vs 1 and reset voltage Vr 1 of the first resistance change layer 12A1 and the set voltage Vs 2 and reset voltage Vr 2 of the second resistance change layer 12A2 is If they are different from each other, it is possible to record more than two values, which may be sufficient.
  • the materials used for the resistance change unit 12, the lower electrode 11, and the upper electrode 13A of the resistance change element 310 according to this embodiment will be described later.
  • Example 1 The variable resistance element (310a) of the first example according to the variable resistance element 310 of the present embodiment was produced.
  • TiN is used for the lower electrode 11.
  • first resistance change layer 12A1 a film in which about 10% of metal Mn was dispersed in Mn 3 O 4 was used, and the film thickness was 20 nm.
  • second resistance change layer 12A2 a film in which about 10% of MnO 2 was dispersed in Mn 3 O 4 was used, and the film thickness was 20 nm.
  • Pt was used as the upper electrode 13A.
  • the resistance difference between the reset (erase) state and the set (write) state of the resistance change element 310a is evaluated.
  • the configuration of the probe memory described later is used.
  • a probe pair whose tip diameter is sharpened to 10 nm or less is used.
  • the first variable resistance layer 12A1 and the second variable resistance layer 12A2 are stacked on the lower electrode 11, and the protective layer 13B is formed thereon.
  • the probe pair is brought into contact with the protective layer 13B, and writing / erasing is executed using one of them.
  • Writing is performed by applying a voltage pulse of 1 V to the variable resistance element 310a, for example, with a width of 10 nsec.
  • Erasing is performed by applying a voltage pulse of 0.2 V with a width of 100 nsec, for example, to the variable resistance element 310a.
  • DC-like evaluation is also possible like a semiconductor parameter analyzer.
  • read is executed using the other one of the probe pair between write / erase. Reading is performed by applying a voltage pulse of 0.1 V, for example, with a width of 10 nsec to the variable resistance element 310a and measuring the resistance value of the variable resistance element 310a.
  • FIG. 7 is a graph illustrating characteristics of the variable resistance element according to the first example of the invention. That is, this figure shows voltage-current characteristics when a pulse voltage is applied to the resistance change element 310a while gradually increasing.
  • the horizontal axis is voltage
  • the vertical axis is current.
  • variable resistance element 310a As shown in FIG. 7, in the variable resistance element 310a, four voltages having different resistances were observed. That is, four voltages of about 0.6V, about 1.25V, about 1.45V, and about 1.65V.
  • the initial state is the high resistance state, and when set, the low resistance state is set, and when reset, the high resistance state is set.
  • the process of setting the low resistance state by setting may be called forming.
  • the resistance change element 310a of this embodiment has four voltages at which the resistances are changed to different states, and a resistance change element capable of multi-value recording can be provided.
  • the respective set voltages and reset voltages of the first resistance change layer 12A1 and the second resistance change layer 12A2 constituting the resistance change unit 12 are obtained as shown in Table 1.
  • the electrical resistivity, the set, and the reset voltage of each layer were used as parameters, and the calculation was performed by fitting.
  • the set voltage and the reset voltage of each resistance change layer have any resistance change.
  • the layer is assigned as one of the resistance change layers.
  • the reset voltage is 0.59V and the set voltage is 1.45V.
  • the reset voltage is 1.25V and the set voltage is 1.65V.
  • the reset voltage and the set voltage are different between the first resistance change layer 12A1 and the second resistance change layer 12A2 of the resistance change unit 12.
  • the resistance change element 310a of the present embodiment can be used as a multi-value memory having four different resistance states.
  • the characteristics shown in FIG. 7 and Table 1 are examples of characteristics in the case of unipolar operation.
  • the voltage value having a different resistance value is different from that in the unipolar operation, but the bipolar operation is also possible.
  • the first variable resistance layer 12A1 and the second variable resistance layer 12A2 are formed independently from each other. Further, since it is not always necessary to continuously form the lower electrode 11 and the first variable resistance layer 12A1 in a vacuum, a natural oxide film, that is, a TiOx is formed on TiN to be the lower electrode 11. (1 ⁇ x ⁇ 2) may be present.
  • the composition of the interface between the first resistance change layer 12A1 or the second resistance change layer 12A2 and another film is slightly deviated from the above composition.
  • the film in which about 10% of metal Mn is dispersed in Mn 3 O 4 used as the first resistance change layer 12A1 may be replaced with a film in which about 20% of MnO 2 is dispersed in Mn 3 O 4. it can. Further, a film in which about 5% of metal Mn is dispersed in Mn 3 O 4 can be substituted. Further, a film in which about 10% of MnO 2 is dispersed in Mn 3 O 4 can be substituted.
  • variable resistance element (310b) of the second example according to this embodiment Zn 1.1 Mn 1.9 O 4 having a thickness of 20 nm is used for the first variable resistance layer 12A1, and the second variable resistance layer is used.
  • 12A2 uses NiO having a thickness of 50 nm
  • the lower electrode 11 uses TiN
  • the upper electrode 13A uses Pt. It should be noted that NiO is accurately described as NiO 1- ⁇ (0 ⁇ ⁇ ⁇ 1), and the ratio of Ni and oxygen O may be slightly deviated from 1: 1.
  • Table 2 shows the voltage-current characteristics of the resistance change film 310b of the second example having four different resistance states as illustrated in FIG. Thereby, the resistance change element 310b of the present embodiment can also be used as a multi-value memory having four different resistance states.
  • the reset voltage was 0.6V and the set voltage was 1.7V.
  • the reset voltage was 1.6V and the set voltage was 2.05V.
  • the reset voltage and the set voltage are different in each of the first resistance change layer 12A1 and the second resistance change layer 12A2, and as a result, the four resistance states are changed.
  • the thicknesses of the first and second resistance change layers 12A1 and 12A2 are a combination of 20 nm and 50 nm is shown, but these are suitable in the range of 5 nm or more and 50 nm or less, Thereby, the characteristic of the information recording / reproducing apparatus using the variable resistance element according to the present embodiment can be improved.
  • the first resistance change layer 12A1 has a thickness of 30 nm and a 1: 1 mixture of microcrystalline graphite and amorphous carbon is used. .
  • a 2: 1 mixture of microcrystalline graphite and amorphous carbon having a thickness of 30 nm is used for the second resistance change layer 12A2.
  • TiN is used for both the lower electrode 11 and the upper electrode 13A.
  • the mixture of microcrystalline graphite and amorphous carbon hardly reacts and remains in that state, except when heated to a temperature that cannot be experienced in a normal use environment, such as 1000 ° C. or higher.
  • the mixture of microcrystalline graphite and amorphous carbon hardly reacts and remains in that state, except when heated to a temperature that cannot be experienced in a normal use environment, such as 1000 ° C. or higher.
  • the resistance change element 310c of this example also exhibited voltage-current characteristics having four different resistance states, as illustrated in FIG. Thereby, the resistance change element 310c of the present embodiment can also be used as a multi-value memory having four different resistance states.
  • the reset voltage was 0.4V and the set voltage was 1.2V in the first variable resistance layer 12A1.
  • the reset voltage was 1.4V and the set voltage was 1.9V.
  • the reset voltage and the set voltage are different in each of the first resistance change layer 12A1 and the second resistance change layer 12A2, and as a result, the four resistance states are changed.
  • the thicknesses of the first and second resistance change layers 12A1 and 12A2 are a combination of 30 nm and 30 nm is shown, but these are suitable in the range of 5 nm or more and 50 nm or less, Thereby, the characteristic of the information recording / reproducing apparatus using the variable resistance element according to the present embodiment can be improved.
  • the mixing ratio can be measured by various methods. For example, X-ray photoelectron spectroscopy (ESR) is performed by electron spin resonance (ESR) by cross-sectional TEM exploration by comparing the ratio of the peak of D-band and G-band or the ratio of area intensity by Raman spectroscopy. XPS) or electron beam energy loss spectroscopy (EELS). Further, by measuring the temperature change of the electrical resistivity, the mixing ratio of the microcrystalline graphite and the amorphous carbon can be estimated from the absolute value of the electrical resistivity and the temperature coefficient.
  • ESR X-ray photoelectron spectroscopy
  • ESR electron spin resonance
  • EELS electron beam energy loss spectroscopy
  • the electrical resistivity of the mixture of microcrystalline graphite and amorphous carbon was varied between 10 ⁇ 4 ⁇ cm and 10 2 ⁇ cm.
  • the electrical resistivity of the mixture of microcrystalline graphite and amorphous carbon depends not only on the mixing ratio of microcrystalline graphite and amorphous carbon, but also on the crystal grain size of microcrystalline graphite and its graphitization degree.
  • the crystal grain size of microcrystalline graphite has a different contribution to electrical resistivity even if the so-called in-plane direction and c-axis direction are different. In general, the electrical resistivity in the in-plane direction of graphite is lower than that in the c-axis direction.
  • the crystal grain size of microcrystalline graphite is preferably 5 nm or less, more preferably 2 nm or less.
  • a hydrocarbon method for example, a CVD method using a gas such as CH 4 or C 3 H 6 as a reaction gas, or a sputtering target of graphite (graphite) is used.
  • the sputtering method used is preferable.
  • the graphite component increases as the temperature is raised to 400 ° C, 500 ° C, and 600 ° C.
  • the graphite component is unlikely to increase.
  • hydrogen as a reactive gas component may remain in the film, but it is not uncommon for the amount to reach about 15 atomic percent (atomic percentage). Even in this case, it does not depart from the spirit of the present invention.
  • graphite layer also called two-dimensional graphite or graphene
  • GIC graphite intercalation compounds
  • B nitrogen and boron
  • carbon can take various forms such as diamond, dynemond-like carbon (DLC), fullerene, and carbon nano tube (CNT). Even if these are contained in trace amounts, they do not depart from the scope of the present invention.
  • the first variable resistance layer 12A1 has a thickness of 0 nm and a 1: 1 mixture of microcrystalline graphite and amorphous carbon is used. It is done.
  • a 1: 1 mixture of microcrystalline graphite and amorphous carbon having a thickness of 30 nm to which 2 atomic percent of nitrogen is added is used.
  • TiN is used for both the lower electrode 11 and the upper electrode 13A.
  • the resistance change film 310d of this example also exhibited voltage-current characteristics having four different resistance states, as illustrated in FIG. Thereby, the variable resistance element 310d of the present embodiment can also be used as a multi-value memory having four different resistance states.
  • the reset voltage was 0.4V and the set voltage was 1.1V in the first resistance change layer 12A1.
  • the reset voltage was 1.4V and the set voltage was 1.8V.
  • the reset voltage and the set voltage are different in each of the first resistance change layer 12A1 and the second resistance change layer 12A2, and as a result, the four resistance states are changed.
  • the thicknesses of the first and second resistance change layers 12A1 and 12A2 are a combination of 40 nm and 30 nm is shown, but these are suitable in the range of 5 nm or more and 50 nm or less, Thereby, the characteristic of the information recording / reproducing apparatus using the variable resistance element according to the present embodiment can be improved.
  • the first resistance change layer 12A1 has a thickness of 40 nm and a 1: 1 mixture of microcrystalline graphite and amorphous carbon is used. .
  • a 1: 1 mixture of microcrystalline graphite and amorphous carbon having a thickness of 30 nm and nitrogen added at 2 atomic percent is used.
  • TiN is used for both the lower electrode 11 and the upper electrode 13A.
  • the resistance change film 310e of this example also exhibited voltage-current characteristics having four different resistance states, as illustrated in FIG. Thereby, the resistance change element 310e of the present embodiment can also be used as a multi-value memory having four different resistance states.
  • the reset voltage was 0.4V and the set voltage was 1.1V in the first variable resistance layer 12A1.
  • the reset voltage was 1.3V and the set voltage was 2.0V.
  • the reset voltage and the set voltage are different in each of the first resistance change layer 12A1 and the second resistance change layer 12A2, and as a result, the four resistance states are changed.
  • the thicknesses of the first and second resistance change layers 12A1 and 12A2 are a combination of 40 nm and 30 nm is shown, but these are suitable in the range of 5 nm or more and 50 nm or less, Thereby, the characteristic of the information recording / reproducing apparatus using the variable resistance element according to the present embodiment can be improved.
  • the first resistance change layer 12A1 has a thickness of 40 nm and a 1: 1 mixture of microcrystalline graphite and amorphous carbon is used. .
  • a 2: 1 mixture of microcrystalline graphite and amorphous carbon having a thickness of 40 nm and boron (B) added at 3 atomic percent is used.
  • TiN is used for both the lower electrode 11 and the upper electrode 13A.
  • the resistance change film 310f of this example also exhibited voltage-current characteristics having four different resistance states, as illustrated in FIG. Thereby, the variable resistance element 310f of the present embodiment can also be used as a multi-value memory having four different resistance states.
  • the reset voltage was 0.4V and the set voltage was 1.1V in the first variable resistance layer 12A1.
  • the reset voltage was 1.4V and the set voltage was 1.8V.
  • variable resistance element 310f of this example the reset voltage and the set voltage are different in each of the first variable resistance layer 12A1 and the second variable resistance layer 12A2, and as a result, the four resistance states are changed.
  • a threshold voltage which can be used as a multi-value memory having four different states.
  • the thicknesses of the first and second resistance change layers 12A1 and 12A2 are a combination of 40 nm and 40 nm is shown, but these are suitable in the range of 5 nm or more and 50 nm or less, Thereby, the characteristic of the information recording / reproducing apparatus using the variable resistance element according to the present embodiment can be improved.
  • variable resistance element of the first comparative example the variable resistance portion 12 is made of one type of material. That is, the resistance change layer 12 is made of only a material of 20 nm thick Mn 1.9 O 3 . Except this, it is the same as the resistance change element 310a of the first embodiment.
  • the reset voltage during the unipolar operation was about + 0.5V, and the set voltage was about + 1.5V.
  • the reset voltage during bipolar operation was about + 0.5V and the set voltage was about -0.5V.
  • the stability of the characteristics in the repeated energization cycle was poor, and the above operation was performed for each element several hundred times. I can't do it.
  • multi-value information cannot be recorded and reproduced in one resistance change element.
  • FIG. 8 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to the second embodiment of the invention.
  • the first resistance change layer 12A1, the second resistance change layer 12A2,... Nth resistance are formed on the lower electrode 11.
  • the change layer 12AN is sequentially stacked, and the upper electrode 13A is stacked on the uppermost Nth resistance change layer 12AN.
  • N is an integer of 2 or more.
  • the resistance change unit 12 includes a plurality of resistance change layers having different compositions and different electrical characteristics. That is, the first resistance change layer 12A1, the second resistance change layer 12A2,... The Nth resistance change layer 12AN have different compositions.
  • the resistance change element 320 since the resistance change element 320 according to this embodiment includes N resistance change layers having different characteristics, the resistance change element 320 has 2 N different states.
  • the state of the lowermost first resistance change layer 12A1 is LSB and the state of the uppermost Nth resistance change layer 12AN is MSB, which functions as an N-bit memory cell.
  • variable resistance portion 12 can have a plurality of arbitrary variable resistance layers having different compositions and different electrical characteristics.
  • FIG. 9 is a schematic cross-sectional view illustrating the configuration of a variable resistance element according to the third embodiment of the invention.
  • the resistance change element 330 according to the third embodiment of the present invention, the first resistance change layer 12A1 and the second resistance change layer 12A2 are provided, and an interlayer separation layer is provided therebetween.
  • (Separation layer) 12C1 is provided.
  • the description is omitted.
  • interlayer separation layer 12C a material different from the resident tail used for the first resistance change layer 12A1 and the second resistance change layer 12A2 can be used.
  • various metal films can be used for the interlayer separation layer 12C1.
  • the first resistance change layer 12A1 and the first resistance change layer are provided. Diffusion of elements between 12A2 can be suppressed. Thereby, there is an effect that heat resistance, environment resistance, and rewriting durability are increased.
  • the crystallinity of the resistance change portion 12 is improved, and variations between elements and lots can be greatly reduced.
  • the resistance change element 330 according to the present embodiment, multi-value recording is possible, the performance is stable, and the resistance change element having a high number of rewrites can be provided.
  • Example 7 The variable resistance element 330a of the seventh example according to this embodiment was produced.
  • the lower electrode 11, the first resistance change layer 12A1, the second resistance change layer 12A1, and the upper electrode 13A have the same configuration as the resistance change element 310b of the second embodiment.
  • an interlayer separation layer 12C1 between the first resistance change layer 12A and the second resistance change layer 12A2 a film in which 6 atomic percent of Al was added to ZnO was formed to a thickness of 2 nm.
  • the characteristics of the resistance change element 330a of the present example produced in this way are substantially the same as the first to fourth threshold voltages of the resistance change element 310b of the second example.
  • FIG. 10 is a schematic cross-sectional view illustrating the configuration of another variable resistance element according to the third embodiment of the invention.
  • the resistance change unit 12 includes three or more resistance change layers. In between, the above-mentioned interlayer separation layer is provided.
  • variable resistance part 12 of the variable resistance element 311 includes a first variable resistance layer 12A1, a second variable resistance layer 12A2,... An Nth variable resistance layer 12AN, and a first interlayer separation layer 12C1 therebetween.
  • Second interlayer isolation layer 12C2... (N-1) interlayer isolation layer 12C (N-1) are provided.
  • the crystallinity of each layer of the resistance change portion 12 is improved, and variations between elements and lots can be greatly reduced.
  • resistance change element 331 According to another resistance change element 331 according to the present embodiment, multi-value recording with a higher number of bits is possible, a resistance change element with a stable performance and a high number of rewrites can be provided.
  • FIG. 11 is a schematic cross-sectional view illustrating the configuration of a variable resistance element according to the fourth embodiment of the invention.
  • the resistance change element 340 according to the fourth exemplary embodiment of the present invention includes an electrode side separation between the lower electrode 11 and the first resistance change layer 12 ⁇ / b> A ⁇ b> 1 in the resistance change element 330.
  • Layer 12C0 is provided.
  • the electrode-side separation layer (separation layer) 12C0 between the lower electrode 11 and the first resistance change layer 12A1
  • the diffusion of elements between the lower electrode 11 and the first resistance change layer 12A1 is reduced. It is possible to prevent heat resistance, environmental resistance, and rewriting durability.
  • first interlayer separation layer 12C1 to Nth interlayer separation layer 12CN and electrode side separation layer 12C0 are collectively referred to as a separation layer 12C.
  • Example 8 A variable resistance element 340a according to an eighth example of the fourth embodiment of the present invention was produced. At this time, a material in which Sb 2 O 3 was added at 5 atomic percent to SnO 2 was used for the electrode-side separation layer 12C0. Other than that, it is the same as the variable resistance element 330a of the seventh embodiment.
  • Zn 1.1 Mn 1.9 O 4 with a thickness of 20 nm is used for the first resistance change layer 12A2
  • NiO with a thickness of 50 nm is used for the second resistance change layer 12A2
  • TiN is used for the lower electrode 11.
  • Pt is used for the upper electrode 13A.
  • the reset voltage and set voltage of the variable resistance element 340a having the above configuration are the same as those in Table 2 and are different from each other. Therefore, as in the first to seventh embodiments, so-called multi-value information can be recorded and reproduced.
  • Example 9 As a ninth example according to the fourth embodiment of the present invention, variable resistance elements having various configurations were produced. That is, TiN is used for the lower electrode 11, a 20 nm-thick film in which Mn of metal is dispersed in Mn 3 O 4 is used for the first resistance change layer 12A1, and Mn is used for the second resistance change layer 12A2. A 20 nm thick film in which MnO 2 was dispersed in 3 O 4 was used, and Pt was used for the upper electrode 13A. At this time, Mn 3 O 4 ratio of metal of Mn to be dispersed in, and to prepare a sample with different ratio of MnO 2 dispersed in the Mn 3 O 4.
  • a mixed film of TiOs (1 ⁇ s ⁇ 2) and SnO 2 having a thickness of 1 nm was used for the interlayer separation layer 12C1 and the separation layer 12C0.
  • a mixed film of ZnO and Al 2 O 3 also referred to as ZnO doped with Al
  • a mixed film of ZnO and Ga 2 O 3 this is doped with ZnO with Ga
  • film of a mixture of Sb 2 O 3 to SnO 2 the in 2 O 3
  • a film obtained by mixing, IrO 2 and Ir mixed film, and RuO 2 and Ru mixed film were used.
  • Table 7 shows the measurement results of the reset voltage and set voltage of these first and second resistance change layers.
  • the ratio of the metal Mn dispersed in Mn 3 O 4, and controls the Mn 3 O 4 ratio and dispersion state of MnO 2 dispersed in such also, the interlayer separating layer 12C1 and the separation layer 12C0 used materials Is changed, the reset voltage and the set voltage of each variable resistance layer of the variable resistance element are controlled.
  • the thickness of each variable resistance layer is also controlled to an appropriate value so that the reset voltage and the set voltage fall within a predetermined range as exemplified in Table 7.
  • Samples 1 to 14 shown in Table 7 were capable of multi-value recording and reproduction as well as the resistance change element 310a of the first example, for example.
  • variable resistance elements All of the variable resistance elements were observed to have a stable rewrite operation of several thousand times or more, and could be rewritten more times.
  • the difference between the reset voltage of one of the first variable resistance layer 12A1 and the second variable resistance layer 12A2 and the set voltage of the other is the repetitive operation.
  • 0.1 V or more is desirable, although it depends on variations in resistance, variations between resistance change elements, and also in the pulse operation, such as the magnitude of noise components such as ringing. .
  • the effect of the film thickness of the interlayer separation layer 12C1 and the separation layer 12C0 is 0.5 nm or more. That is, when the thickness is 50 nm or more, the state of the resistance change layers (first resistance change layer 12A1 and second resistance change layer 12A2) in contact with the interlayer isolation layer 12C1 and the isolation layer 12C0 is changed. In view of manufacturing requirements, it is desirable that the thickness of the interlayer separation layer 12C1 and the separation layer 12C0 be too large. The most preferable range is about 1 to 5 nm. There was no.
  • the thickness of the interlayer separation layer 12C1 and the separation layer 12C0 is preferably 0.5 nm or more and 50 nm or less.
  • the thickness of the first variable resistance layer 12A1 and the second variable resistance layer 12A2 is a combination of 20 nm and 50 nm is exemplified, but these are suitable information recording / reproducing in the range of 5 nm or more and 50 nm or less. It can be a device.
  • the reset voltage of the first resistance change layer 12A1 and the second resistance change layer 12A2 of the resistance change unit 12 is the same at 0.5 V, and the first resistance change layer 12A1 of the resistance change unit 12 and A sample having the same configuration with the second variable resistance layer 12A2 having a set voltage of 1.8 V was evaluated.
  • the reset voltage of the resistance change unit 12 is about + 0.5V, and the reset voltage is about + 1.8V. Also, multi-value information could not be recorded and reproduced.
  • any of the first to ninth embodiments as the information recording / reproducing apparatus, it was possible to record and reproduce multi-value information by controlling the characteristics of the recording film.
  • the power consumption can be reduced as compared with the prior art, and the present embodiment is remarkably superior in view of cycle characteristics.
  • FIG. 12 is a schematic cross-sectional view illustrating the configuration of another variable resistance element according to the fourth embodiment of the invention.
  • the resistance change unit 12 includes N resistance change layers (first to Nth resistance changes 12A1 to 12AN).
  • the interlayer separation layers 12C1 to 12C (N-1) are provided between the resistance change layers, the isolation layer 12C0 is provided between the resistance change portion 12 and the lower electrode 11, and the resistance change portion 12 A separation layer 12CN is provided between the upper electrode 13A.
  • an interlayer separation layer can be provided between any N variable resistance layers.
  • an interlayer separation layer may not be provided between all of the N resistance change layers, and may be provided at an arbitrary position.
  • a separation layer can be provided between any of the lower electrode 11 and the upper electrode 13.
  • the first to Nth interlayer separation layers 12C1 to 12C (N-1) are collectively referred to as an interlayer separation layer 12C.
  • the separation layer 12C0 may also be used as at least one of the lower electrode 11 and the upper electrode 13A.
  • FIG. 13 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to the fifth embodiment of the invention.
  • the current limiting layer 12 ⁇ / b> D is provided between the lower electrode 11 and the first resistance change layer 12 ⁇ / b> A ⁇ b> 1.
  • variable resistance element for example, when only the first variable resistance layer 12A1 changes from the erased state to the set state, it is applied to both the first variable resistance layer 12A1 and the second variable resistance layer 12A2.
  • the voltage is applied only to the second resistance change layer 12A2, and a rush current flows.
  • the second resistance change layer 12A2 may be reset at the same time. Therefore, in the variable resistance element 350 according to the present embodiment, a current limiting layer 12D is provided between the lower electrode 11 and the variable resistance portion 12 in order to limit such a rush current.
  • a transistor or a diode that is an active device can be used, but a so-called resistance layer that increases the electric resistance of the element electric conductor including the resistance change element can be used.
  • the current limiting layer 12D can be provided between at least one of the lower electrode 11 and the resistance change portion 12 and between the resistance change portion 12 and the upper electrode 13A.
  • the current can be limited by a driver circuit using a transistor, a diode, a resistor, and a capacitor in an information recording / reproducing apparatus to which a variable resistance element is applied.
  • FIG. 14 is a schematic cross-sectional view illustrating the configuration of another variable resistance element according to the fifth embodiment of the invention.
  • the resistance change unit 12 includes N resistance change layers (first to Nth resistance changes 12A1 to 12AN). Interlayer separation layers 12C1 to 12C (N-1) are provided between the respective resistance change layers, and a current limiting layer 12D is provided between the lower electrode 12 and the first resistance change layer 12A1.
  • the current limiting layer 12D may be provided between the resistance change layer 12D and the upper electrode 13A, and the current limiting layer 12D may be provided at any place between the lower electrode 11 and the upper electrode 13A. Any number of current limiting layers 12D can be provided.
  • FIG. 15 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to the sixth embodiment of the invention.
  • the resistance change element 360 according to the sixth exemplary embodiment of the present invention includes an orientation control layer 11 ⁇ / b> A that controls the orientation of the resistance change layer between the lower electrode 11 and the first recording element 12 ⁇ / b> A ⁇ b> 1. Is provided.
  • orientation control layer 11A for example, compounds of various metals and nitrogen can be used, thereby improving the orientation of the resistance change layer and obtaining a resistance change layer with good characteristics with good reproducibility.
  • variable resistance element 360 In the information recording / reproducing apparatus to which the variable resistance element 360 according to this embodiment is applied, multi-value recording is performed. At this time, the variable resistance element 360 is required to have high quality, and for this purpose, it is very important that the characteristics of the plurality of variable resistance layers are stabilized. At this time, in the resistance change element 360 according to the present embodiment, the orientation control layer 11D is provided to stabilize the quality of the resistance change layer. Thereby, the resistance change element which enables multi-value recording with high quality can be resisted.
  • FIG. 16 is a schematic cross-sectional view illustrating the configuration of a resistance change element according to the seventh embodiment of the invention.
  • the first resistance change layer 12A1 and the second resistance change layer 12A2 are adjacent to each other, respectively.
  • a 1 ion storage layer 12B1 and a second ion storage layer 12B2 are provided.
  • the first ion storage layer 12B1 and the second ion storage layer 12A2 have a function of storing ions discharged from the first resistance change layer 12A1 and the second resistance change layer 12A2, and an effect of facilitating the movement of ions.
  • the material to be used it is possible to always have high electron conductivity regardless of the entry and exit of ions, and also to have the effect of ensuring the stability of the crystal structure. As a result, it is possible to improve the disturbance resistance due to reverse voltage application.
  • the first ion storage layer 12B1 is provided adjacent to the first resistance change layer 12A1. As shown in FIG.
  • the second ion storage layer 12B2 is provided adjacent to the second resistance change layer 12A2.
  • an ion storage layer may be provided in at least one of the first resistance change layer 12A1 and the second resistance change layer 12A2.
  • the resistance change unit 12 includes N resistance change layers, that is, first to Nth resistance change layers 12A1 to 12AN.
  • the first to Nth ion storage layers 12B1 to 12BN are provided in at least one of the first to Nth resistance change layers 12A1 to 12AN, respectively.
  • variable resistance layer 12A The first to Nth variable resistance layers 12A1 to 12AN are collectively referred to as the variable resistance layer 12A.
  • the first to Nth ion storage layers 12B1 to 12BN are collectively referred to as the ion storage layer 12B.
  • a resistance change element having a stable resistance change operation can be provided.
  • first ion storage layer 12A1 and the second ion storage layer 12A2 Materials that can be used for the first ion storage layer 12A1 and the second ion storage layer 12A2 will be described later.
  • FIG. 17 is a schematic view illustrating the configuration and operation of a part of the variable resistance element according to the embodiment of the invention.
  • the operation in one resistance change layer is illustrated, so that one resistance change layer (resistance change portion 12) is provided between the lower electrode 11 and the upper electrode 13A.
  • one resistance change layer resistance change portion 12
  • the recording unit (resistance change unit) 12 includes a first type layer 81, and the first type layer 81 includes diffusion ions 52 (A ions) and transition element ions 51 ( M ion) and a first type compound 71 having anion 61 (X ion).
  • the compound used for the resistance change layer 12A is composed of, for example, a composite compound having at least two types of cation elements, and at least one of the cation elements has a d orbital in which electrons are incompletely filled.
  • the compound used for the recording layer 12A is composed of a composite compound having at least two kinds of cation elements, and at least one of the cation elements is d orbital in which electrons are incompletely filled. It can be set as the electroconductive oxide containing the transition element which has.
  • the initial state is set to the high resistance state HR
  • the state of the recording unit 12 is changed by the potential gradient formed in the recording unit 12, and the recording unit 12 is made conductive to be in the low resistance state LR.
  • An example of a mechanism for recording information will be described.
  • the set operation SO for example, a state in which the potential of the upper electrode 13A is relatively lower than the potential of the lower electrode 11 is created. That is, for example, the lower electrode 11 is set to a fixed potential (for example, ground potential), and a negative potential is applied to the upper electrode 13A.
  • a fixed potential for example, ground potential
  • the diffused ions 52 that have moved to the upper electrode 13A side receive electrons from the upper electrode 13A and are deposited as metal (A metal 52m) to form the metal layer 14.
  • the anions 61 become excessive, and as a result, the valence of the transition element ions 51 in the recording unit 12 is increased. That is, since the recording unit 12 has electron conductivity due to carrier injection, the recording unit 12 is set and information recording is completed.
  • Information reproduction is performed by passing a current pulse through the recording unit 12 and detecting the resistance value of the recording unit 12.
  • the current pulse is set to such a minute value that the material constituting the recording unit 12 does not change state.
  • the above process is a kind of electrolysis, and an oxidizing agent is produced by electrochemical oxidation on the lower electrode (anode) 11 side, and a reducing agent is produced by electrochemical reduction on the upper electrode (cathode) 13A side. It can be considered that it has occurred.
  • the recording unit 12 in order to return the information recording state (low resistance state LR) to the initial state (high resistance state HR), for example, the recording unit 12 is Joule-heated by a large current pulse, and the redox reaction of the recording unit 12 is performed. It should be promoted. That is, the recording unit 12 returns to the high resistance state HR due to the residual heat after the interruption of the large current pulse (reset operation RO).
  • the retention time is sufficiently long so that the reset operation RO does not occur at room temperature. And the power consumption of the reset operation RO is reduced.
  • the coordination number of the diffusion ions 52 is reduced (ideally 2 or less), the valence is 2 or more, or the anion 61 is increased (ideally 3). By doing so, the retention time can be sufficiently reduced.
  • the valence of the diffusion ions 52 is set to 2 or less, and at the same time, the above consumption is achieved by using a material having many movement paths of the diffusion ions 52 moving in the recording portion (crystal) 12. Electric power can be made sufficiently small.
  • an element and crystal structure as described below and an ion storage layer may be employed.
  • At least one of the materials represented by the following (1) to (3) can be used for each layer (each resistance change layer) of the recording portion (resistance change portion) 12.
  • a x M y X 4 (0.1 ⁇ x ⁇ 2.2,1.8 ⁇ y ⁇ 2)
  • A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Au, Cd, Sn, Sb
  • M is Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co
  • the X is an element including at least one selected from the group consisting of O and N , A and M are different elements.
  • a x M y X 3 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1)
  • A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Au, Cd, Sn, Sb
  • M is Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co
  • X is an element including at least one selected from the group consisting of O and N , A and M are different elements.
  • a x M y X 4 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1)
  • A is at least any selected from the group consisting of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, and Bi.
  • M is an element containing at least one selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, and Os.
  • X is an element containing at least one selected from the group consisting of O and N, and A and M are different elements.
  • each layer (each resistance change layer) of the recording part (resistance change part) 12 includes a corundum structure, a rutile structure, a spinel structure, a ramsdellite structure, an anatase structure, a hollandite structure, a brookite structure, a pyrolose structure, a NaC structure, and a probeskite. It may have a crystal structure having any structure selected from the group consisting of a structure, an ilmenite structure, and a wolframite structure.
  • each of the plurality of resistance change layers 12A (first resistance change layer 12A1 to Nth resistance change layer 12AN) of the resistance change element according to the first to seventh embodiments the materials and configurations exemplified above are used. Of these, at least one of different materials, different component ratios, and different configurations is used. Accordingly, at least one of the set voltage and the reset voltage can be made different in each of the plurality of resistance change layers 12A (first resistance change layer 12A1 to Nth resistance change layer 12AN).
  • FIG. 18 is a schematic cross-sectional view illustrating the configuration and operation of a part of the variable resistance element according to the embodiment of the invention. That is, this figure schematically illustrates the action of the ion storage layer 12B in the resistance change element, and the resistance change layer 12A is a single layer and the ion storage layer 12B is a single layer.
  • an ion storage layer 12B is provided adjacent to the resistance change layer 12A.
  • the ion storage layer 12B includes a second type layer 82.
  • the second type layer 82 includes transition metal ions 53 and anions 61, and can further store A ions 52 that the resistance change layer 12A moves. It consists of a second type of compound 72 having a void site ⁇ . Thereby, in the set operation (SO), the A ions 52 that have moved from the resistance change layer 12A are stored in the void sites ⁇ of the ion storage layer 12B.
  • FIG. 19 is a schematic cross-sectional view illustrating the configuration and operation of a part of another variable resistance element according to an embodiment of the invention.
  • the first resistance change layer 12A1 to the Nth resistance change layer 12A2 is an ion. It has a storage layer (first ion storage layer 12B1 to Nth ion storage layer 12BN).
  • first ion storage layer 12B1 to Nth ion storage layer 12BN is an ion.
  • each A ion 52 of the plurality of resistance change layers 12A can be stored in the void site ⁇ of the ion storage layer 12B adjacent thereto, and two states of a high resistance state and a low resistance state can be obtained. It can be expressed stably.
  • the ion storage layer 12B is preferably made of, for example, a conductive oxide.
  • the resistivity of the conductive oxide layer is less than the resistivity of the resistance change layer 12A, and preferably 10-1 ⁇ cm or less.
  • the ion storage layer 12B is characterized by having a void site ⁇ . However, the gap site ⁇ may be partially filled with cations that have moved from the resistance change layer 12A.
  • the ion storage layer 12B at least one of the materials represented by the following (4) to (6) can be used.
  • A is at least one element selected from the group consisting of Ti, Zr, Hf and Sn
  • M is a group consisting of V, Nb, Ta, Cr, Mo, W, As, Sb and Bi.
  • X is at least one element selected from the group consisting of O, N and F, and is an element different from A and M, and 0.001 ⁇ x ⁇ 0.2 and 0 ⁇ u ⁇ 0.2.
  • a 2-x M x X 3-u A is at least one element selected from the group consisting of V, Nb, Ta, Cr, Mo, W, Mn, Fe, Co, Ga and In, and M is Ti, Zr, Hf, At least one element selected from the group consisting of Sn, V, Nb, Ta, As, Sb, Bi, Cr, Mo and W, and X is at least selected from the group consisting of O, N and F
  • One element, different from A and M 0.001 ⁇ x ⁇ 0.2 and 0 ⁇ u ⁇ 0.3.
  • a 2-x M x X 5-u A is at least one element selected from the group consisting of V, Nb and Ta, M is at least one element selected from the group consisting of Cr, Mo and W, and X is , O, N and F are at least one element selected from the group consisting of A and M, and 0.001 ⁇ x ⁇ 0.2 and 0 ⁇ u ⁇ 0.5 .
  • these materials have a function of storing ions ejected from the resistance change layer 12A, they have an effect of facilitating the movement of ions and limit the composition range to x> 0.001. Regardless of going in and out, it always has an electron conductivity of 10 S / cm or more, and has an effect of ensuring the stability of the crystal structure by limiting the composition range to x ⁇ 0.2. As a result, it is possible to improve the disturbance resistance by applying the reverse voltage.
  • the following materials can be used for the lower electrode 11. That is, since an oxidant is generated on the lower electrode (anode) 11 side after the set operation SO, the lower electrode 11 is made of a material that is not easily oxidized (for example, electrically conductive nitride, electrically conductive oxide, etc.). It is preferable to configure.
  • the electrode layer 11 is preferably made of a material that does not have ion conductivity.
  • LaNiO 3 can be said to be the most preferable material from the viewpoint of comprehensive performance including good electrical conductivity and the like.
  • At least one of the materials represented by the following (7) to (10) can be used.
  • MN includes at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta, and N is nitrogen.
  • MO x consists of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, and Pt. It includes at least one element selected from the group, and the molar ratio x satisfies 1 ⁇ x ⁇ 4.
  • AMO 3 contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba and Ln (Lanthanide), and M is Ti, V, Cr, Mn, Fe, Co, Ni , Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os and Pt, and at least one element selected from the group consisting of Pt, O is oxygen is there.
  • B contains at least 1 type of element selected from the group which consists of K, Ca, Sr, Ba, and Ln (Lanthanide), M is Ti, V, Cr, Mn, Fe, Co, Ni, Cu And at least one element selected from the group consisting of Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, and Pt, and O is oxygen.
  • the lower electrode 11 can be made of metal such as Au, Ru, Ir and W.
  • the upper electrode 13A preferably has a function of preventing the recording unit 12 from reacting with the atmosphere.
  • Examples of such a material include semiconductors such as amorphous carbon, diamond-like carbon, and SnO 2 .
  • metals such as Au, Ru, Ir and W can also be used for the upper electrode 13A.
  • the upper electrode 13A may function as a protective layer for protecting the recording unit 12, or a protective layer may be provided instead of the upper electrode 13A.
  • the protective layer may be an insulator or a conductor.
  • the lower electrode 11 and the upper electrode 13A can be interchanged with each other, and materials that can be used for the lower electrode 11 and the upper electrode 13A can be interchanged with each other.
  • TiSiN, TaN, TaSiN, and WN can be used for the lower electrode 11 and the upper electrode 13A in addition to the materials described in the embodiments.
  • SiN, TiC, TaC, and SiC are also suitable, and mixing these is also suitable.
  • Metals such as Au, Ru, Ir, and W can also be used for the lower electrode 11 and the upper electrode 13A.
  • the lower electrode 11 and the upper electrode 13A include Ti—N, Ti—Si—N, Ta—N, Ta—Si—N, Si—N, Ti—N, Ta—C, Si—C, and W—.
  • At least one selected from the group consisting of N, nitride, carbide, oxide, and a mixture of at least two of nitride, carbide, and oxide can be used. . That is, at least one nitride selected from the group, carbide, oxide, a mixture of nitride and oxide, a mixture of nitride and carbide, a mixture of oxide and carbide, or Any of a mixture of nitride, carbide and oxide can be used.
  • the separation layer 12C that is, the interlayer separation layer 12C (the first interlayer separation layer 12C1 to the Nth separation layer 12CN) and the separation layer 12C0 are Ti—N, Ti—Si—N, Ta—N, Ta—Si—. N, Si—N, Ti—C, Ta—C, Si—C, and at least one nitride selected from the group consisting of W—N, carbide, oxide, and nitride, carbide, and oxide And / or a mixture of at least two of them.
  • the separation layer 12C was selected from the group consisting of ZnO, SnO 2 , In 2 O 3 , TiO s (1 ⁇ s ⁇ 2), In 2 O 3 , IrO 2 , RuO 2 , Ir, Ru, and Ta. At least one of them can be included.
  • the separation layer 12C can use at least one selected from the group consisting of Ga 2 O 3 , Al 2 O 3 , Nb 2 O 5 , SnO 2 , Ta 2 O 5 and Sb 2 O 3 .
  • the separation layer 12C can include at least one selected from the group consisting of W, Ta, Si, Ir, Ru, Au, Pt, Pd, Mo, Ni, Cr, and Co.
  • an information recording / reproducing apparatus for a probe memory, a semiconductor memory, and a flash memory using at least one of the resistance change elements of the first to seventh embodiments will be described.
  • the seventh embodiment of the present invention is a probe memory type information recording / reproducing apparatus.
  • FIG. 20 is a schematic perspective view illustrating the configuration of the information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • FIG. 21 is a schematic plan view illustrating the configuration of part of the information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • FIG. 22 is a schematic view illustrating the operation of the information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • FIG. 23 is a schematic view illustrating the recording operation of the information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • FIG. 24 is a schematic view illustrating the reproducing operation of the information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • any of the first to seventh embodiments of the present invention is placed on the XY scanner 516.
  • a recording medium 410 provided with the variable resistance element 310 is disposed.
  • a probe array is arranged to face the recording medium 410.
  • the recording medium 410 includes, for example, a substrate 520, an electrode layer 521 on the substrate 520, and a first resistance change layer 12A1 and a second resistance change layer 12A2 on the electrode layer 521.
  • the electrode layer 521 the lower electrode 11 described in the first to sixth embodiments can be used. That is, the recording medium 410 is obtained by providing the resistance change element according to the first to seventh embodiments on the substrate 520.
  • the variable resistance element 310 according to the first embodiment will be described.
  • the protective layer 13B is made of, for example, a thin insulator.
  • the probe array has a substrate 523 and a plurality of probes (heads) 524 arranged in an array on one surface side of the substrate 523.
  • Each of the plurality of probes 524 is composed of a cantilever, for example, and is driven by multiplex drivers 525 and 526.
  • Each of the plurality of probes 524 can be individually operated by using the microactuator in the substrate 523.
  • an example in which all of the probes 524 are collectively operated to access the data area of the recording medium 410 will be described. To do.
  • all the probes 524 are reciprocated in the X direction at a constant period, and the position information in the Y direction is read from the servo area of the recording medium 410.
  • the position information in the Y direction is transferred to the driver 515.
  • the driver 15 drives the XY scanner 516 based on this position information, moves the recording medium 410 in the Y direction, and positions the recording medium 419 and the probe 524.
  • Data reading and writing are continuously performed because the probe 524 is reciprocating in the X direction. Data reading and writing are performed on the data area 531 line by line by sequentially changing the position of the recording medium 410 in the Y direction.
  • the recording medium 410 may be reciprocated in the X direction at a constant cycle to read position information from the recording medium 410, and the probe 524 may be moved in the Y direction.
  • the resistance change element 310 includes a plurality of data areas 531 and servo areas 532 arranged at both ends of the plurality of data areas 531 in the X direction.
  • the plurality of data areas 531 occupy the main part of the recording medium 410.
  • Servo burst signals are recorded in the servo area 531.
  • the servo burst signal indicates position information in the Y direction within the data area 531.
  • variable resistance element 310 in addition to these pieces of information, an address area in which address data is recorded and a preamble area for synchronization are arranged.
  • the data and servo burst signal are recorded in the resistance change element 310 as recording bits (electrical resistance fluctuation).
  • Information of “3”, “2”, “1”, “0” of the recording bit is read by detecting the electric resistance of the variable resistance element 310 and quantizing the quaternary information.
  • one probe (head) is provided corresponding to one data area 531, and one probe is provided for one servo area 532.
  • the data area 531 is composed of a plurality of tracks.
  • the track of the data area 531 is specified by the address signal read from the address area.
  • the servo burst signal read from the servo area 532 is for moving the probe 524 to the center of the track and eliminating the recording bit reading error.
  • the X direction correspond to the down-track direction and the Y direction correspond to the track direction, it becomes possible to use the HDD head position control technology.
  • Each probe 524 is connected to the drive unit 600 via, for example, multiplex drivers 525 and 526.
  • the drive unit 600 supplies each probe 524 with at least one of voltage and current for information recording. Then, the recording unit 12 of the resistance change element 310 transitions between three or more resistance states according to the voltage and current applied via the probe 524.
  • the drive unit 600 detects three or more resistance states recorded in the recording unit 12 and reads the recorded information.
  • the information recording / reproducing apparatus 210 includes at least one of the resistance change elements according to the first to seventh embodiments, application of a voltage to the recording unit of the resistance change element, A drive unit 600 is provided that records information by causing the recording unit to transition between three or more resistance states by at least one of supplying a current to the recording unit.
  • the information recording / reproducing apparatus 210 further includes a probe 524 attached to the resistance change element, and the drive unit 600 applies a voltage to the recording unit of the resistance change element via the probe 524, and At least one of current supply to the recording unit is performed.
  • the information recording / reproducing apparatus 210 uses at least one of the resistance change elements according to the first to seventh embodiments, it is possible to provide an information recording / reproducing apparatus that enables multi-value recording.
  • FIG. 22 conceptually illustrates the recording operation (set operation SO).
  • the recording operation is performed by applying a voltage to the surface of the recording bit 527 of the variable resistance element 310 to generate a potential gradient inside the recording bit 527.
  • a current or voltage pulse is applied to the resistance change section 12 (first resistance change layer 12A1 and second resistance change layer 12A2) of the resistance change element 310 to be the recording bit 527 through the probe 524.
  • FIG. 23 conceptually illustrates the recording operation.
  • a state in which the potential of the probe 524 is relatively lower than the potential of the electrode layer 521 is created.
  • the electrode layer 521 is set to a fixed potential (eg, ground potential)
  • a negative potential may be applied to the probe 524.
  • the current pulse is generated by emitting electrons from the probe 524 toward the electrode layer 521 using, for example, an electron generation source or a hot electron source.
  • the voltage pulse may be applied by bringing the probe 524 into contact with the surface of the recording bit 527.
  • the A ions 52 moves to the probe (cathode) 524 side and crystal (resistance change)
  • the A ions 52 in the layer 12A) decrease relative to the X ions 61.
  • the A ions 52 that have moved to the probe 24 side receive electrons from the probe 524 and are deposited as metal.
  • the X ion 61 becomes excessive, and as a result, the valence of the A ion 52 or the M ion 51 in the recording bit 527 is increased. That is, since the recording bit 527 has electron conductivity due to carrier injection due to phase change, resistance in the film thickness direction is reduced, and recording (set operation) is completed.
  • the current pulse for recording can be generated by creating a state in which the potential of the probe 524 is relatively higher than the potential of the electrode layer 521.
  • FIG. 24 conceptually illustrates the reproduction operation. Reproduction is performed by passing a current pulse through the recording bit 527 of the variable resistance element 310 and detecting the resistance value of the recording bit 527. However, the current pulse is set to a minute value such that the resistance change element 310 used for the recording bit 527 does not change in resistance.
  • a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 524 to the recording bit 527, and the resistance value of the recording bit 527 is measured by the sense amplifier S / A.
  • recording and reproduction of 2 bits per memory cell is possible by quantizing the measured quaternary information.
  • the erase operation (reset operation RO) is performed by heating the recording bit 527 of the variable resistance element 310 with a large current pulse to promote the oxidation-reduction reaction in the recording bit 527.
  • a pulse that gives a potential difference opposite to that in the set operation SO may be applied.
  • the erasing operation can be performed for each recording bit 527, or can be performed in units of a plurality of recording bits 527 or blocks.
  • FIG. 25 is a schematic view illustrating the recording operation of another information recording / reproducing apparatus according to the eighth embodiment of the invention.
  • FIG. 26 is a schematic view illustrating the playback operation of another information recording / playback apparatus according to the eighth embodiment of the invention.
  • the resistance change element 370 according to the seventh embodiment is used. That is, the resistance change unit 12 includes a first resistance change layer 12A1 and a second resistance change layer 12A2 (resistance change layer 12A), and a first ion storage layer 12B1 and a second ion storage layer 12B2 (ion storage layer 12B).
  • the electrode layer 521 is used as the lower electrode 11 of the resistance change element 370, and the protective layer 13B is used instead of the upper electrode 13A.
  • FIG. 25 conceptually illustrates the recording operation.
  • a state in which the potential of the probe 524 is relatively lower than the potential of the electrode layer 521 is created. If the electrode layer 521 is set to a fixed potential (eg, ground potential), a negative potential is applied to the probe 524.
  • a fixed potential eg, ground potential
  • a part of the A ions 52 in at least one of the first resistance change layer 12A1 and the second resistance change layer 12A2 of the resistance change element 370 move in the crystal, and the first ion storage layer 12B1 and the first ion storage layer 12B1 respectively. It fits in the void site ⁇ of the two-ion storage layer 12B2. Accordingly, the valence of A ions 52 or M1 ions 51 in at least one of the first resistance change layer 12A1 and the second resistance change layer 12A2 increases, and the first ion storage layer 12B1 and the second ion storage layer. The valence of at least one A ion 52 or M2 ion 53 of 12B2 decreases.
  • the recording operation if the positional relationship between the first resistance change layer 12A1 and the second resistance change layer 12A2 and the first ion storage layer 12B1 and the second ion storage layer 12B2 is reversed, the potential of the probe 524 is changed. It is also possible to execute the set operation SO in a state that is relatively lower than the potential of the electrode layer 21.
  • FIG. 26 conceptually shows the reproduction operation.
  • the reproduction operation is performed by passing a current pulse through the recording bit 527 and detecting the resistance value of the recording bit 527.
  • the current pulse is set to a minute value such that the resistance change element 370 used for the recording bit 527 does not change in resistance.
  • a read current (current pulse) generated by the sense amplifier S / A is passed from the probe 524 to the resistance change element 370 (recording bit 527), and the resistance value of the recording bit 527 is measured by the sense amplifier S / A.
  • recording and reproduction of 2 bits per memory cell is possible by quantizing the measured quaternary information.
  • the reproduction operation can be continuously performed by scanning the probe 524 in the direction of the arrow 524a, for example.
  • the reset operation RO erase operation
  • the A ions 52 are converted into the first ion storage layer 12B1 and the second ion using the Joule heat generated by flowing a large current pulse through the resistance change element 370 (recording bit) and the residual heat.
  • action which tries to return from the space
  • a pulse that gives a potential difference opposite to that in the set operation SO may be applied.
  • the erasing operation can be performed for each recording bit 527, or can be performed in units of a plurality of recording bits 527 or blocks.
  • an information recording / reproducing apparatus using a plurality of resistance change layers uses many stages of resistance states, and it is difficult to perform impedance matching for all states. Therefore, noise components such as ringing can be increased as the operating frequency band becomes higher. In order to reduce these, it is also important to reduce the parasitic component and the inductance component of the transmission line connected to the ground.
  • the information recording / reproducing apparatuses 210 and 211 for example, by providing a band pass filter, a low pass filter, or the like, noise components such as the above ringing are reduced, and the parasitic capacitance or ground is reduced. It is possible to reduce connected transmission lines and inductance components.
  • an information recording / reproducing apparatus capable of multi-value recording is provided by using at least one of the resistance change elements according to the embodiment of the present invention. It is possible to realize higher recording density and lower power consumption than current hard disks and flash memories.
  • the information recording / reproducing apparatus according to the ninth embodiment of the present invention is a cross-point type information recording / reproducing apparatus.
  • FIG. 27 is a schematic view illustrating the configuration of an information recording / reproducing apparatus according to the ninth embodiment of the invention.
  • FIG. 28 is a schematic perspective view illustrating the configuration of an information recording / reproducing apparatus according to the ninth embodiment of the invention.
  • the information recording / reproducing apparatus 220 according to the present embodiment is a cross-point type memory using at least one of the resistive recording elements according to the first to seventh embodiments.
  • the word lines WL i ⁇ 1 , WL i , WL i + 1 extend in the X direction
  • the bit lines BL j ⁇ 1 , BL j , BL j + 1 extend in the Y direction.
  • each of the word lines WL i ⁇ 1 , WL i , WL i + 1 is connected to a word line driver 31 having a decoder function via a MOS transistor RSW as a selection switch
  • the bit lines BL j ⁇ 1 , BL j , BL j + 1 is connected to a bit line driver 32 having a decoder and a read function via a MOS transistor CSW as a selection switch.
  • Selection signals R i ⁇ 1 , R i and R i + 1 for selecting one word line (row) are input to the gate of the MOS transistor RSW, and one bit line is input to the gate of the MOS transistor CSW.
  • Selection signals C j ⁇ 1 , C j , C j + 1 for selecting (column) are input.
  • the memory cell 33 is arranged at the intersection of the word lines WL i ⁇ 1 , WL i , WL i + 1 and the bit lines BL j ⁇ 1 , BL j , BL j + 1 . That is, the information recording / reproducing apparatus 220 has a so-called cross-point cell array structure.
  • the memory cell 33 At least one of the resistance change elements according to the first to seventh embodiments is used.
  • the variable resistance element 310 according to the first embodiment is used.
  • a rectifying element (diode) 34 for preventing a sneak current during recording / reproduction is added to the memory cell 33.
  • FIG. 28 conceptually shows the structure of the memory cell array portion of the information recording / reproducing apparatus 220.
  • word lines WL i ⁇ 1 , WL i , WL i + 1 and bit lines BL j ⁇ 1 , BL j , BL j + 1 are arranged, and memory cells 33, rectifying elements 34, , Is arranged.
  • the feature of such a cross-point cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33.
  • the memory cell 33 is provided with a resistance change element having a lower electrode 11, a first resistance change layer 12A1, a second resistance change layer 12A2, and an upper electrode 13A. Layer 35 and protective layer 13B are provided. The memory cell 33 and the rectifying element 34 are provided between the word line WL i and the bit line BL j . Then, 2-bit data is stored in one memory cell 33.
  • At least one of the heater layer 35 and the protective layer 33B can be omitted.
  • Various buffer layers (not shown) may be provided.
  • the lower electrode 11 and the upper electrode 13A may be used also as the word line WL i , the bit line BL j , the heater layer 35, the protective layer 13B, and the like.
  • the lower electrode 11 and the upper electrode 13A are It is regarded as various layers that are combined.
  • the information recording / reproducing apparatus 220 includes at least one of the resistance change elements according to the first to seventh embodiments, the application of a voltage to the recording unit of the resistance change element, A word line driver 31 and a bit line driver 32 serving as a drive unit for recording information by causing the recording unit to transit between three or more resistance states by at least one of supplying a current to the recording unit.
  • the information recording / reproducing apparatus 220 further includes a word line and a bit line provided so as to sandwich the variable resistance element, and the word line driver 31 and the bit line driver 32 are connected via the word line and the bit line. At least one of application of a voltage to the recording unit of the variable resistance element and energization of a current to the recording unit is performed.
  • the information recording / reproducing apparatus 220 uses at least one of the resistance change elements according to the first to seventh embodiments, it is possible to provide an information recording / reproducing apparatus that enables multi-value recording.
  • a voltage is applied to the selected memory cell 33, a potential gradient is generated in the memory cell 33, and a current pulse is passed. For example, a state is created in which the potential of the word line WL i is relatively lower than the potential of the bit line BL j .
  • the bit line BL j is set to a fixed potential (for example, ground potential), and a negative potential is applied to the word line WL i .
  • the A ion 52 moves to the word line (cathode) WL i side, and the A ion 52 in the crystal is relative to the X ion 61. Decrease.
  • the A ions 52 that have moved to the word line WL i side receive electrons from the word line WL i and are deposited as metal.
  • the X ions 61 become excessive, and as a result, the valence of the A ions 52 or M ions 51 in the crystal is increased. That is, since the selected memory cell 33 surrounded by the dotted line A has electron conductivity due to carrier injection due to the state change, the recording (set operation SO) is completed.
  • the unselected word lines WL i ⁇ 1 and WL i + 1 and the unselected bit lines BL j ⁇ 1 and BL j + 1 are all biased to the same potential. Further, at the time of standby before recording, it is desirable to precharge all the word lines WL i ⁇ 1 , WL i , WL i + 1 and all the bit lines BL j ⁇ 1 , BL j , BL j + 1 .
  • the current pulse for recording may be generated by creating a state in which the potential of the word line WL i is relatively higher than the potential of the bit line BL j .
  • Regeneration is performed by flowing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33.
  • the current pulse is set to a minute value that does not cause the resistance change portion 12 of the memory cell 33 to change in resistance.
  • read current generated by the reading circuit (current pulses) to the memory cell 33 surrounded by the dotted line A from the bit line BL j, measure the resistance value of the memory cell 33 by the read circuit.
  • current pulses current pulses
  • 2 bits can be recorded per memory cell.
  • the erase operation (reset operation RO) is performed by heating the selected memory cell 33 surrounded by the dotted line A with a large current pulse to promote the oxidation-reduction reaction in the memory cell 33.
  • the resistance change element 370 resistance change element having an ion storage layer
  • a voltage is applied to the selected memory cell 33, a potential gradient is generated in the memory cell 33, and a current pulse flows.
  • the potential of the word line WL i is made relatively lower than the potential of the bit line BL j . That is, for example, the bit line BL j is set to a fixed potential (for example, ground potential), and a negative potential is applied to the word line WL i .
  • a part of the A ions 52 of at least one of the first resistance change layer 12A1 and the second resistance change layer 12A1 is respectively the first ion storage layer. It moves to the void site 58 of 12B1 and the second ion storage layer 12B2. For this reason, the valence of A ions 52 or M2 ions 53 in at least one of the first ion storage layer 12B1 and the second ion storage layer 12B2 decreases, and the first resistance change layer 12A1 and the second resistance change layer 12A2 The valence of at least one of the A ions 52 or the M1 ions 51 increases.
  • the unselected word lines WL i ⁇ 1 and WL i + 1 and the unselected bit lines BL j ⁇ 1 and BL j + 1 are all biased to the same potential. Further, at the time of standby before recording, it is desirable to precharge all the word lines WL i ⁇ 1 , WL i , WL i + 1 and all the bit lines BL j ⁇ 1 , BL j , BL j + 1 .
  • the current pulse may be generated by creating a state in which the potential of the word line WL i is relatively higher than the potential of the bit line BL j .
  • the reproduction operation is performed by flowing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. At this time, the current pulse is set to a minute value that does not cause the resistance change element used in the memory cell 33 to change in resistance.
  • a read current (current pulse) generated by the read circuit is supplied from the bit line BLj to the memory cell 33 surrounded by the dotted line A, and the resistance value of the memory cell 33 is measured by the read circuit.
  • 2 bits can be recorded / reproduced per memory cell 33.
  • the A ion element 52 is converted into the first ion storage layer 12B1 and the first ion storage layer 12B by using Joule heat and residual heat generated by applying a large current pulse to the selected memory cell 33 surrounded by the dotted line A. What is necessary is just to promote the action of returning to the first resistance change layer 12A1 and the second resistance change layer 12A2 from at least one of the void sites 58 of the two ion storage layer 12B2.
  • noise components such as the above ringing are reduced, leading to parasitic capacitance or ground. Transmission lines and inductance components can be reduced.
  • 29 and 30 are schematic perspective views illustrating the configuration of another information recording / reproducing apparatus according to the ninth embodiment of the invention.
  • FIG. 29 in another information recording / reproducing device 221 according to the present embodiment, words extending in the X direction above and below the bit lines BL j ⁇ 1 , BL j , BL j + 1 extending in the Y direction.
  • Lines WL i ⁇ 1 , WL i , WL i + 1 are provided, respectively.
  • a memory cell 33 and a rectifying element 34 are provided at the cross points between these bit lines and word lines. That is, the bit line is shared by the upper and lower memory cells.
  • the memory cell 33 is provided with at least one of the resistance change elements according to the first to seventh embodiments.
  • bit lines BL j ⁇ 1 , BL j , BL j + 1 extending in the Y direction and word lines WL extending in the X direction. i ⁇ 1 , WL i and WL i + 1 are alternately stacked.
  • a memory cell 33 and a rectifying element 34 are provided at the cross points between these bit lines and word lines.
  • the memory cell 33 is provided with at least one of the resistance change elements according to the first to seventh embodiments.
  • the memory cells 33 are stacked and the memory cell array has a three-dimensional structure, so that the recording density can be increased. Note that the number of stacked memory cells 33 is arbitrary.
  • information recording that enables multi-level recording by using at least one of the resistance change elements according to the embodiment of the present invention.
  • a playback device can be provided, and higher recording density and lower power consumption can be realized than the current hard disk or flash memory.
  • the information recording / reproducing apparatus according to the tenth embodiment of the present invention is a flash memory type information recording / reproducing apparatus.
  • FIG. 31 is a schematic cross-sectional view illustrating the configuration of the main part of the information recording / reproducing apparatus according to the tenth embodiment of the invention.
  • FIG. 32 is a schematic cross-sectional view illustrating the operation of the information recording / reproducing apparatus according to the tenth embodiment of the invention.
  • the information recording / reproducing apparatus 260 according to the present embodiment has a flash memory type memory cell, and this memory cell is composed of a MIS (metal-insulator-semiconductor) transistor.
  • MIS metal-insulator-semiconductor
  • the diffusion layer 42 is formed in the surface region of the semiconductor substrate 41.
  • a gate insulating layer 43, a resistance change element 44, and a control gate electrode 45 are sequentially formed.
  • At least one of the resistance change elements according to the first to seventh embodiments is used for the resistance change element 44.
  • the resistance change element 44 includes the upper electrode 13A and the recording unit 12 (that is, the first resistance change layer 12A1 and the second resistance change layer 12A2) described in the first to seventh embodiments. And have. Furthermore, the resistance change element 44 can further include the lower electrode 12 described in the first to seventh embodiments.
  • the information recording / reproducing apparatus 260 applies a voltage to at least one of the resistance change elements described in the first to seventh embodiments and the recording unit 12 of the resistance change element, or And a drive unit (not shown) for recording information by causing the recording unit 12 to transition between three or more resistance states.
  • the drive unit in this case is connected to the control gate electrode 45, and the drive unit applies the voltage to the recording unit 12 of the resistance change element 44 and the recording unit of the resistance change element 44 through the control gate electrode 45. At least one of energization of current to 12 is performed.
  • the information recording / reproducing apparatus 260 further includes a MIS transistor having a gate electrode (control gate electrode 45) and a gate insulating film (gate insulating layer 43).
  • the resistance change element 44 is provided between the gate electrode of the MIS transistor and the gate insulating layer.
  • any one of the upper electrode 13A and the lower electrode 11 of the resistance change element 44 may be used as the control gate electrode 45, for example.
  • the semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types.
  • the control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.
  • the set operation SO (write operation) is executed by applying a potential V1 to the control gate electrode 45 and applying a potential V2 to the semiconductor substrate 41.
  • the difference between the potential V1 and the voltage V2 is a voltage at which the resistance value of the resistance change element 44 changes to four values corresponding to the values of the record information “3”, “2”, “1”, “0”, that is,
  • the threshold voltages Vsh 1 , Vsh 2 , Vsh 3 , and Vsh 4 are set to an appropriate magnitude, but the direction is not particularly limited. That is, either V1> V2 or V1 ⁇ V2 may be used.
  • the gate insulating layer 43 is substantially thick. Therefore, the threshold value of the memory cell (MIS transistor) is the highest.
  • the gate insulating layer 43 is substantially thin. Therefore, the threshold value of the memory cell (MIS transistor) changes according to the recorded information.
  • the potential V2 is applied to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.
  • the erasing operation is performed by applying a potential V1 'to the control gate electrode 45, applying a potential V3 to one of the diffusion layers 42, and applying a potential V4 ( ⁇ V3) to the other of the diffusion layers 42.
  • V2 and potential V1 ' is set to a value exceeding the threshold voltage Vsh 4 to a first variable resistance layer 12A1 and the second variable resistance layer 12A2 in the reset state.
  • the memory cell is turned on, electrons flow from the other side of the diffusion layer 42 toward one side, and hot electrons are generated. Since the hot electrons are injected into the resistance change element 44 through the gate insulating layer 43, the temperature of the resistance change element 44 rises.
  • the first resistance change layer 12A1 and the second resistance change layer 12A2 of the resistance change element 44 change from the low resistance state LR to the high resistance state HR, so that the gate insulating layer 43 is substantially thickened.
  • the threshold value of the memory cell is increased.
  • the information recording / reproducing apparatus 260 can change the threshold value of the memory cell to multiple values according to the recording information, based on the principle similar to that of the flash memory. That is, the information recording / reproducing apparatus can be put into practical use by utilizing the technology of the flash memory. Since the information recording / reproducing apparatus 260 according to the present embodiment uses at least one of the resistance change elements according to the first to seventh embodiments, an information recording / reproducing apparatus capable of multi-value recording can be provided.
  • FIG. 33 is a schematic view illustrating the configuration of the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention.
  • FIG. 34 is a schematic cross-sectional view illustrating the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention. That is, another information recording / reproducing device 261 according to the present embodiment is a NAND flash memory.
  • FIG. 33 illustrates the NAND cell unit 261c and the drive unit 600 connected thereto, and FIG. The structure of the cell unit 261c is illustrated.
  • an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
  • a NAND cell unit 261c according to the example of this embodiment is formed in the P-type well region 41c.
  • the NAND cell unit 261c is composed of a NAND string composed of a plurality of memory cells MC connected in series and a total of two select gate transistors ST connected one to the both ends.
  • the memory cell MC and the select gate transistor ST have the same structure. Specifically, these are the N-type diffusion layer 42, the gate insulating layer 43 on the channel region between the N-type diffusion layers 42, the resistance change element 44 on the gate insulation layer 43, and the resistance change element 44. Control gate electrode 45 (CG).
  • the resistance change element according to the first to seventh embodiments may not be used, and a single resistance change layer or conductive layer can be used instead.
  • Each control gate electrode 45 is electrically connected to the drive unit 600.
  • the driving unit 600 may be provided on a substrate on which the NAND cell unit 261c is provided, or may be provided on a different substrate.
  • the resistance change element 44 is used for the resistance change element 44. That is, although not shown in these drawings, the variable resistance element 44 is provided with the first variable resistance layer 12A1 and the second variable resistance layer 12A2 described in the first to seventh embodiments.
  • the state of the resistance change element 44 of the memory cell MC (high resistance state HR / low resistance state LR) can be changed by the basic operation described above.
  • the first resistance change layer 12A1 and the second resistance change layer 12A2 of the resistance change element 44 of the select gate transistor ST are fixed to the set state, that is, the low resistance state LR.
  • One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.
  • the set operation SO (write operation) is sequentially performed one by one from the memory cell MC on the source line SL side toward the memory cell on the bit line BL side.
  • V1 plus potential
  • Vpass is given as a transfer potential (potential at which the memory cell MC is turned on) to the unselected word line WL.
  • the select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
  • program data is “3”
  • a write inhibit potential for example, the same potential as V1
  • the resistance value is not changed from a high state to a low state.
  • the voltage V2 ( ⁇ V1) corresponding to the data to be recorded in the channel region of the selected memory cell MC is transferred, and the selected memory
  • the resistance value of the resistance change element 44 of the cell MC is changed from a high reset state to a low state.
  • V1 ′ is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 ( ⁇ V3) is applied to the source line SL. At this time, since hot electrons are injected into the resistance change elements 44 of all the memory cells MC in the NAND cell unit 261c, a reset operation is collectively performed on all the memory cells MC in the NAND cell unit 261c.
  • a read potential V (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0” to “0” on the unselected word line (control gate electrode) WL.
  • a potential to be turned on regardless of 3 ′′ is given. Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
  • the threshold voltage corresponding to the recording data “0” to “3” is set to WL.
  • data “0” to “3” can be read by selecting the read potential V and repeating detection of a change in read current by changing V, for example.
  • FIG. 35 is a schematic cross-sectional view illustrating the main part of an information recording / reproducing apparatus according to a modification of the tenth embodiment of the invention.
  • a normal MIS transistor is used as the select gate transistor ST without forming the resistance change element 44.
  • the structure of the select transistor ST is arbitrary.
  • FIG. 36 is a schematic cross-sectional view illustrating the main part of an information recording / reproducing apparatus according to a modification of the tenth embodiment of the invention.
  • the gate insulating layers of the plurality of memory cells MC constituting the NAND string are replaced with the P-type semiconductor layer 47.
  • the P-type semiconductor layer 47 is filled with a depletion layer in a state where no voltage is applied.
  • a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and a positive voltage is applied to the control gate electrode 45 of the non-selected memory cell MC.
  • Transfer potential (for example, 1 V).
  • the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.
  • the select gate transistor ST on the bit line BL side is turned on and the program data “0” to “2” is transferred from the bit line BL to the channel region of the selected memory cell MC, the set operation is performed. It can be performed.
  • the NAND string Can be performed collectively for all the memory cells MC constituting the memory cell MC.
  • a negative erase potential for example, ⁇ 3.5 V
  • a ground potential (0 V)
  • a positive read potential V (for example, 0.25 V, 0.5 V, 0.75 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the control gate electrode of the non-selected memory cell MC
  • a transfer potential (for example, 1 V) is always applied to the memory cell MC which is always turned on regardless of the data “0” to “3”.
  • the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0 than that of the P-type well region 41c. It is desirable that the depth is about 5V. This is because when a positive potential is applied to the control gate electrode 45, inversion from the P-type to N-type starts from the surface portion of the P-type well region 41c between the N-type diffusion layers 42, and a channel is formed. It is for doing so.
  • the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed.
  • the channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
  • the diffusion layer 42 and the control gate electrode 45 are not short-circuited.
  • FIG. 37 is a schematic view illustrating the configuration of the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention.
  • FIG. 38 is a schematic cross-sectional view illustrating the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention. That is, another information recording / reproducing apparatus 264 according to the present embodiment is a NOR flash memory.
  • FIG. 37 illustrates the NOR cell unit 264c and the drive unit 600 connected thereto
  • FIG. 38 illustrates the NOR. The structure of the cell unit 264c is illustrated.
  • an N-type well region 41b and a P-type well region 41c are formed in a P-type semiconductor substrate 41a.
  • a NOR cell according to the example of this embodiment is formed in the P-type well region 41c.
  • the NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
  • the memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a resistance change element 44 on the gate insulation layer 43, and a control gate on the resistance change element 44. And an electrode 45.
  • Each control gate electrode 45 is electrically connected to the drive unit 600.
  • the driving unit 600 may be provided on a substrate on which the NOR cell unit 264c is provided, or may be provided on a different substrate.
  • the state of the resistance change element 44 of the memory cell MC (high resistance state HR / low resistance state) can be changed by the basic operation described above.
  • FIG. 39 is a schematic view illustrating the configuration of the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention.
  • FIG. 40 is a schematic cross-sectional view illustrating the main part of another information recording / reproducing apparatus according to the tenth embodiment of the invention. That is, another information recording / reproducing apparatus 265 according to the present embodiment is a two-tra type flash memory.
  • FIG. 39 illustrates a two-tracell unit 265c and a drive unit 600 connected thereto, and FIG. The structure of the 2 tracell unit 265c is illustrated.
  • the two-transistor cell unit 265c has a cell structure having both the characteristics of a NAND cell unit and the characteristics of a NOR cell.
  • an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
  • a two-transistor cell unit 265c is formed in the P-type well region 41c.
  • the 2-transistor type cell unit 265c is composed of one memory cell MC and one select gate transistor ST connected in series.
  • the memory cell MC and the select gate transistor ST have the same structure. Specifically, these are the N-type diffusion layer 42, the gate insulating layer 43 on the channel region between the N-type diffusion layers 42, the resistance change element 44 on the gate insulation layer 43, and the resistance change element 44. Control gate electrode 45.
  • Each control gate electrode 45 is electrically connected to the drive unit 600.
  • the drive part 600 may be provided in the board
  • the select gate transistor ST it is not necessary to use the resistance change element according to the first to seventh embodiments. Instead, one resistance change layer or a conductive layer can be used.
  • the state of the resistance change element 44 of the memory cell MC (high resistance state HR / low resistance state LR) can be changed by the basic operation described above.
  • the resistance change element 44 of the select gate transistor ST is fixed to a set state, that is, a conductor (low resistance).
  • the select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.
  • the state of the resistance change element 44 of the memory cell MC (high resistance state HR / low resistance state) can be changed by the basic operation described above.
  • FIG. 41 is a schematic cross-sectional view illustrating the main part of an information recording / reproducing apparatus according to a modification according to the tenth embodiment of the invention.
  • the select gate transistor ST is a normal MIS transistor without forming the resistance change element 44.
  • noise components such as the above ringing can be reduced, and parasitic capacitance or grounding can be performed.
  • the transmission line connected to and the inductance component can be reduced.
  • variable resistance elements and information recording / reproducing apparatuses that can be implemented by those skilled in the art based on the variable resistance elements and information recording / reproducing apparatuses described above as embodiments of the present invention are also included in the present invention. As long as the gist is included, it belongs to the scope of the invention.
  • variable resistance element and an information recording / reproducing apparatus capable of multi-value recording.

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Abstract

L'invention concerne un élément à variation de résistance comprenant une partie à variation de résistance dotée d'une première couche à variation de résistance amenée à présenter une pluralité d'états de résistivités électriques différentes via au moins une tension appliquée et un courant appliqué, et une seconde couche à variation de résistance conçue pour afficher une pluralité d'états de résistivités électriques différentes via au moins une tension appliquée et un courant appliqué. L'invention concerne également une couche d'électrode conçue pour réaliser l’application de tension et/ou l'application de courant normal à la surface du film de la partie à variation de résistance. L'élément à variation de résistance est caractérisé en ce qu'une tension et/ou un courant devant transiter parmi une pluralité d'états différents dans la première couche à variation de résistance et au moins une tension et un courant devant transiter parmi une pluralité d'états différents dans la seconde couche à variation de résistance sont différents l'un de l'autre.
PCT/JP2008/066471 2008-09-11 2008-09-11 Elément à variation de résistance, et dispositif de reproduction/d'enregistrement d’informations WO2010029634A1 (fr)

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WO2015125449A1 (fr) * 2014-02-24 2015-08-27 株式会社アルバック Élément à résistance variable et son procédé de fabrication
CN106030800A (zh) * 2014-02-24 2016-10-12 株式会社爱发科 电阻可变元件及其制造方法
JPWO2015125449A1 (ja) * 2014-02-24 2017-03-30 株式会社アルバック 抵抗変化素子及びその製造方法
TWI637485B (zh) * 2014-02-24 2018-10-01 日商愛發科股份有限公司 電阻變化元件及其製造方法
JP2020047711A (ja) * 2018-09-18 2020-03-26 株式会社アルバック 記憶素子製造方法
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