WO2010013984A2 - 박막 트랜지스터의 제조방법 및 제조장치 - Google Patents

박막 트랜지스터의 제조방법 및 제조장치 Download PDF

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Publication number
WO2010013984A2
WO2010013984A2 PCT/KR2009/004320 KR2009004320W WO2010013984A2 WO 2010013984 A2 WO2010013984 A2 WO 2010013984A2 KR 2009004320 W KR2009004320 W KR 2009004320W WO 2010013984 A2 WO2010013984 A2 WO 2010013984A2
Authority
WO
WIPO (PCT)
Prior art keywords
electrode pattern
pattern
forming
ohmic contact
film transistor
Prior art date
Application number
PCT/KR2009/004320
Other languages
English (en)
French (fr)
Other versions
WO2010013984A3 (ko
Inventor
이형섭
Original Assignee
부경디스플레이 (주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR20080075669A external-priority patent/KR101494152B1/ko
Priority claimed from KR1020080075652A external-priority patent/KR101531691B1/ko
Priority claimed from KR1020080075640A external-priority patent/KR20100013900A/ko
Application filed by 부경디스플레이 (주) filed Critical 부경디스플레이 (주)
Priority to US13/056,970 priority Critical patent/US8278127B2/en
Priority to DE112009001874T priority patent/DE112009001874T5/de
Priority to CN2009801387593A priority patent/CN102177462A/zh
Publication of WO2010013984A2 publication Critical patent/WO2010013984A2/ko
Publication of WO2010013984A3 publication Critical patent/WO2010013984A3/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)
  • Liquid Crystal (AREA)

Abstract

본 발명은 레이저 패터닝 공정을 통해 오믹 컨택층을 패터닝하여 반도체층의 손상을 방지함과 아울러 공정 시간을 감소시킬 수 있는 박막 트랜지스터의 제조방법 및 제조장치에 관한 것으로, 기판 상에 게이트 전극 패턴을 형성하는 공정; 상기 게이트 전극 패턴상에 게이트 절연막을 형성하는 공정; 상기 게이트 절연막 상 에 반도체층 패턴 및 오믹 콘택층 패턴을 차례로 형성하는 공정; 상기 오믹 콘택층 패턴 상에 소정 간격으로 이격된 소스 전극 패턴 및 드레인 전극 패턴을 형성하는 공정; 및 레이저를 이용하여 상기 소스 전극 패턴 및 드레인 전극 패턴 사이에 노출된 상기 오믹 콘택층 패턴을 제거하는 공정을 포함하여 이루어진 박막 트랜지스터의 제조방법을 제공하는 것을 특징으로 한다.
PCT/KR2009/004320 2008-08-01 2009-08-03 박막 트랜지스터의 제조방법 및 제조장치 WO2010013984A2 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US13/056,970 US8278127B2 (en) 2008-08-01 2009-08-03 Method for manufacturing a thin-film transistor using a laser
DE112009001874T DE112009001874T5 (de) 2008-08-01 2009-08-03 Verfahren und Vorrichtung zur Herstellung eines Dünnschichttransistors
CN2009801387593A CN102177462A (zh) 2008-08-01 2009-08-03 制造薄膜晶体管的方法和装置

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR20080075669A KR101494152B1 (ko) 2008-08-01 2008-08-01 박막 트랜지스터 어레이 기판의 제조방법 및 제조장치
KR10-2008-0075640 2008-08-01
KR10-2008-0075652 2008-08-01
KR10-2008-0075669 2008-08-01
KR1020080075652A KR101531691B1 (ko) 2008-08-01 2008-08-01 박막 트랜지스터 어레이 기판의 제조방법 및 제조장치
KR1020080075640A KR20100013900A (ko) 2008-08-01 2008-08-01 박막 트랜지스터의 제조방법 및 제조장치

Publications (2)

Publication Number Publication Date
WO2010013984A2 true WO2010013984A2 (ko) 2010-02-04
WO2010013984A3 WO2010013984A3 (ko) 2010-06-10

Family

ID=41610877

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/004320 WO2010013984A2 (ko) 2008-08-01 2009-08-03 박막 트랜지스터의 제조방법 및 제조장치

Country Status (5)

Country Link
US (1) US8278127B2 (ko)
CN (1) CN102177462A (ko)
DE (1) DE112009001874T5 (ko)
TW (1) TWI484563B (ko)
WO (1) WO2010013984A2 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2754524B1 (de) 2013-01-15 2015-11-25 Corning Laser Technologies GmbH Verfahren und Vorrichtung zum laserbasierten Bearbeiten von flächigen Substraten, d.h. Wafer oder Glaselement, unter Verwendung einer Laserstrahlbrennlinie
EP2781296B1 (de) 2013-03-21 2020-10-21 Corning Laser Technologies GmbH Vorrichtung und verfahren zum ausschneiden von konturen aus flächigen substraten mittels laser
US11556039B2 (en) 2013-12-17 2023-01-17 Corning Incorporated Electrochromic coated glass articles and methods for laser processing the same
US9517963B2 (en) 2013-12-17 2016-12-13 Corning Incorporated Method for rapid laser drilling of holes in glass and products made therefrom
US9815144B2 (en) 2014-07-08 2017-11-14 Corning Incorporated Methods and apparatuses for laser processing materials
CN107073642B (zh) 2014-07-14 2020-07-28 康宁股份有限公司 使用长度和直径可调的激光束焦线来加工透明材料的系统和方法
HUE055461T2 (hu) 2015-03-24 2021-11-29 Corning Inc Kijelzõ üveg kompozíciók lézeres vágása és feldolgozása
KR102078294B1 (ko) 2016-09-30 2020-02-17 코닝 인코포레이티드 비-축대칭 빔 스폿을 이용하여 투명 워크피스를 레이저 가공하기 위한 기기 및 방법
KR102428350B1 (ko) * 2016-10-24 2022-08-02 코닝 인코포레이티드 시트형 유리 기판의 레이저 기반 기계 가공을 위한 기판 프로세싱 스테이션
US20180118602A1 (en) * 2016-11-01 2018-05-03 Corning Incorporated Glass sheet transfer apparatuses for laser-based machining of sheet-like glass substrates
WO2019236725A1 (en) * 2018-06-06 2019-12-12 Accelerat3d Inc. Apparatuses and methods for fabricating parts on a multi gantry machine during additive manufacturing
KR20200053720A (ko) * 2018-11-08 2020-05-19 삼성디스플레이 주식회사 표시장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557499B1 (ko) * 2002-12-31 2006-03-07 엘지.필립스 엘시디 주식회사 패턴형성방법 및 이를 이용한 액정표시소자와 그 제조방법
KR20060108945A (ko) * 2005-04-13 2006-10-18 삼성에스디아이 주식회사 박막 트랜지스터의 제조방법 및 이에 의해 제조된 박막트랜지스터
KR20060108943A (ko) * 2005-04-13 2006-10-18 삼성에스디아이 주식회사 식각 방법 및 이를 이용한 박막 트랜지스터의 제조방법
KR20080062647A (ko) * 2006-12-29 2008-07-03 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 그의 제조방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100934810B1 (ko) * 2002-12-18 2009-12-31 엘지디스플레이 주식회사 액정표시소자 및 그 제조방법
KR20080075669A (ko) 2007-02-13 2008-08-19 오의진 문자입력장치
KR20080075640A (ko) 2007-02-13 2008-08-19 엘지전자 주식회사 네 방향 프로젝터
KR101203836B1 (ko) 2007-02-13 2012-11-23 에스케이플래닛 주식회사 도로상황 실시간 업데이트를 통한 텔레메틱스 서비스시스템 및 방법
WO2009139104A1 (ja) * 2008-05-13 2009-11-19 シャープ株式会社 液晶表示装置、及び液晶表示装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557499B1 (ko) * 2002-12-31 2006-03-07 엘지.필립스 엘시디 주식회사 패턴형성방법 및 이를 이용한 액정표시소자와 그 제조방법
KR20060108945A (ko) * 2005-04-13 2006-10-18 삼성에스디아이 주식회사 박막 트랜지스터의 제조방법 및 이에 의해 제조된 박막트랜지스터
KR20060108943A (ko) * 2005-04-13 2006-10-18 삼성에스디아이 주식회사 식각 방법 및 이를 이용한 박막 트랜지스터의 제조방법
KR20080062647A (ko) * 2006-12-29 2008-07-03 엘지디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 그의 제조방법

Also Published As

Publication number Publication date
CN102177462A (zh) 2011-09-07
TWI484563B (zh) 2015-05-11
DE112009001874T5 (de) 2011-06-16
US20110136303A1 (en) 2011-06-09
US8278127B2 (en) 2012-10-02
TW201025458A (en) 2010-07-01
WO2010013984A3 (ko) 2010-06-10

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