WO2010010602A1

WO2010010602A1 - Plasma display panel

Info

Publication number: WO2010010602A1
Application number: PCT/JP2008/001991
Authority: WO
Inventors: 佐々木孝; 高木彰浩
Original assignee: 株式会社日立製作所
Priority date: 2008-07-25
Filing date: 2008-07-25
Publication date: 2010-01-28

Abstract

A plasma display panel comprises a first substrate and a second substrate opposed to each other via a discharge space. A plurality of first electrodes and second electrodes extending in a first direction and a dielectric layer covering the first and second electrodes are provided on the first substrate. A plurality of first division walls extending in a second direction intersecting with the first direction are provided on the second substrate. An address electrode extending in the second direction is provided on the dielectric layer for each first region formed between the first division walls adjacent to each other. For example, the address electrodes arranged along the first direction are drawn out from the first region to one side of the second direction and the other side thereof alternately. Further, a protection layer exposed to the discharge space of a cell is provided on the dielectric layer in such a manner that the layer covers the surface of the dielectric layer and the address electrode. As a result, unintended discharge between the address electrodes can be prevented and the destruction of a circuit can be prevented.

Description

Plasma display panel

The present invention relates to a plasma display panel used for a display device.

A plasma display panel (PDP) is formed by bonding two glass substrates (a front glass substrate and a back glass substrate) to each other, and generates a discharge in a space (discharge space) formed between the glass substrates. To display the image. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

For example, a three-electrode PDP displays an image by generating a sustain discharge between the X electrode and the Y electrode. A cell that generates a sustain discharge (a cell to be lit) is selected by, for example, selectively generating an address discharge between the Y electrode and the address electrode.

In recent years, a PDP in which three electrodes, that is, an X electrode, a Y electrode, and an address electrode are arranged on a front glass substrate has been proposed (see, for example, Patent Document 1). In this type of PDP, partition walls that partition the discharge space are provided on the back glass substrate along the address electrodes. Further, an exhaust path for enclosing the discharge gas in the discharge space is provided at the edge of the back glass substrate. In addition, the partition is not provided in the edge part in which the exhaust path is provided.
JP-A-2005-116508

In recent years, the number of pixels per screen has increased due to high definition of the PDP, and the cell area of each PDP tends to become smaller. That is, the distance between the address electrodes adjacent to each other is reduced. In this case, there is a possibility that unintentional discharge (erroneous discharge) may occur between the address electrodes adjacent to each other in the vicinity of the exhaust path where no partition wall is provided. For example, when an erroneous discharge occurs between an address electrode of a cell that generates an address discharge and an address electrode adjacent to the address electrode, a current flows through the address electrode where the erroneous discharge has occurred. In this case, for example, an unexpected current flows through a circuit that is turned off (a circuit connected to an address electrode of a cell that does not generate an address discharge), and there is a possibility that parts of the circuit (such as a transistor) are damaged. That is, the circuit may be damaged due to erroneous discharge between the address electrodes.

An object of the present invention is to prevent erroneous discharge between address electrodes and prevent circuit breakage in a PDP having three electrodes on a front glass substrate.

The plasma display panel has a first substrate and a second substrate that face each other through a discharge space. On the first substrate, there are provided a plurality of first and second electrodes that extend in the first direction and are spaced from each other, and a dielectric layer that covers the first and second electrodes. Yes. On the second substrate, a plurality of first barrier ribs extending in the second direction intersecting the first direction and arranged along the first direction are provided. An address electrode extending in the second direction is provided on the dielectric layer for each first region formed between the first barrier ribs adjacent to each other. For example, the address electrodes arranged along the first direction are alternately drawn from the first region to one side and the other side in the second direction. Further, a protective layer is provided on the dielectric layer, covering the surface of the dielectric layer and the address electrode, and being exposed to the discharge space of the cell.

In the present invention, in a PDP having three electrodes on the front glass substrate, erroneous discharge between address electrodes can be prevented, and circuit damage can be prevented.

It is a figure which shows the principal part of PDP in one Embodiment. It is a figure which shows the outline | summary of PDP shown in FIG. It is a figure which shows an example of the plasma display apparatus comprised using PDP shown in FIG. It is a figure which shows the outline | summary of the circuit part shown in FIG. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the principal part of PDP in another embodiment. It is a figure which shows the outline | summary of PDP shown in FIG. It is a figure which shows the outline | summary of PDP in another embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a main part of a plasma display panel (hereinafter also referred to as PDP) in an embodiment of the present invention. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. The PDP 10 includes a front substrate portion 12 that forms an image display surface, and a rear substrate portion 14 that faces the front substrate portion 12. A discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, a concave portion of the rear substrate portion 14).

The front substrate portion 12 is provided to extend in the first direction D1 on the surface (lower side in the drawing) of the glass substrate FS (first substrate) facing the glass substrate RS (second substrate). A plurality of X bus electrodes Xb and Y bus electrodes Yb are arranged at intervals. For example, the X bus electrode Xb and the Y bus electrode Yb are opaque electrodes formed of a metal material or the like. An X transparent electrode Xt extending in the second direction D2 from the X bus electrode Xb to the Y bus electrode Yb is connected to the X bus electrode Xb. A Y transparent electrode Yt extending in the second direction D2 from the Y bus electrode Yb to the X bus electrode Xb is connected to the Y bus electrode Yb.

In the example shown in the figure, the X transparent electrode Xt and the Y transparent electrode Yt face each other along an oblique direction with respect to the first direction D1 (or the second direction D2). The transparent electrodes Xt and Yt may be provided so as to face each other along the first direction D1, or may be provided so as to face each other along the second direction D2. For example, the X transparent electrode Xt and the Y transparent electrode Yt are transparent electrodes that transmit light formed of an ITO film or the like. Note that an electrode integral with the bus electrodes Xb and Yb may be formed in place of the transparent electrodes Xt and Yt, using the same material (metal material or the like) as the bus electrodes Xb and Yb. Further, the transparent electrodes Xt and Yt may be disposed on the entire surface between the bus electrodes Xb and Yb to which the transparent electrodes Xt and Yt are connected and the glass substrate FS.

X electrode XE (first electrode, sustain electrode) is composed of X bus electrode Xb and X transparent electrode Xt, and Y electrode YE (second electrode, scan electrode) is composed of Y bus electrode Yb and Y transparent electrode Yt. And is paired with the X electrode XE. That is, a plurality of X electrodes XE and Y electrodes YE extending in the first direction D1 and spaced from each other are provided on the glass substrate FS (lower side in the figure). Then, a discharge (sustain discharge) is repeatedly generated between the X electrode XE and the Y electrode YE paired with each other (more specifically, between the X transparent electrode Xt and the Y transparent electrode Yt).

The electrodes Xb, Xt, Yb, Yt are covered with the dielectric layer DL. For example, the dielectric layer DL is an insulating film such as a silicon dioxide film formed by a CVD method. A plurality of address electrodes AE extending in a direction orthogonal to the bus electrodes Xb and Yb (second direction D2) are provided on the dielectric layer DL (lower side in the figure). Thus, the PDP of this embodiment has three electrodes (electrodes XE, YE, AE) on the front substrate portion 12.

The surfaces of the address electrode AE and the dielectric layer DL are covered with a protective layer PL. The protective layer PL is exposed to the discharge space DS, and protects the address electrode AE and the dielectric layer DL from ion collision due to discharge. That is, in this embodiment, the second dielectric layer covering the address electrode AE is not formed, and the protective layer PL is formed directly on the address electrode AE and the first dielectric layer DL. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collisions in order to easily generate discharge.

The back substrate unit 14 has a glass base RS that faces the glass base FS through the discharge space DS. On the glass substrate RS (on the surface of the glass substrate RS facing the glass substrate FS), a first partition (barrier rib) BR1 extending in the second direction D2 and a second extending in the first direction D1. A grid-like partition wall constituted by the partition wall BR2 is formed. In other words, the first partition BR1 is provided on the glass substrate RS so as to extend in the second direction D2, and is disposed along the first direction D1. Further, the second partition wall BR2 is provided to extend in the first direction D1 on the glass substrate RS, and is disposed along the second direction D2.

For example, the barrier ribs BR1 and BR2 are formed integrally with the glass substrate RS by cutting the glass substrate RS by a sandblast method or the like. The barrier ribs BR1 and BR2 may be formed by applying a paste-like barrier rib material on the glass substrate RS, followed by drying, sandblasting, and baking processes, or may be formed by lamination by printing. The partition walls BR1 and BR2 constitute cell side walls. Further, red (R), green (G), and blue (B) are visible on the side surfaces of the barrier ribs BR1 and BR2 and on the glass substrate RS in a portion surrounded by the barrier ribs BR1 and BR2. Phosphors PHr, PHg, and PHb that generate light are respectively applied.

One pixel of the PDP 10 is composed of three cells that generate red, green, and blue light. Here, one cell (one color pixel) is formed in a region surrounded by partition walls BR1 and BR2, for example, as shown in FIG. As described above, the PDP 10 is configured by arranging cells in a matrix to display an image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes Xb and Yb.

In the PDP 10, the front substrate portion 12 and the rear substrate portion 14 are bonded together so that the protective layer PL and the partition wall BR (for example, the first partition wall BR1) are in contact with each other, and a discharge gas such as Ne or Xe is enclosed in the discharge space DS. Consists of.

FIG. 2 shows an outline of the PDP 10 shown in FIG. FIG. 2 shows the state of the PDP 10 as viewed from the image display surface side (upper side in FIG. 1). The shaded portion in the figure shows the outer peripheral portion of the glass substrate RS and the partition walls BR1 and BR2. The meanings of arrows D1 and D2 in the figure are the same as those in FIG. Moreover, the code | symbol D21 in a figure has shown the one side of the 2nd direction D2, and the code | symbol D22 has shown the other side of the 2nd direction D2. The cell CLr indicates a cell that generates red visible light, the cell CLg indicates a cell that generates green visible light, and the cell CLb indicates a cell that generates blue visible light. Hereinafter, the cells CLr, CLg, and CLb are also referred to as cells CL, for example, when they are not distinguished for each color of visible light. In the example of the figure, a PDP having the number of pixels of 2 pixels × 2 pixels (6 cells × 2 cells) is shown for easy viewing of the drawing. Actually, the number of pixels of the PDP is 1920 pixels × 1080 pixels, 1280 pixels × 1080 pixels, 1024 pixels × 1080 pixels, 1366 pixels × 768 pixels, and the like.

As described above with reference to FIG. 1, the PDP 10 is configured by adhering the front substrate portion 12 and the rear substrate portion 14 and enclosing a discharge gas such as Ne or Xe in the discharge space DS. The sealing material SL for bonding the front substrate part 12 and the rear substrate part 14 is arranged in a frame shape outside (outer peripheral part) outside the region where the barrier ribs BR1 and BR2 are formed. The exhaust space ES formed between the sealing material SL and the partition walls BR1 and BR2 is provided with an exhaust hole EH that penetrates to the outer surface of the glass substrate RS. Thereby, the discharge space DS of the assembled PDP 10 (the concave portion of the back substrate portion 14 shown in FIG. 1 described above) can be set in a vacuum state, and the discharge gas can be enclosed in the discharge space DS.

For example, both end portions of the partition wall BR1 protrude outward from the outermost partition wall BR2 (the uppermost partition wall BR2 and the lowermost partition wall BR2 in the figure). That is, both end portions of the partition wall BR1 are respectively positioned outside the partition wall BR2 disposed on the outermost side. Further, for example, the width W20 along the second direction D2 of the partition wall BR2 disposed on the outermost side is smaller than the width W10 along the second direction D2 of the partition wall BR2 disposed between the cells CL. Thereby, in this embodiment, the ratio of the area of the cell CL to the area of the PDP 10 can be increased. Note that the width W20 along the second direction D2 of the partition wall BR2 arranged on the outermost side is the same as the width W10 along the second direction D2 of the partition wall BR2 arranged between the cells CL, as shown in FIG. But you can.

Here, for example, the partition wall BR2 (second partition wall BR2 from the top in the figure) disposed between the cells CL is opposed to both the bus electrodes Xb and Yb, and the partition wall BR2 disposed on the outermost side is the bus electrode. It faces one of Xb and Yb. Note that the partition wall BR2 disposed between the cells CL may be provided to face only one of the bus electrodes Xb and Yb or may be provided between the bus electrodes Xb and Yb. In this case, the outermost partition wall BR2 is provided at a position where the distances between the partition walls BR2 are the same.

As described above, the cell CL is formed in a region surrounded by the barrier ribs BR1 and BR2 (for example, a region surrounded by a fine broken line in the drawing), and the pixel PX is configured by the cells CLr, CLg, and CLb. The transparent electrode Yt is disposed adjacent to the address electrode AE in each cell CL, and the transparent electrode Xt is disposed adjacent to the transparent electrode Yt in each cell CL. Thus, by applying a voltage between the address electrode AE and the transparent electrode Yt, an address discharge can be generated in the cell CL of interest. Further, by applying a voltage between the transparent electrode Xt and the transparent electrode Yt, a sustain discharge can be generated in the cell CL selected by the address discharge.

For example, when the address discharge is generated only in the second upper cell CL from the left in the figure (the cell CLg surrounded by the fine broken line in the figure), a scan pulse is applied to the Y electrode YE on the upper side in the figure, To the second address electrode AE. In this case, for example, the circuit for applying the address pulse to the other address electrodes AE (the address electrodes AE excluding the second address electrode AE from the left in the drawing) is turned off.

Note that the address electrode AE is arranged for each first area AR10 (for example, an area surrounded by a thick broken line in the drawing) including the cells CL arranged along the second direction D2. For example, when viewed from the image display surface side (the upper side in FIG. 1), the first area AR10 is an area sandwiched between the adjacent partitions BR1. That is, the address electrode AE is provided to extend in the second direction D2 for each first region AR10 formed between the adjacent barrier ribs BR1.

Further, the address electrodes AE arranged along the first direction D1 are alternately arranged from the first area AR10 on one side (for example, D21 side in the figure) and the other side (for example, D22 side in the figure) from the second direction D2. Pulled out. Thereby, for example, in this embodiment, the distance S20 between the address electrodes AE outside the first area AR10 can be made twice the distance S10 between the adjacent address electrodes AE. That is, in this embodiment, the distance S20 between the address electrodes AE in the portion exposed to the exhaust space ES through the protective layer PL can be increased. Note that the end portion EG10 in the first region AR10 of the address electrode AE (the end portion EG10 not drawn out from the first region AR10) is located outside the partition wall BR2 arranged on the outermost side.

In this embodiment, the end portion EG10 of the address electrode AE located in the first region AR10, and the portion of the address electrode AE adjacent to the end portion EG10 located in the exhaust space ES (outside the first region AR10) The distance S30 can be larger than the distance S10. That is, in this embodiment, the distances S20 and S30 where the partition walls BR1 and BR2 are not provided between the address electrodes AE can be made larger than the distance S10 between the adjacent address electrodes AE.

Thereby, in this embodiment, it is possible to prevent unintended discharge (erroneous discharge) from occurring between the address electrodes AE. Note that, in a place where the distance between the address electrodes AE is small (for example, a place where the distance between the address electrodes AE is the distance S10), since the partition wall BR1 is provided between the address electrodes AE, erroneous discharge occurs between the address electrodes AE. Does not occur. For example, in this embodiment, when the address discharge is generated only in the second upper cell CL from the left in the figure, the second address electrode AE from the left in the figure and another address electrode AE (for example, in the figure) It is possible to prevent erroneous discharge from occurring with the first, third, or fourth address electrode AE) from the left.

In this embodiment, since an erroneous discharge between the address electrodes AE is prevented, it is possible to prevent an unexpected current from flowing through the address electrode AE of a cell CL that does not generate an address discharge (hereinafter also referred to as an off-cell CL). Therefore, in this embodiment, it is possible to prevent an unexpected current from flowing through a circuit that is turned off (for example, a circuit connected to the address electrode AE of the off cell CL), and components of the circuit (such as transistors) are damaged. Can be prevented. Further, in this embodiment, since erroneous discharge between the address electrodes AE is prevented, unnecessary light can be prevented from being generated, and the quality of an image displayed on the PDP 10 can be improved.

Here, in order to prevent erroneous discharge between the address electrodes AE, a configuration in which a dielectric layer different from the first dielectric layer DL is provided between the address electrodes AE and the protective layer PL is the present invention. It was thought of in the process. In this configuration, a process for providing a dielectric layer different from the first dielectric layer DL is required, and the manufacturing cost increases. On the other hand, in this embodiment, as described above, a dielectric layer different from the first dielectric layer DL is not provided between the address electrodes AE and the protective layer PL, and the address electrodes AE are not provided. Incorrect discharge can be prevented. Therefore, in this embodiment, the manufacturing cost can be reduced.

FIG. 3 shows an example of a plasma display device configured using the PDP 10 shown in FIG. The plasma display device (hereinafter also referred to as a PDP device) includes a PDP 10, an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, and a front housing 30 disposed on the image display surface 16 side of the PDP 10. The rear housing 40 and the base chassis 50 disposed on the back surface 18 side of the PDP 10, the circuit unit 60 for driving the PDP 10 attached to the rear housing 40 side of the base chassis 50, and the PDP 10 are attached to the base chassis 50. A double-sided adhesive sheet 70 for attaching is provided. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

FIG. 4 shows an outline of the circuit unit 60 shown in FIG. The circuit unit 60 includes a control unit CNT, an X driver XDRV, a Y driver YDRV, an address driver ADRV (ADRV1, ADRV2), and a power supply unit PWR. The power supply unit PWR generates power supply voltages −Vsc, Vs / 2, −Vs / 2, Vsa and the like to be supplied to the drivers YDRV, XDRV, and ADRV.

The control unit CNT controls the operation of the drivers XDRV, YDRV, and ADRV. For example, the control unit CNT selects a subfield to be used based on the image data R0-R7, G0-G7, B0-B7, and outputs control signals YCNT, XCNT, and ACNT to the drivers YDRV, XDRV, and ADRV. Here, the subfield is a field obtained by dividing one field for displaying one screen of the PDP 10, and the number of sustain discharges is set for each subfield. Then, by selecting a subfield to be used for each cell constituting the pixel, a multi-gradation image is displayed. For example, the subfield includes an address period for selecting a cell to be lit (a cell for generating a sustain discharge), a sustain period for generating a sustain discharge in the cell selected in the address period, and the like.

The drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10. For example, the X driver XDRV alternately applies voltages −Vs / 2 and Vs / 2 (negative and positive sustain pulses) to the X electrode XE during the sustain period. The Y driver YDRV alternately applies voltages Vs / 2 and −Vs / 2 (positive and negative sustain pulses) having different polarities from the voltage applied to the X electrode XE to the Y electrode YE during the sustain period, In the address period, the voltage −Vsc (scan pulse) is selectively applied to the Y electrode YE. The address driver ADRV selectively applies a voltage Vsa (address pulse) to the address electrode AE during the address period.

For example, the address driver ADRV1 selectively applies the voltage Vsa (address pulse) to the address electrode AE drawn to one side (for example, D21 side in FIG. 2) in the second direction D2 shown in FIG. ) Is applied. The address driver ADRV2 selectively applies the voltage Vsa (address pulse) to the address electrode AE drawn to the other side (for example, D22 side in FIG. 2) in the second direction D2 shown in FIG. 2 during the address period. Apply. As described above with reference to FIG. 2, in this embodiment, erroneous discharge between the address electrodes AE is prevented, so that the circuits in the address drivers ADRV1 and ADRV2 can be prevented from being damaged.

In the cell selected by the scan pulse and the address pulse, a discharge (address discharge) is temporarily generated between the Y electrode YE and the address electrode AE. Thereby, in the address period, a cell to be lit in the sustain period is selected. In the sustain period, the sustain pulses having different polarities are repeatedly applied to the X electrode XE and the Y electrode YE, so that the discharge of the cells lit in the sustain period (sustain discharge) is repeatedly performed.

As described above, in this embodiment, the address electrodes AE arranged along the first direction D1 are alternately arranged on the opposite sides (D21 side and D22 side in FIG. 2) from the first area AR10 along the second direction D2. Pulled out. Thereby, in this embodiment, erroneous discharge between the address electrodes AE can be prevented, and damage to the circuit can be prevented.

FIG. 5 shows an outline of the PDP 10 in another embodiment. In this embodiment, the third partition BR3 is added to the configuration shown in FIG. 2 described above. Other configurations are the same as those of the embodiment described with reference to FIGS. Is the same. The same elements as those described in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the meanings of arrows D1 and D2 in the figure are the same as those in FIG.

FIG. 5 shows the state of the PDP 10 viewed from the image display surface side (upper side in FIG. 1). The shaded portion in the figure shows the outer peripheral portion of the glass substrate RS and the partition walls BR1 and BR2. In the example of the figure, a PDP having the number of pixels of 2 pixels × 2 pixels (6 cells × 2 cells) is shown for easy viewing of the drawing. Actually, the number of pixels of the PDP is 1920 pixels × 1080 pixels, 1280 pixels × 1080 pixels, 1024 pixels × 1080 pixels, 1366 pixels × 768 pixels, and the like.

The third partition wall BR3 extends in the first direction D1 on the glass substrate RS, and is disposed on the outermost side (the uppermost partition wall BR2 and the lowermost partition wall BR2 in the figure). They are arranged on the outer sides. The partition wall BR1 extends from one partition wall BR3 (for example, the upper partition wall BR3 in the drawing) to the other partition wall BR3 (for example, the lower partition wall BR3 in the drawing). In the illustrated example, both end portions of the partition wall BR1 are located outside the partition wall BR3. That is, both end portions of the partition wall BR1 protrude outward from the partition wall BR3. Note that the end portion of the partition wall BR1 may not protrude outward from the partition wall BR3. Here, the exhaust space ES is formed, for example, between the seal material SL and the partition walls BR1 and BR3.

Further, the end EG10 (the end EG10 not drawn from the first area AR10) in the first area AR10 of the address electrode AE is outside the partition BR2 arranged on the outermost side and from the partition BR3. Located inside. That is, at least one of the barrier ribs BR1 and BR3 is provided between the end portion EG10 located in the first region AR10 of the address electrode AE and the address electrode AE adjacent to the end portion EG10. As a result, in this embodiment, the erroneous discharge occurs between the end portion EG10 located in the first region AR10 of the address electrode AE and the address electrode AE adjacent to the end portion EG10, as described above with reference to FIG. -It can be reliably prevented compared to the embodiment described in FIG.

As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 4 can be obtained. Further, in this embodiment, the end portion EG10 in the first region AR10 of the address electrode AE is located in a region surrounded by the barrier ribs BR2 and BR3 and the barrier rib BR1 adjacent to each other. As a result, in this embodiment, erroneous discharge between the adjacent address electrodes AE can be surely prevented as compared with the embodiment described with reference to FIGS.

FIG. 6 shows a main part of the PDP 10 in another embodiment. In this embodiment, the second partition BR2 is omitted from the configuration shown in FIG. 1 described above. Other configurations are the same as those of the embodiment described with reference to FIGS. The same elements as those described in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the meanings of arrows D1 and D2 in the figure are the same as those in FIG.

On the glass substrate RS, a stripe-shaped partition wall (partition wall BR1) in which the second partition wall BR2 is omitted from the configuration illustrated in FIG. 2 described above is provided. That is, the first partition wall BR1 extending in the second direction D2 is provided on the surface of the glass substrate RS that faces the glass substrate FS. For example, the partition wall BR1 is formed integrally with the glass substrate RS by cutting the glass substrate RS by a sandblast method or the like. The partition wall BR1 may be formed by applying a paste-like partition wall material on the glass substrate RS, followed by drying, sandblasting, and baking processes, or may be formed by lamination by printing.

A phosphor that generates visible light of red (R), green (G), and blue (B) when excited by ultraviolet rays on the side surface of the barrier rib BR1 and the glass substrate RS between the barrier ribs BR1 adjacent to each other. PHr, PHg, and PHb are respectively applied. In this case, for example, as shown in FIG. 7 described later, the cell CL is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR1.

FIG. 7 shows an outline of the PDP 10 shown in FIG. FIG. 7 shows the state of the PDP 10 viewed from the image display surface side (upper side in FIG. 6). The shaded portion in the figure shows the outer peripheral portion of the glass substrate RS and the partition wall BR1. In the example of the figure, a PDP having the number of pixels of 2 pixels × 2 pixels (6 cells × 2 cells) is shown for easy viewing of the drawing. Actually, the number of pixels of the PDP is 1920 pixels × 1080 pixels, 1280 pixels × 1080 pixels, 1024 pixels × 1080 pixels, 1366 pixels × 768 pixels, and the like.

As described with reference to FIG. 6, the cell CL is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR1 (for example, a region surrounded by a fine broken line in the figure). The address electrodes AE arranged along the first direction D1 are alternately drawn from the first area AR10 to the opposite sides (D21 side and D22 side in the drawing) along the second direction D2. That is, the address electrodes AE arranged along the first direction D1 are alternately arranged from the first area AR10 to one side (for example, D21 side in the figure) and the other side (for example, D22 side in the figure) from the second direction D2. Pulled out.

For example, among the address electrodes AE adjacent to each other, one address electrode AE is drawn from the first area AR10 to one side in the second direction (for example, D21 side in the drawing) and the other side in the second direction ( For example, the end portion EG10 on the D22 side in the drawing is disposed so as to be located in the first region AR10. The other address electrode AE is drawn from the first area AR10 to the other side (for example, the D22 side in the figure), and the end EG10 on one side (for example, the D21 side in the figure) is within the first area AR10. It arrange | positions so that it may be located in. As a result, in this embodiment, the distances S20 and S30 where the partition walls BR1 and BR2 are not provided between the address electrodes AE can be made larger than the distance S10 between the adjacent address electrodes AE. Note that the end portion EG10 in the first area AR10 of the address electrode AE is positioned outside the bus electrodes Xb and Yb arranged on the outermost side.

As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 4 can be obtained. Further, in this embodiment, since the second partition BR2 is omitted from the embodiment described with reference to FIGS. 1 to 4 described above, the partition BR1 can be easily formed, and the manufacturing cost can be reduced.

FIG. 8 shows an outline of the PDP 10 in another embodiment. In this embodiment, the width of the partition wall BR2 arranged on the outermost side and the arrangement of the end portion EG10 of the address electrode AE are different from the configuration shown in FIG. Other configurations are the same as those of the embodiment described with reference to FIGS. Is the same. The same elements as those described in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the meanings of arrows D1 and D2 in the figure are the same as those in FIG.

FIG. 8 shows the state of the PDP 10 viewed from the image display surface side (upper side in FIG. 1). The shaded portion in the figure shows the outer peripheral portion of the glass substrate RS and the partition walls BR1 and BR2. In the example of the figure, a PDP having the number of pixels of 2 pixels × 2 pixels (6 cells × 2 cells) is shown for easy viewing of the drawing. Actually, the number of pixels of the PDP is 1920 pixels × 1080 pixels, 1280 pixels × 1080 pixels, 1024 pixels × 1080 pixels, 1366 pixels × 768 pixels, and the like.

The address electrodes AE arranged along the first direction D1 are alternately drawn from the first area AR10 to the opposite sides (D21 side and D22 side in the drawing) along the second direction D2. When viewed from the image display surface side, the end portion EG10 in the first region AR10 of the address electrode AE (the end portion EG10 not drawn out from the first region AR10) is the outermost partition BR2. Located on the top. That is, in this embodiment, it is possible to prevent the end portion EG10 in the first region AR10 of the address electrode AE from being exposed to the exhaust space ES via the protective layer PL.

As a result, in this embodiment, the erroneous discharge occurs between the end portion EG10 located in the first region AR10 of the address electrode AE and the address electrode AE adjacent to the end portion EG10, as described above with reference to FIG. -It can be reliably prevented compared to the embodiment described in FIG. In this embodiment, the partition wall BR1 only needs to extend from one partition wall BR2 of the partition wall BR2 disposed on the outermost side to the other partition wall BR2, and the end portion is more than the partition wall BR2 disposed on the outermost side. It does not have to protrude outward.

For example, the width W10 of the partition wall BR2 along the second direction D2 is disposed between the outermost partition wall BR2 (the uppermost partition wall BR2 and the lowermost partition wall BR2 in the drawing) and the cell CL. The same applies to the partition wall BR2 (second partition wall BR2 from the top in the drawing). That is, in this embodiment, the area of the portion of the partition wall BR2 arranged on the outermost side that does not face the bus electrodes Xb and Yb can be made larger than in the embodiment described with reference to FIGS. Thereby, in this embodiment, the end portion EG10 in the first region AR10 of the address electrode AE can be easily arranged on the partition wall BR2. Note that the width along the second direction D2 of the partition wall BR2 disposed on the outermost side is smaller than the width W10 along the second direction D2 of the partition wall BR2 disposed between the cells CL as described above with reference to FIG. Also good.

As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 4 can be obtained. Further, in this embodiment, since the end portion EG10 in the first region AR10 of the address electrode AE is located on the barrier rib BR2, the erroneous discharge between the adjacent address electrodes AE is described with reference to FIGS. Compared to the described embodiment, it can be reliably prevented.

In the above-described embodiment, an example in which one pixel includes three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), Cells that generate colors other than blue (B) may be included. That is, the pixel column area PA may be configured by four or more cell column areas CA that respectively generate light of different colors. Also in this case, the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

In the embodiment described with reference to FIG. 5 described above, the example in which the end portion EG10 in the first region AR10 of the address electrode AE is located in the region surrounded by the partition wall BR2 and the partition wall BR3 and the partition wall BR1 adjacent to each other is described. . The present invention is not limited to such an embodiment. For example, the end portion EG10 in the first area AR10 of the address electrode AE may be located on the partition wall BR3 when viewed from the image display surface side. Also in this case, the same effect as the above-described embodiment can be obtained.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modification are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

The present invention can be applied to a plasma display panel used in a display device.

Claims

A first substrate and a second substrate facing each other through a discharge space;
A plurality of first and second electrodes provided on the first substrate and extending in the first direction and spaced apart from each other;
A plurality of first barrier ribs provided on the second substrate, extending in a second direction intersecting the first direction, and disposed along the first direction;
A dielectric layer provided on the first substrate and covering the first and second electrodes;
Address electrodes provided extending in the second direction on the dielectric layer for each first region formed between the first barrier ribs adjacent to each other;
A protective layer provided on the dielectric layer, covering the surface of the dielectric layer and the address electrode, and exposed to a discharge space of the cell;
The plasma display panel, wherein the address electrodes arranged along the first direction are alternately drawn from the first region to one side and the other side of the second direction.
The plasma display panel according to claim 1, wherein
A plurality of second partition walls provided in the first direction and extending along the second direction on the second substrate;
The plasma display panel according to claim 1, wherein both ends of the first barrier rib are positioned outside the second barrier rib disposed on the outermost side.
The plasma display panel according to claim 2, wherein
The plasma display panel according to claim 1, wherein an end portion of the address electrode in the first region is located outside a second partition wall disposed on the outermost side.
The plasma display panel according to claim 3, wherein
A third partition wall provided on the second substrate so as to extend in the first direction and disposed outside the second partition wall disposed on the outermost side;
The first partition wall is provided to extend from at least one third partition wall to the other third partition wall,
The plasma display panel according to claim 1, wherein an end portion of the address electrode in the first region is located outside the second partition disposed outside and outside the third partition.
The plasma display panel according to claim 1, wherein
A plurality of second partition walls provided in the first direction and extending along the second direction on the second substrate;
The first partition is provided to extend from one second partition to the other second partition of at least the second partition disposed on the outermost side,
The plasma display panel according to claim 1, wherein an end portion of the address electrode in the first region is positioned on the outermost second partition.