WO2009098733A1

WO2009098733A1 - Plasma display panel

Info

Publication number: WO2009098733A1
Application number: PCT/JP2008/000164
Authority: WO
Inventors: Takashi Sasaki; Tetsuya Sakamoto; Akihiro Takagi
Original assignee: Hitachi, Ltd.
Priority date: 2008-02-06
Filing date: 2008-02-06
Publication date: 2009-08-13

Abstract

A plasma display panel comprises a first substrate and a second substrate that face each other. The first substrate includes bus electrode pairs each constituted by a first and a second bus electrode that extend in a first direction with a discharge gap between them, and the second substrate includes barrier ribs extending in a second direction crossing the first direction. The first and the second bus electrode of each of the bus electrode pairs are provided with, in each display column area formed between the barrier ribs, a first and a second projecting electrode which respectively project along the second direction from the first and the second bus electrode to the side opposite to the area where the discharge gap is formed and adjoin the barrier ribs different from each other. The first or the second projecting electrodes that are provided on the bus electrodes pairs different from each other and are adjacent to each other in the display column area are disposed adjacent to each of one and the other of the barrier ribs forming the display column area. Consequently, image brightness can be increased.

Description

Plasma display panel

The present invention relates to a plasma display panel used for a display device.

A plasma display panel (PDP) is formed by bonding two glass substrates (a front glass substrate and a back glass substrate) to each other, generating a discharge in a space formed between the glass substrates, An image is displayed by emitting light. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

For example, a PDP having a three-electrode structure having X, Y electrodes and address electrodes displays an image by generating a sustain discharge with an electrode pair composed of X electrodes and Y electrodes. A cell that generates a sustain discharge (a cell to be lit) is selected by, for example, selectively generating an address discharge between the Y electrode and the address electrode.

In a general PDP, an electrode pair composed of an X electrode and a Y electrode is disposed on a front glass substrate at an interval, and is disposed between partition walls extending in the orthogonal direction of the X electrode and partition walls adjacent to each other. Address electrodes are disposed on the rear glass substrate. For example, the X electrode is composed of an X bus electrode and an X transparent electrode connected to the X bus electrode, and the Y electrode is composed of a Y bus electrode and a Y transparent electrode connected to the Y bus electrode. Generally, the X and Y transparent electrodes are disposed between the X and Y bus electrodes that are paired with each other (see, for example, Patent Document 1).
JP 2006-185903 A

In this type of PDP, when an electrode pair adjacent to each other generates a sustain discharge in one electrode pair, an erroneous discharge occurs in the X bus electrode of one electrode pair and the Y bus electrode of the other electrode pair. In order to prevent this, it is arranged at intervals. A region sandwiched between the electrode pairs adjacent to each other is a non-light emitting region. Therefore, when the interval between the electrode pairs adjacent to each other is large, the non-light-emitting region becomes large and the light-emitting region becomes small. For this reason, the brightness of the image decreases.

Further, in the PDP of Patent Document 1, a partition wall (lateral partition wall) extending along the X electrode is disposed between one electrode pair and the other electrode pair of electrode pairs adjacent to each other. That is, the back glass substrate is provided with a grid-like partition wall constituted by partition walls (vertical partition walls) extending in the orthogonal direction of the X electrode and partition walls (horizontal partition walls) extending along the X electrode. In this case, the light emitting area becomes smaller by the area where the horizontal barrier rib is formed (non-light emitting area), and the luminance of the image is lowered.

An object of the present invention is to reduce the non-light emitting area and increase the luminance of the image. In particular, an object of the present invention is to increase the luminance of an image while preventing erroneous discharge.

The plasma display panel has a first substrate and a second substrate facing each other. The first substrate has a plurality of bus electrode pairs configured by first and second bus electrodes extending in the first direction across the discharge gap, and the second substrate intersects with the first direction. It has a plurality of partition walls extending in the direction. The first and second bus electrodes are provided on the first and second bus electrodes of each bus electrode pair for each display column region formed between the partition walls. For example, the first and second protruding electrodes provided in each bus electrode pair respectively protrude along the second direction on the opposite side of the region where the discharge gap is formed from the first and second bus electrodes, and are different from each other. It is arranged adjacent to each partition. Note that the first or second projecting electrodes provided in different bus electrode pairs and adjacent to each other in the display column region are respectively disposed adjacent to one and the other of the partition walls forming the display column region.

In the present invention, the non-light emitting area can be reduced and the brightness of the image can be increased. In particular, according to the present invention, the luminance of an image can be increased while preventing erroneous discharge.

It is a figure which shows the principal part of PDP in one Embodiment. It is a figure which shows the outline | summary of PDP shown in FIG. It is a figure which shows an example of the plasma display apparatus comprised using PDP shown in FIG. It is a figure which shows the outline | summary of the circuit part shown in FIG. It is a figure which shows an example of the discharge operation | movement of the subfield for displaying an image on PDP shown in FIG. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the outline | summary of the circuit part for driving PDP shown in FIG. It is a figure which shows an example of the discharge operation | movement of the subfield for displaying an image on PDP shown in FIG. It is a figure which shows the outline | summary of PDP in another embodiment. It is a figure which shows the principal part of PDP in another embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a main part of a plasma display panel (hereinafter also referred to as PDP) in an embodiment of the present invention. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. The PDP 10 includes a front substrate portion 12 that forms an image display surface, and a rear substrate portion 14 that faces the front substrate portion 12. A discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, a concave portion of the rear substrate portion 14).

The front substrate portion 12 includes a plurality of bus electrode pairs BEp arranged at intervals on a surface (lower side in the drawing) of the glass substrate FS (first substrate) facing the glass substrate RS (second substrate). have. Each bus electrode pair BEp is configured by an X bus electrode Xb (first bus electrode) and a Y bus electrode Yb (second bus electrode) extending in the first direction D1 across the discharge gap DG.

The X-projection electrode Xp (first projection electrode) extending in the second direction D2 is connected to the X-bus electrode Xb on the opposite side of the region where the discharge gap DG is formed from the X-bus electrode Xb. Further, a Y-projection electrode Yp (second projection electrode) extending in the second direction D2 is connected to the Y bus electrode Yb on the side opposite to the region where the discharge gap DG is formed from the Y bus electrode Yb. For example, the X electrode XE (sustain electrode) is composed of the X bus electrode Xb and the X projection electrode Xp, and the Y electrode YE (scanning electrode) is composed of the Y bus electrode Yb and the Y projection electrode Yp. Then, a discharge (sustain discharge) is repeatedly generated between the X electrode XE and the Y electrode YE that are paired with each other.

Here, the X bus electrode Xb and the Y bus electrode Yb are opaque electrodes formed of a metal material or the like, and the X protruding electrode Xp and the Y protruding electrode Yp transmit visible light formed of an ITO film or the like. It is a transparent electrode. The protruding electrodes Xp and Yp may be disposed on the entire surface between the bus electrodes Xb and Yb to which the protruding electrodes Xp and Yp are connected and the glass substrate FS. The electrodes Xb, Xp, Yb, Yp are covered with the dielectric layer DL1, and the surface of the dielectric layer DL1 is covered with the protective layer PL. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collision in order to easily generate discharge.

The rear substrate portion 14 facing the front substrate portion 12 through the discharge space DS has a plurality of address electrodes AE extending on the glass base RS in the orthogonal direction (second direction D2) of the bus electrodes Xb and Yb. Is provided. For example, the address electrode AE is an opaque electrode made of a metal material or the like. The address electrode AE is covered with the dielectric layer DL2, and a plurality of partition walls (barrier ribs) BR extending in the second direction D2 are formed on the dielectric layer DL2. That is, the barrier ribs BR are arranged at intervals on the surface of the glass substrate RS that faces the glass substrate FS. For example, the barrier ribs BR are disposed between the address electrodes AE adjacent to each other.

The side wall of the cell is constituted by the partition wall BR. Further, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall BR and the glass substrate RS between the adjacent partition walls BR by being excited by ultraviolet rays. Phosphors PHr, PHg, and PHb are respectively applied.

One pixel of the PDP 10 is composed of three cells that generate red, green, and blue light. Here, as shown in FIG. 2 to be described later, one cell (one color pixel) is formed in a region including a pair of protruding electrodes Xp and Yp in a region sandwiched between a pair of adjacent barrier ribs BR. The As described above, the PDP 10 is configured by arranging cells in a matrix to display an image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes Xb and Yb.

The PDP 10 is configured by bonding the front substrate portion 12 and the rear substrate portion 14 so that the protective layer PL and the partition wall BR are in contact with each other, and enclosing a discharge gas such as Ne or Xe in the discharge space DS.

FIG. 2 shows an outline of the PDP 10 shown in FIG. 2 shows the state of the electrodes Xb, Xp, Yb, Yp, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1).

In the example of the figure, the bus electrode pairs BEp adjacent to each other are arranged such that the bus electrode Xb of one bus electrode pair BEp and the bus electrode Xb of the other bus electrode pair BEp are adjacent to each other. In other words, the bus electrode pairs BEp adjacent to each other are arranged such that the bus electrode Yb of one bus electrode pair BEp and the bus electrode Yb of the other bus electrode pair BEp are adjacent to each other.

As described above, the protruding electrodes Xp and Yp protrude along the second direction D2 from the bus electrodes Xb and Yb of each bus electrode pair BEp on the side opposite to the region where the discharge gap DG is formed. The protruding electrodes Xp and Yp that are paired with each other are provided on the bus electrodes Xb and Yb of each bus electrode pair BEp for each display column region RA formed between a pair of adjacent barrier ribs BR. Arranged adjacent to one and the other of the pair of partition walls BR forming the region RA. That is, the protruding electrodes Xp and Yp that make a pair are adjacent to different partition walls BR.

For example, by applying a voltage between the sustain electrode XE and the scan electrode YE, first, a discharge is generated between the bus electrodes Xb and Yb facing each other through the discharge gap DG, and this discharge is a pair of protruding electrodes Xp. , Spread to Yp. Then, a phosphor (for example, the phosphor PHr shown in FIG. 1 described above) that has received ultraviolet rays generated by discharge generates visible light (for example, red visible light). That is, in this embodiment, one cell C1 (one color pixel) includes, as described above, a region including the protruding electrodes Xp and Yp that are paired with each other in the display column region RA (a region surrounded by a broken line in the drawing). Formed.

In each display row region RA, the protruding electrode Xp (or Yp) of one cell C1 of the cells C1 adjacent to each other and the protruding electrode Xp (or Yp) of the other cell C1 secure a distance from each other in the first direction D1. In order to achieve this, each of the pair of partition walls BR forming the display row region RA is disposed adjacent to each other. That is, the protruding electrodes Xp or Yp that are provided on different bus electrode pairs BEp and are adjacent to each other in the display column region RA are disposed adjacent to one and the other of the pair of partition walls BR forming the display column region RA. ing.

For example, in the display row region RA, the protruding electrodes Xp and Yp are connected between the bus electrodes Xb and Yb where the shortest distance S1 between the adjacent protruding electrodes Xp and the shortest distance S1 between the protruding electrodes Yp form the discharge gap DG. It arrange | positions so that it may become larger than the distance S2. For example, the shortest distance S1 between the protruding electrodes Xp (or between the protruding electrodes Yp) is about 200 μm, and the distance S2 between the bus electrodes Xb and Yb is about 100 μm. Thereby, in this embodiment, for example, the sustain discharge generated between the electrodes XE and YE of one cell C1 of the cells C1 adjacent to each other in the display column region RA is changed to the electrode YE (or XE) of the other cell C1. Can be prevented from spreading.

In the cell C1 adjacent to each other in the display row region RA, the electrode XE (or YE) of one cell C1 and the electrode XE (or YE) of the other cell C1 are adjacent. That is, the electrode XE (or YE) of one cell C1 is arranged away from the electrode YE (or XE) of the other cell C1. Thus, in this embodiment, when a sustain discharge is generated between the electrodes XE and YE of one cell C1 of the cells C1 adjacent to each other in the display column region RA, the electrode XE (or YE) of one cell C1 is generated. And erroneous discharge between the electrode YE (or XE) of the other cell C1 can be prevented.

In this embodiment, since the distance between the protruding electrodes Xp (and the protruding electrodes Yp) of the cells C1 adjacent to each other in the display row region RA is mainly secured in the first direction D1, the cells C1 adjacent to each other. The distance in the second direction D2 can be reduced. That is, in this embodiment, the non-light emitting area formed between the adjacent cells C1 can be reduced, and the brightness of the image can be increased. In other words, in this embodiment, the light emitting region (cell C1) including the protruding electrodes Xp and Yp paired with each other can be increased, and the luminance of the image can be increased. In particular, in this embodiment, the luminance of the image can be increased while preventing erroneous discharge.

The address electrode AE is disposed between the adjacent barrier ribs BR. In the example shown in the figure, the address electrode AE is disposed so as to extend in the second direction D2 through between the protruding electrodes Xp and Yp of each cell C1. Thereby, by applying a voltage between the address electrode AE and the scan electrode YE (projection electrode Yp), an address discharge can be generated in the cell C1 of interest.

FIG. 3 shows an example of a plasma display device configured using the PDP 10 shown in FIG. A plasma display device (hereinafter also referred to as a PDP device) includes a PDP 10, an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, and a front housing 30 disposed on the image display surface 16 side of the PDP 10. The rear housing 40 and the base chassis 50 disposed on the back surface 18 side of the PDP 10, the circuit unit 60 for driving the PDP 10 attached to the rear housing 40 side of the base chassis 50, and the PDP 10 are attached to the base chassis 50. A double-sided adhesive sheet 70 for attaching is provided. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

FIG. 4 shows an outline of the circuit unit 60 for driving the PDP 10 shown in FIG. The circuit unit 60 includes an X driver XDRV, a Y driver YDRV, an address driver ADRV, a power supply unit PWR, and a control unit CNT. The drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10. For example, the X driver XDRV applies a common pulse to the bus electrode Xb, the Y driver YDRV selectively applies a pulse to the bus electrode Yb, and the address driver ADRV selectively applies an address pulse to the address electrode AE. Apply. The power supply unit PWR generates power supply voltages Vsc, Vs / 2, −Vs / 2, Vbx, Vsa and the like to be supplied to the drivers YDRV, XDRV, and ADRV.

The control unit CNT controls the operation of the drivers XDRV, YDRV, and ADRV. For example, the control unit CNT selects a subfield to be used based on the image data R0-7, G0-7, and B0-7, and outputs control signals YCNT, XCNT, and ACNT to the drivers YDRV, XDRV, and ADRV. Here, the subfield is a field obtained by dividing one field for displaying one screen of the PDP 10, and the number of sustain discharges is set for each subfield. A multi-tone image is displayed by selecting a subfield to be used for each cell C1 constituting the pixel.

FIG. 5 shows an example of the subfield discharge operation for displaying an image on the PDP shown in FIG. The star in the figure indicates the occurrence of discharge. In this example, each subfield SF has a reset period RST, an address period ADR, and a sustain period SUS.

First, in the reset period RST, a negative voltage (blunt wave) that gently falls is applied to the sustain electrode XE, and a positive voltage is applied to the scan electrode YE (FIG. 5A). The sustain electrode XE is maintained at a negative write voltage, and a positive write voltage (write obtuse wave) that gradually increases is applied to the scan electrode YE (FIG. 5B). As a result, positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively, while suppressing light emission of the cell. Next, a positive adjustment voltage is applied to the sustain electrode XE, and a negative adjustment voltage (adjusted obtuse wave) is applied to the scan electrode YE (FIG. 5C). This reduces the amount of positive and negative wall charges accumulated in the sustain electrode XE and the scan electrode YE, respectively, and adjusts the amount of wall charges in all cells. For example, the positive adjustment voltage is a voltage lower than the voltage Vs / 2, and the minimum value of the negative adjustment voltage is a voltage higher than the voltage −Vs / 2.

In the address period ADR, a bias voltage Vbx that serves as an anode at the time of address discharge is applied to the sustain electrode XE, a scan pulse (voltage −Vs / 2) that serves as a cathode at the time of address discharge is applied to the scan electrode YE, The address pulse (voltage Vsa) is applied to the address electrode AE corresponding to the cell to be lit (FIG. 5D). In the cell selected by the scan pulse and the address pulse, a discharge is temporarily generated between the scan electrode YE and the address electrode AE (address discharge), and this discharge is used as a trigger to temporarily stop between the sustain electrode XE and the scan electrode YE. Discharge (address discharge) occurs. Thereby, a cell to be lit in the sustain period SUS is selected. For example, the bias voltage Vbx is the same voltage as the positive adjustment voltage applied to the sustain electrode XE during the reset period RST.

Further, when a cell of another display line is selected, for example, a bias voltage Vby that is a difference voltage between the voltage −Vs / 2 and the voltage Vsc is applied to the scanning electrode YE of the display line other than the selection target. . Note that the second address pulse shown in the waveform of the address electrode AE is applied to select a cell of another display line (FIG. 5E).

In the sustain period SUS, negative and positive sustain pulses (voltage -Vs / 2, voltage Vs / 2) are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 5 (f)). As a result, a discharge (sustain discharge) is generated between the sustain electrode XE and the scan electrode YE in the cell selected in the address period ADR (cell to be lit). Next, positive and negative sustain pulses (voltage Vs / 2, voltage −Vs / 2) are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 4G), and the discharge state of the lit cell is maintained. Is done. Sustain pulses having different polarities are repeatedly applied to the sustain electrode XE and the scan electrode YE, so that the discharge of the cells lit in the sustain period SUS (sustain discharge) is repeatedly performed.

As described above, in this embodiment, the protruding electrodes Xp and Yp protrude along the second direction D2 from the bus electrodes Xb and Yb of each bus electrode pair BEp on the opposite side to the region where the discharge gap DG is formed. In the display row region RA, the distance between the protruding electrodes Xp (and the protruding electrodes Yp) of the cells C1 adjacent to each other is ensured mainly in the first direction D1. As a result, in this embodiment, it is possible to reduce the distance in the second direction D2 between the adjacent cells C1 while preventing erroneous discharge. That is, in this embodiment, it is possible to reduce the non-light emitting region formed between the cells C1 adjacent to each other while preventing erroneous discharge, and to increase the luminance of the image.

FIG. 6 shows an outline of the PDP 10 in another embodiment. FIG. 6 shows the state of the electrodes Xb, Xp2, Yb, Yp2, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, protruding electrodes Xp2, Yp2 are formed instead of the protruding electrodes Xp, Yp shown in FIGS. Other configurations are the same as those of the embodiment described with reference to FIGS. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 5 except for voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The protruding electrodes Xp2 and Yp2 are made of the same material (metal material or the like) as the bus electrodes Xb and Yb, are formed integrally with the bus electrodes Xb and Yb, and are arranged so that a part thereof is located on the partition wall BR. In this embodiment, since the projecting electrodes Xp2 and Yp2 are formed integrally with the bus electrodes Xb and Yb, the process for forming the electrodes XE and YE can be simplified, and the manufacturing cost can be reduced.

In this embodiment, part of the protruding electrodes Xp2 and Yp2 is positioned on the barrier rib BR, so that visible light is not transmitted without reducing the width of the protruding electrodes Xp2 and Yp2 that block the light emission of the phosphor. The non-light emitting region by the protruding electrodes Xp2 and Yp2 can be reduced. Thereby, in this embodiment, the width of the protruding electrodes Xp2, Yp2 can be secured to a certain size (for example, about 40 μm), and the protruding electrodes Xp2, Yp2 can be prevented from being disconnected. That is, in this embodiment, the light emitting region can be enlarged while preventing the protruding electrodes Xp2, Yp2 from being disconnected. Note that the protruding electrodes Xp2 and Yp2 may be arranged so that only one part of the protruding electrodes Xp2 and Yp2 (for example, the protruding electrode Xp2) is positioned on the partition wall BR. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 5 can be obtained. Moreover, in this embodiment, since the protruding electrodes Xp2 and Yp2 can be prevented from being disconnected, the manufacturing yield of the PDP or the reliability of the PDP can be improved.

FIG. 7 shows an outline of the PDP 10 in another embodiment. FIG. 7 shows the state of the electrodes Xb, Xp, Yb, Yp, AE2 and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, an address electrode AE2 having an address pad Ap is formed instead of the address electrode AE shown in FIGS. Other configurations are the same as those of the embodiment described with reference to FIGS. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 5 except for voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The address electrode AE2 is provided to extend in the second direction D2 on the glass base RS shown in FIG. 1 described above. That is, the address electrode AE2 is provided on the surface of the glass substrate RS that faces the glass substrate FS, extends in the second direction D2, and is disposed between the protruding electrode Yp and the protruding electrode Xp. The address electrode AE2 has an address pad Ap that protrudes in the first direction D1 toward one of the protruding electrodes Yp of the protruding electrodes Xp and Yp when viewed from the image display surface side.

For example, the address pad Ap is integrally formed with the address electrode AE2 for each cell C1 with the same material (metal material or the like) as the address electrode AE2. Further, in the example shown in the figure, the address pad Ap is arranged so as to partially overlap the protruding electrode Yp when viewed from the image display surface side. The address pad Ap may be formed so as to protrude toward the protruding electrode Yp so as not to overlap with the protruding electrode Yp when viewed from the image display surface side. In this embodiment, since the distance between the address electrode AE2 (more specifically, the address pad Ap) and the protruding electrode Yp is shorter than the embodiment described with reference to FIGS. 1 to 5 described above, the address electrode AE2 and the protruding electrode The discharge start voltage between the electrodes Yp can be lowered. Thereby, in this embodiment, the power consumption of the circuit for driving the address electrode AE2 (for example, the driver ADRV in FIG. 4 described above) can be reduced.

Here, in order to reduce the distance between the address electrode AE2 and the protruding electrode Yp, a configuration in which the width of the address electrode AE2 is increased as a whole was considered in the process of the present invention. However, with this configuration, the wiring capacity of the address electrode AE2 increases, and the power consumption of the circuit for driving the address electrode AE2 increases.

On the other hand, in this embodiment, compared to the configuration in which the width of the address electrode AE2 is increased as a whole, the wiring width of the address electrode AE2 in the portion excluding the portion where the address pad Ap is provided can be reduced, and the address electrode AE2 Wiring capacity can be reduced. Therefore, in this embodiment, the power consumption of the circuit for driving the address electrode AE2 can be reduced. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 5 can be obtained.

FIG. 8 shows an outline of the PDP 10 in another embodiment. FIG. 8 shows the state of the electrodes Xb, Xp3, Yb, Yp3, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the shape of the protruding electrodes Xp3 and Yp3 is different from the shape of the protruding electrodes Xp and Yp shown in FIGS. Other configurations are the same as those of the embodiment described with reference to FIGS. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 5 except for voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The protruding electrodes Xp3 and Yp3 are formed in a chamfered tip. That is, the protruding electrodes Xp3 and Yp3 have a chamfered portion TA chamfered at the tip. For example, in the projection electrode Xp3 (or Yp3) whose tips are adjacent to each other in the display row region RA, the chamfered portion TA of one projection electrode Xp3 (or Yp3) is the chamfered portion of the other projection electrode Xp3 (or Yp3). Opposite TA. That is, in the protruding electrodes Xp3 (or Yp3) that are provided on different bus electrode pairs BEp and are adjacent to each other in the display row region RA, the chamfered portion TA of one protruding electrode Xp3 (or Yp3) is the other protruding Opposite the chamfer TA of the electrode Xp3 (or Yp3).

Accordingly, in this embodiment, the shortest distance S1 between the adjacent projecting electrodes Xp3 and the shortest distance S1 between the projecting electrodes Yp3 can be increased as compared with the embodiment described with reference to FIGS. Therefore, in this embodiment, when the sustain discharge is generated between the electrodes XE and YE of one cell C1 of the cells C1 adjacent to each other in the display column region RA, the electrode XE (or YE) of one cell C1 and It is possible to reliably prevent erroneous discharge from occurring between the electrode YE (or XE) of the other cell C1. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 5 can be obtained.

FIG. 9 shows an outline of the PDP 10 in another embodiment. FIG. 9 shows the state of the electrodes Xb, Xp3, Yb, Yp3, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the positions of the tips of the protruding electrodes Xp3 and Yp3 are different from the configuration shown in FIG. 8 described above. Other configurations are the same as those of the embodiment described with reference to FIG. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 5 except for voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 and 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the projection electrode Xp3 (or Yp3) where the tips TP1 and TP2 are adjacent to each other in the display row region RA, the tip TP1 of one projection electrode Xp3 (or Yp3) is the tip TP2 of the other projection electrode Xp3 (or Yp3). Therefore, it is located on the bus electrode Xb (or Yb) side to which the other protruding electrode Xp3 (or Yp3) is connected. That is, in the protruding electrodes Xp3 (or Yp3) that are provided on different bus electrode pairs BEp and are adjacent to each other in the display row region RA, the tip TP1 of one protruding electrode Xp3 (or Yp3) is the other protruding electrode. It is located on the bus electrode Xb (or Yb) side to which the other protruding electrode Xp3 (or Yp3) is connected from the tip TP2 of Xp3 (or Yp3).

Thereby, in this embodiment, the non-light emitting area formed between the cells C1 adjacent to each other can be reduced and the luminance of the image can be increased as compared with the configuration of FIG. 8 described above. In other words, in this embodiment, the light emitting region (the region surrounded by the broken line in the figure, cell C1) including the protruding electrodes Xp3 and Yp3 that are paired with each other can be increased, and the luminance of the image can be increased.

Note that the chamfered portion TA of each protruding electrode Xp3, Yp3 is between the bus electrodes Xb, Yb where the distance S1 between the protruding electrodes Xp3 adjacent to each other (and between the protruding electrodes Yp3) in the display row region RA forms the discharge gap DG. It is formed to be larger than the distance S2. Thus, in this embodiment, when a sustain discharge is generated between the electrodes XE and YE of one cell C1 of the cells C1 adjacent to each other in the display column region RA, the electrode XE (or YE) of one cell C1 is generated. And erroneous discharge between the electrode YE (or XE) of the other cell C1 can be prevented. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 5 and FIG. 8 can be obtained.

FIG. 10 shows an outline of the PDP 10 in another embodiment. 10 shows the state of the electrodes Xb, Xp, Yb, Yp, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the arrangement order of the bus electrodes Xb and Yb and the arrangement of the address electrodes AE are different from the configuration shown in FIGS. Other configurations are the same as those shown in FIGS. The same elements as those described in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the illustrated example, electrodes XE (od) and YE (od) indicate sustain electrodes XE and scan electrodes YE corresponding to odd-numbered display lines, respectively, and electrodes XE (ev) and YE (ev) are even-numbered. The sustain electrode XE and the scan electrode YE corresponding to the display line are respectively shown. In the following description, when the odd and even numbers are not distinguished, the electrodes XE (od) and XE (ev) are also referred to as electrodes XE (or sustain electrodes XE), and the electrodes YE (od) and YE (ev) are referred to as electrodes YE (or Also referred to as scanning electrode YE).

The bus electrode pairs BEp adjacent to each other are arranged such that the bus electrode Xb of one bus electrode pair BEp and the bus electrode Yb of the other bus electrode pair BEp are adjacent to each other. That is, the sustain electrode XE (od) of the odd display line is adjacent to the scan electrode YE (ev) of the even display line, and the scan electrode YE (od) of the odd display line is the even display. Adjacent to the sustain electrode XE (ev) of the line.

Therefore, in each display row region RA, the protruding electrode Xp of one cell C1 and the protruding electrode Yp of the other cell C1 of the cells C1 adjacent to each other are displayed in order to secure a mutual distance in the first direction D1. Arranged adjacent to one and the other of the pair of partition walls BR forming the row region RA. That is, the protruding electrodes Xp or Yp that are provided on different bus electrode pairs BEp and are adjacent to each other in the display column region RA are disposed adjacent to one and the other of the pair of partition walls BR forming the display column region RA. ing.

For example, in the display row region RA, the projecting electrodes Xp and Yp are such that the shortest distance S1 between the projecting electrodes Xp and Yp adjacent to each other is larger than the distance S2 between the bus electrodes Xb and Yb forming the discharge gap DG. Has been placed. For example, the shortest distance S1 between the protruding electrodes Xp (or between the protruding electrodes Yp) is about 200 μm, and the distance S2 between the bus electrodes Xb and Yb is about 100 μm. Thereby, in this embodiment, when sustain discharge is generated between the electrodes XE and YE of one cell C1 of the cells C1 adjacent to each other in the display column region RA, the sustain electrode XE (projection electrode) of one cell C1 is generated. Xp) and the scan electrode YE (projection electrode Yp) of the other cell C1 can be prevented from being erroneously discharged.

In this embodiment, since the distance between the protruding electrodes Xp and Yp of the cells C1 adjacent to each other in the display row region RA is mainly secured in the first direction D1, the second direction between the cells C1 adjacent to each other. The distance D2 can be reduced. That is, in this embodiment, the non-light emitting area formed between the adjacent cells C1 can be reduced, and the brightness of the image can be increased. In other words, in this embodiment, the light emitting region (cell C1) including the protruding electrodes Xp and Yp paired with each other can be increased, and the luminance of the image can be increased. In particular, in this embodiment, the luminance of the image can be increased while preventing erroneous discharge.

In the example shown in the figure, the address electrode AE extends between the protruding electrodes Xp and Yp of each cell C1 in the second direction D2 and is disposed adjacent to the protruding electrode Yp. Note that the address electrode AE may be arranged so that a part thereof overlaps the protruding electrode Yp when viewed from the image display surface side. Further, the address electrode AE is provided on the glass substrate RS as described with reference to FIG. That is, the address electrode AE is provided between the dielectric layer DL1 shown in FIG. 1 and the glass substrate RS, extends in the second direction D2, and is adjacent to one of the protruding electrodes Yp of the protruding electrodes Xp and Yp. Are arranged.

In this embodiment, since the address electrode AE and the protruding electrode Yp are adjacent to each other, the discharge start voltage between the address electrode AE and the protruding electrode Yp can be lowered, and a circuit for driving the address electrode AE (for example, described later) The power consumption of the driver ADRV in FIG. 11 can be reduced.

FIG. 11 shows an outline of the circuit unit 62 for driving the PDP 10 shown in FIG. The circuit unit 62 is provided with an X driver XDRV2 and a control unit CNT2 in place of the X driver XDRV and the control unit CNT of the circuit unit 60 shown in FIG. 4 described above. Other configurations are the same as those of the circuit unit 60 shown in FIG. The same elements as those described in FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, the PDP device configured using the PDP 10 shown in FIG. 10 is the same as the configuration of FIG. 3 described above except that the circuit unit 62 is provided instead of the circuit unit 60 shown in FIG.

For example, as shown in FIG. 12 to be described later, the X driver XDRV2 applies the bias voltage Vbx to the bus electrode Xb (sustain electrode XE) in the address period ADR separately for the odd-numbered display lines and the even-numbered display lines. To do. Other operations of the X driver XDRV2 are the same as those of the X driver XDRV shown in FIG. For example, as shown in FIG. 12 to be described later, the control unit CNT2 controls the operations of the drivers XDRV2, YDRV, and ADRV so as to select the cells to be lit in the odd-numbered display lines and the even-numbered display lines. To do. Other operations of the control unit CNT2 are the same as those of the control unit CNT shown in FIG. 4 described above.

FIG. 12 shows an example of the subfield discharge operation for displaying an image on the PDP 10 shown in FIG. In the discharge operation of this embodiment, the waveform of the address period ADR is different from the waveform shown in FIG. The discharge operation in other periods (reset period RST, sustain period SUS) is the same as the discharge operation shown in FIG. The same elements as those described in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted. The star in the figure indicates the occurrence of discharge.

In the address period ADR, first, in order to select the cells of the odd-numbered display lines, the bias voltage Vbx is applied to the sustain electrodes XE (od) corresponding to the odd-numbered display lines, and the ground voltage GND is set to the even-numbered display lines. Is applied to the sustain electrode XE (ev) corresponding to. For example, a bias voltage Vbx serving as an anode during address discharge is applied to the sustain electrode XE (od), and a scan pulse (voltage −Vs / 2) serving as a cathode during address discharge is applied to the scan electrode YE (od). An address pulse (voltage Vsa) that sometimes serves as an anode is applied to the address electrode AE corresponding to the cell to be lit (FIG. 12 (h)).

In the cell selected by the scan pulse and the address pulse, a discharge is temporarily generated (address discharge) between the scan electrode YE (od) and the address electrode AE, and this discharge is used as a trigger to generate the sustain electrode XE (od). Discharge (address discharge) is temporarily generated between the scan electrodes YE (od). Thereby, the cells of the even-numbered display lines that are lit in the sustain period SUS are selected.

Since the ground voltage GND lower than the bias voltage Vbx is applied to the sustain electrode XE (ev), the voltage between the sustain electrode XE (ev) and the scan electrode YE (od) is scanned with the sustain electrode XE (od). It is smaller than the voltage between the electrodes YE (od). Accordingly, in this embodiment, it is possible to prevent erroneous discharge from occurring between the sustain electrode XE (ev) and the scan electrode YE (od) when the discharge is generated between the scan electrode YE (od) and the address electrode AE. it can.

Further, when selecting the cells of the other odd-numbered display lines, the scan electrode YE (od) of the odd-numbered display lines other than the selection target is applied with, for example, a difference voltage between the voltage −Vs / 2 and the voltage Vsc. A certain bias voltage Vby is applied. Note that the second address pulse shown in the waveform of the address electrode AE is applied to select cells of other odd-numbered display lines (FIG. 12 (i)).

Next, in order to select cells of even-numbered display lines, the bias voltage Vbx is applied to the sustain electrode XE (ev), and the ground voltage GND is applied to the sustain electrode XE (od). For example, a bias voltage Vbx serving as an anode at the time of address discharge is applied to the sustain electrode XE (ev), and a scan pulse (voltage −Vs / 2) serving as a cathode at the time of address discharge is applied to the scan electrode YE (ev). An address pulse (voltage Vsa) that sometimes becomes the anode is applied to the address electrode AE corresponding to the cell to be lit (FIG. 12 (j)).

In the cell selected by the scan pulse and the address pulse, a discharge is temporarily generated (address discharge) between the scan electrode YE (ev) and the address electrode AE, and this discharge is used as a trigger to generate the sustain electrode XE (ev) and Discharge (address discharge) is temporarily generated between the scan electrodes YE (ev). Thereby, the cells of the odd-numbered display lines that are turned on in the sustain period SUS are selected. Since the ground voltage GND is applied to the sustain electrode XE (od), even if a discharge occurs between the scan electrode YE (ev) and the address electrode AE, the sustain electrode XE (od) and the scan electrode YE (ev) ) No erroneous discharge occurs between.

Further, when selecting cells of other even-numbered display lines, for example, a bias voltage Vby is applied to the scan electrodes YE (ev) of even-numbered display lines other than the selection target. Note that the last address pulse shown in the waveform of the address electrode AE is applied to select cells of other even-numbered display lines (FIG. 12 (k)). Note that the bias voltage Vby may be applied to the scanning electrodes YE of the display lines other than the selection target regardless of the odd-numbered and even-numbered display lines. The cell selection order may be reversed between the odd-numbered display lines and the even-numbered display lines. For example, after cells of even-numbered display lines are selected, cells of odd-numbered display lines may be selected.

As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 5 can be obtained. Further, in this embodiment, the address electrode AE is disposed adjacent to the protruding electrode Yp without providing the address pad Ap or the like shown in FIG. As a result, in this embodiment, the power consumption of the circuit for driving the address electrode AE can be reduced.

FIG. 13 shows an outline of the PDP 10 in another embodiment. FIG. 13 shows the state of the electrodes Xb, Xp, Yb, Yp, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 1). In this embodiment, the arrangement of the protruding electrodes Yp and the address electrodes AE is different from the configuration shown in FIG. 10 described above. Other configurations are the same as those of the embodiment described with reference to FIGS. The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 12 except for the voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 and 10 to 12 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The address electrode AE passes between the partition wall BR and the protruding electrode Yp, extends in the second direction D2, and is disposed adjacent to the protruding electrode Yp. Note that the protruding electrode Yp may be arranged so that a part thereof overlaps the address electrode AE when viewed from the image display surface side. In this embodiment, since the address electrode AE and the protruding electrode Yp are adjacent to each other, the discharge start voltage between the address electrode AE and the protruding electrode Yp can be lowered, and a circuit for driving the address electrode AE (for example, as described above) The power consumption of the driver ADRV in FIG. 11 can be reduced. As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 10 to 12 can be obtained.

FIG. 14 shows a main part of the PDP 10 in another embodiment. This embodiment is different from the embodiment described with reference to FIG. 13 described above in that the address electrodes AE are provided on the front substrate portion 12. Further, the rear substrate portion 14 of this embodiment is configured by omitting the dielectric layer DL2 from the configuration shown in FIG. 1 described above. Other configurations are the same as those of the embodiment described with reference to FIG. That is, the state of the electrodes Xb, Xp, Yb, Yp, AE and the partition wall BR viewed from the image display surface side (upper side in FIG. 14) is the same as that in FIG.

The discharge operation for displaying an image on the PDP 10 is the same as that in FIG. 12 except for the voltage values (for example, the voltages Vs / 2, −Vs / 2, and Vsa shown in FIG. 5 described above). The same elements as those described in FIGS. 1 to 5 and 10 to 13 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The address electrode AE is provided so as to extend in the second direction D2 on the dielectric layer DL1 (lower side in the figure). Further, when viewed from the image display surface side (upper side in FIG. 14), the address electrode AE is disposed between the partition wall BR and the protruding electrode Yp as shown in FIG. Note that a part of the address electrode AE may be disposed on the partition wall BR. In addition, a part of the protruding electrode Yp may be disposed on the address electrode AE.

The address electrode AE and the dielectric layer DL1 are covered with a protective layer PL. For example, in this embodiment, the dielectric layer DL1 is an insulating film such as a silicon dioxide film formed by a CVD method. The rear substrate portion 14 facing the front substrate portion 12 through the discharge space DS has a partition wall BR extending along the address electrode AE on the glass base RS. That is, the barrier ribs BR are arranged on the surface of the glass substrate RS that faces the glass substrate FS at an interval, and extend in the second direction D2. As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIG. 13 described above can be obtained.

In the above-described embodiment, an example in which one pixel includes three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), A cell that generates a color other than blue (B) may be included.

In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

In the embodiment described with reference to FIGS. 1 to 9, the bus electrode pairs BEp adjacent to each other are adjacent to the bus electrode Xb of one bus electrode pair BEp and the bus electrode Xb of the other bus electrode pair BEp. An example to be arranged in is described. The present invention is not limited to such an embodiment. For example, the bus electrode pairs BEp adjacent to each other may be arranged such that the bus electrode Xb of one bus electrode pair BEp and the bus electrode Yb of the other bus electrode pair BEp are adjacent to each other. Also in this case, the same effect as the embodiment described with reference to FIGS. 1 to 9 can be obtained.

In the embodiments described with reference to FIGS. 1 to 5 and FIGS. 7 to 14 described above, examples in which the protruding electrodes Xp (Xp3) and Yp (Yp3) are formed of a material that transmits visible light, such as an ITO film, have been described. . The present invention is not limited to such an embodiment. For example, the protruding electrodes Xp (Xp3) and Yp (Yp3) may be formed of the same material (metal material or the like) as the bus electrodes Xb and Yb and integrally formed with the bus electrodes Xb and Yb. In this case, the process for forming the electrodes XE and YE can be simplified, and the manufacturing cost can be reduced. Also in this case, the same effects as those of the embodiments described with reference to FIGS. 1 to 5 and FIGS. 7 to 14 can be obtained.

In the embodiments described with reference to FIGS. 1 to 6 and FIGS. 8 to 13, the example in which the address electrode AE is provided on the glass substrate RS has been described. The present invention is not limited to such an embodiment. For example, the address electrode AE may be provided on the dielectric layer DL1 covering the electrodes Xb, Xp, Yb, Yp as shown in FIG. Also in this case, the same effects as those of the embodiments described with reference to FIGS. 1 to 6 and FIGS. 8 to 13 can be obtained.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modification are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

The present invention can be applied to a plasma display panel used in a display device.

Claims

A first substrate and a second substrate facing each other;
A plurality of bus electrode pairs configured by first and second bus electrodes arranged on the surface of the first substrate facing the second substrate at an interval and extending in a first direction across a discharge gap. When,
A plurality of barrier ribs arranged on the surface of the second substrate facing the first substrate at intervals and extending in a second direction intersecting the first direction;
For each display column region formed between the barrier ribs, a region is provided on the first and second bus electrodes of each bus electrode pair, and the discharge gap is formed from the first and second bus electrodes. First and second protruding electrodes respectively protruding along the second direction on opposite sides and adjacent to the partition walls different from each other;
The first or second projecting electrodes provided on the bus electrode pairs different from each other and adjacent to each other in the display column region are respectively disposed adjacent to one and the other of the partition walls forming the display column region. A plasma display panel.
The plasma display panel according to claim 1, wherein
In the display row region, the first and second bus electrodes are formed such that the shortest distance between the bump electrodes provided on the bus electrode pairs different from each other forms the discharge gap. A plasma display panel, wherein the plasma display panel is formed so as to be larger than a distance therebetween.
The plasma display panel according to claim 1, wherein
The first protruding electrode is formed integrally with the first bus electrode,
The plasma display panel, wherein the second protruding electrode is formed integrally with the second bus electrode.
The plasma display panel according to claim 3, wherein
A plasma display panel, wherein at least one of the first and second projecting electrodes is partially located on the partition wall.
The plasma display panel according to claim 1, wherein
The plasma electrode display, wherein the bus electrode pairs adjacent to each other are arranged such that the first bus electrode of one bus electrode pair and the first bus electrode of the other bus electrode pair are adjacent to each other. panel.
The plasma display panel according to claim 1, wherein
The bus electrode pairs adjacent to each other are arranged such that the first bus electrode of one bus electrode pair and the second bus electrode of the other bus electrode pair are adjacent to each other. panel.
The plasma display panel according to claim 6, wherein
A dielectric layer provided on the first substrate and covering the bus electrode and the protruding electrode;
An address electrode is provided between the dielectric layer and the second substrate, extends in the second direction, and is disposed adjacent to one of the first and second protruding electrodes. A plasma display panel.
The plasma display panel according to claim 7, wherein
The plasma display panel, wherein the address electrode is provided on the dielectric layer and is disposed between the partition wall and the one protruding electrode.
The plasma display panel according to claim 1, wherein
An address electrode provided on a surface of the second substrate facing the first substrate, extending in the second direction, and disposed between the first protruding electrode and the second protruding electrode;
The address electrode includes an address pad that protrudes in the first direction toward one of the first and second protruding electrodes when viewed from a direction perpendicular to the first substrate. Plasma display panel.
The plasma display panel according to claim 1, wherein
The first and second protruding electrodes include a chamfered portion chamfered at the tip,
In the first or second protruding electrode provided on the bus electrode pair different from each other and adjacent to each other in the display column region, the chamfered portion of one protruding electrode faces the chamfered portion of the other protruding electrode. A plasma display panel characterized by the above.
The plasma display panel according to claim 10, wherein
In the first or second protruding electrode provided on the bus electrode pair different from each other and adjacent to each other in the display column region, the tip of one protruding electrode is connected to the other protruding electrode from the tip of the other protruding electrode. A plasma display panel, which is located on the bus electrode side to be connected.