WO2009150741A1 - Photovoltaic device manufacturing method - Google Patents

Photovoltaic device manufacturing method Download PDF

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Publication number
WO2009150741A1
WO2009150741A1 PCT/JP2008/060795 JP2008060795W WO2009150741A1 WO 2009150741 A1 WO2009150741 A1 WO 2009150741A1 JP 2008060795 W JP2008060795 W JP 2008060795W WO 2009150741 A1 WO2009150741 A1 WO 2009150741A1
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WIPO (PCT)
Prior art keywords
electrode
conductive paste
insulating film
diffusion layer
forming
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PCT/JP2008/060795
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French (fr)
Japanese (ja)
Inventor
昇市 唐木田
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三菱電機株式会社
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Priority to PCT/JP2008/060795 priority Critical patent/WO2009150741A1/en
Publication of WO2009150741A1 publication Critical patent/WO2009150741A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a method for manufacturing a photovoltaic device.
  • This silicon solar cell As a photovoltaic device, there is a silicon solar cell used for residential use.
  • This silicon solar cell generally includes an n-type diffusion layer formed on one main surface side (hereinafter referred to as a front surface side or a light receiving surface side) of a p-type silicon substrate, and the other main surface side (hereinafter referred to as a back surface).
  • P + layer functioning as a BSF (Back Surface Field) is formed on the side, and electrodes for taking out photovoltaic power output by photoelectric conversion are provided on the front surface side and the back surface side, respectively.
  • the electrode on the surface side blocks incident sunlight, it is desirable to reduce the formation area as much as possible from the viewpoint of improving the power generation efficiency.
  • the contact interface between the front and back electrodes of the solar cell having such a structure and silicon has a high recombination speed, which causes a decrease in the efficiency of the solar cell. Therefore, it is necessary to reduce the area of the electrode-silicon interface as much as possible. Therefore, conventionally, a structure called PERC (the passivated emitter and rear cell) structure has been proposed (for example, see Non-Patent Document 1).
  • the surface electrode has a comb shape, and the other regions are covered with an insulating film such as a silicon nitride film or an oxide film, thereby providing an antireflection effect and a surface recombination speed reduction effect.
  • the back electrode is also covered with an insulating film such as a silicon nitride film or an oxide film, and silicon and the back electrode are directly contacted only in a part of the region to have the effect of reducing the back surface recombination rate. ing.
  • an insulating film such as a silicon nitride film or an oxide film
  • a manufacturing method has been proposed in which electrodes are selectively attached to the silicon surface (laser removal region) on the bottom surface of the contact hole, which is a non-insulating region, by performing plating (see, for example, Patent Document 1).
  • this method conduction is made to the opening region where the underlying silicon substrate is exposed by plating, and the thickness is further increased, so that the plated portion extends in the lateral direction above the insulating film, so that the contact holes are Bond through plating.
  • the surface electrode has a comb-shaped electrode structure, but the actual contact between the silicon and the electrode is removed by the laser. As a result, the surface recombination rate can be further reduced.
  • Patent Document 1 In the method described in Patent Document 1, two processing steps, laser processing and plating, are added to the conventional processing, and the adhesion between the electrode formed by plating and the underlying silicon substrate is increased. However, it is difficult to obtain good performance and increases the contact resistance, so that the efficiency of the solar cell is lowered.
  • the present invention has been made in view of the above, and it is possible to easily reduce the contact area between the surface electrode and the underlying silicon substrate using the conventional photovoltaic device manufacturing method as much as possible. It is an object of the present invention to obtain a method for manufacturing a photovoltaic device capable of improving adhesion to a substrate.
  • a method for manufacturing a photovoltaic device comprises diffusing impurities of a second conductivity type on the light incident surface side of a semiconductor substrate of a first conductivity type.
  • FIG. 1-1 is a top view illustrating an example of a solar cell.
  • FIG. 1-2 is a partially enlarged view of the AA cross section of the solar cell of FIG. 1-1.
  • 1-3 is a partially enlarged view of the BB cross section of FIG. 1-1.
  • FIG. 2-1 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 1).
  • FIG. 2-2 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 2).
  • FIG. 2-3 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 3).
  • FIG. 2-5 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 5).
  • FIG. 2-6 is a partial cross-sectional view schematically showing an example of the procedure of the method for manufacturing the solar cell according to the first embodiment (No. 6).
  • FIG. 3A is a diagram showing a top view of the solar cell of FIG. 2-5.
  • FIG. 3-2 is a partially enlarged view of FIG. 3-1.
  • FIG. 4 is a partial cross-sectional view in a direction parallel to the grid electrode in the state of FIG. 2-6.
  • FIG. 5-1 is a diagram illustrating an example of an application state of the electrode forming paste according to the third embodiment.
  • FIG. 5B is a partially enlarged view of FIG.
  • FIG. 5C is a partially enlarged view of the DD cross section of FIG.
  • FIG. 6A is a top view schematically showing a state where the tab line is formed on the bus electrode.
  • FIG. 6B is a partially enlarged view of the EE cross section of FIG. 6A.
  • FIG. 7-1 is a top view showing an example of an application state of the electrode forming paste according to the fourth embodiment.
  • FIG. 7-2 is a partially enlarged view of FIG. 7-1.
  • FIG. 7C is a partially enlarged view of the FF cross section of FIG. FIG.
  • 8-1 is a top view showing an example of an application state of the electrode forming paste according to the fourth embodiment.
  • 8-2 is a partially enlarged cross-sectional view of the GG cross section of FIG. 8-1.
  • FIG. 9A is a partially enlarged cross-sectional view in a direction perpendicular to the grid electrode after the electrode firing process.
  • FIG. 9-2 is a partially enlarged cross-sectional view in a direction parallel to the grid electrode after the electrode firing process.
  • FIG. 1-1 is a top view showing an example of a solar cell
  • FIG. 1-2 is a partially enlarged view of the AA cross section of the solar cell of FIG. 1-1
  • FIG. 3 is a partially enlarged view of a BB cross section of 1-1.
  • This solar cell 10 includes a p-type silicon substrate 12 as a semiconductor substrate, an n-type diffusion layer 13 in which an n-type impurity of a group V element such as phosphorus (P) is diffused on the surface of the p-type silicon substrate 12, A semiconductor layer portion 11 having a photoelectric conversion function including a p + layer 14 containing a p-type impurity of a group III element such as boron (B) at a higher concentration than the p-type silicon substrate, and light reception of the semiconductor layer portion 11 An antireflection film 15 provided on the surface for preventing the reflection of incident light, and a grid provided in parallel in a predetermined direction on the light receiving surface in order to locally collect electricity generated by the semiconductor layer portion 11
  • the electrode 16, the bus electrode 17 provided on the light receiving surface substantially orthogonal to the grid electrode 16 in order to take out the electricity collected by the grid electrode 16, and the electricity generated by the semiconductor layer unit 11 are collected and back surface Back side provided on It includes an aluminum electrode 18.
  • the p-type silicon substrate 12 may be a single crystal substrate or a polycrystalline substrate.
  • a single crystal substrate having a (100) plane orientation is used will be described as an example.
  • at least the light receiving surface side of the semiconductor layer portion 11 is provided with a texture having a concavo-convex structure so as to confine incident light in the semiconductor layer portion 11.
  • the texture structure is formed so that the (111) plane is exposed on the light-receiving surface side of the (100) plane single crystal silicon substrate.
  • the grid electrode 16 has a width of about 100 to 200 ⁇ m, for example, and is arranged at intervals of about 2 mm, and the bus electrode 17 has a width of about 1 to 3 mm, for example.
  • Two to three solar cells 10 are arranged. Since the surface electrode composed of the grid electrode 16 and the bus electrode 17 is disposed on the light receiving surface side, it is desirable to reduce the size as much as possible from the viewpoint of power generation efficiency. As this surface electrode, a material such as silver can be used. The surface electrode is in contact with the surface of the underlying semiconductor layer portion 11 (n-type diffusion layer 13) through the opening 32 formed in the antireflection film 15.
  • the openings 32 formed in the antireflection film 15 are formed in a circular shape or the like at a predetermined interval in the surface electrode formation region by a processing method using laser irradiation, and the grid electrodes are connected so as to connect the openings 32. 16 and bus electrodes 17 are formed. Therefore, as shown in FIG. 1-1, the surface electrode appears to be formed on the semiconductor layer portion 11 from the light receiving surface side, but in actuality, the opening formed on the antireflection film 15 is formed.
  • the semiconductor layer portion 11 is in contact with the semiconductor layer 11 in a spot shape via the portion 32.
  • the p + layer 14 of the semiconductor layer portion 11 expects the BSF effect, and the p-layer electron concentration is applied in a band structure electric field so that electrons in the p layer (p-type silicon substrate 12) of the semiconductor layer portion 11 do not disappear.
  • the back surface aluminum electrode 18 is provided on the entire back surface of the semiconductor layer portion 11 with the expectation of a BSR (Back Surface Reflection) effect that reflects long wavelength light passing through the semiconductor layer portion 11 and reuses it for power generation. .
  • BSR Back Surface Reflection
  • the warp of the p-type silicon substrate 12 becomes remarkable and induces substrate cracking. Therefore, it is often removed after the p + layer 14 is formed by heat treatment. In this case, a silver electrode is formed at a predetermined position as the back electrode.
  • FIGS. 2-1 to 2-6 are partial cross-sectional views schematically showing an example of the procedure of the method for manufacturing the solar cell according to the first embodiment, and FIG. 3-1 shows the solar cell of FIG. 2-5.
  • FIG. 3-2 is a partially enlarged view of FIG. 3-1, and FIG. 4 is a view parallel to the extending direction of the grid electrode in the state of FIG. 2-6.
  • FIG. FIGS. 2-1 to 2-6 schematically show the direction perpendicular to the extending direction of the grid electrode (the direction of the AA cross section in FIG. 1-1).
  • a single crystal p-type silicon substrate 12 is prepared (FIG. 2-1).
  • the p-type silicon substrate 12 is sliced and cut out from a cast ingot. Therefore, in order to remove the damaged layer on the surface of the substrate generated at the time of slicing, the surface of the p-type silicon substrate 12 is removed with a thickness of 10 to 20 ⁇ m using, for example, several to 20 wt% of caustic soda or carbonated caustic soda.
  • anisotropic etching is performed with a solution obtained by adding IPA (isopropyl alcohol) to a similar alkaline low concentration solution, and a texture 31 is formed on the surface of the p-type silicon substrate 12 so that the (111) plane of silicon is exposed ( Fig. 2-2).
  • IPA isopropyl alcohol
  • the p-type silicon substrate 12 on which the texture 31 is formed is treated at a temperature of 800 to 900 ° C./several times in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ), nitrogen, and oxygen to obtain the surface of the p-type silicon substrate 12.
  • An n-type diffusion layer 13 is uniformly formed on the entire surface. Since the sheet resistance range of the n-type diffusion layer 13 uniformly formed on the surface of the p-type silicon substrate 12 is 30 to 80 ⁇ / ⁇ , good solar cell electrical characteristics can be obtained. Thus, the n-type diffusion layer 13 is formed.
  • a polymer resist paste is attached and dried by a method such as a screen printing method, and a mask is formed with the resist.
  • the p-type silicon substrate 12 is dipped in a 20 wt% potassium hydroxide solution for several minutes to form an n-type diffusion layer 13 formed on the surface of the p-type silicon substrate 12 outside the desired region (such as the back surface).
  • the mask (resist) is removed with an organic solvent (FIG. 2-3).
  • end face separation may be performed by laser or dry etching at the end of the process.
  • an insulating film made of at least one material such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed as a reflection preventing film 15 on the entire surface of the n-type diffusion layer 13 with a uniform thickness (FIG. 2). -4).
  • a silicon nitride film is formed under reduced pressure at a temperature of 300 ° C. or higher using SiH 4 gas and NH 4 gas as raw materials by plasma CVD (Chemical Vapor Deposition).
  • the silicon nitride film thus formed has a refractive index of about 2.0 to 2.2, and the optimum thickness of the antireflection film 15 is 70 to 90 nm.
  • the surface electrode does not contact the n-type diffusion layer 13 simply by forming the surface electrode on the antireflection film 15 in a later step. Therefore, it does not act as a solar cell. Therefore, in the next step, a plurality of holes smaller than the size of the surface electrode are formed in the formation region of the surface electrode (grid electrode 16 and bus electrode 17) of the antireflection film 15 to form the opening 32 (FIG. 2-5).
  • the opening method include laser irradiation, etching paste, and photoengraving. From the viewpoint of simplicity, it is desirable to use laser irradiation or etching paste. Further, in FIG.
  • openings 32 are uniformly formed on the entire surface of the antireflection film 15, but actually, as shown in FIG. Opening 32 is formed only in the region where the surface electrode is formed.
  • opening diameter in the example of FIG. 3B, four openings 32 are provided for the width of the grid electrode 16 of about 100 ⁇ m. However, this is only an example, and for the optimum value of the aperture diameter, it is necessary to determine the conditions regarding the aperture diameter and how far each aperture 32 is separated.
  • the shape of the opening 32 may be any shape such as a circle, a corner, or a line.
  • a silver paste 33 as a conductive paste is applied on the region including the opening 32 on the antireflection film 15 by a screen printing method using a mask pattern for a comb electrode and dried.
  • the antireflection film 15 is melted by the components including the glass material in the baking step described later, All of the surface electrodes have the same structure as the conventional structure in contact with the n-type diffusion layer 13. Therefore, in this Embodiment 1, the silver paste 33 which adjusted the glass component and the other component is used to such an extent that the antireflection film 15 does not melt at the time of baking.
  • FIG. 2-6 shows a partially enlarged view of the CC cross section of FIG. 3-1.
  • the front and back electrode pastes 33 and 35 are simultaneously fired at 600 to 900 ° C. for several minutes, and the solar cell 10 shown in FIGS. 1-1 to 1-3 is manufactured.
  • a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed from the back surface aluminum electrode.
  • the silver paste 33 in which the glass component and other components are adjusted to such an extent that the antireflection film 15 is not melted is used, the antireflection in which the opening 32 is not formed by baking.
  • the silver paste 33 applied on the film 15 does not melt the antireflection film 15 and come into contact with the underlying n-type diffusion layer 13, and the surface electrode baked only at the opening 32 comes into contact with the n-type diffusion layer 13. To do.
  • a plurality of openings 32 smaller than the width of the electrode are formed in the electrode formation region on the surface side by a method such as laser irradiation. Since the silver paste 33 whose components are adjusted so as not to melt the antireflection film 15 is used, the interface between the fired surface electrode (grid electrode 16, bus electrode 17) and silicon substrate (n-type diffusion layer 13) The surface recombination rate can be reduced, and the surface electrode and the silicon substrate (n-type diffusion layer 13) can be connected with good adhesion, so that the photoelectric conversion efficiency is improved compared to the conventional structure.
  • Embodiment 2 a solar cell manufacturing method capable of reducing the resistance component at the contact portion between the silicon substrate (n-type diffusion layer) and the surface electrode, as compared with the first embodiment, will be described.
  • the p-type silicon substrate 12 is again placed in a mixed gas atmosphere of, for example, phosphorus oxychloride, nitrogen and oxygen at 800 to 900 ° C./several. Sufficient treatment is performed to diffuse n-type impurities into the surface of the silicon substrate (n-type diffusion layer 13) exposed through the opening 32. As a result, phosphorus diffuses only in the silicon substrate (n-type diffusion layer 13) in the region where the antireflection film 15 is opened, so that the surface phosphorus concentration in the region of the n-type diffusion layer 13 exposed in the opening 32 increases. To do. As a result, the contact resistance between the n-type diffusion layer 13 and the surface electrode formed in a later step can be reduced. Thereafter, the processing described in FIG. 2-6 and thereafter in Embodiment 1 is performed to manufacture the solar cell.
  • a mixed gas atmosphere for example, phosphorus oxychloride, nitrogen and oxygen at 800 to 900 ° C./several.
  • Sufficient treatment is performed to
  • the contaminated layer on the outermost surface of the n-type diffusion layer 13 is slightly removed by wet etching or the like to expose a clean surface layer, and then the diagram of the first embodiment.
  • the printing process after 2-6 may be performed.
  • the contact resistance between the n-type diffusion layer 13 and the surface electrode in the opening 32 formed in the antireflection film 15 is reduced. It has the effect that it can reduce rather than the case of the form 1.
  • FIG. 5-1 is a diagram illustrating an example of an application state of the electrode forming paste according to Embodiment 3
  • FIG. 5-2 is a partially enlarged view of FIG. 5-1
  • FIG. FIG. 5 is a partially enlarged view of a DD cross section of FIG. 5-1.
  • the n-type diffusion layer is formed on the main surface on the light-receiving surface side. 13 is formed, and an antireflection film 15 is further formed thereon.
  • a silver paste 34 is applied to the surface by screen printing using a mask pattern for forming a surface electrode.
  • a silver electrode 34 is applied so that a linear electrode pattern is formed on the grid electrode formation region 41 on the antireflection film 15 and a dot electrode pattern is formed on the bus electrode formation region 42. Apply and dry.
  • the silver paste 34 used in the third embodiment is a silver paste in which glass components and other components are adjusted so that the antireflection film 15 can be eroded in a later baking step.
  • the back electrode aluminum paste 35 and the back electrode silver paste (not shown) are applied to the back surface of the semiconductor layer 11 using a back electrode mask pattern and dried. In FIG. 5-3, illustration of the back electrode silver paste is omitted.
  • the front and back electrode pastes 34 and 35 are simultaneously fired at 600 to 900 ° C. for several minutes. Thereby, on the back surface, a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed on the back surface aluminum electrode 18. It becomes. Further, as described above, since the silver paste 34 in which the glass component for melting the antireflection film 15 and other components are adjusted is used on the surface, at each position of the surface electrode by firing, while the contained glass material melts the antireflection film 15, the silver material comes into contact with silicon and re-solidifies, and conduction between the surface electrode and silicon (n-type diffusion layer 13) is ensured. . Thus, a solar cell is obtained.
  • FIG. 6A is a top view schematically showing a state where the tab line is formed on the bus electrode
  • FIG. 6B is a partially enlarged view of the EE cross section of FIG. 6A.
  • the bus electrode 17 is a dot electrode, so that the output cannot be taken out.
  • a copper foil called a tab wire 22 is uniformly placed on the dot-shaped bus electrode 17, so that this The dots constituting the bus electrode 17 are connected to each other via the tab line 22 and the output can be taken out.
  • the bus electrode 17 having a size larger than that of the grid electrode 16 is formed in a dot shape, the dot-shaped bus electrodes 17 are electrically connected by the tab wire 22 in the modularization process.
  • the output can be taken out while reducing the surface recombination velocity at the interface between the bus electrode 17 and the n-type diffusion layer 13 (silicon substrate).
  • FIG. 7-1 is a top view showing an example of an application state of the electrode forming paste according to Embodiment 4,
  • FIG. 7-2 is a partially enlarged view of FIG. 7-1, and
  • FIG. 7 is a partially enlarged view of the FF cross section of FIG.
  • FIG. 8A is a top view showing an example of the application state of the electrode forming paste according to the fourth embodiment, and
  • FIG. 8B is a partially enlarged view of the GG section of FIG. is there.
  • FIGS. 9-1 to 9-2 are partially enlarged views of a cross section after the electrode firing process,
  • FIG. 9-1 shows a cross section in a direction perpendicular to the grid electrode, and
  • FIG. A cross section in a direction parallel to the grid electrode is shown.
  • the n-type diffusion layer is formed on the main surface on the light-receiving surface side. 13 is formed, and an antireflection film 15 is further formed thereon.
  • the grid electrode formation region 41 and the bus electrode formation region on the antireflection film 15 are formed on the antireflection film 15 by screen printing using a mask pattern for forming the surface electrode.
  • the first silver paste 34 is applied and dried so as to form a dot-like electrode pattern.
  • the first silver paste 34 is a silver paste that erodes the antireflection film 15.
  • the dot-shaped first silver paste 34 is arranged on the electrode formation region of the antireflection film 15.
  • the second silver paste 33 is applied and dried so as to form a continuous linear electrode pattern on the grid electrode formation region 41 and the bus electrode formation region.
  • the second silver paste 33 is a silver paste whose components are adjusted so as not to erode the antireflection film 15. As a result, a linear second silver paste 33 is formed so as to cover the dot-shaped first silver paste 34.
  • the back electrode aluminum paste 35 and the back electrode silver paste are applied to the back surface of the semiconductor layer portion 11 by screen printing using a back electrode mask pattern and dried.
  • the case where the aluminum paste for back electrode 35 and the silver paste for back electrode are performed before forming the silver paste on the surface is shown.
  • the front and back electrode pastes 33 to 35 are simultaneously fired at 600 to 900 ° C. for several minutes (FIGS. 9-1 and 9-2). Thereby, on the back surface, a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed on the back surface aluminum electrode 18. It becomes. On the surface, at each position where the dot-shaped first silver paste 34 is formed, components such as a glass material contained in the first silver paste 34 melt the antireflection film 15. In the meantime, the silver material comes into contact with silicon, and conduction between the surface electrode and silicon (n-type diffusion layer 13) is ensured.
  • the second silver paste 33 does not have a component such as a glass material that melts the antireflection film 15 by firing, the first silver paste 34 does not penetrate the antireflection film 15 by firing. It functions as an electrode for electrical connection between them.
  • the grid electrode 16 is formed in the grid electrode formation region, and the bus electrode 17 is formed in the bus electrode formation region.
  • a baking process of 600 to 900 ° C. is performed, and then the line of FIGS. 8-1 to 8-2 is performed.
  • firing may be performed again at a lower temperature than in the firing step of the first silver paste 34. .
  • FIG. 5 After the dot-shaped first silver paste is printed in FIGS. 7-1 to 7-3 of the fourth embodiment, a plating process step for forming wirings connecting the dot-shaped silver pastes by plating is introduced. May be.
  • the contact area of the interface between the surface electrode and the n-type diffusion layer 13 (silicon substrate) is reduced by using the plating process without using the laser processing process, and at the interface. This has the effect of reducing the surface recombination rate.
  • the method for manufacturing a photovoltaic device according to the present invention is useful for manufacturing a photovoltaic device such as a solar cell.

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Abstract

Provided is a photovoltaic device manufacturing method by which a contact area between a surface electrode and a base silicon substrate is easily reduced by using conventional photovoltaic device manufacturing methods as much as possible, and adhesiveness between the surface electrode and the silicon substrate is improved. The method includes a step of forming an n-type diffusion layer (13) by diffusing an n-type impurity on a light incoming surface of a p-type silicon substrate (12); a step of forming a reflection preventing film (15) on the n-type diffusion layer (13); a step of forming a plurality of openings (32), each of which has a diameter smaller than the dimension of the surface electrode, in the region where the surface electrode is formed on the reflection preventing film (15) so that the n-type diffusion layer (13) is exposed; a step of applying a silver paste (33) whose components are adjusted not to erode the reflection preventing film (15) while being burnt onto the region where the surface electrode including the openings (32) is formed; and a step of burning the silver paste (33).

Description

光起電力装置の製造方法Method for manufacturing photovoltaic device
　この発明は、光起電力装置の製造方法に関するものである。 The present invention relates to a method for manufacturing a photovoltaic device.
　光起電力装置として、住宅用などに使用されるシリコン太陽電池がある。このシリコン太陽電池は、概略的には、ｐ型シリコン基板の一方の主面側（以下、表面側または受光面側という）にｎ型拡散層を形成し、他方の主面側（以下、裏面側という）にＢＳＦ（Back　Surface　Field）として機能するｐ＋層を形成し、表面側と裏面側にそれぞれ光電変換によって出力される光起電力を取り出すための電極を設けた構造を有するものである。なお、表面側の電極は、入射する太陽光を遮ってしまうために、可能な限りその形成面積を小さくすることが発電効率向上の点では望ましい。 As a photovoltaic device, there is a silicon solar cell used for residential use. This silicon solar cell generally includes an n-type diffusion layer formed on one main surface side (hereinafter referred to as a front surface side or a light receiving surface side) of a p-type silicon substrate, and the other main surface side (hereinafter referred to as a back surface). P + layer functioning as a BSF (Back Surface Field) is formed on the side, and electrodes for taking out photovoltaic power output by photoelectric conversion are provided on the front surface side and the back surface side, respectively. In addition, since the electrode on the surface side blocks incident sunlight, it is desirable to reduce the formation area as much as possible from the viewpoint of improving the power generation efficiency.
　このような構造の太陽電池の表裏の電極とシリコンとの接触界面は、再結合速度が大きく、太陽電池の効率低下の原因となる。そのため、できる限り電極－シリコン界面の面積を減らす必要がある。そこで、従来では、ＰＥＲＣ（the　passivated　emitter　and　rear　cell）構造と呼ばれる構造が提案されている（たとえば、非特許文献１参照）。この構造では、表面電極については、電極形状を櫛型とし、その他の領域はシリコン窒化膜や酸化膜のような絶縁膜で覆うことによって、反射防止効果と表面の再結合速度低減の効果を持たせている。また、裏面電極についても同様に、シリコン窒化膜や酸化膜のような絶縁膜で覆い、一部領域のみシリコンと裏面電極とを直接コンタクトさせることで、裏面の再結合速度低減の効果を持たせている。 The contact interface between the front and back electrodes of the solar cell having such a structure and silicon has a high recombination speed, which causes a decrease in the efficiency of the solar cell. Therefore, it is necessary to reduce the area of the electrode-silicon interface as much as possible. Therefore, conventionally, a structure called PERC (the passivated emitter and rear cell) structure has been proposed (for example, see Non-Patent Document 1). In this structure, the surface electrode has a comb shape, and the other regions are covered with an insulating film such as a silicon nitride film or an oxide film, thereby providing an antireflection effect and a surface recombination speed reduction effect. It is Similarly, the back electrode is also covered with an insulating film such as a silicon nitride film or an oxide film, and silicon and the back electrode are directly contacted only in a part of the region to have the effect of reducing the back surface recombination rate. ing.
　さらに、表面電極とシリコンとの接触界面を減らす方法として、シリコン基板表面の全面を絶縁膜で覆った後、この絶縁膜の一部をレーザビームで点状に除去してコンタクトホールを形成し、その後メッキ処理することによって、非絶縁領域であるコンタクトホール底面のシリコン表面（レーザの除去領域）に選択的に電極を付着させる製造方法が提案されている（たとえば、特許文献１参照）。この方法では、メッキによって下地のシリコン基板が露出した開口領域へ導通を取った上、さらに厚みを増すことで、絶縁膜から上の領域で横方向にもメッキ部が伸長し、コンタクトホール同士がメッキを通して結合する。したがって、この方法によって形成された太陽電池を表面側の上方から眺めると、表面電極は櫛型電極構造を有しているが、実際にシリコンと電極が接触しているのは、レーザにより除去された点状の領域となり、表面の再結合速度をさらに低減することができる。 Furthermore, as a method of reducing the contact interface between the surface electrode and silicon, after covering the entire surface of the silicon substrate with an insulating film, a part of this insulating film is removed in a dot shape with a laser beam to form a contact hole, A manufacturing method has been proposed in which electrodes are selectively attached to the silicon surface (laser removal region) on the bottom surface of the contact hole, which is a non-insulating region, by performing plating (see, for example, Patent Document 1). In this method, conduction is made to the opening region where the underlying silicon substrate is exposed by plating, and the thickness is further increased, so that the plated portion extends in the lateral direction above the insulating film, so that the contact holes are Bond through plating. Therefore, when the solar cell formed by this method is viewed from the upper side on the surface side, the surface electrode has a comb-shaped electrode structure, but the actual contact between the silicon and the electrode is removed by the laser. As a result, the surface recombination rate can be further reduced.
特表平４－５０４０３３号公報Japanese National Publication No. 4-504033
　しかしながら、特許文献１に記載の方法では、レーザ加工処理とメッキ処理という２つの処理工程が、従来の処理工程に付加される上、メッキで形成された電極と下地のシリコン基板との間の密着性を上手く取ることが難しく、接触抵抗の増大を招くため、太陽電池の効率が低下してしまうという問題点があった。 However, in the method described in Patent Document 1, two processing steps, laser processing and plating, are added to the conventional processing, and the adhesion between the electrode formed by plating and the underlying silicon substrate is increased. However, it is difficult to obtain good performance and increases the contact resistance, so that the efficiency of the solar cell is lowered.
　この発明は上記に鑑みてなされたもので、従来の光起電力装置の製造方法をできる限り使用して、簡便に表面電極と下地のシリコン基板との接触面積を低減させるとともに、表面電極とシリコン基板との密着性を高めることができる光起電力装置の製造方法を得ることを目的とする。 The present invention has been made in view of the above, and it is possible to easily reduce the contact area between the surface electrode and the underlying silicon substrate using the conventional photovoltaic device manufacturing method as much as possible. It is an object of the present invention to obtain a method for manufacturing a photovoltaic device capable of improving adhesion to a substrate.
　上記目的を達成するため、この発明にかかる光起電力装置の製造方法は、第１の導電型の半導体基板の光の入射面側に第２の導電型の不純物を拡散させて、第１の拡散層を形成する第１の拡散層形成工程と、前記第１の拡散層上に前記光の入射面における反射を防止する機能を有する絶縁膜を形成する絶縁膜形成工程と、前記絶縁膜の表面電極の形成領域に、前記第１の拡散層が露出するように前記表面電極の寸法よりも小さい径の複数の開口部を形成する開口部形成工程と、焼成時に前記絶縁膜を侵食しないように成分調整された導電性ペーストを、前記開口部を含む前記表面電極の形成領域上に塗布する導電性ペースト塗布工程と、前記導電性ペーストを焼成する導電性ペースト焼成工程と、を含むことを特徴とする。 In order to achieve the above object, a method for manufacturing a photovoltaic device according to the present invention comprises diffusing impurities of a second conductivity type on the light incident surface side of a semiconductor substrate of a first conductivity type. A first diffusion layer forming step of forming a diffusion layer, an insulating film forming step of forming an insulating film having a function of preventing reflection of the light on the light incident surface on the first diffusion layer; and An opening forming step of forming a plurality of openings having a diameter smaller than the size of the surface electrode so that the first diffusion layer is exposed in the formation region of the surface electrode, and the insulating film is not eroded during firing. A conductive paste applying step of applying the conductive paste whose components are adjusted to the surface electrode forming region including the opening, and a conductive paste baking step of baking the conductive paste. Features.
　この発明によれば、光入射面側の絶縁膜の電極形成領域に電極の幅よりも微細な複数の開口部を形成し、焼成時に絶縁膜を溶融させないように成分を調整した導電性ペーストを用いて表面電極を形成するようにしたので、焼成後の表面電極と第１の拡散層との界面での表面再結合速度を低減することができるとともに、表面電極と第１の拡散層とを密着性よく接続することができるという効果を有する。また、従来の太陽電池の高効率化のために行っていたレーザ加工処理工程やメッキ工程を一部簡略化することができ、さらに、従来よりも高効率で高歩留まりの光起電力装置を作製することができるという効果を有する。 According to this invention, the conductive paste in which a plurality of openings smaller than the width of the electrode are formed in the electrode formation region of the insulating film on the light incident surface side and the components are adjusted so as not to melt the insulating film during firing. Since the surface electrode is formed by using the surface electrode, the surface recombination speed at the interface between the fired surface electrode and the first diffusion layer can be reduced, and the surface electrode and the first diffusion layer can be reduced. It has the effect that it can connect with sufficient adhesiveness. In addition, it is possible to simplify the laser processing process and plating process that have been performed to improve the efficiency of conventional solar cells, and to produce photovoltaic devices with higher efficiency and higher yield than conventional ones. It has the effect that it can be done.
図１－１は、太陽電池の一例を示す上面図である。FIG. 1-1 is a top view illustrating an example of a solar cell. 図１－２は、図１－１の太陽電池のＡ－Ａ断面の一部拡大図である。FIG. 1-2 is a partially enlarged view of the AA cross section of the solar cell of FIG. 1-1. 図１－３は、図１－１のＢ－Ｂ断面の一部拡大図である。1-3 is a partially enlarged view of the BB cross section of FIG. 1-1. 図２－１は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その１）。FIG. 2-1 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 1). 図２－２は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その２）。FIG. 2-2 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 2). 図２－３は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その３）。FIG. 2-3 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 3). 図２－４は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その４）。FIG. 2-4 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 4). 図２－５は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その５）。FIG. 2-5 is a partial cross-sectional view schematically showing an example of the procedure of the solar cell manufacturing method according to the first embodiment (part 5). 図２－６は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図である（その６）。FIG. 2-6 is a partial cross-sectional view schematically showing an example of the procedure of the method for manufacturing the solar cell according to the first embodiment (No. 6). 図３－１は、図２－５の太陽電池の上面図を示す図である。FIG. 3A is a diagram showing a top view of the solar cell of FIG. 2-5. 図３－２は、図３－１の一部拡大図である。FIG. 3-2 is a partially enlarged view of FIG. 3-1. 図４は、図２－６の状態におけるグリッド電極に平行な方向の一部断面図である。FIG. 4 is a partial cross-sectional view in a direction parallel to the grid electrode in the state of FIG. 2-6. 図５－１は、実施の形態３による電極形成用ペーストの塗布状態の一例を示す図である。FIG. 5-1 is a diagram illustrating an example of an application state of the electrode forming paste according to the third embodiment. 図５－２は、図５－１の一部拡大図である。FIG. 5B is a partially enlarged view of FIG. 図５－３は、図５－１のＤ－Ｄ断面の一部拡大図である。FIG. 5C is a partially enlarged view of the DD cross section of FIG. 図６－１は、バス電極にタブ線を形成した状態を模式的に示す上面図である。FIG. 6A is a top view schematically showing a state where the tab line is formed on the bus electrode. 図６－２は、図６－１のＥ－Ｅ断面の一部拡大図である。FIG. 6B is a partially enlarged view of the EE cross section of FIG. 6A. 図７－１は、実施の形態４による電極形成用ペーストの塗布状態の一例を示す上面図である。FIG. 7-1 is a top view showing an example of an application state of the electrode forming paste according to the fourth embodiment. 図７－２は、図７－１の一部拡大図である。FIG. 7-2 is a partially enlarged view of FIG. 7-1. 図７－３は、図７－１のＦ－Ｆ断面の一部拡大図である。FIG. 7C is a partially enlarged view of the FF cross section of FIG. 図８－１は、実施の形態４による電極形成用ペーストの塗布状態の一例を示す上面図である。FIG. 8-1 is a top view showing an example of an application state of the electrode forming paste according to the fourth embodiment. 図８－２は、図８－１のＧ－Ｇ断面の一部拡大断面図である。8-2 is a partially enlarged cross-sectional view of the GG cross section of FIG. 8-1. 図９－１は、電極焼成処理後のグリッド電極に垂直な方向の一部拡大断面図である。FIG. 9A is a partially enlarged cross-sectional view in a direction perpendicular to the grid electrode after the electrode firing process. 図９－２は、電極焼成処理後のグリッド電極に平行な方向の一部拡大断面図である。FIG. 9-2 is a partially enlarged cross-sectional view in a direction parallel to the grid electrode after the electrode firing process.
符号の説明Explanation of symbols
１０　太陽電池
１１　半導体層部
１２　ｐ型シリコン基板
１３　ｎ型拡散層
１４　ｐ＋層
１５　反射防止膜
１６　グリッド電極
１７　バス電極
１８　裏面アルミニウム電極
２２　タブ線
３１　テクスチャ
３２　開口部
３３　銀ペースト、第２の銀ペースト
３４　銀ペースト、第１の銀ペースト
３５　アルミニウムペースト
４１　グリッド電極形成領域
４２　バス電極形成領域 DESCRIPTION OF SYMBOLS 10 Solar cell 11 Semiconductor layer part 12 p-type silicon substrate 13 n-type diffused layer 14 p + layer 15 Antireflection film 16 Grid electrode 17 Bus electrode 18 Back surface aluminum electrode 22 Tab line 31 Texture 32 Opening part 33 Silver paste, 2nd silver Paste 34 Silver paste, first silver paste 35 Aluminum paste 41 Grid electrode formation region 42 Bus electrode formation region
　以下に添付図面を参照して、この発明にかかる光起電力装置の製造方法の好適な実施の形態を詳細に説明する。なお、以下の実施の形態では、光起電力装置として太陽電池を例に挙げて説明を行うが、この発明がこれらの実施の形態により限定されるものではない。また、以下の実施の形態で用いられる太陽電池の断面図は模式的なものであり、層の厚みと幅との関係や各層の厚みの比率などは現実のものとは異なる。 DETAILED DESCRIPTION Exemplary embodiments of a method for producing a photovoltaic device according to the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiments, a solar cell will be described as an example of a photovoltaic device, but the present invention is not limited to these embodiments. Moreover, the cross-sectional views of the solar cells used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.
実施の形態１．
　まず、この発明の実施の形態の製造方法によって製造される太陽電池の一般的な構造について説明する。図１－１は、太陽電池の一例を示す上面図であり、図１－２は、図１－１の太陽電池のＡ－Ａ断面の一部拡大図であり、図１－３は、図１－１のＢ－Ｂ断面の一部拡大図である。この太陽電池１０は、半導体基板としてのｐ型シリコン基板１２と、このｐ型シリコン基板１２の表面にリン（Ｐ）などのＶ族元素のｎ型不純物を拡散させたｎ型拡散層１３と、ホウ素（Ｂ）などのＩＩＩ族元素のｐ型の不純物をｐ型シリコン基板よりも高濃度に含むｐ＋層１４と、を含む光電変換機能を有する半導体層部１１と、この半導体層部１１の受光面に設けられ入射光の反射を防止する反射防止膜１５と、この半導体層部１１で発電された電気を局所的に集電するために受光面に所定の方向に複数並行して設けられるグリッド電極１６と、グリッド電極１６で集電された電気を取り出すためにグリッド電極１６にほぼ直交して受光面に設けられるバス電極１７と、半導体層部１１で発電された電気を集電し、裏面に設けられる裏面アルミニウム電極１８と、を備える。なお、図示されていないが、裏面の所定の位置には、裏面アルミニウム電極１８で集められた電気を取出す裏面銀電極が設けられている。 Embodiment 1 FIG.
First, a general structure of a solar cell manufactured by the manufacturing method according to the embodiment of the present invention will be described. FIG. 1-1 is a top view showing an example of a solar cell, FIG. 1-2 is a partially enlarged view of the AA cross section of the solar cell of FIG. 1-1, and FIG. FIG. 3 is a partially enlarged view of a BB cross section of 1-1. This solar cell 10 includes a p-type silicon substrate 12 as a semiconductor substrate, an n-type diffusion layer 13 in which an n-type impurity of a group V element such as phosphorus (P) is diffused on the surface of the p-type silicon substrate 12, A semiconductor layer portion 11 having a photoelectric conversion function including a p + layer 14 containing a p-type impurity of a group III element such as boron (B) at a higher concentration than the p-type silicon substrate, and light reception of the semiconductor layer portion 11 An antireflection film 15 provided on the surface for preventing the reflection of incident light, and a grid provided in parallel in a predetermined direction on the light receiving surface in order to locally collect electricity generated by the semiconductor layer portion 11 The electrode 16, the bus electrode 17 provided on the light receiving surface substantially orthogonal to the grid electrode 16 in order to take out the electricity collected by the grid electrode 16, and the electricity generated by the semiconductor layer unit 11 are collected and back surface Back side provided on It includes an aluminum electrode 18. Although not shown, a back surface silver electrode for taking out the electricity collected by the back surface aluminum electrode 18 is provided at a predetermined position on the back surface.
　ここで、ｐ型シリコン基板１２としては単結晶基板でも多結晶基板でもよい。なお、以下では、（１００）面方位の単結晶基板を用いる場合を例に挙げて説明する。また、半導体層部１１の少なくとも受光面側は、入射した光を半導体層部１１に閉じ込めるように凹凸構造を有するテクスチャが設けられている。ここでは、（１００）面方位の単結晶シリコン基板の受光面側に、（１１１）面が露出するようにテクスチャ構造を形成している。 Here, the p-type silicon substrate 12 may be a single crystal substrate or a polycrystalline substrate. In the following, a case where a single crystal substrate having a (100) plane orientation is used will be described as an example. Further, at least the light receiving surface side of the semiconductor layer portion 11 is provided with a texture having a concavo-convex structure so as to confine incident light in the semiconductor layer portion 11. Here, the texture structure is formed so that the (111) plane is exposed on the light-receiving surface side of the (100) plane single crystal silicon substrate.
　さらに、グリッド電極１６は、図１－２に示されるように、たとえば１００～２００μｍ程度の幅を有し、２ｍｍ程度の間隔で配置され、バス電極１７は、たとえば１～３ｍｍ程度の幅を持ち、１枚の太陽電池１０当たり２～３本配置される。これらのグリッド電極１６とバス電極１７からなる表面電極は、受光面側に配置されるため、発電効率の観点からは可能な限りその寸法を小さくすることが望ましい。この表面電極として、銀などの材料を用いることができる。そして、この表面電極は、反射防止膜１５に形成された開口部３２で下地の半導体層部１１（ｎ型拡散層１３）の表面と接触している。反射防止膜１５に形成された開口部３２は、表面電極の形成領域にレーザ照射による加工法などで円形などの形状で所定の間隔で形成され、これらの開口部３２間を結ぶようにグリッド電極１６やバス電極１７が形成される。そのため、表面電極は、図１－１に示されるように、受光面側からは、半導体層部１１上に形成されているように見えるが、実際には反射防止膜１５上に形成された開口部３２を介してスポット状に半導体層部１１と接触していることになる。 Further, as shown in FIG. 1-2, the grid electrode 16 has a width of about 100 to 200 μm, for example, and is arranged at intervals of about 2 mm, and the bus electrode 17 has a width of about 1 to 3 mm, for example. Two to three solar cells 10 are arranged. Since the surface electrode composed of the grid electrode 16 and the bus electrode 17 is disposed on the light receiving surface side, it is desirable to reduce the size as much as possible from the viewpoint of power generation efficiency. As this surface electrode, a material such as silver can be used. The surface electrode is in contact with the surface of the underlying semiconductor layer portion 11 (n-type diffusion layer 13) through the opening 32 formed in the antireflection film 15. The openings 32 formed in the antireflection film 15 are formed in a circular shape or the like at a predetermined interval in the surface electrode formation region by a processing method using laser irradiation, and the grid electrodes are connected so as to connect the openings 32. 16 and bus electrodes 17 are formed. Therefore, as shown in FIG. 1-1, the surface electrode appears to be formed on the semiconductor layer portion 11 from the light receiving surface side, but in actuality, the opening formed on the antireflection film 15 is formed. The semiconductor layer portion 11 is in contact with the semiconductor layer 11 in a spot shape via the portion 32.
　また、半導体層部１１のｐ＋層１４は、ＢＳＦ効果を期待して、半導体層部１１のｐ層（ｐ型シリコン基板１２）中の電子が消滅しないようにバンド構造の電界でｐ層電子濃度を高めるようにしている。また、裏面アルミニウム電極１８は、半導体層部１１を通過する長波長光を反射させて発電に再利用するＢＳＲ（Back　Surface　Reflection）効果も期待して半導体層部１１の裏面全面に設けられている。ただし、裏面アルミニウム電極１８を形成すると、ｐ型シリコン基板１２の反りが顕著となり、基板割れを誘発するため、熱処理でｐ＋層１４を形成した後に除去することも多い。この場合には、裏面電極として所定の位置に銀の電極を形成する。 In addition, the p + layer 14 of the semiconductor layer portion 11 expects the BSF effect, and the p-layer electron concentration is applied in a band structure electric field so that electrons in the p layer (p-type silicon substrate 12) of the semiconductor layer portion 11 do not disappear. To increase. Further, the back surface aluminum electrode 18 is provided on the entire back surface of the semiconductor layer portion 11 with the expectation of a BSR (Back Surface Reflection) effect that reflects long wavelength light passing through the semiconductor layer portion 11 and reuses it for power generation. . However, when the back surface aluminum electrode 18 is formed, the warp of the p-type silicon substrate 12 becomes remarkable and induces substrate cracking. Therefore, it is often removed after the p + layer 14 is formed by heat treatment. In this case, a silver electrode is formed at a predetermined position as the back electrode.
　つぎに、この実施の形態１による太陽電池の製造方法について説明する。図２－１～図２－６は、この実施の形態１による太陽電池の製造方法の手順の一例を模式的に示す一部断面図であり、図３－１は、図２－５の太陽電池の上面図を示す図であり、図３－２は、図３－１の一部拡大図であり、図４は、図２－６の状態におけるグリッド電極の延在方向に平行な方向の一部断面図である。なお、図２－１～図２－６は、グリッド電極の延在方向に垂直な方向（図１－１におけるＡ－Ａ断面の方向）を模式的に示している。 Next, a method for manufacturing the solar cell according to Embodiment 1 will be described. FIGS. 2-1 to 2-6 are partial cross-sectional views schematically showing an example of the procedure of the method for manufacturing the solar cell according to the first embodiment, and FIG. 3-1 shows the solar cell of FIG. 2-5. FIG. 3-2 is a partially enlarged view of FIG. 3-1, and FIG. 4 is a view parallel to the extending direction of the grid electrode in the state of FIG. 2-6. FIG. FIGS. 2-1 to 2-6 schematically show the direction perpendicular to the extending direction of the grid electrode (the direction of the AA cross section in FIG. 1-1).
　まず、単結晶のｐ型シリコン基板１２を用意する（図２－１）。このｐ型シリコン基板１２は、たとえば、鋳造インゴットからスライスして切出されたものである。そのため、このスライス時に発生する基板表面のダメージ層を除去するために、たとえば数～２０ｗｔ％の苛性ソーダや炭酸苛性ソーダを用いてｐ型シリコン基板１２の表面を１０～２０μｍの厚さで除去する。その後、同様のアルカリ低濃度液にＩＰＡ（イソプロピルアルコール）を添加した溶液で異方性エッチングを行ない、シリコンの（１１１）面が出るようにｐ型シリコン基板１２の表面にテクスチャ３１を形成する（図２－２）。 First, a single crystal p-type silicon substrate 12 is prepared (FIG. 2-1). For example, the p-type silicon substrate 12 is sliced and cut out from a cast ingot. Therefore, in order to remove the damaged layer on the surface of the substrate generated at the time of slicing, the surface of the p-type silicon substrate 12 is removed with a thickness of 10 to 20 μm using, for example, several to 20 wt% of caustic soda or carbonated caustic soda. Thereafter, anisotropic etching is performed with a solution obtained by adding IPA (isopropyl alcohol) to a similar alkaline low concentration solution, and a texture 31 is formed on the surface of the p-type silicon substrate 12 so that the (111) plane of silicon is exposed ( Fig. 2-2).
　ついで、テクスチャ３１を形成したｐ型シリコン基板１２を、たとえばオキシ塩化リン（ＰＯＣｌ3）、窒素、酸素の混合ガス雰囲気で８００～９００℃／数十分処理を行い、ｐ型シリコン基板１２の表面全面に一様にｎ型拡散層１３を形成する。ｐ型シリコン基板１２の表面に一様に形成されたｎ型拡散層１３のシート抵抗の範囲が、３０～８０Ω／□で良好な太陽電池の電気特性が得られるので、このシート抵抗の範囲となるようにｎ型拡散層１３の形成処理を行う。 Next, the p-type silicon substrate 12 on which the texture 31 is formed is treated at a temperature of 800 to 900 ° C./several times in a mixed gas atmosphere of, for example, phosphorus oxychloride (POCl 3 ), nitrogen, and oxygen to obtain the surface of the p-type silicon substrate 12. An n-type diffusion layer 13 is uniformly formed on the entire surface. Since the sheet resistance range of the n-type diffusion layer 13 uniformly formed on the surface of the p-type silicon substrate 12 is 30 to 80Ω / □, good solar cell electrical characteristics can be obtained. Thus, the n-type diffusion layer 13 is formed.
　その後、受光面側のｎ型拡散層１３を保護するために、高分子レジストペーストをスクリーン印刷法などの方法で付着乾燥させ、レジストによってマスクを形成する。ついで、ｐ型シリコン基板１２を２０ｗｔ％の水酸化カリウム溶液などの中へ数分間浸漬して、所望の領域以外（裏面など）のｐ型シリコン基板１２の表面に形成されたｎ型拡散層１３を除去する。なお、マスクされた受光面側のｎ型拡散層１３は除去されない。その後、マスク（レジスト）を有機溶剤で除去する（図２－３）。このｐ型シリコン基板１２の受光面以外の面に形成されたｎ型拡散層１３の影響を除くための別の方法として、工程の最後にレーザやドライエッチングによって端面分離を行ってもよい。 Thereafter, in order to protect the n-type diffusion layer 13 on the light receiving surface side, a polymer resist paste is attached and dried by a method such as a screen printing method, and a mask is formed with the resist. Next, the p-type silicon substrate 12 is dipped in a 20 wt% potassium hydroxide solution for several minutes to form an n-type diffusion layer 13 formed on the surface of the p-type silicon substrate 12 outside the desired region (such as the back surface). Remove. The masked n-type diffusion layer 13 on the light receiving surface side is not removed. Thereafter, the mask (resist) is removed with an organic solvent (FIG. 2-3). As another method for removing the influence of the n-type diffusion layer 13 formed on the surface other than the light-receiving surface of the p-type silicon substrate 12, end face separation may be performed by laser or dry etching at the end of the process.
　ついで、ｎ型拡散層１３上の全面に、反射防止膜１５として、シリコン酸化膜やシリコン窒化膜、酸化チタン膜などの少なくとも１つの材料から成る絶縁膜を一様な厚みで形成する（図２－４）。たとえば、シリコン窒化膜では、プラズマＣＶＤ（Chemical　Vapor　Deposition）法でＳｉＨ4ガスおよびＮＨ4ガスを原材料にして３００℃以上の温度で、減圧下で成膜する。このようにして形成されたシリコン窒化膜の屈折率は２．０～２．２程度であり、最適な反射防止膜１５の厚さは７０～９０ｎｍである。 Next, an insulating film made of at least one material such as a silicon oxide film, a silicon nitride film, or a titanium oxide film is formed as a reflection preventing film 15 on the entire surface of the n-type diffusion layer 13 with a uniform thickness (FIG. 2). -4). For example, a silicon nitride film is formed under reduced pressure at a temperature of 300 ° C. or higher using SiH 4 gas and NH 4 gas as raw materials by plasma CVD (Chemical Vapor Deposition). The silicon nitride film thus formed has a refractive index of about 2.0 to 2.2, and the optimum thickness of the antireflection film 15 is 70 to 90 nm.
　このようにして形成される反射防止膜１５は絶縁体であるので、後の工程で、表面電極をこの反射防止膜１５上に単に形成しただけでは、表面電極がｎ型拡散層１３と接触しないために、太陽電池として作用しない。そこで、つぎの工程では、反射防止膜１５の表面電極（グリッド電極１６とバス電極１７）の形成領域に表面電極の寸法よりも小さな孔を複数開け、開口部３２を形成する（図２－５、図３－１、図３－２）。開口する方法としては、レーザ照射、エッチングペースト、写真製版による方法などあるが、簡便性の観点からは、レーザ照射またはエッチングペーストによる方法を用いることが望ましい。また、図３－１では、反射防止膜１５上の全面に一様に開口部３２が形成されているように見えるが、実際には、図３－２に示されるように、グリッド電極１６などの表面電極が形成される領域にのみ開口部３２が形成される。開口径については、図３－２の例では、凡そ１００μｍ前後のグリッド電極１６の幅に対して、４つ分の開口部３２を設けている。しかし、これは一例であり、開口径の最適値については、開口径や各開口部３２をどれだけ離すかについて、条件出しが必要となる。なお、開口部３２の形状は、丸、角、線状のものなど任意の形状のものでよい。 Since the antireflection film 15 formed in this way is an insulator, the surface electrode does not contact the n-type diffusion layer 13 simply by forming the surface electrode on the antireflection film 15 in a later step. Therefore, it does not act as a solar cell. Therefore, in the next step, a plurality of holes smaller than the size of the surface electrode are formed in the formation region of the surface electrode (grid electrode 16 and bus electrode 17) of the antireflection film 15 to form the opening 32 (FIG. 2-5). FIG. 3-1, FIG. 3-2). Examples of the opening method include laser irradiation, etching paste, and photoengraving. From the viewpoint of simplicity, it is desirable to use laser irradiation or etching paste. Further, in FIG. 3A, it seems that the openings 32 are uniformly formed on the entire surface of the antireflection film 15, but actually, as shown in FIG. Opening 32 is formed only in the region where the surface electrode is formed. Regarding the opening diameter, in the example of FIG. 3B, four openings 32 are provided for the width of the grid electrode 16 of about 100 μm. However, this is only an example, and for the optimum value of the aperture diameter, it is necessary to determine the conditions regarding the aperture diameter and how far each aperture 32 is separated. The shape of the opening 32 may be any shape such as a circle, a corner, or a line.
　ついで、櫛型電極用のマスクパターンを使用してスクリーン印刷法によって、反射防止膜１５上の開口部３２を含む領域上に、導電性ペーストとしての銀ペースト３３を塗布し、乾燥させる。なお、銀ペースト３３に従来使用されている程度にガラス材料やその他の成分が含まれていると、後述する焼成工程でガラス材料を初めとする成分によって、反射防止膜１５が溶融してしまい、表面電極のすべてがｎ型拡散層１３と接触した従来の構造と同じ構造となってしまう。そのため、この実施の形態１では、焼成時に反射防止膜１５が溶融しない程度に、ガラス成分やその他の成分を調整した銀ペースト３３を用いている。さらに、裏面電極用のマスクパターンを用いてスクリーン印刷法によって、ｐ型シリコン基板１２の裏面上に、裏面電極用アルミニウムペースト３５と図示しない裏面電極用銀ペーストを塗布し、乾燥させる（図２－６、図４）。なお、この図２－６は、図３－１のＣ－Ｃ断面の一部拡大図を示している。 Next, a silver paste 33 as a conductive paste is applied on the region including the opening 32 on the antireflection film 15 by a screen printing method using a mask pattern for a comb electrode and dried. In addition, when the glass material and other components are contained to the extent that silver paste 33 is conventionally used, the antireflection film 15 is melted by the components including the glass material in the baking step described later, All of the surface electrodes have the same structure as the conventional structure in contact with the n-type diffusion layer 13. Therefore, in this Embodiment 1, the silver paste 33 which adjusted the glass component and the other component is used to such an extent that the antireflection film 15 does not melt at the time of baking. Further, a back electrode aluminum paste 35 and a back electrode silver paste (not shown) are applied on the back surface of the p-type silicon substrate 12 by screen printing using a mask pattern for the back electrode and dried (FIG. 2- 6, FIG. 4). FIG. 2-6 shows a partially enlarged view of the CC cross section of FIG. 3-1.
　ついで、表裏の電極用ペースト３３，３５を同時に６００～９００℃で数分間焼成し、図１－１～図１－３に示される太陽電池１０が製造される。この工程によって、裏面では、裏面電極用アルミニウムペースト３５を構成するアルミニウムの一部がｐ型シリコン基板１２上に拡散し、ｐ＋層１４を形成し、残りの裏面電極用アルミニウムペースト３５は裏面アルミニウム電極１８となる。また、表面では、上述したように、反射防止膜１５を溶融させない程度にガラス成分やその他の成分を調整した銀ペースト３３を用いているので、焼成によって、開口部３２が形成されていない反射防止膜１５上に塗布された銀ペースト３３が反射防止膜１５を溶融して下地のｎ型拡散層１３と接触することはなく、開口部３２でのみ焼成した表面電極がｎ型拡散層１３と接触する。 Next, the front and back electrode pastes 33 and 35 are simultaneously fired at 600 to 900 ° C. for several minutes, and the solar cell 10 shown in FIGS. 1-1 to 1-3 is manufactured. By this process, on the back surface, a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed from the back surface aluminum electrode. 18 Further, on the surface, as described above, since the silver paste 33 in which the glass component and other components are adjusted to such an extent that the antireflection film 15 is not melted is used, the antireflection in which the opening 32 is not formed by baking. The silver paste 33 applied on the film 15 does not melt the antireflection film 15 and come into contact with the underlying n-type diffusion layer 13, and the surface electrode baked only at the opening 32 comes into contact with the n-type diffusion layer 13. To do.
　この実施の形態１によれば、反射防止膜１５を形成した後に、レーザ照射などの方法によって、表面側の電極形成領域に電極の幅よりも微細な複数の開口部３２を形成し、焼成時に反射防止膜１５を溶融させないように成分を調整した銀ペースト３３を用いるようにしたので、焼成後の表面電極（グリッド電極１６、バス電極１７）とシリコン基板（ｎ型拡散層１３）との界面での表面再結合速度を低減することができるとともに、表面電極とシリコン基板（ｎ型拡散層１３）とを密着性よく接続することができ、光電変換効率が従来の構造のものに比べて改善されるという効果を有する。また、従来の太陽電池の製造方法に、反射防止膜１５に表面電極形成位置に対応して開口を形成する工程を付加し、銀ペースト３３として、銀ペーストの焼成時に反射防止膜１５を溶融させる成分が、反射防止膜１５を溶融しない程度に調整したものを使用するようにしたので、従来の工程を大幅に変更する必要がなくなるという効果も有する。 According to the first embodiment, after the antireflection film 15 is formed, a plurality of openings 32 smaller than the width of the electrode are formed in the electrode formation region on the surface side by a method such as laser irradiation. Since the silver paste 33 whose components are adjusted so as not to melt the antireflection film 15 is used, the interface between the fired surface electrode (grid electrode 16, bus electrode 17) and silicon substrate (n-type diffusion layer 13) The surface recombination rate can be reduced, and the surface electrode and the silicon substrate (n-type diffusion layer 13) can be connected with good adhesion, so that the photoelectric conversion efficiency is improved compared to the conventional structure. Has the effect of being In addition, a process for forming an opening corresponding to the surface electrode formation position is added to the antireflection film 15 to the conventional solar cell manufacturing method, and the antireflection film 15 is melted as the silver paste 33 when the silver paste is baked. Since the components adjusted to such an extent that the antireflection film 15 is not melted are used, there is an effect that it is not necessary to significantly change the conventional process.
実施の形態２．
　この実施の形態２では、実施の形態１の場合よりも、シリコン基板（ｎ型拡散層）と表面電極との接触部分における抵抗成分を減少させることができる太陽電池の製造方法について説明する。 Embodiment 2. FIG.
In the second embodiment, a solar cell manufacturing method capable of reducing the resistance component at the contact portion between the silicon substrate (n-type diffusion layer) and the surface electrode, as compared with the first embodiment, will be described.
　実施の形態１の図２－５で反射防止膜１５に開口部３２を形成した後、再びｐ型シリコン基板１２を、たとえばオキシ塩化リン、窒素、酸素の混合ガス雰囲気で８００～９００℃／数十分処理を行い、開口部３２で露出したシリコン基板（ｎ型拡散層１３）の表面にｎ型不純物を拡散させる。これによって、反射防止膜１５を開口した領域のシリコン基板（ｎ型拡散層１３）にのみリンの拡散が進行するため、開口部３２で露出したｎ型拡散層１３の領域における表面リン濃度が増加する。その結果、ｎ型拡散層１３と後の工程で形成される表面電極との間の接触抵抗を低減させることができる。その後は、実施の形態１の図２－６以降で説明した処理を行い、太陽電池が製造される。 After the opening 32 is formed in the antireflection film 15 in FIG. 2-5 of the first embodiment, the p-type silicon substrate 12 is again placed in a mixed gas atmosphere of, for example, phosphorus oxychloride, nitrogen and oxygen at 800 to 900 ° C./several. Sufficient treatment is performed to diffuse n-type impurities into the surface of the silicon substrate (n-type diffusion layer 13) exposed through the opening 32. As a result, phosphorus diffuses only in the silicon substrate (n-type diffusion layer 13) in the region where the antireflection film 15 is opened, so that the surface phosphorus concentration in the region of the n-type diffusion layer 13 exposed in the opening 32 increases. To do. As a result, the contact resistance between the n-type diffusion layer 13 and the surface electrode formed in a later step can be reduced. Thereafter, the processing described in FIG. 2-6 and thereafter in Embodiment 1 is performed to manufacture the solar cell.
　また、上記の拡散処理を行った後、ｎ型拡散層１３の最表面の汚染された層を僅かにウエットエッチングなどで除去して清浄な表面層を露出させた後に、実施の形態１の図２－６以降の印刷工程を実施してもよい。 Further, after performing the above-described diffusion treatment, the contaminated layer on the outermost surface of the n-type diffusion layer 13 is slightly removed by wet etching or the like to expose a clean surface layer, and then the diagram of the first embodiment. The printing process after 2-6 may be performed.
　この実施の形態２によれば、実施の形態１の効果に加えて、反射防止膜１５に形成された開口部３２でのｎ型拡散層１３と表面電極との間の接触抵抗を、実施の形態１の場合よりも低減させることができるという効果を有する。 According to the second embodiment, in addition to the effects of the first embodiment, the contact resistance between the n-type diffusion layer 13 and the surface electrode in the opening 32 formed in the antireflection film 15 is reduced. It has the effect that it can reduce rather than the case of the form 1.
実施の形態３．
　この実施の形態３による太陽電池の製造方法について説明する。図５－１は、実施の形態３による電極形成用ペーストの塗布状態の一例を示す図であり、図５－２は、図５－１の一部拡大図であり、図５－３は、図５－１のＤ－Ｄ断面の一部拡大図である。 Embodiment 3 FIG.
A method for manufacturing a solar cell according to Embodiment 3 will be described. FIG. 5-1 is a diagram illustrating an example of an application state of the electrode forming paste according to Embodiment 3, FIG. 5-2 is a partially enlarged view of FIG. 5-1, and FIG. FIG. 5 is a partially enlarged view of a DD cross section of FIG. 5-1.
　まず、実施の形態１の図２－２～図２－４で説明したように、ｐ型シリコン基板１２の主面上にテクスチャ３１を形成した後、受光面側の主面にｎ型拡散層１３を形成し、さらにその上に反射防止膜１５を形成する。 First, as described in FIGS. 2-2 to 2-4 of the first embodiment, after the texture 31 is formed on the main surface of the p-type silicon substrate 12, the n-type diffusion layer is formed on the main surface on the light-receiving surface side. 13 is formed, and an antireflection film 15 is further formed thereon.
　その後、図５－１～図５－３に示されるように、表面電極形成用のマスクパターンを用いてスクリーン印刷法によって、表面に銀ペースト３４を塗布する。ここでは、反射防止膜１５上のグリッド電極形成領域４１には、線状の電極パターンを形成し、バス電極形成領域４２上には、ドット状の電極パターンを形成するように、銀ペースト３４を塗布し、乾燥させる。なお、このとき、実施の形態１，２とは異なり、反射防止膜１５上の表面電極形成位置には開口部３２を形成していない。そのため、この実施の形態３で用いる銀ペースト３４は、後の焼成工程で反射防止膜１５を侵食することができるようにガラス成分やその他の成分が調整された銀ペーストを用いる。また、半導体層部１１の裏面には、裏面電極用のマスクパターンを用いて、裏面電極用アルミニウムペースト３５と図示しない裏面電極用銀ペーストを塗布し、乾燥させる。なお、図５－３では、裏面電極用銀ペーストの図示を省略している。 Thereafter, as shown in FIGS. 5-1 to 5-3, a silver paste 34 is applied to the surface by screen printing using a mask pattern for forming a surface electrode. Here, a silver electrode 34 is applied so that a linear electrode pattern is formed on the grid electrode formation region 41 on the antireflection film 15 and a dot electrode pattern is formed on the bus electrode formation region 42. Apply and dry. At this time, unlike the first and second embodiments, the opening 32 is not formed at the surface electrode formation position on the antireflection film 15. Therefore, the silver paste 34 used in the third embodiment is a silver paste in which glass components and other components are adjusted so that the antireflection film 15 can be eroded in a later baking step. Further, the back electrode aluminum paste 35 and the back electrode silver paste (not shown) are applied to the back surface of the semiconductor layer 11 using a back electrode mask pattern and dried. In FIG. 5-3, illustration of the back electrode silver paste is omitted.
　その後、表裏の電極用ペースト３４，３５を同時に６００～９００℃で数分間焼成する。これによって、裏面では、裏面電極用アルミニウムペースト３５を構成するアルミニウムの一部がｐ型シリコン基板１２上に拡散してｐ＋層１４を形成し、残りの裏面電極用アルミニウムペースト３５は裏面アルミニウム電極１８となる。また、表面では、上述したように、反射防止膜１５を溶融させるガラス成分やその他の成分を調整した銀ペースト３４を用いているので、焼成によって、表面電極の各位置では、銀ペースト３４中に含まれているガラス材料が反射防止膜１５を溶融している間に銀材料がシリコンと接触して再凝固し、表面電極とシリコン（ｎ型拡散層１３）との間の導通が確保される。以上によって、太陽電池が得られる。 Thereafter, the front and back electrode pastes 34 and 35 are simultaneously fired at 600 to 900 ° C. for several minutes. Thereby, on the back surface, a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed on the back surface aluminum electrode 18. It becomes. Further, as described above, since the silver paste 34 in which the glass component for melting the antireflection film 15 and other components are adjusted is used on the surface, at each position of the surface electrode by firing, While the contained glass material melts the antireflection film 15, the silver material comes into contact with silicon and re-solidifies, and conduction between the surface electrode and silicon (n-type diffusion layer 13) is ensured. . Thus, a solar cell is obtained.
　図６－１は、バス電極にタブ線を形成した状態を模式的に示す上面図であり、図６－２は、図６－１のＥ－Ｅ断面の一部拡大図である。図５－１～図５－３に示されるような状態では、バス電極１７がドット状の電極であるために、出力を取り出せない。しかし、後のモジュール工程で、図６－１～図６－２に示されるように、このドット状のバス電極１７の上にタブ線２２と呼ばれる銅箔を一様に載置するため、このタブ線２２を介してバス電極１７を構成する各ドット間が導通し、出力を取り出すことが可能となる。 FIG. 6A is a top view schematically showing a state where the tab line is formed on the bus electrode, and FIG. 6B is a partially enlarged view of the EE cross section of FIG. 6A. In the state as shown in FIGS. 5A to 5C, the bus electrode 17 is a dot electrode, so that the output cannot be taken out. However, in the subsequent module process, as shown in FIGS. 6A and 6B, a copper foil called a tab wire 22 is uniformly placed on the dot-shaped bus electrode 17, so that this The dots constituting the bus electrode 17 are connected to each other via the tab line 22 and the output can be taken out.
　この実施の形態３によれば、グリッド電極１６に比して寸法が大きなバス電極１７をドット形状として、モジュール化工程でドット形状のバス電極１７間をタブ線２２で導通させるようにしたので、バス電極１７とｎ型拡散層１３（シリコン基板）との間の界面における表面再結合速度を低減しながら出力を取り出すことができる。 According to the third embodiment, since the bus electrode 17 having a size larger than that of the grid electrode 16 is formed in a dot shape, the dot-shaped bus electrodes 17 are electrically connected by the tab wire 22 in the modularization process. The output can be taken out while reducing the surface recombination velocity at the interface between the bus electrode 17 and the n-type diffusion layer 13 (silicon substrate).
実施の形態４．
　実施の形態３では、バス電極形成領域にはドット状のペーストを塗布し、グリッド電極形成領域には線状のペーストを塗布していたが、この実施の形態４では、表面電極用ペーストの他の塗布方法について説明する。図７－１は、実施の形態４による電極形成用ペーストの塗布状態の一例を示す上面図であり、図７－２は、図７－１の一部拡大図であり、図７－３は、図７－１のＦ－Ｆ断面の一部拡大図である。また、図８－１は、実施の形態４による電極形成用ペーストの塗布状態の一例を示す上面図であり、図８－２は、図８－１のＧ－Ｇ断面の一部拡大図である。さらに、図９－１～図９－２は、電極焼成処理後の断面の一部拡大図であり、図９－１は、グリッド電極に垂直な方向の断面を示し、図９－２は、グリッド電極に平行な方向の断面を示している。 Embodiment 4 FIG.
In the third embodiment, a dot-like paste is applied to the bus electrode formation region and a linear paste is applied to the grid electrode formation region. However, in the fourth embodiment, in addition to the surface electrode paste, The coating method will be described. FIG. 7-1 is a top view showing an example of an application state of the electrode forming paste according to Embodiment 4, FIG. 7-2 is a partially enlarged view of FIG. 7-1, and FIG. FIG. 7 is a partially enlarged view of the FF cross section of FIG. FIG. 8A is a top view showing an example of the application state of the electrode forming paste according to the fourth embodiment, and FIG. 8B is a partially enlarged view of the GG section of FIG. is there. Further, FIGS. 9-1 to 9-2 are partially enlarged views of a cross section after the electrode firing process, FIG. 9-1 shows a cross section in a direction perpendicular to the grid electrode, and FIG. A cross section in a direction parallel to the grid electrode is shown.
　まず、実施の形態１の図２－２～図２－４で説明したように、ｐ型シリコン基板１２の主面上にテクスチャ３１を形成した後、受光面側の主面にｎ型拡散層１３を形成し、さらにその上に反射防止膜１５を形成する。 First, as described in FIGS. 2-2 to 2-4 of the first embodiment, after the texture 31 is formed on the main surface of the p-type silicon substrate 12, the n-type diffusion layer is formed on the main surface on the light-receiving surface side. 13 is formed, and an antireflection film 15 is further formed thereon.
　その後、図７－１～図７－３に示されるように、表面電極形成用のマスクパターンを用いてスクリーン印刷法によって、反射防止膜１５上のグリッド電極形成領域４１とバス電極形成領域上に、ドット状の電極パターンを形成するように第１の銀ペースト３４を塗布し、乾燥させる。なお、この第１の銀ペースト３４は、反射防止膜１５を侵食する銀ペーストである。これによって、反射防止膜１５の電極形成領域上には、ドット状の第１の銀ペースト３４が配置される。 Thereafter, as shown in FIGS. 7A to 7C, the grid electrode formation region 41 and the bus electrode formation region on the antireflection film 15 are formed on the antireflection film 15 by screen printing using a mask pattern for forming the surface electrode. The first silver paste 34 is applied and dried so as to form a dot-like electrode pattern. The first silver paste 34 is a silver paste that erodes the antireflection film 15. Thereby, the dot-shaped first silver paste 34 is arranged on the electrode formation region of the antireflection film 15.
　ついで、図８－１と図８－２に示されるように、表面電極形成用のマスクパターンを用いてスクリーン印刷法によって、ドット状の第１の銀ペースト３４を配置した反射防止膜１５上のグリッド電極形成領域４１とバス電極形成領域上に、連続した線状の電極パターンを形成するように、第２の銀ペースト３３を塗布し、乾燥させる。なお、この第２の銀ペースト３３は、反射防止膜１５を侵食しないように成分が調整された銀ペーストである。これによって、ドット状の第１の銀ペースト３４を覆うように、線状の第２の銀ペースト３３が形成される。 Next, as shown in FIGS. 8A and 8B, on the antireflection film 15 on which the dot-shaped first silver paste 34 is disposed by screen printing using a mask pattern for forming a surface electrode. The second silver paste 33 is applied and dried so as to form a continuous linear electrode pattern on the grid electrode formation region 41 and the bus electrode formation region. The second silver paste 33 is a silver paste whose components are adjusted so as not to erode the antireflection film 15. As a result, a linear second silver paste 33 is formed so as to cover the dot-shaped first silver paste 34.
　また、半導体層部１１の裏面には、裏面電極用のマスクパターンを用いてスクリーン印刷法によって、裏面電極用アルミニウムペースト３５と図示しない裏面電極用銀ペーストとを塗布し、乾燥させる。なお、ここでは、裏面電極用アルミニウムペースト３５と裏面電極用銀ペーストとは、表面の銀ペースト形成前に行っている場合が示されている。 Further, the back electrode aluminum paste 35 and the back electrode silver paste (not shown) are applied to the back surface of the semiconductor layer portion 11 by screen printing using a back electrode mask pattern and dried. Here, the case where the aluminum paste for back electrode 35 and the silver paste for back electrode are performed before forming the silver paste on the surface is shown.
　そして、表裏の電極用ペースト３３～３５を同時に６００～９００℃で数分間焼成する（図９－１、図９－２）。これによって、裏面では、裏面電極用アルミニウムペースト３５を構成するアルミニウムの一部がｐ型シリコン基板１２上に拡散し、ｐ＋層１４を形成し、残りの裏面電極用アルミニウムペースト３５は裏面アルミニウム電極１８となる。また、表面では、ドット状の第１の銀ペースト３４が形成されている各位置では、第１の銀ペースト３４中に含まれているガラス材料などの成分が反射防止膜１５を溶融している間に銀材料がシリコンと接触し、表面電極とシリコン（ｎ型拡散層１３）との間の導通が確保される。また、焼成によって第２の銀ペースト３３は、反射防止膜１５を溶融するほどのガラス材料などの成分を有さないため、焼成によって反射防止膜１５を貫通することなく、第１の銀ペースト３４間を電気的に接続する電極として機能する。これによって、グリッド電極形成領域には、グリッド電極１６が形成され、バス電極形成領域には、バス電極１７が形成される。 The front and back electrode pastes 33 to 35 are simultaneously fired at 600 to 900 ° C. for several minutes (FIGS. 9-1 and 9-2). Thereby, on the back surface, a part of aluminum constituting the back electrode aluminum paste 35 is diffused on the p-type silicon substrate 12 to form the p + layer 14, and the remaining back electrode aluminum paste 35 is formed on the back surface aluminum electrode 18. It becomes. On the surface, at each position where the dot-shaped first silver paste 34 is formed, components such as a glass material contained in the first silver paste 34 melt the antireflection film 15. In the meantime, the silver material comes into contact with silicon, and conduction between the surface electrode and silicon (n-type diffusion layer 13) is ensured. Further, since the second silver paste 33 does not have a component such as a glass material that melts the antireflection film 15 by firing, the first silver paste 34 does not penetrate the antireflection film 15 by firing. It functions as an electrode for electrical connection between them. As a result, the grid electrode 16 is formed in the grid electrode formation region, and the bus electrode 17 is formed in the bus electrode formation region.
　なお、図７－１～図７－３のドット状の第１の銀ペースト３４の印刷工程の後に、６００～９００℃の焼成工程を行い、ついで、図８－１～図８－２の線状の第２の銀ペースト３３と裏面電極用のアルミニウムペースト３５と銀ペーストの印刷工程の後に、再度、第１の銀ペースト３４の焼成工程のときよりも低温で焼成を行うようにしてもよい。このように異なる銀ペースト３３，３４の印刷を行うたびに焼成を行うことで、絶縁膜に対する侵食作用の異なる銀ペーストの混ざり込みを抑制することができるため、安定した歩留まりが期待できる。 In addition, after the printing process of the dot-shaped first silver paste 34 of FIGS. 7-1 to 7-3, a baking process of 600 to 900 ° C. is performed, and then the line of FIGS. 8-1 to 8-2 is performed. After the step of printing the second silver paste 33, the aluminum paste 35 for the back electrode, and the silver paste, firing may be performed again at a lower temperature than in the firing step of the first silver paste 34. . By firing each time the different silver pastes 33 and 34 are printed in this way, mixing of silver pastes having different erosion effects on the insulating film can be suppressed, so that a stable yield can be expected.
　この実施の形態４によっても、実施の形態１と同様の効果を得ることができる。 The effect similar to that of the first embodiment can be obtained also by the fourth embodiment.
実施の形態５．
　実施の形態４の図７－１～図７－３でドット状の第１の銀ペーストを印刷した後、メッキ処理によって、ドット状の銀ペースト間を結ぶ配線を形成するメッキ処理工程を導入してもよい。 Embodiment 5. FIG.
After the dot-shaped first silver paste is printed in FIGS. 7-1 to 7-3 of the fourth embodiment, a plating process step for forming wirings connecting the dot-shaped silver pastes by plating is introduced. May be.
　この実施の形態５によれば、レーザ加工工程を用いずに、メッキ処理工程を用いて、表面電極とｎ型拡散層１３（シリコン基板）との界面の接触面積を小さくするとともに、その界面での表面再結合速度を低減することができるという効果を有する。 According to the fifth embodiment, the contact area of the interface between the surface electrode and the n-type diffusion layer 13 (silicon substrate) is reduced by using the plating process without using the laser processing process, and at the interface. This has the effect of reducing the surface recombination rate.
　以上のように、この発明にかかる光起電力装置の製造方法は、太陽電池などの光起電力装置の製造に有用である。 As described above, the method for manufacturing a photovoltaic device according to the present invention is useful for manufacturing a photovoltaic device such as a solar cell.

Claims (8)

  1. 　第１の導電型の半導体基板の光の入射面側に第２の導電型の不純物を拡散させて、第１の拡散層を形成する第１の拡散層形成工程と、
    　前記第１の拡散層上に前記光の入射面における反射を防止する機能を有する絶縁膜を形成する絶縁膜形成工程と、
    　前記絶縁膜の表面電極の形成領域に、前記第１の拡散層が露出するように前記表面電極の寸法よりも小さい径の複数の開口部を形成する開口部形成工程と、
    　焼成時に前記絶縁膜を侵食しないように成分調整された導電性ペーストを、前記開口部を含む前記表面電極の形成領域上に塗布する導電性ペースト塗布工程と、
    　前記導電性ペーストを焼成する導電性ペースト焼成工程と、
    　を含むことを特徴とする光起電力装置の製造方法。     A first diffusion layer forming step of diffusing impurities of the second conductivity type on the light incident surface side of the first conductivity type semiconductor substrate to form a first diffusion layer;
    An insulating film forming step of forming an insulating film having a function of preventing reflection on the light incident surface on the first diffusion layer;
    An opening forming step of forming a plurality of openings having a diameter smaller than the size of the surface electrode so that the first diffusion layer is exposed in the formation region of the surface electrode of the insulating film;
    A conductive paste applying step of applying a conductive paste whose components are adjusted so as not to erode the insulating film during firing on a formation region of the surface electrode including the opening; and
    A conductive paste baking step of baking the conductive paste;
    A method for manufacturing a photovoltaic device, comprising:
  2. 　前記開口部形成工程の後で前記導電性ペースト塗布工程の前に、
    　前記第２の導電型の不純物を、前記絶縁膜に形成された前記開口部の底部で露出した前記第１の拡散層に拡散させる拡散処理工程をさらに含むことを特徴とする請求項１に記載の光起電力装置の製造方法。     After the opening forming step and before the conductive paste coating step,
    The diffusion process step according to claim 1, further comprising a diffusion process step of diffusing the second conductivity type impurity into the first diffusion layer exposed at a bottom of the opening formed in the insulating film. Manufacturing method of photovoltaic device.
  3. 　前記拡散処理工程の後、前記導電性ペースト塗布工程の前に、
    　前記拡散処理工程で形成された前記開口部の底部で露出した前記第１の拡散層の最表面をエッチングして除去する最表面除去工程をさらに含むことを特徴とする請求項２に記載の光起電力装置の製造方法。     After the diffusion treatment step and before the conductive paste application step,
    3. The light according to claim 2, further comprising an outermost surface removing step of etching and removing an outermost surface of the first diffusion layer exposed at a bottom portion of the opening formed in the diffusion treatment step. A method for manufacturing an electromotive force device.
  4. 　第１の導電型の半導体基板の光の入射面側に第２の導電型の不純物を拡散させて、第１の拡散層を形成する第１の拡散層形成工程と、
    　前記第１の拡散層上に前記光の入射面における反射を防止する機能を有する絶縁膜を形成する絶縁膜形成工程と、
    　前記絶縁膜のグリッド電極の形成領域には、連続したパターンで、バス電極の形成領域には、前記バス電極の寸法よりも小さい径の複数のドット状パターンで、焼成時に前記絶縁膜を侵食するように成分調整された導電性ペーストを塗布する導電性ペースト塗布工程と、
    　前記導電性ペーストを焼成する導電性ペースト焼成工程と、
    　を含むことを特徴とする光起電力装置の製造方法。     A first diffusion layer forming step of diffusing impurities of the second conductivity type on the light incident surface side of the first conductivity type semiconductor substrate to form a first diffusion layer;
    An insulating film forming step of forming an insulating film having a function of preventing reflection on the light incident surface on the first diffusion layer;
    The insulating film erodes the insulating film during firing with a continuous pattern in the grid electrode formation region and a plurality of dot-shaped patterns having a diameter smaller than the bus electrode size in the bus electrode formation region. A conductive paste application step for applying a component-adjusted conductive paste;
    A conductive paste baking step of baking the conductive paste;
    A method for manufacturing a photovoltaic device, comprising:
  5. 　第１の導電型の半導体基板の光の入射面側に第２の導電型の不純物を拡散させて、第１の拡散層を形成する第１の拡散層形成工程と、
    　前記第１の拡散層上に前記光の入射面における反射を防止する機能を有する絶縁膜を形成する絶縁膜形成工程と、
    　前記絶縁膜の表面電極の形成領域に、焼成時に前記絶縁膜を侵食するように成分調整された第１の導電性ペーストを、前記表面電極の寸法よりも小さい径の複数のドット状パターンに塗布する第１の導電性ペースト塗布工程と、
    　前記ドット状パターンが形成された前記表面電極の形成領域に、焼成時に前記絶縁膜を侵食しないように成分調整された第２の導電性ペーストを、前記複数のドット状パターン間を所定の形状につなぐ連続パターン状に塗布する第２の導電性ペースト塗布工程と、
    　前記第１および第２の導電性ペーストを焼成する導電性ペースト焼成工程と、
    　を含むことを特徴とする光起電力装置の製造方法。     A first diffusion layer forming step of diffusing impurities of the second conductivity type on the light incident surface side of the first conductivity type semiconductor substrate to form a first diffusion layer;
    An insulating film forming step of forming an insulating film having a function of preventing reflection on the light incident surface on the first diffusion layer;
    A first conductive paste whose components are adjusted so as to erode the insulating film during firing is applied to a plurality of dot-like patterns having a diameter smaller than the size of the surface electrode in the surface electrode forming region of the insulating film A first conductive paste applying step,
    A second conductive paste whose components are adjusted so as not to erode the insulating film during firing is formed in a predetermined shape between the plurality of dot-shaped patterns in the formation region of the surface electrode on which the dot-shaped patterns are formed. A second conductive paste application step for applying in a continuous pattern,
    A conductive paste baking step of baking the first and second conductive pastes;
    A method for manufacturing a photovoltaic device, comprising:
  6. 　第１の導電型の半導体基板の光の入射面側に第２の導電型の不純物を拡散させて、第１の拡散層を形成する第１の拡散層形成工程と、
    　前記第１の拡散層上に前記光の入射面における反射を防止する機能を有する絶縁膜を形成する絶縁膜形成工程と、
    　前記絶縁膜の表面電極の形成領域に、焼成時に前記絶縁膜を侵食するように成分調整された第１の導電性ペーストを、前記表面電極の寸法よりも小さい径の複数のドット状パターンに塗布する第１の導電性ペースト塗布工程と、
    　前記第１の導電性ペーストを焼成する第１の導電性ペースト焼成工程と、
    　前記ドット状パターンが形成された前記表面電極の形成領域に、前記複数のドット状パターンを前記表面電極の形状につなぐ連続パターン状に電極層を形成する電極層形成工程と、
    　を含むことを特徴とする光起電力装置の製造方法。     A first diffusion layer forming step of diffusing impurities of the second conductivity type on the light incident surface side of the first conductivity type semiconductor substrate to form a first diffusion layer;
    An insulating film forming step of forming an insulating film having a function of preventing reflection on the light incident surface on the first diffusion layer;
    A first conductive paste whose components are adjusted so as to erode the insulating film during firing is applied to a plurality of dot-like patterns having a diameter smaller than the size of the surface electrode in the surface electrode forming region of the insulating film A first conductive paste applying step,
    A first conductive paste baking step of baking the first conductive paste;
    An electrode layer forming step of forming an electrode layer in a continuous pattern connecting the plurality of dot-shaped patterns to the shape of the surface electrodes in the formation region of the surface electrode in which the dot-shaped pattern is formed;
    A method for manufacturing a photovoltaic device, comprising:
  7. 　前記電極層形成工程は、
    　前記ドット状パターンが形成された前記表面電極の形成領域に、焼成時に前記絶縁膜を侵食しないように成分調整された第２の導電性ペーストを、前記複数のドット状パターンを前記表面電極の形状につなぐ連続パターン状に塗布する第２の導電性ペースト塗布工程と、
    　前記第２の導電性ペーストを前記第１の導電性ペースト焼成工程での焼成温度よりも低い温度で焼成する導電性ペースト焼成工程と、
    　を含むことを特徴とする請求項６に記載の光起電力装置の製造方法。     The electrode layer forming step includes
    In the formation region of the surface electrode on which the dot-shaped pattern is formed, the second conductive paste whose component is adjusted so as not to erode the insulating film during baking, and the plurality of dot-shaped patterns are formed in the shape of the surface electrode. A second conductive paste coating step for coating in a continuous pattern,
    A conductive paste firing step of firing the second conductive paste at a temperature lower than a firing temperature in the first conductive paste firing step;
    The method for manufacturing a photovoltaic device according to claim 6, comprising:
  8. 　前記電極層形成工程では、前記ドット状パターンが形成された前記表面電極の形成領域に、前記複数のドット状パターンを前記表面電極の形状につなぐ連続パターン状に、メッキ処理によって前記電極層を形成することを特徴とする請求項６に記載の光起電力装置の製造方法。 In the electrode layer forming step, the electrode layer is formed by a plating process in a continuous pattern connecting the plurality of dot-like patterns to the shape of the surface electrode in the formation region of the surface electrode where the dot-like pattern is formed. A method for manufacturing a photovoltaic device according to claim 6.
PCT/JP2008/060795 2008-06-12 2008-06-12 Photovoltaic device manufacturing method WO2009150741A1 (en)

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