WO2009145918A1 - Système de calcul évolutif et unifié - Google Patents

Système de calcul évolutif et unifié Download PDF

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Publication number
WO2009145918A1
WO2009145918A1 PCT/US2009/003316 US2009003316W WO2009145918A1 WO 2009145918 A1 WO2009145918 A1 WO 2009145918A1 US 2009003316 W US2009003316 W US 2009003316W WO 2009145918 A1 WO2009145918 A1 WO 2009145918A1
Authority
WO
WIPO (PCT)
Prior art keywords
scalable
texture
texel data
data
unified
Prior art date
Application number
PCT/US2009/003316
Other languages
English (en)
Inventor
Michael J. Mantor
Jeffrey T. Brady
Mark C. Fowler
Marcos P. Zini
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to JP2011511650A priority Critical patent/JP5491498B2/ja
Priority to EP09755281.4A priority patent/EP2297723A4/fr
Priority to CN200980119829.0A priority patent/CN102047315B/zh
Priority to KR1020107029824A priority patent/KR101427408B1/ko
Publication of WO2009145918A1 publication Critical patent/WO2009145918A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/04—Texture mapping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Definitions

  • the present invention generally relates to computing operations performed by computing systems, and more particularly to graphics processing tasks performed by computing systems.
  • a graphics processing unit is a complex integrated circuit that is specially configured to carry out graphics processing tasks.
  • a GPU can, for example, execute graphics processing tasks required by an end-user application, such as a video game application.
  • an end-user application such as a video game application.
  • graphics processing tasks required by an end-user application, such as a video game application.
  • an end-user application such as a video game application.
  • the end-user application communicates with an application programming interface (API).
  • API allows the end-user application to output graphics data and commands in a standardized format, rather than in a format that is dependent on the GPU.
  • Several types of APIs are commercially available, including DirectX® developed by Microsoft Corp. and OpenGL® developed by Silicon Graphics, Inc.
  • the API communicates with a driver.
  • the driver translates standard code received from the API into a native format of instructions understood by the GPU.
  • the driver is typically written by the manufacturer of the GPU.
  • the GPU then executes instructions from the driver.
  • a GPU produces, by carrying out a process known as "rendering” creates individual pixels that together form an image based on a higher level description of image components.
  • a GPU typically carries out continuous rendering using pipelines to process pixel, texture, and geometric data. These pipelines are often referred to as a collection of fixed function special purpose pipelines such as rasterizers, setup engines, color blenders, hieratical depth, texture mapping and programmable stages that can be accomplished in shader pipes or shader pipelines, "shader” being a term in computer graphics referring to a set of software instructions used by a graphic resource primarily to perform rendering effects.
  • GPU's can also employ multiple programmable pipelines in a parallel processing design to obtain higher throughput.
  • a multiple of shader pipelines can also be referred to as a shader pipe array.
  • GPUs also support texture mapping.
  • Texture mapping is a process used to determine the texture color for a texture mapped pixel through the use of the colors of nearby pixels of the texture, or texels. The process is also referred to as texture smoothing or texture interpolation.
  • texture smoothing or texture interpolation.
  • high image quality texture mapping requires a high degree of computational complexity.
  • GPUs equipped with a Unified Shader also simultaneously support many types of shader processing, from pixel, vertex, primitive, surface and generalized compute are raising the demand for higher performance generalized memory access capabilities.
  • the present invention includes method and apparatus related to a row based Scalable and Unified Compute Unit Module.
  • the Scalable and Unified Compute Unit Module includes a shader pipe array and texture mapping unit with a level one cache system to perform texture mapping and general load/store accesses with the ability to process shader pipe data destined to a defective shader pipe.
  • the Scalable and Unified Compute System comprises a sequencer, Scalable and Unified Compute Unit Module with access to a level two texture cache system and thus an external memory system.
  • the Scalable and Unified Compute System is configured to accept an executing shader program instruction including input, output, ALU and texture or general memory load/store requests with address data from the shader pipes and program constants to generate the return texel or memory data based on state data controlling the pipelined address and filtering operations for a specific pixel or thread.
  • the texture filter system is configured based on the shader program instruction and constant to generate a formatted interpolation based on texel data stored in the cache system for the addresses stored in the shader pipeline.
  • the row based shader pipe Scalable and Unified Compute System further comprises a redundant shader pipe system.
  • the redundant shader pipe system is configured to process shader pipe data destined to a defective shader pipes in the shader pipe array.
  • the System further comprises a level two texture cache system.
  • the level two texture cache system can be read and written to by any level one row based texture cache system.
  • the texture filter in the texture mapping unit in the Scalable and Unified Compute Unit Module further comprises a pre- formatter module, an interpolator module, an accumulator module, and a format module.
  • the pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format.
  • the interpolator module is configured to perform an interpolation on the normalized fixed point texel data from the pre-formatter module and generate re-normalized floating point texel data.
  • the accumulator module is configured to accumulate floating point texel data from the interpolator module to achieve the desired level of bilinear, trilinear, and anisotropic filtering.
  • the format module is configured to convert texel data from the accumulator module into a standard floating point representation.
  • FIG. 1 is a system diagram depicting an implementation of a Scalable and Unified Compute System.
  • FIG. 2 is a system diagram depicting an implementation of a Scalable and Unified Compute System illustrating the details of the shader pipe array.
  • FIG. 3 is a system diagram depicting an implementation of a Scalable and Unified Compute System illustrating the details of the texture mapping unit.
  • FIG. 4 is a flowchart depicting an implementation of a method for a
  • the invention relates to a Scalable and Unified Compute System whereby a shader pipe array processes shader program instructions on input pixel, vertex, and primitive, surface or compute work items to create output data for each item using generated texel data or memory load/store operations, hi embodiments of this invention, bilinear texture mapping, trilinear texture mapping, and anisotropic texture mapping are applied to the texel data that is stored in a multi-level cache system.
  • a redundant shader system can be added and configured to process shader pipe data directed to defective shader pipes within the shader pipe array to recover devices with a defective sub-circuit in one or more shader pipes.
  • Embodiments of this invention that have configurations containing two or more Scalable and Unified Compute Systems, a subset of the Unified Compute Unit System itself can be configured to be a repairable unit, hi such an embodiment workloads destined to a defective Unified Compute Unit System will instead be sent to a redundant Unified Compute Unit System to process all ALU, texture, and memory operations. This increases the portion of the device that is covered by repair significantly due to the inclusion of texture mapping unit and Ll cache system and thus significantly improves on the yield of such a device.
  • an embodiment indicates that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to incorporate such a feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • FIG. 1 is an illustration of a Scalable and Unified Compute System 100 according to an embodiment of the present invention.
  • System 100 comprises a sequencer 110, a Scalable and Unified Compute Unit Module 120, and a level two cache system 130.
  • Scalable and Unified Compute Unit Module 120 comprises a shader pipe array 122, optional redundant shader pipe array 124, texture mapping unit 126, and level one texture cache system 128.
  • Shader pipe array 122 performs ALU operations on input data.
  • Sequencer 110 controls the shader program instruction issue for contained workloads and the flow of data through shader pipe array 122.
  • sequencer 110 reacts to defective shader pipes that occur within shader pipe array 122 by scheduling instructions to the appropriate redundant units.
  • Sequencer 110 can issue a texture fetch or load/store operation that will initiate shader pipe array 122 to send addresses with the instruction issued to texture mapping unit 126.
  • texture mapping unit 126 generates appropriate addresses to the level one texture cache system 128 that contains texel data or memory data associated with the addresses.
  • Level one cache system 128, after receiving the addresses, will return the associated texel or memory data to texture mapping unit 126.
  • the request is forwarded to a level two cache system 130 obtain and return the requested texel data.
  • FIG. 2 is an illustration of a Scalable and Unified Compute Unit
  • Shader pipe array 122 comprises one or more shader pipe blocks, here represented as SP_O through SP_M, where "M" represents a positive integer greater than one.
  • redundant shader pipe array 124 In an embodiment where redundant shader pipe array 124 is present, if sequencer 110 identifies, as an example, that the shader pipe located in shader pipe block SP_1 is defective, then the shader pipe data destined to the defective pipe would be sent to redundant shader pipe array 124 via the input stream by the input module and processed by redundant shader pipe array 124. All texture mapping requests would be intercepted by redundant shader pipe array 124 when instructed via horizontal control path 211 from sequencer 110. Once redundant shader pipe array 124 processes the shader pipe data initially destined to the defective shader pipe, the processed redundant shader pipe array 124 data would be transferred from redundant shader pipe array 124 back to the output stream of shader pipe 122 and realigned in an output unit (not shown).
  • redundant shader pipe array 124 consists of a single block, and therefore can only process shader pipe data destined to a single defective shader pipe at a time. In another embodiment wherein redundant shader pipe array 124 comprises multiple redundant shader blocks, then redundant shader pipe array 124 can process shader pipe data destined to more than one defective shader pipe simultaneously.
  • FIG. 3 illustrates a more detailed view of texture mapping unit 126 according to an embodiment of the present invention.
  • shader pipe array 122 generates a texture or memory load/store request to texture mapping unit 126 that comprises an address generator system 318, a pre-formatter module 310, an interpolator module 312, an accumulator module 314, and a format module 316.
  • the texture mapping unit 126 receives a request from shader arrays 122 and 124 and sequencer 110 respectively, and processes the instruction in address generator system 318 to determine the actual addresses to service.
  • the resultant texel data is sent back to the requesting resource in shader pipe array 122 and/or redundant shader pipe array 124.
  • Pre-formatter module 310 is configured to receive texel data and perform a block normalization thereby generating normalized fixed point texel data.
  • Interpolator module 312 receives the normalized fixed point texel data from pre-formatter module 310 and performs one or more interpolations, each of that are accumulated in accumulator module 314, to achieve the desired level of bilinear, trilinear, and anisotropic texture mapping.
  • Format module 316 converts the accumulated texel data in accumulator module 314 to a standard floating point representation for the requesting resource, shader pipe array 122. For general load/store data pre-formatter module 310, interpolator module 312, accumulator module 314, and format module 316 pass the requested return data unmodified.
  • FIG. 3 also illustrates the use of a level two cache system 130.
  • the level two cache system is additional memory that is available to Scalable and Unified Computer Unit Module 120 when it is necessary or desirable to read and/or write data from and to the level one cache system 128.
  • FIG. 4 is a flowchart depicting a method 400 for texture mapping using a Scalable and Unified Compute System.
  • Method 400 begins at step 402.
  • a shader pipe receives set texture requests from a sequencer for a specific set of pixels, vertices, primitives, surfaces, or computer work items.
  • the shader pipe generates data set addresses based on shader program instructions for the specified set of pixels, vertices, primitives, surfaces, or compute work items.
  • a texture mapping unit retrieved stored texel data from a level one and/or level two texture cache system.
  • the texture mapping unit calculates a formatted accumulated interpolation based on the retrieved texel data and the originating shader instruction.
  • Method 400 ends at step 412.
  • 3, and 4 can be implemented in software, firmware, or hardware, or using any combination thereof. If programmable logic is used, such logic can execute on a commercially available processing platform or a special purpose device.
  • HDL hardware description language
  • Verilog Verilog
  • VHDL hardware description language
  • the HDL-design can model the behavior of an electronic system, where the design can be synthesized and ultimately fabricated into a hardware device, hi addition, the HDL-design can be stored in a computer product and loaded into a computer system prior to hardware manufacture.

Abstract

L'invention concerne un système de calcul évolutif et unifié exécutant des opérations de nuançage graphique et des opérations générales de réparation évolutives, des opérations de chargement/stockage de mémoire et un filtrage de texture. Un module d'unité de calcul évolutif et unifié comprend un réseau de pipelines de nuançage, une unité de mappage de textures, et un système de mémoire cache de textures de niveau un. Le module d'unité de calcul évolutif et unifié accepte des instructions ALU, des instructions d'entrées/sorties et des demandes de texture ou de mémoire pour un ensemble spécifié de pixels, de sommets, de primitives, de surfaces, ou des éléments de travail de calcul général provenant d'un programme de nuançage, et exécute des opérations associées pour calculer les données de sortie programmées. L'unité de mappage de textures accepte des adresses de données sources et des constantes d'instruction afin de récupérer, formatter, et exécuter des interpolations de filtrage demandées pour générer des résultats formattés en fonction des données spécifiques correspondantes stockées dans le système de mémoire cache de textures de niveau un. L'unité de mappage de texture comprend un système de génération d'adresses, un module de pré-formattage, un module d'interpolation, un module d'accumulation et un module de formattage. L'invention concerne également un système de calcul évolutif et unifié.
PCT/US2009/003316 2008-05-30 2009-06-01 Système de calcul évolutif et unifié WO2009145918A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2011511650A JP5491498B2 (ja) 2008-05-30 2009-06-01 拡大縮小可能で且つ統合化されたコンピュータシステム
EP09755281.4A EP2297723A4 (fr) 2008-05-30 2009-06-01 Système de calcul évolutif et unifié
CN200980119829.0A CN102047315B (zh) 2008-05-30 2009-06-01 可扩展及整合的计算系统
KR1020107029824A KR101427408B1 (ko) 2008-05-30 2009-06-01 스케일링가능하고 통합된 컴퓨팅 시스템

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5748308P 2008-05-30 2008-05-30
US61/057,483 2008-05-30

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WO2009145918A1 true WO2009145918A1 (fr) 2009-12-03

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EP (1) EP2297723A4 (fr)
JP (1) JP5491498B2 (fr)
KR (1) KR101427408B1 (fr)
CN (1) CN102047315B (fr)
WO (1) WO2009145918A1 (fr)

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CN109559367A (zh) * 2017-09-25 2019-04-02 Arm有限公司 图形纹理映射设备及其操作方法以及存储介质
CN110930493A (zh) * 2019-11-21 2020-03-27 中国航空工业集团公司西安航空计算技术研究所 一种gpu纹素并行获取方法
CN109559367B (zh) * 2017-09-25 2024-05-17 Arm有限公司 图形纹理映射设备及其操作方法以及存储介质

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KR101926570B1 (ko) 2011-09-14 2018-12-10 삼성전자주식회사 포스트 프레그먼트 쉐이더를 사용하는 그래픽 처리 방법 및 장치
KR101862785B1 (ko) 2011-10-17 2018-07-06 삼성전자주식회사 타일 기반 렌더링을 위한 캐쉬 메모리 시스템 및 캐슁 방법
US10089708B2 (en) * 2016-04-28 2018-10-02 Qualcomm Incorporated Constant multiplication with texture unit of graphics processing unit
CN109614086B (zh) * 2018-11-14 2022-04-05 西安翔腾微电子科技有限公司 基于SystemC和TLM模型的GPU纹理缓冲区数据存储硬件及存储装置
CN112581575B (zh) * 2020-12-05 2024-05-03 西安翔腾微电子科技有限公司 一种外视频做纹理系统

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CN109559367B (zh) * 2017-09-25 2024-05-17 Arm有限公司 图形纹理映射设备及其操作方法以及存储介质
CN110930493A (zh) * 2019-11-21 2020-03-27 中国航空工业集团公司西安航空计算技术研究所 一种gpu纹素并行获取方法

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Publication number Publication date
CN102047315A (zh) 2011-05-04
KR20110019764A (ko) 2011-02-28
JP2011524562A (ja) 2011-09-01
EP2297723A4 (fr) 2015-08-19
EP2297723A1 (fr) 2011-03-23
JP5491498B2 (ja) 2014-05-14
CN102047315B (zh) 2015-09-09
KR101427408B1 (ko) 2014-08-07

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