EP2297723A4 - Système de calcul évolutif et unifié - Google Patents

Système de calcul évolutif et unifié

Info

Publication number
EP2297723A4
EP2297723A4 EP09755281.4A EP09755281A EP2297723A4 EP 2297723 A4 EP2297723 A4 EP 2297723A4 EP 09755281 A EP09755281 A EP 09755281A EP 2297723 A4 EP2297723 A4 EP 2297723A4
Authority
EP
European Patent Office
Prior art keywords
scalable
compute system
unified compute
unified
compute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09755281.4A
Other languages
German (de)
English (en)
Other versions
EP2297723A1 (fr
Inventor
Michael J Mantor
Jeffrey T Brady
Mark C Fowler
Marcos P Zini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP2297723A1 publication Critical patent/EP2297723A1/fr
Publication of EP2297723A4 publication Critical patent/EP2297723A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/04—Texture mapping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
EP09755281.4A 2008-05-30 2009-06-01 Système de calcul évolutif et unifié Withdrawn EP2297723A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5748308P 2008-05-30 2008-05-30
PCT/US2009/003316 WO2009145918A1 (fr) 2008-05-30 2009-06-01 Système de calcul évolutif et unifié

Publications (2)

Publication Number Publication Date
EP2297723A1 EP2297723A1 (fr) 2011-03-23
EP2297723A4 true EP2297723A4 (fr) 2015-08-19

Family

ID=41377445

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09755281.4A Withdrawn EP2297723A4 (fr) 2008-05-30 2009-06-01 Système de calcul évolutif et unifié

Country Status (5)

Country Link
EP (1) EP2297723A4 (fr)
JP (1) JP5491498B2 (fr)
KR (1) KR101427408B1 (fr)
CN (1) CN102047315B (fr)
WO (1) WO2009145918A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101926570B1 (ko) 2011-09-14 2018-12-10 삼성전자주식회사 포스트 프레그먼트 쉐이더를 사용하는 그래픽 처리 방법 및 장치
KR101862785B1 (ko) 2011-10-17 2018-07-06 삼성전자주식회사 타일 기반 렌더링을 위한 캐쉬 메모리 시스템 및 캐슁 방법
US10089708B2 (en) * 2016-04-28 2018-10-02 Qualcomm Incorporated Constant multiplication with texture unit of graphics processing unit
GB2566733B (en) * 2017-09-25 2020-02-26 Advanced Risc Mach Ltd Performimg convolution operations in graphics texture mapping units
CN109614086B (zh) * 2018-11-14 2022-04-05 西安翔腾微电子科技有限公司 基于SystemC和TLM模型的GPU纹理缓冲区数据存储硬件及存储装置
CN110930493A (zh) * 2019-11-21 2020-03-27 中国航空工业集团公司西安航空计算技术研究所 一种gpu纹素并行获取方法
CN112581575A (zh) * 2020-12-05 2021-03-30 西安翔腾微电子科技有限公司 一种外视频做纹理系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104415A (en) * 1998-03-26 2000-08-15 Silicon Graphics, Inc. Method for accelerating minified textured cache access
US20060055695A1 (en) * 2004-09-13 2006-03-16 Nvidia Corporation Increased scalability in the fragment shading pipeline
US20070211070A1 (en) * 2006-03-13 2007-09-13 Sony Computer Entertainment Inc. Texture unit for multi processor environment
US20080094407A1 (en) * 2006-06-20 2008-04-24 Via Technologies, Inc. Systems and Methods for Storing Texture Map Data

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3645024B2 (ja) * 1996-02-06 2005-05-11 株式会社ソニー・コンピュータエンタテインメント 描画装置及び描画方法
US7136068B1 (en) * 1998-04-07 2006-11-14 Nvidia Corporation Texture cache for a computer graphics accelerator
US6771264B1 (en) * 1998-08-20 2004-08-03 Apple Computer, Inc. Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor
US6525737B1 (en) * 1998-08-20 2003-02-25 Apple Computer, Inc. Graphics processor with pipeline state storage and retrieval
US6919895B1 (en) * 1999-03-22 2005-07-19 Nvidia Corporation Texture caching arrangement for a computer graphics accelerator
US6731303B1 (en) * 2000-06-15 2004-05-04 International Business Machines Corporation Hardware perspective correction of pixel coordinates and texture coordinates
US7124318B2 (en) * 2003-09-18 2006-10-17 International Business Machines Corporation Multiple parallel pipeline processor having self-repairing capability
CN1239023C (zh) * 2003-10-16 2006-01-25 上海交通大学 基于运动自适应和边缘保护的三维视频格式转换方法
KR100519779B1 (ko) * 2004-02-10 2005-10-07 삼성전자주식회사 깊이영상기반 3차원 그래픽 데이터의 고속 시각화 방법 및장치
US7385607B2 (en) * 2004-04-12 2008-06-10 Nvidia Corporation Scalable shader architecture
US7577869B2 (en) * 2004-08-11 2009-08-18 Ati Technologies Ulc Apparatus with redundant circuitry and method therefor
JP2006244426A (ja) * 2005-03-07 2006-09-14 Sony Computer Entertainment Inc テクスチャ処理装置、描画処理装置、およびテクスチャ処理方法
JP4660254B2 (ja) * 2005-04-08 2011-03-30 株式会社東芝 描画方法及び描画装置
WO2007049610A1 (fr) * 2005-10-25 2007-05-03 Mitsubishi Electric Corporation Processeur d'image

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104415A (en) * 1998-03-26 2000-08-15 Silicon Graphics, Inc. Method for accelerating minified textured cache access
US20060055695A1 (en) * 2004-09-13 2006-03-16 Nvidia Corporation Increased scalability in the fragment shading pipeline
US20070211070A1 (en) * 2006-03-13 2007-09-13 Sony Computer Entertainment Inc. Texture unit for multi processor environment
US20080094407A1 (en) * 2006-06-20 2008-04-24 Via Technologies, Inc. Systems and Methods for Storing Texture Map Data

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
MARCO CHIAPPETTA: "ATI Radeon HD 2900 XT - R600 Has Arrived - Architectural Overview (Cont.)", 14 May 2007 (2007-05-14), pages 1 - 3, XP055200921, Retrieved from the Internet <URL:http://hothardware.com/reviews/ati-radeon-hd-2900-xt--r600-has-arrived?page=3> [retrieved on 20150708] *
MIKE MANTOR: "2007 Hot Chips 19 AMD's Radeon(TM) HD 2900 2nd Generation Unified Shader Architecture", PROCEEDINGS OF 2007 IEEE HOT CHIPS 19 SYMPOSIUM (HCS), 20 August 2007 (2007-08-20), Stanford University, pages 1 - 13, XP055200868, Retrieved from the Internet <URL:http://www.hotchips.org/wp-content/uploads/hc_archives/hc19/2_Mon/HC19.03/HC19.03.01.pdf> [retrieved on 20150708] *
See also references of WO2009145918A1 *

Also Published As

Publication number Publication date
CN102047315A (zh) 2011-05-04
JP5491498B2 (ja) 2014-05-14
KR20110019764A (ko) 2011-02-28
JP2011524562A (ja) 2011-09-01
EP2297723A1 (fr) 2011-03-23
CN102047315B (zh) 2015-09-09
KR101427408B1 (ko) 2014-08-07
WO2009145918A1 (fr) 2009-12-03

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Legal Events

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RA4 Supplementary search report drawn up and despatched (corrected)

Effective date: 20150716

RIC1 Information provided on ipc code assigned before grant

Ipc: G09G 5/00 20060101AFI20150710BHEP

Ipc: G09G 5/36 20060101ALN20150710BHEP

Ipc: G06T 15/04 20110101ALI20150710BHEP

Ipc: G06T 15/00 20110101ALI20150710BHEP

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Effective date: 20171219

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Owner name: ADVANCED MICRO DEVICES, INC.

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Effective date: 20191014