WO2009140305A1 - Matériau à électron corrélé et procédé de fabrication - Google Patents

Matériau à électron corrélé et procédé de fabrication Download PDF

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Publication number
WO2009140305A1
WO2009140305A1 PCT/US2009/043668 US2009043668W WO2009140305A1 WO 2009140305 A1 WO2009140305 A1 WO 2009140305A1 US 2009043668 W US2009043668 W US 2009043668W WO 2009140305 A1 WO2009140305 A1 WO 2009140305A1
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cem
layer
titanium nitride
layers
state
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PCT/US2009/043668
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English (en)
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Jolanta Celinska
Carlos A. Paz De Araujo
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Symetrix Corporation
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the invention in general relates to integrated circuit memories, and in particular, to the formation of non-volatile integrated circuit memories containing materials which exhibit a change in resistance.
  • RRAM variable resistance memory
  • Typical materials vary and include GeSbTe, where Sb and Te can be exchanged with other elements of same properties on the periodic table. These materials are often referred to as chalcogenides. See, for example, Stephan Lai, "Current Status of the Phase Change Memory and Its Future", Intel Corporation,
  • variable resistance memory category includes materials that require an initial high "forming" voltage and current to activate the variable resistance function. These materials include Pr x Ca y Mn z O ⁇ , with x, y, z and e of varying stoichiometry, transition metal oxides, such as CuO, CoO, VO x , NiO, TiO 2 , Ta 2 Os, and some perovskites such as Cr; SrTi ⁇ 3. See, for example, "Resistive Switching Mechanisms Of TiO 2 Thin Films Grown By Atomic-Layer Deposition", B. J.
  • the invention provides an integrated circuit resistive switching component comprising: a resistive switching cell, including a correlated electron material (CEM), wherein the CEM and and a switching circuit for placing the resistive switching cell in a first resistive state and a second resistive state, wherein the resistance of the second resistive state is higher than the first resistive state; characterized in that the CEM material includes at least one bulk layer and at least one capping layer, the capping layer having a different carbon content then the bulk layer.
  • the capping layer has a higher carbon content than the bulk layer.
  • the CEM contains three or more of the layers, each of the layers having a different carbon content.
  • the invention also provides a method of making an integrated circuit resistive memory, the method comprising depositing a correlated electron material (CEM) including a transition metal, the method comprising depositing a first precursor solution to form a first layer of the CEM and then depositing a second precursor solution to form a second layer of the CEM, the method characterized by the first precursor solution having a different molarity of the transition metal than the second precursor solution.
  • the second precursor solution has a lower molarity of the transition metal than the first precursor solution.
  • the second precursor solution has a molarity of 0.2M.
  • the second precursor solution has a molarity of a 0.1 M.
  • the method further comprises depositing three or more of the layers, each of the layers being deposited with a different precursor solution, thereby forming a graded CEM.
  • the invention provides a resistive switching memory cell comprising: a bottom electrode; a top electrode; and correlated electron material (CEM) between the top and bottom electrodes; the resistive switching memory cell characterized in that the bottom electrode comprises at least two different metals, the metals selected from platinum, tungsten, titanium nitride, and aluminum.
  • the bottom electrode is composed of a first layer of titanium nitride, a layer of tungsten, and a second layer of titanium nitride.
  • the first layer of titanium nitride is 100-300 angstroms thick
  • the layer of tungsten is 100-300 angstroms thick
  • the second layer of titanium nitride is 100-300 angstroms thick.
  • the top electrode is composed of titanium nitride and aluminum.
  • the top electrode is composed of a first layer of titanium nitride, a layer of aluminum, and a second layer of titanium nitride.
  • the first layer of titanium nitride is 200 angstroms thick
  • the layer of aluminum is 500 angstroms thick
  • the second layer of titanium nitride is 200 angstroms thick.
  • the cell further comprises an interfacial dielectric limiting the contact between the bottom electrode and the CEM.
  • the invention provides, a resistive switching memory that is stable both with respect to temperature and time.
  • FIG. 1 shows the current in amperes versus bias voltage in volts curves for an NiO resistor
  • FIG. 2 is the same curves as shown in FIG. 1 except on a logarithmic scale which shows higher resolution at the smaller values of current;
  • FIG. 3 illustrates a silicon wafer with CEM "elements” comprising a CEM material sandwiched between two electrodes;
  • FIG. 4 shows a cross-sectional view of one of the "elements” of FIG. 3 taken through the line 4-4 of FIG. 3;
  • FIG. 5 is a graph of voltage versus current illustrating the SET and RESET functions for an NiO element having a diameter of 50 microns;
  • FIG. 6 is a graph of voltage versus current illustrating the SET and RESET functions for an NiO element with the CEM material doped with 5% cobalt and having a diameter of 50 microns;
  • FIG. 7 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, illustrating the ON, OFF, RESET, and SET modes
  • FIG. 8 is an illustration of the energy bands of a Mott-Hubbard insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani;
  • FIG. 9 is an illustration of the energy bands of a charge transfer type insulator taken from Introduction to the Electron Theory of Metals by Uichiro Mizutani;
  • FIG. 10 is an Arrhenius curve of the log of 1/Tau versus MT[MK) for prior art sputtered NiO (without carbon) illustrating that the transition from the high resistance state to the low resistance state is caused by detrapping of electrons from oxygen vacancies in the sputtered NiO;
  • FIG. 1 1 shows a graph of Kelvin temperature versus resistance in Ohms for the ON and OFF states for a CEM thin film and for a prior art thin film that crystallizes in the OFF state and requires forming before exhibiting variable resistance
  • FIG. 12 is a graph of number of reading cycles versus resistance in Ohms for the ON and OFF states for a CEM thin film, demonstrating that there is little or no fatigue;
  • FIG. 13 is a graph of current versus voltage on a linear scale of a CEM film formed according to an embodiment of a method for forming CEM films;
  • FIG. 14 is a graph of current versus voltage on a logarithmic scale of a CEM film
  • FIG. 15 is a graph of voltage versus current for a film of a 0.1 M solution
  • FIG. 16 is a graph of current versus voltage for the film of a 0.2M solution after one day of recovery and four days of recovery;
  • FIG. 17 is a graph of current versus voltage after hysteresis for the film of a 0.2M solution after one day of recovery and four days of recovery;
  • FIG. 18 is a graph of voltage versus current for a smooth film of 0.2M solution Of NiO;
  • FIG. 19 is a graph of current versus voltage for the deposition of three bulk layers of NiO 0.2M solution followed by various numbers of capping layers of NiO 0.1 M solution;
  • FIG. 20 is a graph of current versus voltage after full hysteresis for the deposition of three bulk layers of NiO 0.2M solution followed by various numbers of capping layers of NiO 0.1 M solution;
  • FIG. 21 is a graph of SET and RESET voltages versus cycle number for uncapped NiO layers
  • FIG. 22 is a graph of SET and RESET voltages versus cycle number for capped NiO layers
  • FIGS. 23 - 25 are graphs of current versus voltage for various sizes of CEM resistors
  • FIG. 26 is a graph of Poisson yield analysis for various sized resistors
  • FIG. 27 is a graph of the number of devices off versus the device area
  • FIG. 28 is a graph of surface feature density versus radius
  • FIG. 29 is a graph of feature density versus radius
  • FIG. 30 is a graph of current versus voltage showing the reset for various locations on a wafer;
  • FIG. 31 is a graph of the fatigue for reading cycles;
  • FIG. 32 is a graph of the current versus voltage for the OFF state of a CEM at various temperatures
  • FIG. 33 is a graph of the degradation of the OFF state resistance versus temperature
  • FIG. 34 is a diagram of a liquid source misted chemical deposition system
  • FIGS. 35a and b are graphs of the effect of scaling on OFF and ON States
  • FIGS. 36a and b are graphs of cycling for a 10 x 10 micrometer CeRam
  • FIGS. 37a and b show graphs for the first three sweeps for a 10 x 10 micrometer CeRam;
  • FIGS. 38a and b show graphs of initial sweeps for a CeRam with a capping layer
  • FIGS. 39a and b show graphs of the initial reset current for a capped CeRam
  • FIGS. 40a and b show graphs of current vs. voltage for a 5 x 5 micrometer CeRam
  • FIGS. 41 a and b show graphs of current vs. voltage for a 5 x 5 micrometer CeRam with a patterned bottom electrode vs. a non-patterned;
  • FIGS. 42a and b are graphs of cycling for a 5 x 5 micrometer CeRam;
  • FIGS. 43a and b show graphs for the first three sweeps for a 5 x 5 micrometer CeRam;
  • FIGS. 44a and b show graphs for the first three sweeps for a 3 x 3 micrometer CeRam
  • FIGS. 45a and b show graphs of current vs voltage for a 3 x 3 micrometer CeRam; and FIGS. 46a and b are graphs of cycling for a 3 x 3 micrometer CeRAM.
  • the present disclosure provides transition metal oxides as exemplary correlated electron materials (CEM), though the methods and systems are applicable to other CEM materials as well.
  • Nickel oxide, NiO is disclosed as the exemplary transition metal oxide.
  • the exemplary NiO materials discussed herein are doped with extrinsic ligands which stabilize the variable resistance properties. In general, this may be written as NiO(Lx), where Lx is a ligand element or compound and x indicates the number of units of the ligand for one unit of NiO.
  • Lx is a ligand element or compound
  • x indicates the number of units of the ligand for one unit of NiO.
  • One skilled in the art can determine the value of x for any specific ligand and any specific combination of ligand with NiO or any other transition metal, simply by balancing valences.
  • the preferred NiO variable resistance materials disclosed herein include at least a ligand containing carbon, which may indicated by NiO(Cx).
  • a Correlated Electron Material is a material that switches from a first resistive state to a second resistive state, with the second resistive state having a resistance at least one hundred times higher than the first resistance state, and the change in resistance is primarily due to correlations between the electrons.
  • the resistance of the second state is at least two hundred times the resistance of the first state, and most preferably, five hundred times.
  • these materials include any transition metal oxide, such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators.
  • transition metal oxide such as perovskites, Mott insulators, charge exchange insulators, and Anderson disorder insulators.
  • Several embodiments representing switching materials are nickel oxide, cobalt oxide, iron oxide, yttrium oxide, and perovskites such as Cr doped strontium titanate, lanthanum titanate, and the manganate family including praesydium calcium manganate and praesydium lanthanum manganate.
  • oxides incorporating elements with incomplete d and f orbital shells exhibit CEM resistive switching properties.
  • resistance can be changed by setting at one voltage and resetting at a second voltage.
  • no electroforming is required to prepare a CEM.
  • This disclosure contemplates that many other transition metal compounds can be used. For example, ⁇ M(chxn)2Br ⁇ Br2 where M can be Pt, Pd, or Ni, and chxn is 1 R,2R-cyclohexanediamine, and other such metal complexes may be used.
  • G (q2pmpNiO/hm)T, where q is the electron charge, pm is the density of states in the electrode, pNiO is the density of states in the nickel oxide, m is the mass of the charge carrier, and T is the transmission probability through the film.
  • CEM memory materials A number of advances to the technology of CEM materials is explained below. Briefly, these advances relate to a number of aspects of CEM memory materials. The discussion herein, includes, but is not limited to the following advances: the usage of a capping layer, annealing in methane, a higher carbon in the surface, the usage of a graded extrinsic ligand, and the choice of electrodes.
  • FIG. 1 shows the current in amperes (amps) versus bias voltage in volts curves for an NiO(Cx) CEM.
  • FIG. 2 shows the same curves except the absolute value of the current is plotted logarithmically to show more detail in the low current values.
  • RESET point the point at which the CEM changes in resistance from a conductor to an insulator
  • SET point the point at which the resistance changes from an insulator to a conductor
  • the CEMs are crystallized in the conducting state. We shall refer to this as the ON state and the insulative state will be called the OFF state.
  • the solid line 40 is the ON state curve for positive voltages and the solid line 60 is the ON curve for negative voltages.
  • the dotted line 54 is the OFF curve for positive voltages, while the dotted line 62 is the OFF curve for negative voltages.
  • the current rises at 47, until the RESET voltage is reached, which is about 0.65 volts, which is also the point at which critical electron density is reached, then, at point 48 the material suddenly becomes insulative and the current drops sharply along curve 49.
  • the current stays low along the line 52 as the voltage rises until the SET voltage is reached at about 1.65 volts, which corresponds to the Neel temperature for these materials, at which point the material again becomes conductive and the current rises along line 54.
  • FIG. 4 shows a cross-section through element 80 taken through line 4-4 of FIG. 3.
  • Element 80 is formed on a silicon substrate 82 having a silicon dioxide coating 84.
  • a thin layer 86 of titanium or titanium oxide may be formed on oxide layer 84, though the elements reported on herein did not have such a layer.
  • a bottom electrode layer 88 is formed on either layer 86 or directly on oxide layer 84.
  • Layer 86 is an adhesion layer to assist the bottom electrode layer 88 in adhering to silicon dioxide layer 84.
  • CEM material 90 (composed of a transition metal oxide is formed on bottom electrode 88, preferably by a liquid deposition process, such as spin coating, misted deposition, CVD or atomic layer deposition. The deposition of the CEM material will be described in greater detail below.
  • top electrode 92 is formed on CEM layer 90.
  • the elements 77, 80, etc. are then patterned by etching down to bottom electrode 88.
  • the CEM material is subjected to a recovery annealing.
  • an inter-layer dielectric 94 is deposited. At this point a contact vias 96 is added.
  • CEM integrated circuit elements such as interconnect metallization, further interconnection etching, passivation, etc.
  • interconnect metallization such as interconnect metallization, further interconnection etching, passivation, etc.
  • passivation such as interconnect metallization, interconnection etching, passivation, etc.
  • the CEM integrated circuit element appears to have no fundamental issues with mainstream metallization processes and materials that are know to those skilled in the art.
  • the bottom electrode layer 88 may be formed of Titanium Nitride (TiN) and Tungsten (W).
  • the electrode is formed with a layer of TiN, followed by a layer of W, followed by a layer of TiN.
  • the bottom electrode layer 88 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of W, and a 200 angstrom layer of TiN.
  • the top electrode layer 92 may be formed of Titanium Nitride (TiN) and
  • the electrode is formed with a layer of TiN, followed by a layer of Al, followed by a layer of TiN.
  • the top electrode layer 92 is formed by a 200 angstrom layer of TiN, a 200 angstrom layer of Al, and a 200 angstrom layer of TiN.
  • the bottom electrode layer 88 and the top electrode layer 92 may be formed of platinum.
  • a stack configuration of Si/SiO2/TiOx/Pt/NiO/Pt is used.
  • the top and bottom electrodes are formed of platinum (top electrode 92 and bottom electrode 88).
  • the adhesion layer 86 is titanium oxide.
  • a stack configuration of Si/SiO2/ Pt/NiO/Pt is used, omitting the adhesion layer 86.
  • a top layer of TiN may be deposited over layer 92. This top layer is used as a hard mark. It may be in a range of thicknesses from 10nm to 200nm. In one alternative it is 60 nm thick.
  • the various elements 77, 88 can then be tested by attaching one probe to platinum surface 88 and touching a fine probe to the top electrode, such as 92, of the element to be tested, such as 80.
  • the various curves discussed below were generated in this manner.
  • FIG. 1 the term "metal" when referring to an electrode or other wiring layer generally means a conductor. As known in the art, such "metal" electrodes and/or wiring layers can be made of polysilicon or other conductive material and are not necessarily made of metal.
  • FIG. 7 shows an idealized current versus voltage curve for a resistive switching film with unipolar switching, to better illustrate the ON, OFF, RESET, and SET modes.
  • the material is crystallized in the ON state and the current rises along the ON curve as voltage is increased up VRESET. The current then drops to the OFF curve and increases gradually along the OFF curve until VSET is reached, at which point it increases toward the ON curve. However, in devices, the current is limited the dotted line, lset to prevent overcurrent. The read and write margins are shown in the figure. As shown by FIGS. 6 and 7, the NiO(Cx) films follow these idealized curves better than any prior art material.
  • the CEMs are typically oxides formed from elements that have a partially filled 3d band and materials with partially filled 3f bands in the Periodic Table.
  • the most well known of these oxides are vanadium oxide and nickel oxide.
  • the materials with partially filled 3d bands or partially filled 3f bands are sometimes described also as Metal/Insulator phase transition materials.
  • Such metallic to insulator transition can also occur in combining transition metals with other materials of systems such as sulfides, iodines, tellurides, and others that do not involve oxygen.
  • CEMs Correlated Electron Materials
  • MCS Mott-Bardeen Switch
  • a switch between masses sets the state of the material from insulator to metal (and vice-versa) by increasing or decreasing the interaction energy relative to the energy gap.
  • change in the electron mass was attained mainly by a change in temperature, and these materials were studied for their thermodynamic properties, implying a change in physical structure.
  • the electronic transitions due to correlated electrons occur at room temperature or over a useful temperature region for device operation, and in both polarities of the applied voltage.
  • phase change is used herein with respect to a CEM, it relates to the change of an electronic phase.
  • the transition causes a hysteresis of the current versus voltage characteristic yielding two resistive states which are stable for an undetermined period of time producing a non-volatile memory behavior.
  • Such memories are quite promising because they are not only non-volatile, but the electronic phase change is resistant to radiation damage and the memories can be made very dense.
  • a CEM with a single conducting electrode and the other surface contacted to an insulator or another CEM will be called “Metal/CEM Bardeen Barrier” or an “MCB barrier”, better described by what is known in the literature as a "Bardeen Transfer Hamiltonian” which, when used with different effective mass tensors across the metal to CEM barrier, with or without the aid of vacancies, describes well the metal to CEM tunneling with an effective mass switch occurring as the electron enters the CEM from the common metal electrode, and an electronic phase transition is caused which produces the switching action; and when such an MCB barrier is in contact to a semiconducting material such as polysilicon which is a common floating gate material, this shall be called an "MCB to floating gate switch".
  • extrinsic ligand-forming dopants are added to the transition metal compounds.
  • correlated electron switching can occur in materials other than materials including ligands.
  • the extrinsic ligands stabilize the metals in the compounds to a stable valence state. With such stabilization, electroforming is no longer necessary.
  • stabilized means with respect to both time and temperature.
  • the electrical properties critical to reliable memory operation including the RESET voltage, the SET voltage, and the memory window, i.e., the voltage or capacitance difference between the non-conducting and conducting states, does not change more than thirty percent over operational time period and temperature range, i.e., over a time period of three years, and more preferably, five years, and most preferably, ten years, and a temperature range from 0 0 C to 60 0 C, more preferably from -20 0 C to 80 0 C, and most preferably from -50 0 C to 100 0 C. More preferably, these electronic parameters do not change more then twenty-five percent, and most preferably, they do not change more than twenty percent.
  • ligands may be less useful than others because they are not stabilizing under all circumstances.
  • ligands stabilize the orbital valence states, and particularly the 3d orbital states.
  • the complex [Ti(H2O)6]3+ is not stabilizing for conventional CMOS processing because when it is annealed the water evaporates leaving uncompensated titanium, which can take many different valence states. Such a material will require electroforming. However, it can be stabilizing in other processes.
  • the preferred ligands comprise one or more elements selected from the group consisting of oxygen, hydrogen, fluorine, carbon, nitrogen, chlorine, bromine, sulphur, and iodine.
  • Ligand field theory was developed in the 1930's and 1940's as an extension of crystal field theory. See for example, "Ligand Field Theory” in Wikepedia, the free encyclopedia at http://en.wikipedia.org/wik/Ligand _field theory, which is incorporated by reference herein to the same extent as though fully disclosed herein.
  • ⁇ O the energy difference between certain molecular orbitals
  • the stability of the memory window between the OFF state and the on state is substantially proportional to the stability of ⁇ O.
  • the preferred dopant ligands are those which result in a large and stable ⁇ O.
  • Some useful dopant ligands in descending order of the size of the ⁇ O they create are: CO, CN-, PPh3, NO2-, phen (1 ,10-phenanthroline, biby (2,2'-bipyhdine), en (enthylenediamine), NH3, py (pyridine), CH3CN, NCS-, H2O, C2O42-, OH-, F-, N3-, N03-, Cl-, SCN-, S2-, Br-, and I-.
  • the crystal field splitting energy ( ⁇ O) is not directly related to the Mott-charge transfer barrier or the Rice-Brickman mass.
  • the stability of the metal-native ligand coordination sphere allows the electron-electron correlations inductive of these transitions to occur in a particular material as the nuances of the bonding and crystal structures are set in place.
  • the technical relevant effect is to control or stabilize the oxidation number (or coordination sphere) in such a way the local stoichiometry is "nominal" or otherwise suitable to induce the necessary electron correlation conditions.
  • Extrinsic ligand or "dopant ligand” is defined herein to be the ligand material added to transition metal complexes to stabilize the multiple valence states of the transition metals.
  • the ligand splits the d-orbitals.
  • dopant because the ligand complex is an extrinsic material added to the lattice that is not intrinsic to the lattice structure of the transition metal compound.
  • the oxygen is an intrinsic ligand
  • (C0)4 in forming Ni(CO)4
  • Ni(CO)4 is the extrinsic ligand.
  • other variants such Ni5(CO)12 (nickel carbonate) include a form of CO as extrinsic ligands to the basic NiO lattice. This is analogous to the use of the term dopant in semiconductor technology. That is, in semiconductor technology adding a dopant to silicon, for example, does not change the silicon so much that we refer to it as another compound.
  • the dopant ligand added to say, nickel oxide does not change the fact that the material is nickel oxide. But, local correction of the many possible oxidation numbers (valences) of Ni, such as Ni vacancies, interstitials and oxygen vacancies that modify the nominal "+2" valence value, is achieved with ligands that mediate with the intrinsic ligand yielding a stable net oxidation number and eliminate the defect induced change in charge state.
  • the band structure of correlated electron materials is complex and depends not only on the d-orbitals of the transition metals but also on the p-orbitals of the neighboring oxygen atoms. This is explained in detail in Introduction to the Electron Theory of Metals, Uichiro Mizutani, Cambridge University Press, Cambridge, UK, 2001 , particularly pages 444 - 447. Figures 14.9(a) and 14.9(b) from page 446 of this book are reproduced herein at FIGS. 13 and 14.
  • the ⁇ used in this section is different than the discussed above, so we shall refer to it as ⁇ t, since it is the charge transfer energy, i.e., the energy to transfer of 3d electrons to the oxygen atom.
  • U is the d-orbital coulomb energy, sometimes referred to as the correlation energy
  • EF is the Fermi level of the transition metal.
  • the p-orbital of the intrinsic ligand splits the d- orbital which tends to stabilize the d-orbital valence, yielding a net oxidation state of zero, for example, Ni+20-2.
  • the insulator is a charge-transfer insulator, which leads to lower operating voltages.
  • correlated electron systems in which ⁇ t ⁇ U are preferred systems.
  • the d-orbitals 194 and 195 split with the filled p-orbital valence band between them.
  • One d-orbital 194 is essentially filled, while the other 196 is empty. It requires a large amount of energy for electrons to jump from the lower band 194 into the upper band 196. And, even if a d-d transition could occur with the aid of a hole in the p-orbital band, this requires a higher voltage, which is useful in the insulator to metal transition but not in the metal to insulator transition.
  • this material will be an insulator with high resistance when the lower voltage induces a metal to insulator transition purely caused by increasing the local density of electrons.
  • some electrons will begin to jump to the upper band 196.
  • the metal-ligand-anion (MLA) bond which stabilizes the correlated electron material in some embodiments can be formed in many ways. For example, it may be formed in an anneal or other reaction process.
  • the CEMs may be annealed in a gas that contains the ligand chemical element, the anion element, and preferably also includes both the ligand element and the anion. Any gas incorporating any of the ligands above may be used.
  • the gas may be formed through conventional precursor vaporization processes, such as heating and bubbling.
  • the CEM may be reactive sputtered in a gas containing the ligand chemical element, the anion or both. Again, any of the ligands above may be used.
  • CO and CO2 are possible annealing gases.
  • the anneal may be performed with one or more of these gases, or may be performed in a mixture of an inert gas, such as argon or nitrogen, with the gas containing either the ligand element, the anion element, or both.
  • an inert gas such as argon or nitrogen
  • Electron liquid refers to the state of heavy mass and this "electron condensation" phenomenon
  • electron gas refers to the uncorrelated electron.
  • Electron liquids such as in the Landau theory of "Fermi- liquids” are still a very immature area of condensed matter physics and the term is used here only to describe highly correlated electrons, as in the liquid state, versus non interacting electrons as in the electron gas.
  • FIG. 10 is an Arrhenius curve of the log of 1/Tau versus 1/T(1/K) for prior art sputtered NiO (without carbon) illustrating that the transition from the high resistance state to the low resistance state is caused by detrapping of electrons from oxygen vacancies in the sputtered NiO.
  • the relaxation time for the material to return to the insulative state after SET, Tau was measured for a number of temperatures in the working range of a proposed variable resistance memory (below 70 0 C) for NiO films made by sputtering and without including any carbon ligand.
  • the slope of the Arrhenius curve 960 is proportional to the activation energy for the mechanism that is causing the relaxation.
  • 1 1 shows a graph of Kelvin temperature versus resistance in Ohms for the ON and OFF states for a CEM thin film and for a prior art thin film that crystallizes in the OFF state and requires forming before exhibiting variable resistance.
  • the ON and OFF states vary only a little with temperature over the entire 400 0 K temperature range. Both curves rise a little at the higher temperatures. The rise is essentially uniform for both the ON and OFF state, so the resistance window remains essentially the same.
  • a memory made with the CEM material will be stable over any temperature range that memories should be stable over.
  • the OFF state changes linearly with temperature, while the conducting state is essentially flat.
  • the resistance window changes by more than 500%.
  • the memory window changes by about over 100%. This prior art material clearly could not be used in a memory.
  • FIG. 12 is a graph of number of reading cycles versus resistance in Ohms for the ON and OFF states for a CEM thin film. Measurements were made at both 25 0 C and 85 0 C. Reading fatigue measures the resistance in Ohms versus number of read cycles, where a read cycle comprises the application of a read voltage of one volt across the resistance element for a sufficient time to come to equilibrium with a reference voltage, followed by the removal of the voltage for a sufficient time to come to equilibrium at zero voltage. The measurements of reading fatigue were made for both the ON state and the OFF state at 85 0 C and 25°C. The ON state was measured out to 1010 cycles and the OFF state was measured only to 108 cycles because of time constraints.
  • the vacancy coordination sphere is the region about an ion or electron in which vacancies can affect the ion or electron. As shown by FIG, 16, vacancies within this vacancy coordination sphere trap electrons which are subsequently thermally detrapped. This destabilizes the high resistance state. This is the principle reason for the instability of prior art variable resistance materials. In the materials, the effect of the oxygen vacancies is cancelled, by the ligand structure of the CeRAM materials. As shown by FIG. 12, the resistance states of the CEMs are thermally stable. This further demonstrates vacancy coordination passivation.
  • n-type, p-type, n+, p+, etc. the specific type of semiconductor has been specified, e.g., n-type, p-type, n+, p+, etc.
  • n-type, p-type, n+, p+, etc. those skilled in the art will recognize that other types may be used.
  • most devices work essentially the same if n-type is replaced with p-type and p-type replaced with n-type.
  • platinum electrodes have been given as examples, those skilled in the art will recognize that such electrodes are preferably formed with a thin adhesive layer of titanium, and that the entire literature of oxide structures on platinum/titanium electrodes and the top electrode literature involving platinum, titanium, tungsten, and other materials can be applied.
  • gallium arsenide, germanium, germanium/silicon and other semiconductor technologies can be substituted.
  • metal or “M” is used herein to indicate any suitable conductor, including metals such as platinum and tungsten, or polysilicon or other conventional conductors known in the art.
  • the resistor or CEM cell dimensions for the formed memory switching device is approximately 10 by 20 micrometers.
  • the Pt/NiO/Pt CEM cell exhibits memory switching behavior, similar to that described in reference to FIG. 1 .
  • the solid lines depict the Off-state.
  • FIG. 20 shows the results of testing 2 types of electrodes a tungsten electrode and a tungsten titanium nitride. As shown, as the temperature rises a thicker layer of interfacial dielectric forms. The tungsten titanium nitride electrode appears to yield thinner interfacial dielectric layers and therefore was used in further testing.
  • a resistor composed of CEM material for one embodiment has dimensions of approximately 20 X 20 micrometers. Since the CEM material for this resistor is estimated to have a feature density of approximately 1 feature for 100 square micrometers, the expected dimensions of the resistor are 10 X 10 micrometers. One reason that a resistor of 20 X 20 micrometers exhibits memory switching is due to the interfacial dielectric material that forms over the bottom electrode due to the 450 degree anneal. This may limit the contact area of the bottom electrode with the CEM resistor.
  • CEM resistors One technique that may be employed in the construction of CEM resistors is intentionally limiting the contact area by forming an interfacial dielectric so that the CEM resistor exhibits memory switching due to the limited contact area. Through this procedure, CEM resistors with a greater estimated feature density may be utilized.
  • the deposition of the CEM material is one aspect of fabrication which may be accomplished via multiple techniques.
  • One such deposition technique is referred to as spin-on deposition.
  • spin on deposition a liquid is dispensed onto a wafer surface while the wafer is rapidly rotated in order to uniformly distribute the liquid.
  • the material is solidified using a low temperature bake.
  • Other techniques for deposition may include liquid source chemical deposition and those deposition techniques known to those skilled in the art.
  • metalorganic deposited NiO is used in as the CEM.
  • a bottom electrode is deposited.
  • the bottom electrode may be a platinum electrode with a silicon base.
  • Spin-on deposition is used for the deposition of NiO.
  • the CEM is annealed at a temperature of 450 degrees Celsius in a diffusion furnace.
  • a top electrode is deposited and photoresist is applied.
  • the stack is etched to achieve the desired size components.
  • the molarity of the solution used has an effect on whether the CEM material has memory switching function.
  • the results of a deposition of a NiO deposition with a 450 degree anneal are shown in FIG. 15.
  • a 0.10M solution yields a smooth film with no discernable features or irregularities.
  • the detection of features may be accomplished by way of a scanning electron microscope.
  • this smooth film exhibits threshold switching characteristics, causing it less likely to be suitable for memory applications.
  • FIGS. 16-17 show the result of a 0.15M deposition and a 450 degree anneal.
  • a 0.15M solution yields a film with a spotty appearance, suggesting the existence of irregularities or morphological features in the deposited CEM material. These irregularities are filamentous carbon.
  • FIG. 16 initially, the result of this deposition yields threshold switching characteristics. After aging (FIG. 17), this film takes on the characteristics of memory switching.
  • FIG. 34 shows the result of a 0.20M deposition and a 450 degree anneal.
  • the use of a 0.20M solution yields a high density of irregularities or morphological features.
  • the morphological features appear to be in a vein in trench like pattern.
  • the film resulting from this deposition initially is in the "on” state (FIG. 34). However, despite voltage increases, the resistance of the material is very low and no "reset" is possible.
  • veins For deposition using a 0.2M solution as the number of layers deposited increase the veins take on the appearance of filamentatious carbon. After one layer is deposited, vein like patterns can be detected. At two layers of deposited NiO, the veins take on a hexagonal packing and the spacing of the veins decreases. At three and four layers the veins appear to be filamentatious carbon and the veins propagate into the hexagonal packing.
  • the vein in trench pattern has a trench width of 0.2 to 0.3 micrometers. The vein spacing appears to be approximately 1 micrometer. With two layers of deposition, the vein to vein spacing shrinks to approximately 0.75 micrometers. At 3 layers of deposition and above the veins appear to be 50 nanometer filamentatious carbon in 0.2 micrometer trenches. Furthermore, the veins propagate into the hexagonal patterns. The veins are thought to be filamentatious carbon deposits.
  • capping may be used to change the function of the CEM.
  • Table 3 shows the results of capping 0.2M layers.
  • Three uncapped layers of NiO deposited by 0.2M solution does not result in memory switching characteristics, nor does three layers capped by 2 layers of 0.1 M NiO solution.
  • Depositing four capping layers yields a CEM that is initially in the "on" state, however the resistance of the CEM is still too low for reset to occur. It is of note that this structure (3 layers of 0.2 M (bulk) capped with 4 layers of 0.1 M) functions similarly to a single layer resulting from the deposition of a 0.2M solution. Table 3
  • the deposition of 3 layers of 0.2M solution capped by 6 layers of 0.1 M solution yields a CEM that has memory switching properties.
  • the resulting CEM is Born-On, MS bipolar, and may be reset.
  • the capping layers reduce the initial on state reset current and at the same time preserve the born-on behavior.
  • capping layers reduces the set voltage of the CEM and cause the set voltage to be more precise. Furthermore, the precision in the reset value is improved by the addition of the capping layers. As smooth capping layers are added the prevalence of the vein patterns (features or irregularities) is reduced, resulting in a smoother fa ⁇ ade. The proper density of features appears to be important to the function of the CEM as a memory switch.
  • FIG. 19 depicts the initial trace for a the deposition of 3 layers of 0.2M solution capped by various numbers of layers of 0.1 M solution capping layers. As is shown in the graph, 0-4 capping layers yields a CEM film that does not exhibit memory switching. When six capping layers are used the CEM exhibits memory switching on its initial trace.
  • FIG. 20 shows a graph of the deposition of 3 layers of 0.2M solution capped by 6 layers of 0.1 M solution, exhibiting the memory switching of the CEM. The addition of capping layers may be used to reduce the initial On-state reset current and preserve born-on behavior for a CEM device.
  • a technique that may be utilized in forming CEM devices that exhibit memory switch may begin with the utilization of two types of CEM deposited materials: initially on CEM material with resistance so low that no reset is possible and CEM material that exhibits threshold switching (no matter what voltage is applied, the material only allows for so much current, i.e. as voltage increases, resistance increases).
  • Layers of threshold switching material may be added to an initially on CEM with no reset voltage. By the addition of layers of threshold switching CEM material, the initially on characteristic may be retained, however reset of the CEM device may become possible.
  • FIG. 21 shows set (solid circles) and reset voltages (empty circles) for a CEM device deposited according to a uniform deposition process where each layer of deposited CEM material is a result of the same deposition solution concentration.
  • FIG. 22 shows set and reset voltages for a bulk layer and capping layer process. As is clear, not only does the bulk layer and capping layer process yield memory switching, but the precision of the set and reset voltages is greater.
  • FIGS. 23-25 depicts the results of current versus voltages traces on varying size resistors formed by depositing three bulk layers using a 0.2M concentration of NiO that is capped by six smooth layers of 0.1 M NiO. It appears to be the case that in order for the resistors (or CEM memory cells) to register an initially on state, there must be at least one morphological feature or irregularity on the resistor. As can be seen from FIG. 31 , 70% of the 7.5 urn square resistors were initially in the off state, suggesting that only 30% of the resistors had at least one feature or irregularity. For the 10 urn square 70% of the resistors were initially on (and therefore had at least one surface feature). For the 15 urn square, 87.5% of resistors exhibited the on state.
  • the feature density may not be uniform across a deposited wafer. As can be seen in FIG. 27-28, the feature density is relatively constant in the center of the wafer (1 per 100 um2), however, beyond 20 mm from the center of the wafer, the feature density diverges.
  • the density of surface features may lead the function of the CEM as a memory device, so the uniformity of feature density may have a bearing on where CEMs are formed and the size of the CEM formed.
  • CEMs are formed in respect to the expected density of the wafer, such that each CEM has a high probability of having a single feature.
  • CEMs are formed by depositing three bulk layers using a 0.2M concentration of NiO capped by six smooth layers of 0.1 M NiO. The area of the CEMs are etched such that their area is 100 um2. In one alternative, the CEMs are only formed in the area of the wafer exhibiting relatively constant feature density (less than 20 mm from the center of the wafer).
  • FIGS. 29-30 show the correlation of feature density to initial reset current.
  • the middle feature density 2920, 3020 is about 0.01 features per micrometer squared.
  • different depositions are used yielding different feature densities.
  • the areas of the CEMs are determined in relation to the feature density, such that each CEM is likely to have one and only one feature. In one embodiment the area of the CEM is adjusted as the radius from the center of the wafer departs from the area of the wafer having a uniform density.
  • a CEM is used to achieve a distribution of vein patterns (features or irregularities) in order to achieve memory switching characteristics as described in reference to FIGS. 1 and 2. This is achieved as described above, by the proper distribution of vein patterns. This yields a CEM with on and off states where the off state has a resistance of at least 100 times that of the on state.
  • FIG. 31 shows the fatigue of the CeRAM memory cells at two temperatures, 25 degree Celsius and 85 degrees Celsius.
  • the 85 degree Celsius line 31 10 and the 25 degree Celsius line 3120 show a low level of fatigue.
  • the fatigue of a CEM device formed with 3 bulk layers of NiO 0.2M and 6 capping layers of NiO 0.1 M is low as shown by FIG. 31 .
  • the resistance of the off state does not degrade up to temperatures of 150 degrees Celsius.
  • FIG. 34 depicts an example of a liquid source misted chemical deposition
  • LSMCD LSMCD apparatus
  • LSMCD may be an effective technique for the deposition of CEM, since LSMCD typically yield an even deposition of substrate. Therefore, if LSMCD is used to deposit CEM, then variations in the morphological feature (filamentatious carbon) density may be reduced or eliminated. This would allow for a large percentage of the deposition area to be utilized without compensating for variations in feature density by modifying the area of the memory cell.
  • LSMCD allows for controlled depositions of 4 - 100 nanometers. The layers of CEM deposited are generally in this range. Each bulk layer deposited is typically on the order of 100 angstroms or 10 nanometers.
  • the LSMCD apparatus includes a LSMCD module 3410, a wafer handler 3420, a LTP/RTP module 3430 (Low Temperature Processing (LTP) module, and rapid thermal annealed in the Rapid Thermal Processing (RTP) module), and a wafer loadlock 3440.
  • LTP/RTP module 3430 Low Temperature Processing (LTP) module, and rapid thermal annealed in the Rapid Thermal Processing (RTP) module
  • RTP Rapid Thermal Processing
  • the LSMCD module 3410 is expanded and includes a wafer spinner 3465, a wafer 3470, a field screen 3475, a shower head 3480, a mist channel 3445, an atomizer 3450, a liquid channel 3455 and a precursor reservoir 3460.
  • FIGS. 35a and b show the effect of scaling on the on and off state of the CeRAM memory cell.
  • FIG. 35a is for the OFF state and FIG. 35b is for the ON state.
  • Lines 3510 and 3540 are for a 10 x 10 micrometer cell.
  • Lines 3520 and 3550 are for a 5 x 5 micrometer cell.
  • Lines 3530 and 3560 are for a 3 x 3 micrometer cell.
  • the OFF state current does scale with the area of the device and the on stae does scale with the area of the device.
  • FIGS. 36 and 37 show results for 10 x 10 micrometer CeRAM devices.
  • FIGS. 37a b show results from the first three sweeps, where lines 3710 and 3740 show the initial sweep, lines 3720 and 3750 the second sweep, and lines 3730 and 3760 the third sweep.
  • FIGS. 38 show the initial sweep for a CeRAM with a capping layer as described above.
  • the lines correspond to various sizes of CeRAM devices: lines 3805, 3840 to 25 micrometers (square), lines 3815, 3845 to 15 micrometers (square), line 3820, 3850 to 10 micrometers (square), lines 3825, 3855 to 7.5 micrometers (square), lines 3830, 3860 to 5 micrometers (square), lines 3835, 3865 to 3 micrometers (square).
  • FIGS. 39a and b show the effect of the capping layer. The intent is that the intent is that the
  • CeRAM memory cell have a lower initial reset current but retain the born on property.
  • the standard CeRAM cell 3910 has a much higher reset current than the capped CeRAM cell 3920.
  • the cells remain Born-On, standard CeRAM cell 3930 and capped CeRAM cell 3940.
  • Table 4 shows one embodiment of the process flow for deposition of CeRAM devices.
  • the TMO is the NiO, although in alternative embodiments other extrinsic ligands may be used.
  • An additional interlayer dielectric structure may be deposited over a formed device as shown in steps 12-20. Table 4
  • the amount of carbon filaments on the surface of the CeRAM device may be utilized in step 7 of Table 4.
  • the TMO may be annealed in methane which increases the deposit of carbon.
  • This increase of carbon, which is believed to be filamentary carbon, on the surface can be used to create smaller devices, since the carbon assist in creating a CeRAM switching cell with the needed characteristics.
  • grading of the extrinsic ligand/TMO may be employed.
  • a device formed with a 0.5M solution through the bulk and 0.1 M or 0.2M solution on the surface may function to provide the needed carbon deposits on the surface of the device in alternative methodology to capping a 0.2M solution bulk.
  • FIGS. 40a and b show the results of a 5 x 5 micrometer CeRAM cell deposited according to the methodology of Table 4.
  • Lines 4010, 4030 show the ON curve for the CeRAM cell and lines 4020, 4040 shows the OFF curve.
  • FIGS. 41 a and b show the difference in the first three sweeps for planar bottom electrode (FIG. 41 a) versus a patterned bottom electrode (FIG. 41 b).
  • the initial sweep is line 41 10 with subsequent sweeps represented by line 4120, 4130, respectively.
  • the initial sweep is line 4140 with subsequent sweeps represented by line 4150, 4160, respectively.
  • FIGS. 42a and b show the compliance for the 5 x 5 micrometer CeRAM device.
  • the set points are shown as solid dots and the reset points are shown as open dots.
  • FIGS. 43a and b show results from the first three sweeps for a 5 x 5 micrometer CeRAM cell, where lines 4310 and 4340 show the initial sweep, lines 4320 and 4350 the second sweep, and lines 4330 and 4360 the third sweep.
  • FIGS. 44a and b show results from the first three sweeps for a 3 x 3 micrometer CeRAM cell, where lines 4410 and 4440 show the initial sweep, lines 4420 and 4450 the second sweep, and lines 4430 and 4460 the third sweep.
  • FIGS. 45a and b show the set and reset for a 3 x 3 micrometer CeRAM cell and a regular and logarithmic scale, respectively.
  • Lines 4510, 4530 are for the ON state and lines 4520, 4540 are for the OFF state.
  • FIGS. 46a and b show the compliance for the 3 x 3 micrometer CeRAM device.
  • the set points are shown as solid dots and the reset points are shown as open dots. Since certain changes may be made in the above systems and methods without departing from the scope of the invention, it is intended that all subject matter contained in the above description or shown in the accompanying drawings may be interpreted as illustrative and not in a limiting sense.

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Abstract

Selon l’invention, un composant de commutation résistif à circuit intégré comprend une cellule de commutation résistive, comprenant un matériau à électron corrélé (CEM) (90) entre une électrode inférieure (88) et une électrode supérieure (92). Le CEM comprend une pluralité de couches, ayant chacune une teneur en carbone différente. Les différentes couches sont de préférence formées à l’aide de précurseurs ayant une molarité différente. L’électrode inférieure est composée de tungstène et de nitrure de titane. L’électrode supérieure est composée de nitrure de titane et d’aluminium.
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US10121967B2 (en) 2016-11-29 2018-11-06 Arm Limited CEM switching device
WO2018100341A1 (fr) * 2016-11-29 2018-06-07 Arm Ltd Dispositif de commutation cem
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US10115473B1 (en) 2017-04-06 2018-10-30 Arm Ltd. Method, system and device for correlated electron switch (CES) device operation
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US11636316B2 (en) 2018-01-31 2023-04-25 Cerfe Labs, Inc. Correlated electron switch elements for brain-based computing
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US10833271B2 (en) 2018-03-23 2020-11-10 Arm Ltd. Method for fabrication of a CEM device
US11075339B2 (en) 2018-10-17 2021-07-27 Cerfe Labs, Inc. Correlated electron material (CEM) devices with contact region sidewall insulation
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US11201276B2 (en) 2020-02-13 2021-12-14 Cerfe Labs, Inc. Switch cell device

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