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• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/63—Vertical IGFETs
  • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/83—FETs having PN junction gate electrodes
  • H10D30/831—Vertical FETs having PN junction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
  • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
  • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor

Definitions

• this writing presents a high current density power field effect transistor.
• the present discussion relates to trench based high current density power semiconductor structures made by vertical integration of different kinds of semiconductor devices. Its low forward voltage and on-resistance characteristics at high current allow this normally-off device used as a synchronized rectifier transistor in DC-DC conversion application
• Power MOSFETs metal-oxide-semiconductor field-effect transistors
• a trench-based power MOSFET is built using a vertical structure as opposed to a planar structure.
• the vertical structure enables the transistor to sustain both high blocking voltage and high current.
• the component area and active device density are roughly proportional to the current it can sustain as a device "on” characteristics, and the silicon drift component thickness is proportional to the breakdown voltage as a device “off' characteristics.
• One the most obvious advantages for trench based power MOSFET device is its lower on-resistance (Rdson) with low reverse leakage current.
• a power MOSFET device has another advantage when being used as a synchronized rectifier transistor with its p-n body diode in a free-wheeling mode.
• the use of p-n body diode in conventional power MOSFET plays the role of reverse voltage blocking.
• the reverse recovery from the p-n body diode in the free wheeling mode contributes adversely to the total switching efficiency in DC-DC conversion.
• a p-n diode can be formed in the no body channel region.
• the direct connection between this p type to N+ source can help to reduce reverse leakage, however, the low on-resistance and low forward voltage advantages were not achieved.
• Embodiments here presented preferably implement high density power field effect transistor that avoids the channel mobility problems caused by gate oxide scattering, that exhibits lower forward voltage (Vf) rated at high current; and that shows shorter channel length for faster switching.
• This embodiment can apply to DC-DC conversion as a synchronized rectifier transistor.
• the device is implemented as a power field effect transistor device.
• the device includes a Schottky diode formed in a vertical trench contact, a junction FET (JFET) component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET.
• the JFET component, the vertical Schottky and the first accumulation MOSFET are configured to provide both current path in "on” mode and voltage blocking in "off' mode.
• the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.
• the second accumulation MOSFET 1 formed near the bottom of trench structure can also provide accumulated electrons in the current path when gate electrode is under positive bias for n-channel device, which can help to reduce on- resistance of this device.
• second accumulation MOSFET formed near the trench end can be replaced by a non-accumulation MOSFET with an isolated gate connected to the source.
• This structure is designed to show reduced gate to drain capacitance without changing reverse voltage blocking characteristics.
• the short channel length of this device is formed by defining the contact trench depth, the contact implantation and subsequence anneal relating to the gate trench depth.
• this writing discloses an ultra-short channel hybrid power field effect transistor (FET) device that lets current flow from bulk silicon without npn parasitic.
• the device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.
• Figure 1 shows forward voltage drop (Vf) under different current rating at two different junction temperatures of a device in accordance with one embodiment of the present invention.
• FIG. 2 shows on-resistance (Rdson) of this device measured at two different junction temperatures in accordance with one embodiment of the present invention.
• FIG. 3 shows a schematic cross-section view of a N channel power field effect transistor (FET) in accordance with a first embodiment of the present invention.
• FET field effect transistor
• FIG. 4 shows a schematic cross-section view of a N channel power field effect transistor (FET) in accordance with a second embodiment of the present invention.
• FET field effect transistor
• Figure 5 shows a diagram illustrating current flow implemented by a device in accordance with one embodiment of the present invention.
• Embodiments of the present invention are directed towards a high density power field effect transistor (FET) that reduces electron scattering due to carrier interference at the gate oxide layers.
• FET field effect transistor
• Embodiments of the present invention implement a power FET in which the high current flow of the device is primarily through the bulk silicon of the device as opposed to being along the surface of the channel (e.g., immediately adjacent to the gate oxide layer). This prevents the molecular structure of the gate oxide from inducing electron scattering. This results in a comparatively less channel mobility reduction due to gate oxide interface scattering effect for silicon device.
• Embodiments the present invention and their benefits are further described below.
• the geometry of the features of the power MOSFET components is commonly defined photographically through photolithography.
• the photolithography process is used to define component regions and build up components one layer on top of another.
• Complex devices can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer.
• the resulting topography of these complex devices often resemble familiar terrestrial "mountain ranges", with many "hills” and “valleys” as the device components are built up on the underlying surface of the silicon wafer.
• the general trend is to achieve vertical integration via more complex interconnects for lowing RC delay.
• Figure 1 shows forward voltage drop (Vf) under different current rating at two different junction temperatures of a device in accordance with one embodiment of the present invention
• Figure 2 shows on-resistance (Rdson) of this device measured at two different junction temperatures in accordance with one embodiment of the present invention.
• advantage of a device in accordance with embodiments of the present invention is the fact that the body diode formed without the "body” formation Eke conventional power MOSFET.
• the body diode has three key components: 1) JFET; 2) vertical Schottkey; and 3) p-n junction which is formed under the trench contact by implantation.
• This contact structure location relating to the gate trench height or depth is designed to ensure that N+ source and P+ contact axe not connected, so that a vertical Schottky device can be formed between N+ source and P+ contact in a vertical geometry.
• current can flow from this body diode from "source” to "drain” when gate is grounded.
• the total forward voltage drop (Vf) should come from all three components with a distribution depending on each junction's configuration.
• this device can provide synchronized FET function in a free-wheeling mode used in DC-DC conversion.
• a low forward voltage drop diode can be achieved at high current without Rdson trade-off in silicon real estate use.
• Figure 1 shows this forward voltage drop (Vf) under different current rating at two different junction temperatures, 150C and 25C.
• Figure 2 exhibits on-resistance (Rdson) of this device measured at two different junction temperatures, 125C and 25C.
• a new structure exhibits a vertical integration of Schottky diode, junction field effect transistor (JFET) and MOSFET at accumulation mode, formed in a trench structure.
• JFET junction field effect transistor
• MOSFET MOSFET
• this device Unlike conventional prior art power MOSFET which suffers from electron scattering effects due to the fact that the current flow tends to stay primarily at the surface of the device, the current flow of this vertically integrated structure is made by bulk conduction from silicon. This advantage of this device can avoid the molecular structure of the gate oxide induces electron scattering, which reduces the silicon channel mobility. Unlike ACCUFET 7 this device has build-in body diode even though there is no body. Compared with conventional power junction FET (JFET) which is driven by current, this device is still a voltage drive device, which can be "turned on” at relatively low drive voltage.
• JFET power junction FET
• the three advantages of this power device over conventional power MOSFET, JFET and ACCUFET are: 1) no parasitic npn in N-ch device which can help to improve device ruggness since there is no 'body" formed; 2) the "intrinsic" low forward voltage (Vf) function at high current rating can be achieved in active cells without compromising specific on-resistance; and 3) the channel length of this device is not defined by trench depth and body profile like trench power MOSFET, its channel length is much shorter in the range of 0.1 u to 0.4 u for N-ch device, defined by vertical Schottky and JFET geometries. An equivalent p-ch device can be formed if doping polarity is reversed.
• Figure 3 shows a schematic cross-section view of a N channel power
• the cross-section view of the hybrid power FET 100 shows a source 110 and 111, a drain 130 and 140, and the gates 120 and 121.
• the device 100 is a trench based vertical device structure. As shown in Figure 3, the source and drain regions are N+ doped. The bulk silicon of the device is N- and the substrate itself is N+. The gates 120 and 121 are N silicon with an oxide layer as shown.
• a source contact At the center of the device 100, as indicated by the region 155, is a source contact. This component has a tungsten contact disposed on top of a P+ gate as shown. This source contact component also implements two Schottkey regions 171 and 172.
• the dimension 150 defines the pitch of this device, which is in the range of 2.0 ⁇ to 0.5 ⁇ .
• the channel length is defined by the P+ implant and subsequent anneal.
• the channel width is defined by the dimensions 150 and 155, and the P+ implant lateral profile.
• the pitch 150 between the two gates 120 and 121 is less than 1 ⁇ .
• the width of the contact region 155 is typically less than 0.25 ⁇ .
• the width of the gate region 156 is typically less than 0.25 ⁇ .
• the depth 160 of the device 100 from the surface to the bottom of the gate region is typically less than 1 ⁇ .
• the device 100 can be implemented as a very high density device.
• the device 100 can be used to achieve densities of approximately 1 G cells per square inch, and higher.
• the structure of the device 100 is suited for self alignment trench contact during the fabrication process.
• the device 100 implements a "hybrid" type power MOSFET device with three major components.
• the term hybrid refers to the fact that the device 100 incorporates three different types of components to provide its functionality.
• the first type is the two accumulation MOSFETs with the gates 120 and 121.
• the second type is the JFET (e.g., under the region 155) at center of the device.
• the third type is the two Schottkey regions 171 and 172 adjacent to the drains 130 and 140.
• Figure 4 shows the second embodiment with different gate configuration.
• Figure 4 shows a schematic cross-section view of a N channel hybrid power FET 200 in accordance with one embodiment of the present invention.
• the bottom of the gate of device 200 is different from that of device 100.
• the bottom gate 290 as a second gate is isolated to connect with source.
• the device 200 is substantially similar to the device 100.
• the source and drain regions are N+ doped.
• the bulk silicon of the device is N- and the substrate itself is N+.
• the gates are N silicon with an oxide layer as shown.
• At the center of the device 200 is a source contact having a tungsten contact disposed on top of a P+ gate as shown. This source contact component also implements two Schottkey regions 271 and 272.
• Figure 5 shows a diagram illustrating current flow implemented by the device 100 in accordance with one embodiment of the present invention.
• the current flows through the bulk of the silicon of the device 100.
• the current flow is primarily through the buDc as opposed to being along the surface of the gate oxide. This provides a number of advantages in comparison to the prior art.
• the configuration of the device 100 does not have npn parasitic losses leading to a wider safe operating area.
• current flow is through the bulk of the device 100, which leads to less channel mobility reduction and reduced overall resistance of the device 100.
• the device 100 has a comparatively low threshold voltage.
• the threshold voltage is in the range of 1.0 V to 1.1 V.
• the low threshold voltage allows the device to be turned on with less than two battery cells.
• the device 100 exhibits an improved "raggedness" in comparison to prior art devices, since there is no inversion near the gate oxide.
• the device 100 also exhibits a lower forward voltage at high current rating and tins attribute can be obtained even without extra integrated Schottky or external Schottky diode.
• a hybrid power field effect transistor device comprising: a JFET component; a first accumulation MOSI 1 ET disposed adjacent to the JFET component; a second accumulation MOSFET disposed adjacent to the JFET component at the trench bottom end; and wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device.
• the device of concept 1 further comprising: a first Schottkey region disposed on the side of the JFET component; formed on a side wall of vertical contact trench, without connecting n+ source and p+ contact in an n-channel device.
• concept 3 The device of concept 1, wherein the first accumulation MOSFET and the second accumulation MOSFET include a thin oxide on a side trench wall and a thick gate oxide region near a trench bottom to reduce gate to drain capacitance.
• Concept 4 The device of concept 1 , wherein the first accumulation MOSFET and the second accumulation MOSFET are disposed in accordance with a high-density design layout to facilitate self aligned determination.
• a power MOSFET device comprising: a JFET component; a first accumulation MOSFET disposed adjacent to the JFET component; a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET; wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device; and wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are fabricated as a trench based a vertical structure.
• concept 10 The device of concept 9, further comprising: a first Schottkey region disposed on the side of the JFET component; and a second Schottkey region disposed on the side of the JFET component opposite the first Schottkey region.
• Concept 13 The device of concept 9, wherein the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.
• Concept 14 The device of iconcept 9, wherein the first accumulation MOSFET and the second accumulation MOSFET are N channel MOSFETS.
• a power FET device comprising: a JFET component; a first accumulation MOSFET disposed adjacent to the JFET component; a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET; a first Schottkey region disposed on the side of the JFET component; a second Schottkey region disposed on the side of the JFET component opposite the first Schottkey region; wherein the JFET component, the first accumulation MOSFET and the second accumulation MOSFET are configured to induce current flow through bulk silicon regions of the device.
• concept 17 The device of concept 16, wherein the first accumulation MOSFET and the second accumulation MOSFET include a thick lower oxide gate region to reduce gate to drain capacitance.
• Concept 18 The device of concept 16, wherein the first accumulation MOSFET and the second accumulation MOSFET are disposed in accordance with a high-density design layout to facilitate self aligned determination.

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• Electrodes Of Semiconductors (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Junction Field-Effect Transistors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Bipolar Integrated Circuits (AREA)

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