US8269263B2 - High current density power field effect transistor - Google Patents
High current density power field effect transistor Download PDFInfo
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- US8269263B2 US8269263B2 US12/119,367 US11936708A US8269263B2 US 8269263 B2 US8269263 B2 US 8269263B2 US 11936708 A US11936708 A US 11936708A US 8269263 B2 US8269263 B2 US 8269263B2
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
- H01L29/8083—Vertical transistors
Definitions
- Power MOSFETs metal-oxide-semiconductor field-effect transistors
- a trench-based power MOSFET is built using a vertical structure as opposed to a planar structure.
- the vertical structure enables the transistor to sustain both high blocking voltage and high current.
- the component area and active device density are roughly proportional to the current it can sustain as a device “on” characteristics, and the silicon drift component thickness is proportional to the breakdown voltage as a device “off” characteristics.
- Ron on-resistance
- a power MOSFET device has another advantage when being used as a synchronized rectifier transistor with its p-n body diode in a free-wheeling mode.
- the use of p-n body diode in conventional power MOSFET plays the role of reverse voltage blocking.
- the reverse recovery from the p-n body diode in the free wheeling mode contributes adversely to the total switching efficiency in DC-DC conversion.
- ACCUFET power switching device
- its bi-directional switching nature shows that the reverse and forward blocking are only kept in a finite duration because of the accumulation of minority carriers, which make the depletion width narrower. This effect limits the effectiveness of blocking capability.
- Yoshinori Konishi U.S. Pat. No. 5,844,273
- a p-n diode can be formed in the no body channel region. The direct connection between this p type to N+ source can help to reduce reverse leakage, however, the low on-resistance and low forward voltage advantages were not achieved.
- Embodiments of the present invention implement high density power field effect transistor that avoids the channel mobility problems caused by gate oxide scattering, that exhibits lower forward voltage (Vf) rated at high current; and that shows shorter channel length for faster switching.
- This invention can apply to DC-DC conversion as a synchronized rectifier transistor.
- the present invention is implemented as a power field effect transistor device.
- the device includes a Schottky diode formed in a vertical trench contact, a junction FET (JFET) component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component on the side opposite the first accumulation MOSFET.
- the JFET component, the vertical Schottky and the first accumulation MOSFET are configured to provide both current path in “on” mode and voltage blocking in “off” mode.
- the induced current flow through bulk silicon regions of the device is configured to reduce gate oxide scattering.
- the second accumulation MOSFET, formed near the bottom of trench structure can also provide accumulated electrons in the current path when gate electrode is under positive bias for n-channel device, which can help to reduce on-resistance of this device.
- second accumulation MOSFET formed near the trench end can be replaced by a non-accumulation MOSFET with an isolated gate connected to the source.
- This structure is designed to show reduced gate to drain capacitance without changing reverse voltage blocking characteristics.
- the short channel length of this device is formed by defining the contact trench depth, the contact implantation and subsequence anneal relating to the gate trench depth.
- FIG. 1 shows forward voltage drop (Vf) under different current rating at two different junction temperatures of a device in accordance with one embodiment of the present invention.
- FIG. 2 shows on-resistance (Rdson) of this device measured at two different junction temperatures in accordance with one embodiment of the present invention.
- FIG. 3 shows a schematic cross-section view of a N channel power field effect transistor (FET) in accordance with a first embodiment of the present invention.
- FET field effect transistor
- FIG. 4 shows a schematic cross-section view of a N channel power field effect transistor (FET) in accordance with a second embodiment of the present invention.
- FET field effect transistor
- FIG. 5 shows a diagram illustrating current flow implemented by a device in accordance with one embodiment of the present invention.
- Embodiments of the present invention are directed towards a high density power field effect transistor (FET) that reduces electron scattering due to carrier interference at the gate oxide layers.
- FET field effect transistor
- Embodiments of the present invention implement a power FET in which the high current flow of the device is primarily through the bulk silicon of the device as opposed to being along the surface of the channel (e.g., immediately adjacent to the gate oxide layer). This prevents the molecular structure of the gate oxide from inducing electron scattering. This results in a comparatively less channel mobility reduction due to gate oxide interface scattering effect for silicon device.
- Embodiments the present invention and their benefits are further described below.
- the geometry of the features of the power MOSFET components is commonly defined photographically through photolithography.
- the photolithography process is used to define component regions and build up components one layer on top of another.
- Complex devices can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer.
- the resulting topography of these complex devices often resemble familiar terrestrial “mountain ranges”, with many “hills” and “valleys” as the device components are built up on the underlying surface of the silicon wafer.
- the general trend is to achieve vertical integration via more complex interconnects for lowing RC delay.
- FIG. 1 shows forward voltage drop (Vf) under different current rating at two different junction temperatures of a device in accordance with one embodiment of the present invention
- FIG. 2 shows on-resistance (Rdson) of this device measured at two different junction temperatures in accordance with one embodiment of the present invention.
- advantage of a device in accordance with embodiments of the present invention is the fact that the body diode formed without the “body” formation like conventional power MOSFET.
- the body diode has three key components: 1) JFET; 2) vertical Schottky; and 3) p-n junction which is formed under the trench contact by implantation.
- This contact structure location relating to the gate trench height or depth is designed to ensure that N+ source and P+ contact are not connected, so that a vertical Schottky device can be formed between N+ source and P+ contact in a vertical geometry.
- current can flow from this body diode from “source” to “drain” when gate is grounded.
- the total forward voltage drop (Vf) should come from all three components with a distribution depending on each junction's configuration.
- this device can provide synchronized FET function in a free-wheeling mode used in DC-DC conversion.
- a low forward voltage drop diode can be achieved at high current without Rdson trade-off in silicon real estate use.
- FIG. 1 shows this forward voltage drop (Vf) under different current rating at two different junction temperatures, 150 C. and 25 C.
- FIG. 2 exhibits on-resistance (Rdson) of this device measured at two different junction temperatures, 125 C. and 25 C.
- a new structure exhibits a vertical integration of Schottky diode, junction field effect transistor (JFET) and MOSFET at accumulation mode, formed in a trench structure.
- JFET junction field effect transistor
- MOSFET MOSFET
- this device Unlike conventional prior art power MOSFET which suffers from electron scattering effects due to the fact that the current flow tends to stay primarily at the surface of the device, the current flow of this vertically integrated structure is made by bulk conduction from silicon. This advantage of this device can avoid the molecular structure of the gate oxide induces electron scattering, which reduces the silicon channel mobility. Unlike ACCUFET, this device has build-in body diode even though there is no body. Compared with conventional power junction FET (JFET) which is driven by current, this device is still a voltage drive device, which can be “turned on” at relatively low drive voltage.
- JFET power junction FET
- the three advantages of this power device over conventional power MOSFET, JFET and ACCUFET are: 1) no parasitic npn in N-ch device which can help to improve device ruggness since there is no “body” formed; 2) the “intrinsic” low forward voltage (Vf) function at high current rating can be achieved in active cells without compromising specific on-resistance; and 3) the channel length of this device is not defined by trench depth and body profile like trench power MOSFET, its channel length is much shorter in the range of 0.1 u to 0.4 u for N-ch device, defined by vertical Schottky and JFET geometries. An equivalent p-ch device can be formed if doping polarity is reversed.
- FIG. 3 shows a schematic cross-section view of a N channel power FET 100 in accordance with one embodiment of the present invention.
- the cross-section view of the hybrid power FET 100 shows a source 110 and 111 , a drain 130 and 140 , and the gates 120 and 121 .
- the device 100 is a trench based vertical device structure.
- the source and drain regions are N+ doped.
- the bulk silicon of the device is N ⁇ and the substrate itself is N+.
- the gates 120 and 121 are N silicon with an oxide layer as shown.
- At the center of the device 100 as indicated by the region 155 , is a source contact. This component has a tungsten contact disposed on top of a P+ gate as shown.
- This source contact component also implements two Schottky regions 171 and 172 . It should be noted that the bottom of the gate oxide is thicker than the side wall of the gate oxide layer. This attribute yields a lower gate to drain capacitance.
- the dimension 150 defines the pitch of this device, which is in the range of 2.0 ⁇ to 0.5 ⁇ .
- the channel length is defined by the P+ implant and subsequent anneal.
- the channel width is defined by the dimensions 150 and 155 , and the P+ implant lateral profile.
- the pitch 150 between the two gates 120 and 121 is less than 1 ⁇ .
- the width of the contact region 155 is typically less than 0.25 ⁇ .
- the width of the gate region 156 is typically less than 0.25 ⁇ .
- the depth 160 of the device 100 from the surface to the bottom of the gate region is typically less than 1 ⁇ .
- the device 100 can be implemented as a very high density device.
- the device 100 can be used to achieve densities of approximately 1 G cells per square inch, and higher.
- the structure of the device 100 is suited for self alignment trench contact during the fabrication process.
- the device 100 implements a “hybrid” type power MOSFET device with three major components.
- the term hybrid refers to the fact that the device 100 incorporates three different types of components to provide its functionality.
- the first type is the two accumulation MOSFETs with the gates 120 and 121 .
- the second type is the JFET (e.g., under the region 155 ) at center of the device.
- the third type is the two Schottky regions 171 and 172 adjacent to the drains 130 and 140 .
- FIG. 4 shows the second embodiment with different gate configuration.
- FIG. 4 shows a schematic cross-section view of a N channel hybrid power FET 200 in accordance with one embodiment of the present invention. It should be noted that the bottom of the gate of device 200 is different from that of device 100 . The bottom gate 290 as a second gate is isolated to connect with source. In other respects, the device 200 is substantially similar to the device 100 . As shown in FIG. 4 , the source and drain regions are N+ doped. The bulk silicon of the device is N ⁇ and the substrate itself is N+. The gates are N silicon with an oxide layer as shown. At the center of the device 200 is a source contact having a tungsten contact disposed on top of a P+ gate as shown. This source contact component also implements two Schottky regions 271 and 272 .
- FIG. 5 shows a diagram illustrating current flow implemented by the device 100 in accordance with one embodiment of the present invention.
- the current flows through the bulk of the silicon of the device 100 .
- the current flow is primarily through the bulk as opposed to being along the surface of the gate oxide. This provides a number of advantages in comparison to the prior art.
- the configuration of the device 100 does not have npn parasitic losses leading to a wider safe operating area. As described above, current flow is through the bulk of the device 100 , which leads to less channel mobility reduction and reduced overall resistance of the device 100 .
- the device 100 has a comparatively low threshold voltage.
- the threshold voltage is in the range of 1.0 V to 1.1 V.
- the low threshold voltage allows the device to be turned on with less than two battery cells.
- the device 100 exhibits an improved “raggedness” in comparison to prior art devices, since there is no inversion near the gate oxide.
- the device 100 also exhibits a lower forward voltage at high current rating and this attribute can be obtained even without extra integrated Schottky or external Schottky diode.
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
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Abstract
Description
Claims (18)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
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US12/119,367 US8269263B2 (en) | 2008-05-12 | 2008-05-12 | High current density power field effect transistor |
PCT/US2009/043518 WO2009140224A2 (en) | 2008-05-12 | 2009-05-11 | Power field effect transistor |
JP2011509604A JP5529854B2 (en) | 2008-05-12 | 2009-05-11 | Power field effect transistor |
EP09747308.6A EP2279525A4 (en) | 2008-05-12 | 2009-05-11 | Power field effect transistor |
KR1020107027427A KR101388821B1 (en) | 2008-05-12 | 2009-05-11 | Power field effect transistor |
CN2009801208752A CN102057490B (en) | 2008-05-12 | 2009-05-11 | Power field effect transistor |
TW098115682A TWI407565B (en) | 2008-05-12 | 2009-05-12 | Power field effect transistor |
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US12/119,367 US8269263B2 (en) | 2008-05-12 | 2008-05-12 | High current density power field effect transistor |
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US20090278176A1 US20090278176A1 (en) | 2009-11-12 |
US8269263B2 true US8269263B2 (en) | 2012-09-18 |
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US (1) | US8269263B2 (en) |
EP (1) | EP2279525A4 (en) |
JP (1) | JP5529854B2 (en) |
KR (1) | KR101388821B1 (en) |
CN (1) | CN102057490B (en) |
TW (1) | TWI407565B (en) |
WO (1) | WO2009140224A2 (en) |
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US9443845B1 (en) | 2015-02-23 | 2016-09-13 | Freescale Semiconductor, Inc. | Transistor body control circuit and an integrated circuit |
US9472662B2 (en) * | 2015-02-23 | 2016-10-18 | Freescale Semiconductor, Inc. | Bidirectional power transistor with shallow body trench |
US9559198B2 (en) | 2013-08-27 | 2017-01-31 | Nxp Usa, Inc. | Semiconductor device and method of manufacture therefor |
US9837526B2 (en) | 2014-12-08 | 2017-12-05 | Nxp Usa, Inc. | Semiconductor device wtih an interconnecting semiconductor electrode between first and second semiconductor electrodes and method of manufacture therefor |
US10026835B2 (en) | 2009-10-28 | 2018-07-17 | Vishay-Siliconix | Field boosted metal-oxide-semiconductor field effect transistor |
US10348295B2 (en) | 2015-11-19 | 2019-07-09 | Nxp Usa, Inc. | Packaged unidirectional power transistor and control circuit therefore |
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US8669613B2 (en) * | 2010-09-29 | 2014-03-11 | Alpha & Omega Semiconductor, Inc. | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
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Citations (13)
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US9837526B2 (en) | 2014-12-08 | 2017-12-05 | Nxp Usa, Inc. | Semiconductor device wtih an interconnecting semiconductor electrode between first and second semiconductor electrodes and method of manufacture therefor |
US9443845B1 (en) | 2015-02-23 | 2016-09-13 | Freescale Semiconductor, Inc. | Transistor body control circuit and an integrated circuit |
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US10348295B2 (en) | 2015-11-19 | 2019-07-09 | Nxp Usa, Inc. | Packaged unidirectional power transistor and control circuit therefore |
Also Published As
Publication number | Publication date |
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KR20110009218A (en) | 2011-01-27 |
EP2279525A2 (en) | 2011-02-02 |
KR101388821B1 (en) | 2014-04-23 |
TWI407565B (en) | 2013-09-01 |
CN102057490A (en) | 2011-05-11 |
JP2011522402A (en) | 2011-07-28 |
US20090278176A1 (en) | 2009-11-12 |
JP5529854B2 (en) | 2014-06-25 |
TW201007944A (en) | 2010-02-16 |
CN102057490B (en) | 2013-10-30 |
WO2009140224A3 (en) | 2010-02-18 |
WO2009140224A2 (en) | 2009-11-19 |
EP2279525A4 (en) | 2013-12-18 |
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