Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6324—Formation by anodic treatments, e.g. anodic oxidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
  • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
  • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
  • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon

Definitions

• oxide layers may be formed on a 3D structure in or on a semiconductor substrate, e.g. at the sidewalls of trenches or holes in and/or at the sidewalls of pillars at a major surface of a semiconductor substrate.
• a method according to embodiments of the invention may be applied at low temperatures, e.g. temperatures below 80 °C, for example room temperature.
• Applying a potential between a cathode and an anode may comprise applying a potential between a cathode and an anode located at the front side of the substrate.
• This has the advantage that the method may also be used with very thin substrates.
• Such thin substrates are, for convenience of handling, placed on a handling wafer.
• Such handling wafer is most often non- conductive. Due to the provision of a potential between the cathode and an anode at the front side of the substrate, the presence and type of handling wafer is of no concern for the anodisation process.
• applying a potential between a cathode located in the electrolyte solution and an anode formed on or by the substrate may be performed by applying a potential so as to change current density through the substrate as a function of time.
• the applied potential may change as a function of time.
• the present invention provides a substrate provided with an oxide layer, wherein the oxide layer is formed by a method according to embodiments of the present invention.
• FIG. 1 to FIG. 4 illustrate subsequent steps in a method according to embodiments of the invention.
• FIG. 5 illustrates an example of a device to which a method according to embodiments of the invention can be applied.
• FIG. 6 to FIG. 1 1 show SEM photo's of an oxide layer formed by a method according to embodiments of the invention.
• the present invention relates to the field of semiconductor processing, e.g. silicon processing, for example through-substrate via processing and semiconductor based MEMS technology.
• the semiconductor may be silicon.
• Anodisation is an electrochemical process in which a surface is anodised by placing the surface into an electrolyte solution while applying a potential between a cathode (negative electrode) formed of an inert material and an anode (positive electrode).
• the anode can be the part to be treated or can be additionally provided onto the part to be treated.
• An oxide layer is then grown because of a direct current passing through the electrolyte solution as a consequence of the applied potential. This current releases hydrogen at the cathode and oxygen at a surface of the anode, thereby creating a build-up of the oxide layer.
• the anodisation process is carried out in an acidic electrolyte solution.
• the electrolyte solution may, for example, comprise any of citric acid, acetic acid, oxalic acid, sulfuric acid, phosphoric acid nitric acid or a combination thereof. It has been found that the acid component in the electrolyte solution speeds up the anodisation process. Therefore, by using an acidic electrolyte solution, a thicker oxide can be grown in a particular time compared to an anodisation process with same parameters (starting materials, current, temperature etc.) but using another, non-acidic, electrolyte solution. The more acidic the electrolyte solution, the faster the anodisation process takes place.
• Embodiments of the present invention propose to use an anodisation process to provide oxide layers on or in a three-dimensional (3D) structure formed on or in a semiconductor substrate.
• a device substrate 1 a for example a Si substrate, is provided.
• a dielectric insulating layer 3 such as an oxide or a nitride is provided.
• the dielectric insulating layer 3 may consist of a single layer or a plurality of layers.
• active device such as for example transistors (not illustrated) may be provided in the device substrate 1 a, e.g. the front end of line.
• the device substrate 1 a could be a passive substrate.
• a multilayer interconnect structure 1 b is provided, comprising insulating and interconnect layers, e.g.
• the substrate 1 and more particularly device substrate 1 a thereof, which is the part which will be anodised, may comprise low resistivity silicon.
• the low resistivity silicon may have a resistivity of 30 ⁇ Ohm.cm or lower, the invention however not being limited thereto.
• n- or p- doped semiconductor material such as n- or p-doped silicon may be used.
• holes 5 may be etched from the backside of the semiconductor device wafer 1 a to the insulating layer 3.
• a typical technique would be to use an ICP-RIE plasma etching technique to obtain sloped or straight sidewalls 8.
• These holes 5 may have a variety of shapes: circular, polygons, ring shapes or trenches to name only a few.
• the substrate 40 to be oxidised may be attached onto a carrier wafer 20, for example by means of a temporary glue 30.
• the substrate 40 optionally provided onto and temporarily attached to the carrier wafer 20, may be placed onto a holder chuck 10.
• the anodisation process is selective towards the insulator 3. This means that the oxide will only be formed at exposed conductive substrate material, substantially not on neighbouring non-conductive or non-conducting materials.
• Anodisation is a self limiting process, which means that there exists an equilibrium between the potential that is applied for anodisation and the resulting thickness of the oxide layer 9 formed. According to embodiments of the invention it may be possible to form oxide layers 9 with a thickness up to 200 nm. According to embodiments and depending on the required thickness of the oxide layer 9, e.g. silicon oxide layer, anodisation may be performed during a time period between about 10 min and 10 hours. According to embodiments of the invention, the anodisation process may be a two-step process. In a first phase, a potential may be applied between the cathode and anode such that a fixed current density is obtained which allows forming of the oxide layer 9.
• the applied potential may be a fixed potential which allows healing the formed oxide layer 9, e.g. silicon oxide layer.
• healing of the oxide layer 9, e.g. silicon oxide layer is meant removal of defects such as pinholes so as to obtain an oxide layer of good quality.
• a stoichiometric oxide may be obtained, which exhibits good quality features.
• porous oxide layers 9 e.g. silicon oxide layers.
• the current density may be changed as a function of time during anodisation.
• a method according to embodiments of the invention may be used for providing oxide layers 9, e.g. silicon oxide layers, in vias 5 with high aspect ratio, which may be defined as the width-to-height ratio, e.g. with an aspect ratio below 5, for example an aspect ratio of between 0.01 and 5.
• high aspect ratio which may be defined as the width-to-height ratio, e.g. with an aspect ratio below 5, for example an aspect ratio of between 0.01 and 5.
• the silicon wafer 1 was provided with through-silicon-vias 5 having a high aspect ratio of 0.1 (diameter of 5 ⁇ m and depth of 50 ⁇ m).
• the silicon wafer 1 was cleaned with a HF solution in order to ensure low contact resistance.
• FIG. 10 shows the detail indicated C in FIG. 9.
• part 1 a of the substrate 1 may comprise isolation zones such as STI zones which are well known by a person skilled in the art.
• Part 1 b of the substrate 1 may comprise a plurality of vias vial , ..., via n and a plurality of metal layers M1 , ..., Mn+1 to form contacts 2.
• an insulating layer 3 is present.
• the insulating layer 3 may be formed of a first layer 3a and a second layer 3b.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Formation Of Insulating Films (AREA)

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• 2009
  • 2009-04-30 JP JP2011506732A patent/JP5528430B2/ja not_active Expired - Fee Related
  • 2009-04-30 EP EP09738240.2A patent/EP2272087B1/en not_active Not-in-force
  • 2009-04-30 WO PCT/EP2009/055312 patent/WO2009133196A1/en not_active Ceased
• 2010
  • 2010-10-18 US US12/906,766 patent/US8822330B2/en not_active Expired - Fee Related

Patent Citations (5)

Non-Patent Citations (3)

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