WO2009122571A1 - Dispositif d'enregistrement et de lecture d'informations - Google Patents

Dispositif d'enregistrement et de lecture d'informations Download PDF

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WO2009122571A1
WO2009122571A1 PCT/JP2008/056498 JP2008056498W WO2009122571A1 WO 2009122571 A1 WO2009122571 A1 WO 2009122571A1 JP 2008056498 W JP2008056498 W JP 2008056498W WO 2009122571 A1 WO2009122571 A1 WO 2009122571A1
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recording
layer
conductive oxide
recording layer
oxide layer
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PCT/JP2008/056498
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English (en)
Japanese (ja)
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司 中居
親義 鎌田
塚本　隆之
伸也 青木
隆大 平井
久保　光一
平岡　俊郎
豪 山口
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株式会社 東芝
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Priority to PCT/JP2008/056498 priority Critical patent/WO2009122571A1/fr
Priority to TW098110466A priority patent/TWI396281B/zh
Publication of WO2009122571A1 publication Critical patent/WO2009122571A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B9/00—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor
    • G11B9/04—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using record carriers having variable electric resistance; Record carriers therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B9/00—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor
    • G11B9/12—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using near-field interactions; Record carriers therefor
    • G11B9/14—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using near-field interactions; Record carriers therefor using microscopic probe means, i.e. recording or reproducing by means directly associated with the tip of a microscopic electrical probe as used in Scanning Tunneling Microscopy [STM] or Atomic Force Microscopy [AFM] for inducing physical or electrical perturbations in a recording medium; Record carriers or media specially adapted for such transducing of information
    • G11B9/1463—Record carriers for recording or reproduction involving the use of microscopic probe means
    • G11B9/149—Record carriers for recording or reproduction involving the use of microscopic probe means characterised by the memorising material or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B11/00—Recording on or reproducing from the same record carrier wherein for these two operations the methods are covered by different main groups of groups G11B3/00 - G11B7/00 or by different subgroups of group G11B9/00; Record carriers therefor
    • G11B11/002—Recording on or reproducing from the same record carrier wherein for these two operations the methods are covered by different main groups of groups G11B3/00 - G11B7/00 or by different subgroups of group G11B9/00; Record carriers therefor using recording by perturbation of the physical or electrical structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B11/00—Recording on or reproducing from the same record carrier wherein for these two operations the methods are covered by different main groups of groups G11B3/00 - G11B7/00 or by different subgroups of group G11B9/00; Record carriers therefor
    • G11B11/08—Recording on or reproducing from the same record carrier wherein for these two operations the methods are covered by different main groups of groups G11B3/00 - G11B7/00 or by different subgroups of group G11B9/00; Record carriers therefor using recording by electric charge or by variation of electric resistance or capacitance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/565—Multilevel memory comprising elements in triple well structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/78—Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to an information recording / reproducing apparatus having a high recording density.
  • NAND flash memory and small HDD hard disk drive
  • PCRAM phase change memory
  • a material that can take two states, an amorphous state (ON) and a crystalline state (OFF), as a recording material, and these two states are represented by binary data “0”. , “1” is used to record data.
  • an amorphous state is created by applying a high power pulse to the recording material, and a crystalline state is created by applying a small power pulse to the recording material.
  • Reading is performed by passing a small read current that does not cause writing / erasing to the recording material and measuring the electrical resistance of the recording material.
  • the resistance value of the recording material in the amorphous state is larger than the resistance value of the recording material in the crystalline state, and the ratio is about 10 3 .
  • PCRAM Physical Random Access Memory
  • Tbpsi terra bit per square inch
  • a typical example of a recording material for recording data is nickel oxide, and similarly to PCRAM, a high power pulse and a small power pulse are used for writing / erasing. In this case, it has been reported that the power consumption at the time of writing / erasing is smaller than that of the PCRAM.
  • MEMS memories using MEMS (micro-electro-mechanical systems) technology have been proposed (for example, P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz and G. K. Binnig, IEEE Trans. Nanotechnology 1, 39 (2002)).
  • a MEMS memory called Millipede has a structure in which a plurality of cantilevers arranged in an array and a recording medium coated with an organic substance face each other, and the probe at the tip of the cantilever is applied to the recording medium with an appropriate pressure. In contact.
  • the writing is performed by selectively controlling the temperature of the heater added to the probe. That is, when the temperature of the heater is increased, the recording medium is softened, and the probe is recessed into the recording medium, thereby forming a recess in the recording medium.
  • Reading is performed by causing the probe to scan the surface of the recording medium while causing the probe to pass a current that does not soften the recording medium.
  • the temperature of the probe decreases and the resistance value of the heater increases. Therefore, data can be sensed by reading the change in resistance value.
  • the minimum recording unit is one unit cell of the ferroelectric layer crystal, the recording density becomes a huge value of about 4 Pbpsi (peta bit per square inch).
  • the present invention provides a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption.
  • the information recording / reproducing apparatus of the present invention includes a recording layer in which two or more states having different electrical resistivity are recorded, and a recording layer on the anode side when a voltage or current is applied to the recording layer to change the state of the recording layer
  • a conductive oxide layer disposed at one end of the substrate.
  • the electrical resistivity of the conductive oxide layer is smaller than the minimum value of the electrical resistivity of the recording layer.
  • the conductive oxide layer is made of (i) a first material as a main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ⁇ s ⁇ 2), In 2 O 3 , IrO 2 , and RuO 2.
  • a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
  • FIG. 1 is a diagram showing the recording principle.
  • FIG. 2 is a diagram showing the recording principle.
  • FIG. 3 is a diagram illustrating the recording principle.
  • FIG. 4 shows the recording principle.
  • FIG. 5 shows the recording principle.
  • FIG. 6 is a diagram showing a probe type solid-state memory.
  • FIG. 7 is a diagram showing classification of recording media.
  • FIG. 8 is a diagram showing a state during recording.
  • FIG. 9 is a diagram showing a recording operation.
  • FIG. 10 is a diagram showing a reproduction operation.
  • FIG. 11 is a diagram showing a cross-point type solid-state memory.
  • FIG. 12 is a diagram showing the structure of the memory cell array.
  • FIG. 13 is a diagram showing the structure of the memory cell array.
  • FIG. 14 is a diagram showing the structure of the memory cell array.
  • FIG. 15 is a diagram showing a structure of a memory cell.
  • FIG. 16 is a diagram illustrating an application example to a flash memory.
  • FIG. 17 is a circuit diagram showing a NAND cell unit.
  • FIG. 18 is a diagram showing the structure of the NAND cell unit.
  • FIG. 19 is a diagram showing the structure of the NAND cell unit.
  • FIG. 20 is a diagram showing the structure of the NAND cell unit.
  • FIG. 21 is a circuit diagram showing a NOR cell.
  • FIG. 22 is a diagram showing the structure of a NOR cell.
  • FIG. 23 is a circuit diagram showing a two-tracell unit.
  • FIG. 24 is a diagram illustrating a structure of a two-tracell unit.
  • FIG. 25 is a diagram illustrating the structure of a two-tracell unit.
  • An information recording / reproducing apparatus includes a recording layer in which two or more states having different electrical resistivity are recorded, and an anode side when a voltage or current is applied to the recording layer to change the state of the recording layer. And a conductive oxide layer disposed at one end of the recording layer.
  • the electrode is (i) Ti-N, Ti-Si-N, Ta-N, Ta-Si-N, Si-N, Ti -Nitride, carbide or oxide of material selected from the group of -C, Ta-C, Si-C, (ii) a mixture of nitride and oxide of (i), (iii) of (i) It is composed of a mixture of nitride and carbide, (iv) a mixture of oxide and carbide of (i), or (v) a mixture of nitride, carbide and oxide of (i).
  • a x M y X 4 (0.1 ⁇ x ⁇ 2.2,1.8 ⁇ y ⁇ 2), (2) A x M y X 3 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1 ), constituted by (3) a x M y X 4 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1 material selected from the group of).
  • A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Elements selected from the group of Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi, M is Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, It is an element selected from the group of Ni, Nb, Ta, Mo, W, Ru, Rh.
  • A is an element selected from the group of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, Bi.
  • M is an element selected from the group of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, Os.
  • a and M are mutually different elements
  • X is an element selected from the group of O and N.
  • the recording layer is composed of 1. corundum structure, 2. rutile structure, 3. spinel structure, 4. ramsdellite structure, 5. anatase structure, 6. hollandite structure, 7. brookite structure, 8. pyrolose structure, 9. NaCl structure, 10. It has a crystal structure selected from the group of perovskite structure, 11. ilmenite structure, and 12. wolframite structure.
  • corundum structure examples include Al 2 O 3 , Cr 2 O 3 , ⁇ -Fe 2 O 3 , ⁇ -GaO 3 , Ti 2 O 3 , and V 2 O 3 .
  • Examples of the rutile structure include TiO 2 and SnO 2 .
  • the brookite structure, anatase structure and ramsdellite structure are modified structures of the rutile structure.
  • the brookite structure is an orthorhombic form of a rutile structure.
  • the spinel structure is typified by MgAl 2 O 4 , and other examples include ZnFe 2 O 4 and ZnMnO 3 .
  • Cu 2 Mg and Mn 2 O 3 also have a spinel structure.
  • Ba 2 Fe 12 O 19 and KFe 11 O 17 have a composite spinel structure.
  • a typical example of the hollandite structure and pyroloose structure is MnO 2
  • examples of the hollandite structure include ⁇ -MnO 2 and BiVO.
  • Ilmenite structure includes FeTiO 3 .
  • the perovskite structure which became famous for the discovery of high-temperature oxide superconductors, also has various deformation structures. Examples include BaTiO 3 , CaTiO 3 , GdFeO 3 and the like.
  • NaCl structure examples include TiO and NiO.
  • CuO can be understood as a modified version of the NaCl structure.
  • the base crystal structure may be slightly distorted.
  • a distorted spinel structure or a distorted NaCl structure may be used.
  • another name called a heterolite structure for example, ZnMn 2 O 4
  • ZnMn 2 O 4 ZnMn 2 O 4
  • the recording layer is composed of, for example, a composite compound having one kind or two or more kinds of cation elements, and at least one of the cation elements is a transition element having a d orbital incompletely filled with electrons.
  • the conductive oxide layer stably changes the electrical resistivity of the recording layer (set / reset operation) and applies a voltage or current to the recording layer to ensure its reproducibility. When changing, it is added to one end of the recording layer which becomes the anode side.
  • a change in the electrical resistivity of the conductive oxide layer can be an unstable element of the set / reset operation.
  • the electrical resistivity of the conductive oxide layer is made smaller than the minimum value of the electrical resistivity of the recording layer.
  • the conductive oxide layer preferably has no change in electrical resistivity. However, if the electrical resistivity of the conductive oxide layer is sufficiently smaller than the minimum value of the electrical resistivity of the recording layer, the set / reset operation is performed. May change the electrical resistivity of the conductive oxide layer.
  • the electrical resistivity of the conductive oxide layer is 1 ⁇ 10 ⁇ 1 ⁇ cm or less.
  • the conductive oxide layer is (i) a first main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ⁇ s ⁇ 2), In 2 O 3 , IrO 2 , and RuO 2 . 1 material and selected from the group of (ii) Ga 2 O 3 , Al 2 O 3 , Nb 2 O 5 , SnO 2 , Ta 2 O 5 , Sb 2 O 3 , ZnO, TiO s (1 ⁇ s ⁇ 2) It is comprised from the mixture with the 2nd material as a dopant made.
  • the proportion of the second material in the conductive oxide layer Is preferably 30 wt% or less, more preferably 20 wt% or less, and even more preferably 5 wt% or less.
  • the main point of selecting such a material is to prevent the conductive oxide layer from becoming an unstable element of the set / reset operation.
  • the characteristics of strongly correlated systems change in the same way as materials that can be interpreted by band theory such as semiconductors. That is, the electrical characteristics, magnetic characteristics, dielectric characteristics, and the like of the material change depending on the crystal structure, crystal grain size, orientation, impurities, and the like.
  • the selection of the above-mentioned materials controls the crystallinity such as crystal grain size and orientation, and stably obtains good device characteristics. It is effective for.
  • the material of the conductive oxide layer is composed of electrical resistivity and controllability, adhesion to other films, diffusion prevention, heat resistance, etching property, chemical resistance including gas and solution, crystallinity. , Orientation, and controllability thereof are selected.
  • ITO a material in which In 2 O 3 is doped with SnO 2 is known as ITO. Since ITO is a material having a low electrical resistivity, it is advantageous for realizing an electrical resistivity lower than that of the recording layer.
  • ZnO is known as a material that is easily oriented. Therefore, it is predicted that a highly oriented film can be easily formed if there is a crystal plane with a close lattice constant or a close lattice spacing.
  • the electrical resistivity of ZnO is larger than that of ITO, and since Zn is known as an element that easily volatilizes, simply using only ZnO diffuses Zn into other films, or Zn escapes from the conductive oxide layer, causing problems such as unstable electrical resistivity. In such a case, such a problem can be solved if ZnO contains the second material as a dopant.
  • TiO s may be in the range of TiO s (1 ⁇ s ⁇ 2).
  • the conductive oxide layer is selected from the group consisting of (I) sphalerite structure, (II) wurtzite structure, (III) C-rare earth structure, (IV) rutile structure, and (V) NaCl structure. It preferably has a crystal structure.
  • the recording layer has a thickness of 5 nm or more and 50 nm or less
  • the conductive oxide layer has a thickness of 0.5 nm or more and 10 nm or less.
  • the recording layer assumes one of two states having different electric resistivity, and a description will be given of a system in which two types of ions exist.
  • the initial state of the recording layer is an insulator (high resistance state), for example, a state where the electrical resistivity is 10 3 ⁇ ⁇ cm. Then, by applying a potential difference to both ends of the recording layer, a part of the cation element existing inside the recording layer moves to the cathode (negative electrode) side.
  • the recording layer is positioned on the anode (positive electrode) side and the conductive oxide layer is positioned on the cathode side, the cation element discharged from the recording layer is introduced into the conductive oxide layer, and the conductivity is increased.
  • the proportion of the cationic element is relatively higher than the proportion of the anionic element.
  • the conductive oxide layer receives electrons from the cathode in order to maintain electrical neutrality, and becomes a compound in a low oxidation state as a result of a decrease in the valence of the transition element in the conductive oxide layer.
  • the recording layer on the anode side has a relatively lower proportion of the cationic element than the proportion of the anionic element, it emits electrons to the anode and becomes a highly oxidized compound.
  • the recording layer is in a low resistance state, for example, a state in which the electrical resistivity is 10 0 ⁇ ⁇ cm.
  • the thermal energy returns to the low energy stable state insulator (high resistance state) before setting again.
  • the electrical resistivity of the conductive oxide layer does not change when the resistance of the recording layer is changed as described above, but the electrical resistivity of the conductive oxide layer is the minimum of the electrical resistivity of the recording layer. If the value is sufficiently smaller than the value, there is no problem even if the electric resistivity of the conductive oxide layer changes.
  • a Pbpsi (Peta per square inch) class can be realized, and further a significant improvement in write disturb resistance can be realized.
  • FIG. 1 shows the structure of a recording unit as a premise of the present invention.
  • Reference numeral 11 denotes an electrode layer
  • 12 denotes a recording layer
  • 13A denotes an electrode layer (or a protective layer).
  • a small white circle in the recording layer 12 represents a representative element as a diffusion ion
  • a small black circle represents a transition element as a cation.
  • a large white circle represents a typical element as an anion.
  • the initial state of the recording layer 12 is an insulator (high resistance state), and for information recording, the recording layer 12 is phase-changed by a potential gradient to make the recording layer 12 conductive (see FIG. (Low resistance state)
  • the high resistance state is defined as a reset state
  • the low resistance state is defined as a set state.
  • this definition is intended to simplify the following description. Depending on the selection of materials and the manufacturing method, this definition may be reversed, that is, the low resistance state becomes the reset (initial) state.
  • the state may be set. That is, it goes without saying that such a case is also included in the scope of the present invention.
  • a state in which the potential of the electrode layer 13A is relatively lower than the potential of the electrode layer 11 is created. If the electrode layer 11 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the electrode layer 13A.
  • a fixed potential for example, ground potential
  • the diffusion ions in the recording layer 12 move to the electrode layer (cathode) 13A side, and the diffusion ions in the recording layer (crystal) 12 decrease relative to the anions.
  • the diffused ions that have moved to the electrode layer 13A side receive electrons from the electrode layer 13A and precipitate as metal, so that the metal layer 14 is formed.
  • anions become excessive, and as a result, the valence of transition element ions in the recording layer 12 is increased. That is, since the recording layer 12 has electron conductivity by carrier injection, information recording (set operation) is completed.
  • Information reproduction can be easily performed by flowing a current pulse through the recording layer 12 and detecting the resistance value of the recording layer 12.
  • the current pulse needs to be a minute value that does not cause a phase change in the material constituting the recording layer 12.
  • the above process is a kind of electrolysis, and an oxidizing agent is generated by electrochemical oxidation on the electrode layer (anode) 11 side, and a reducing agent is generated by electrochemical reduction on the electrode layer (cathode) 13A side. Can be considered.
  • the recording layer 12 is Joule-heated with a large current pulse to promote the oxidation-reduction reaction of the recording layer 12. Just do it. That is, the recording layer 12 returns to the insulator due to the residual heat after the interruption of the large current pulse (reset operation).
  • the coordination number of the diffuse ions is reduced (ideally 2 or less), the valence is 2 or more, or the anion valence is increased (ideally 3). This can be done.
  • Such a recording layer 12 can be realized by the elements and crystal structure as described above.
  • the electrode layer 11 is made of a material that is not easily oxidized (for example, electrically conductive nitride, electrically conductive oxide, etc.). Is preferred.
  • the electrode layer 11 is preferably made of a material that does not have ionic conductivity.
  • LaNiO 3 can be said to be the most preferable material from the viewpoint of comprehensive performance in consideration of good electrical conductivity and the like.
  • ⁇ MN M contains at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta. N is nitrogen.
  • ⁇ MO x M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
  • the molar ratio x shall satisfy 1 ⁇ x ⁇ 4.
  • ⁇ AMO 3 A contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba, and Ln (Lanthanide).
  • M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
  • O is oxygen
  • ⁇ B 2 MO 4 B contains at least one element selected from the group of K, Ca, Sr, Ba, and Ln (Lanthanide).
  • M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
  • O is oxygen
  • the electrode layer 13A preferably has a function of preventing the recording layer 12 from reacting with the atmosphere.
  • Examples of such a material include semiconductors such as amorphous carbon, diamond-like carbon, and SnO 2 .
  • the electrode layer 13A may function as a protective layer for protecting the recording layer 12, or a protective layer may be provided instead of the electrode layer 13A.
  • the protective layer may be an insulator or a conductor.
  • FIG. 2 shows the structure of a recording unit according to an example of the present invention.
  • 11 is an electrode layer
  • 12 is a recording layer
  • 13A is an electrode layer (or protective layer)
  • 15 is a conductive oxide layer.
  • Small white circles in the recording layer 12 represent typical elements as diffusion ions, and small black circles represent transition elements as cations.
  • a large white circle represents a typical element as an anion.
  • This structure is different from the structure of FIG. 1, which is the premise of the present invention, in that when a voltage or current is applied to the recording layer 12 to change the state of the recording layer 12, specifically, when a set operation is performed.
  • the conductive oxide layer 15 is disposed at one end of the recording layer 12 on the anode side.
  • the conductive oxide layer 15 may have a cavity site.
  • the void site is a site that stores a cation element that has moved from the recording layer 12.
  • the conductive oxide layer 15 has void sites, the effect of facilitating the movement of ions in the recording layer 12 is exhibited, and the composition range of the conductive oxide layer 15 is adjusted so that the recording layer 12 Improve electronic conductivity and ensure stability of crystal structure. As a result, the disturb resistance of the recording layer 12 is improved.
  • an insulator having a thickness of about several nanometers having a permeability of ions discharged from the recording layer 12 may be inserted between the recording layer 12 and the conductive oxide layer 15.
  • This insulator is composed of a compound or composite compound containing at least an ionic element discharged from the recording layer 12 and other typical elements. This lowers the on-resistance of the recording unit.
  • FIG. 3 represents the structure of FIG. In the recording layer 12, for example, two states with different electrical resistivity are recorded.
  • ⁇ rr is the electrical resistivity of the recording layer 12 in the reset state (high resistance state)
  • ⁇ rs is the electrical resistivity of the recording layer 12 in the set state (low resistance state).
  • ⁇ or is the electrical resistivity of the conductive oxide layer 15 when the recording layer 12 is in the reset state
  • ⁇ os is the electrical resistivity of the conductive recording layer 15 when the recording layer 12 is in the set state.
  • FIG. 4 is a modification of the structure of FIG. For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively.
  • a conductive oxide layer 15 is added to the end of the recording layer 12-1 on the anode side.
  • the conductive oxide layer 15 is also formed on the end of the recording layer 12-2 on the anode side. Added.
  • the threshold value for changing the state of the recording layer 12-1 and the threshold value for changing the state of the recording layer 12-2 are set to different values to enable multi-level recording.
  • ⁇ rr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ⁇ rs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state).
  • ⁇ rr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ⁇ rs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
  • the electrical resistivity ⁇ or, ⁇ os of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ⁇ rr1, ⁇ rs1, ⁇ rr2, ⁇ rs2 of the recording layers 12-1, 12-2.
  • FIG. 5 is also a modification of the structure of FIG. For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. Further, a conductive oxide layer 15 is disposed between the electrode layer 11 as an anode and the recording layer 12-1.
  • the threshold for changing the state of the recording layer 12-1 and the threshold for changing the state of the recording layer 12-2 are set to different values to enable multi-value recording.
  • ⁇ rr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ⁇ rs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state).
  • ⁇ rr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ⁇ rs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
  • the electrical resistivity ⁇ or, ⁇ os of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ⁇ rr1, ⁇ rs1, ⁇ rr2, ⁇ rs2 of the recording layers 12-1, 12-2.
  • Probe type solid-state memory A Structure 6 and 7 show a probe type solid state memory according to an example of the present invention.
  • An electrode layer 21 is disposed on the semiconductor substrate 20, and a recording unit 22 having a data area and a servo area is disposed on the electrode layer 21.
  • the recording unit (recording medium) 22 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG.
  • the recording unit 22 is solidly formed at the center of the semiconductor substrate 20.
  • the servo area is arranged along the edge of the semiconductor substrate 20.
  • the data area and servo area are composed of multiple blocks.
  • a plurality of probes 24 are arranged corresponding to a plurality of blocks.
  • Each of the plurality of probes 24 has a sharpened shape.
  • the plurality of probes 24 constitutes a probe array and is formed on one surface side of the semiconductor substrate 23.
  • the plurality of probes 24 can be easily formed on one surface side of the semiconductor substrate 23 by using the MEMS technology.
  • the position of the probe 24 on the data area is controlled by a servo burst signal read from the servo area. Specifically, the access operation is executed by causing the driver 27 to reciprocate the semiconductor substrate 20 in the X direction and controlling the position of the plurality of probes 24 in the Y direction.
  • the recording medium is formed independently for each block, and the recording medium is configured to rotate in a circle like a hard disk, and each of the plurality of probes 24 is moved in the radial direction of the recording medium, for example, the X direction. You may do it.
  • Each of the plurality of probes 24 has a function as a recording / erasing head and a function as a reproducing head.
  • the multiplex drivers 25 and 26 supply a predetermined voltage to the plurality of probes 24 at the time of recording, reproduction, and erasing.
  • FIG. 8 shows the recording operation (set operation).
  • the recording unit (recording medium) 22 is formed on the electrode layer 21 on the semiconductor chip 20.
  • the recording unit 22 is covered with the protective layer 13B.
  • the tip of the probe 24 is brought into contact with the surface of the protective layer 13B, a voltage pulse is applied to the recording unit 30 of the recording unit (recording medium) 22, and a potential gradient is generated in the recording unit 30 of the recording unit 22.
  • a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.
  • the voltage pulse may be generated by emitting electrons from the probe 24 toward the electrode layer 21 using, for example, an electron generation source or a hot electron source.
  • some of the diffusion ions move to the probe (cathode) 24 side, and the diffusion ions in the crystal are relative to the anions. To decrease.
  • the diffused ions that have moved to the probe 24 side receive electrons from the probe 24 and are deposited as metal.
  • anions become excessive, and as a result, the valence of the transition element ions left in the recording layer 12 is increased. That is, since the recording unit 30 of the recording layer 12 has electron conductivity due to carrier injection due to phase change, information recording (set operation) is completed.
  • the voltage pulse for information recording can be generated by creating a state in which the potential of the probe 24 is relatively higher than the potential of the electrode layer 21.
  • the probe type solid-state memory of this example information can be recorded in the recording unit 30 of the recording medium as in the case of the hard disk, and by adopting a new recording material, the conventional solid-state memory or semiconductor memory can be used. High recording density can be realized.
  • FIG. 10 shows the reproduction operation.
  • the reproduction operation is performed by flowing a voltage pulse to the recording unit 30 of the recording layer 12 and detecting the resistance value of the recording unit 30 of the recording layer 12.
  • the voltage pulse is set to a minute value so that the material constituting the recording unit 30 of the recording layer 12 does not cause a phase change.
  • the read current generated by the sense amplifier S / A is passed from the probe 24 to the recording unit 30 of the recording layer 12, and the resistance value of the recording unit 30 is measured by the sense amplifier S / A. If the new material already described is adopted, the resistance ratio between the high resistance state and the low resistance state can be secured at 10 3 or more.
  • the erasing (reset) operation is performed by heating the recording unit 30 of the recording layer 12 with a large current pulse to promote the oxidation-reduction reaction in the recording unit 30 of the recording layer 12.
  • it can also be performed by applying a voltage pulse in the direction opposite to that at the time of setting to the recording layer 12.
  • the erasing operation can be performed for each recording unit 30, or can be performed for a plurality of recording units 30 or blocks.
  • FIG. 11 shows a cross-point type solid state memory according to an example of the present invention.
  • the word lines WL i ⁇ 1 , WL i , WL i + 1 extend in the X direction, and the bit lines BL j ⁇ 1 , BL j , BL j + 1 extend in the Y direction.
  • each of the word lines WL i ⁇ 1 , WL i , WL i + 1 is connected to the word line driver & decoder 31 via a MOS transistor RSW as a selection switch, and the bit lines BL j ⁇ 1 , BL j , BL j + 1 One end is connected to a bit line driver & decoder & read circuit 32 via a MOS transistor CSW as a selection switch.
  • Selection signals R i ⁇ 1 , R i , and R i + 1 for selecting one word line (row) are input to the gate of the MOS transistor RSW, and one bit line is input to the gate of the MOS transistor CSW.
  • Selection signals C j ⁇ 1 , C j , and C j + 1 for selecting (column) are input.
  • the memory cell 33 is arranged at the intersection of the word lines WL i ⁇ 1 , WL i , WL i + 1 and the bit lines BL j ⁇ 1 , BL j , BL j + 1 . This is a so-called cross-point cell array structure.
  • a diode 34 for preventing a sneak current during recording / reproduction is added to the memory cell 33.
  • FIG. 12 shows the structure of the memory cell array portion of the cross-point type solid-state memory shown in FIG.
  • word lines WL i ⁇ 1 , WL i , WL i + 1 and bit lines BL j ⁇ 1 , BL j , BL j + 1 are arranged, and memory cells 33 and diodes 34 are arranged at intersections of these wirings. Is done.
  • cross-point type cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33.
  • FIGS. 13 and 14 it is possible to stack the memory cells 33 to make the memory cell array have a three-dimensional structure.
  • the memory cell 33 has a stacked structure of a recording layer 12, a conductive oxide layer 15, and a protective layer 13B.
  • One memory cell 33 stores data of 1 bit or more.
  • the diode 34 is disposed between the word line WL i and the memory cell 33.
  • a barrier metal may be disposed between at least one of the word line WL i and the diode 34 and between the protective layer 13B and the bit line BL j .
  • the diode 34 is preferably omitted when the set / reset operation is performed only by the direction of the voltage.
  • the potential of the word line WL i is a bit. making a relatively lower than the potential of the line BL j. If the bit line BL j is set to a fixed potential (for example, ground potential), a negative potential may be applied to the word line WL i .
  • the diffusion ions in the recording layer 12 are anions. It decreases relative to. Further, the diffused ions that have moved to the word line WL i side receive electrons from the word line WL i and are deposited as metal.
  • the non-selected word lines WL i ⁇ 1 and WL i + 1 and the non-selected bit lines BL j ⁇ 1 and BL j + 1 are all biased to the same potential.
  • the voltage pulse for recording information may be generated by creating a state in which the potential of the word line WL i is relatively higher than the potential of the bit line BL j .
  • the erase (reset) operation uses Joule heat generated by flowing a large current pulse to the selected memory cell 33 and its residual heat, for example, the potential of the word line WL i is set higher than the potential of the bit line BL j . Also make it relatively high. If the bit line BL j is set to a fixed potential (eg, ground potential), a positive potential may be applied to the word line WL i .
  • a fixed potential eg, ground potential
  • the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
  • the erase operation can also be performed by the following method.
  • the potential of the word line WL i is made relatively lower than the potential of the bit line BL j .
  • Bit lines BL j and a fixed potential e.g., ground potential
  • a negative potential may be applied to the word line WL i.
  • the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
  • the unselected word lines WL i ⁇ 1 , WL i + 1 and the unselected bit lines BL j ⁇ 1 , BL j + 1 are all biased to the same potential.
  • the read operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33.
  • the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.
  • read current generated by the reading circuit (current pulses) to the memory cell 33 surrounded by the dotted line A from the bit line BL j, measure the resistance value of the memory cell 33 by the read circuit. If the new material already explained is adopted, the difference in resistance value between the set / reset states can be secured at 10 3 or more.
  • probe type solid-state memory and the cross-point type solid-state memory have been described.
  • material and principle proposed in the example of the present invention can be applied to a recording medium such as a current hard disk or DVD. It is.
  • FIG. 16 shows a memory cell of the flash memory.
  • the memory cell of flash memory is composed of MIS (metal-insulator-semiconductor) transistors.
  • a diffusion layer 42 is formed in the surface region of the semiconductor substrate 41.
  • a gate insulating layer 43 is formed on the channel region between the diffusion layers 42.
  • a recording portion (ReRAM: Resistive RAM) 44 is formed on the gate insulating layer 43.
  • a control gate electrode 45 is formed on the recording unit 44.
  • the semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types.
  • the control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.
  • the recording unit 44 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG.
  • the difference between the potentials V1 and V2 needs to be large enough for the recording unit 44 to undergo phase change or resistance change, but the direction is not particularly limited.
  • V1> V2 or V1 ⁇ V2 may be used.
  • the gate insulating layer 43 is substantially thickened, and thus the threshold value of the memory cell (MIS transistor). Get higher.
  • the gate insulating layer 43 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is , Get lower.
  • the potential V2 is applied to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.
  • the reset (erase) operation is performed by applying the potential V1 'to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 ( ⁇ V3) to the other of the diffusion layers 42.
  • the potential V1 ' is set to a value exceeding the threshold value of the memory cell in the set state.
  • the memory cell is turned on, electrons flow from one side of the diffusion layer 42 to the other side, and hot electrons are generated. Since the hot electrons are injected into the recording unit 44 through the gate insulating layer 43, the temperature of the recording unit 44 rises.
  • the recording unit 44 changes from a conductor (low resistance) to an insulator (high resistance)
  • the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is , Get higher.
  • the information recording / reproducing apparatus can be put into practical use by utilizing the technology of the flash memory.
  • FIG. 17 shows a circuit diagram of the NAND cell unit.
  • FIG. 18 shows the structure of a NAND cell unit according to an example of the present invention.
  • an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
  • a NAND cell unit according to an example of the present invention is formed in the P-type well region 41c.
  • the NAND cell unit includes a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to both ends thereof.
  • the memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
  • the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
  • the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
  • One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.
  • the set (write) operation is sequentially performed one by one from the memory cell MC on the source line SL side toward the memory cell on the bit line BL side.
  • V1 (plus potential) is applied as a write potential to the selected word line (control gate electrode) WL
  • Vpass is applied as a transfer potential (potential at which the memory cell MC is turned on) to the unselected word line WL.
  • the select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
  • a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording unit 44 of the selected memory cell MC
  • the resistance value should not change from a high state to a low state.
  • V2 ( ⁇ V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording unit 44 of the selected memory cell MC is changed from a high state to a low state. To change.
  • V1 ' is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 ( ⁇ V3) is applied to the source line SL.
  • the reset operation is executed collectively for all the memory cells MC in the NAND cell unit.
  • a read potential (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL.
  • a potential to be turned on without fail is given.
  • the two select gate transistors ST are turned on to supply a read current to the NAND string.
  • the selected memory cell MC When a read potential is applied to the selected memory cell MC, the selected memory cell MC is turned on or off according to the value of the data stored therein. For example, data can be read by detecting a change in the read current. it can.
  • the select gate transistor ST has the same structure as the memory cell MC.
  • the select gate transistor ST has a recording portion (recording layer and conductive layer). It is also possible to form a normal MIS transistor without forming the conductive oxide layer.
  • FIG. 20 shows a modification of the NAND flash memory.
  • This modification is characterized in that the gate insulating layer of the plurality of memory cells MC constituting the NAND string is replaced with a P-type semiconductor layer 47.
  • the P-type semiconductor layer 47 is filled with a depletion layer in a state where no voltage is applied.
  • a positive write potential for example, 3.5 V
  • a positive transfer potential to the control gate electrode 45 of the non-selected memory cell MC. For example, give 1V).
  • the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.
  • the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.
  • reset is performed by applying a negative erase potential (for example, ⁇ 3.5 V) to all the control gate electrodes 45 and applying a ground potential (0 V) to the P-type well region 41 c and the P-type semiconductor layer 47. This can be performed collectively for all the memory cells MC constituting the NAND string.
  • a negative erase potential for example, ⁇ 3.5 V
  • a positive read potential for example, 0.5 V
  • the memory cell MC receives data “0” to the control gate electrode 45 of the non-selected memory cell MC.
  • a transfer potential for example, 1 V that is always turned on regardless of “1” is applied.
  • the threshold voltage Vth ”1” of the memory cell MC in the “1” state is in the range of 0V ⁇ ⁇ ⁇ Vth ”1” ⁇ 0.5V
  • the threshold voltage Vth ”0 of the memory cell MC in the“ 0 ”state “” Shall be in the range of 0.5V0.5 ⁇ Vth ”0” ⁇ 1V.
  • the two select gate transistors ST are turned on to supply a read current to the NAND string.
  • the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0.5 than that of the P-type well region 41c. It is preferable that the depth is about V.
  • the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed.
  • the channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
  • the diffusion layer 42 and the control gate electrode 45 are not short-circuited.
  • FIG. 21 shows a circuit diagram of the NOR cell unit.
  • FIG. 22 shows the structure of a NOR cell unit according to an example of the present invention.
  • an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
  • a NOR cell according to an example of the present invention is formed in the P-type well region 41c.
  • the NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
  • the memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a control on the recording unit 44. And a gate electrode 45.
  • ReRAM recording unit
  • the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
  • FIG. 23 shows a circuit diagram of a two-tracell unit.
  • FIG. 24 shows the structure of a two-tracell unit according to an example of the present invention.
  • the 2 tracell unit was recently developed as a new cell structure that combines the features of NAND cell units and NOR cells.
  • an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
  • the two tracell unit according to the example of the present invention is formed in the P-type semiconductor substrate 41a.
  • the 2 tracell unit is composed of one memory cell MC and one select gate transistor ST connected in series.
  • the memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
  • the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
  • the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
  • the select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.
  • the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
  • the select gate transistor ST has the same structure as the memory cell MC.
  • the select gate transistor ST has a recording portion (recording layer and conductive oxide).
  • a normal MIS transistor can be formed without forming a physical layer.
  • Example A description will be given of an embodiment in which several samples are prepared and the resistance difference between the reset (erase) state and the set (write) state is evaluated.
  • a device having the system of FIG. 8 and having the recording unit 22 having the structure of FIG. 2 (the recording layer 12 and the conductive oxide layer 15) is used.
  • ⁇ Evaluation uses a probe pair whose tip diameter is sharpened to 10nm or less.
  • the probe pair is brought into contact with the protective layer 13B, and information recording (writing / erasing) is performed using one of them.
  • Writing is performed by applying a voltage pulse of 1 V to the recording unit 22 with a width of 10 nsec, for example.
  • Erasing is performed by applying a voltage pulse of 0.2 V to the recording unit 22 with a width of 100 nsec, for example.
  • DC evaluation is also possible like a semiconductor parameter analyzer.
  • read is executed using the other one of the probe pair between write / erase. Reading is performed by applying a voltage pulse of 0.1 V with a width of 10 nsec to the recording unit 22 and measuring the resistance value of the recording unit (recording bit) 22.
  • the recording layer 12 is made of Zn 1.1 Mn 1.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of ZnO doped with 2 wt.% Ga 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the material of the electrode layer 21 is four types of TiN, TiSiN, TaN, and TaSiN.
  • the electrode layer 21 SiN, TiC, TaC, SiC or the like is considered suitable.
  • Metal materials such as Pt, Ru, and Ir are not preferable as the material of the electrode layer 21 because they are expensive.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the set / reset voltage hardly depends on the thickness of the conductive oxide layer 15. This is thought to be because it is difficult to perfectly match the impedance and measurement error due to ringing or the like is included about 10%. In other words, the influence of the thickness of the conductive oxide layer 15 on the set / reset voltage can be estimated to be about 10%.
  • the recording layer 12 is made of Zn 1.1 Mn 2.0 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of ZnO doped with 2.5 wt.% Of Al 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of ZnCo 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of CoO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • Recording layer 12 a TiZn 2 O 4, are prepared three kinds of thickness (10nm, 20nm, 50nm).
  • the conductive oxide layer 15 is made of TiO 2 doped with 1 wt.% Of Nb 2 O 5 and has three types of thickness (0.5 nm, 5 nm, and 10 nm).
  • the amount of dopant with respect to the conductive oxide layer (TiO 2 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of ZnMnO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is SnO 2 doped with 1 wt.% Of Sb 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant for the conductive oxide layer (SnO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of TiZn 2 O 3.8, and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of In 2 O 3 doped with 1 wt.% Of TiO 2 and ZnO, and three kinds of thicknesses (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (In 2 O 3 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of ZnMoO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of IrO 2 doped with 1% by weight of ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant for the conductive oxide layer (IrO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of ZnFe 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of RuO 2 doped with 1 wt.% ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of Mn 3 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of ZnO doped with 2.6 wt.% Al23, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the recording layer 12 is made of Mn 2.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
  • the conductive oxide layer 15 is made of TiO 2 + doped with 1.1 wt.% Of Nb2O5, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
  • the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
  • the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
  • the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
  • the specification of the sample of the comparative example is as follows.
  • the recording layer 12 is made of Fe 1.9 O 3 having a thickness of 10 nm and does not use a conductive oxide layer. That is, the recording unit 22 is composed of only the recording layer 12.
  • the reset voltage during unipolar operation was + 0.5V
  • the set voltage was + 1.5V
  • the reset voltage during bipolar operation was + 0.5V
  • the set voltage was -0.5V.
  • the cycle characteristics were poor and the upper limit of the number of rewrites was about several hundred times.
  • the set voltage during the bipolar operation is higher than the set voltage during the unipolar operation.
  • the set voltage during the bipolar operation is lower than the set voltage during the unipolar operation.
  • the on-state resistance value increases, the on-current decreases, and a set / reset operation with extremely low power consumption becomes possible. This enables simultaneous processing of a large number of cells and realizes extremely high speed operation.
  • Table 2 summarizes the verification results of the first to eighth examples and the comparative example.
  • the example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention.
  • Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.
  • the example of the present invention According to the information recording / reproducing apparatus according to the example of the present invention, it is possible to perform information recording at a recording density that cannot be achieved by the prior art, and at the same time to achieve high-speed operation, despite the extremely simple mechanism. become. Therefore, the example of the present invention has a great industrial advantage as a next generation technology that breaks down the recording density barrier of the current nonvolatile memory.

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Abstract

La présente invention concerne un dispositif d'enregistrement et de lecture d'informations non volatiles, apte à réaliser un enregistrement de haute densité tout en économisant l'énergie. Le dispositif d'enregistrement et de lecture d'informations comprend une couche d'enregistrement sur laquelle au moins deux états, qui ont des résistances électriques différentes, sont enregistrés, et une couche d'oxyde électroconductrice disposée à une extrémité de la couche d'enregistrement et qui, lorsqu'une tension ou un courant est appliqué sur la couche d'enregistrement de façon à modifier l'état de la couche d'enregistrement, se trouve du côté de l’anode. La résistance électrique de la couche d'oxyde électroconductrice est inférieure à la valeur minimum de la résistance électrique de la couche d'enregistrement. La couche d'oxyde électroconductrice est constituée d'un mélange de (i) une première matière servant de composant principal et sélectionnée dans le groupe comprenant les éléments suivants : ZnO, SnO2, CoO, TiOs (avec 1 ≤ s ≤ 2), In2O3, IrO2, et RuO2 ; et (ii) une seconde matière servant d’agent dopant et sélectionnée dans le groupe comprenant les éléments suivants : Ga2O3, Al2O3, Nb2O5, SnO2, Ta2O5, Sb2O3, ZnO, et TiOs (avec 1 ≤ s ≤ 2).
PCT/JP2008/056498 2008-04-01 2008-04-01 Dispositif d'enregistrement et de lecture d'informations WO2009122571A1 (fr)

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WO2013003978A1 (fr) * 2011-07-06 2013-01-10 复旦大学 Mémoire de type résistif à base d'oxyde de tantale dopé par du ruthénium et son procédé de fabrication
JP5861719B2 (ja) * 2014-01-17 2016-02-16 Tdk株式会社 透明導電体及びタッチパネル
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