WO2009122571A1 - Information recording/reproducing device - Google Patents
Information recording/reproducing device Download PDFInfo
- Publication number
- WO2009122571A1 WO2009122571A1 PCT/JP2008/056498 JP2008056498W WO2009122571A1 WO 2009122571 A1 WO2009122571 A1 WO 2009122571A1 JP 2008056498 W JP2008056498 W JP 2008056498W WO 2009122571 A1 WO2009122571 A1 WO 2009122571A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- recording
- layer
- conductive oxide
- recording layer
- oxide layer
- Prior art date
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- 239000000463 material Substances 0.000 claims abstract description 62
- 230000008859 change Effects 0.000 claims abstract description 26
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000002019 doping agent Substances 0.000 claims abstract description 15
- 239000000203 mixture Substances 0.000 claims abstract description 15
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 4
- 230000015654 memory Effects 0.000 claims description 125
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- 239000013078 crystal Substances 0.000 claims description 19
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052748 manganese Inorganic materials 0.000 claims description 12
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 229910052720 vanadium Inorganic materials 0.000 claims description 10
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 229910052742 iron Inorganic materials 0.000 claims description 9
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052758 niobium Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910052596 spinel Inorganic materials 0.000 claims description 8
- 239000011029 spinel Substances 0.000 claims description 8
- 229910052715 tantalum Inorganic materials 0.000 claims description 8
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical group [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 229910052703 rhodium Inorganic materials 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910007991 Si-N Inorganic materials 0.000 claims description 6
- 229910006294 Si—N Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052787 antimony Inorganic materials 0.000 claims description 6
- 229910052791 calcium Inorganic materials 0.000 claims description 6
- 229910052741 iridium Inorganic materials 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 6
- 229910052712 strontium Inorganic materials 0.000 claims description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052749 magnesium Inorganic materials 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 229910052745 lead Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052700 potassium Inorganic materials 0.000 claims description 4
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(II) oxide Inorganic materials [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 claims description 3
- 239000010431 corundum Substances 0.000 claims description 3
- YDZQQRWRVYGNER-UHFFFAOYSA-N iron;titanium;trihydrate Chemical group O.O.O.[Ti].[Fe] YDZQQRWRVYGNER-UHFFFAOYSA-N 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910018540 Si C Inorganic materials 0.000 claims description 2
- 229910011208 Ti—N Inorganic materials 0.000 claims description 2
- 229910052790 beryllium Inorganic materials 0.000 claims description 2
- ZXOKVTWPEIAYAB-UHFFFAOYSA-N dioxido(oxo)tungsten Chemical group [O-][W]([O-])=O ZXOKVTWPEIAYAB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910052762 osmium Inorganic materials 0.000 claims description 2
- 229910052701 rubidium Inorganic materials 0.000 claims description 2
- 229910052708 sodium Inorganic materials 0.000 claims description 2
- 229910052950 sphalerite Inorganic materials 0.000 claims description 2
- 229910052716 thallium Inorganic materials 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 229910052984 zinc sulfide Inorganic materials 0.000 claims description 2
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 abstract description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract 4
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 abstract 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- GHPGOEFPKIHBNM-UHFFFAOYSA-N antimony(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Sb+3].[Sb+3] GHPGOEFPKIHBNM-UHFFFAOYSA-N 0.000 abstract 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 abstract 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 abstract 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 abstract 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract 1
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 321
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- 239000012212 insulator Substances 0.000 description 13
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- 150000001450 anions Chemical class 0.000 description 9
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- 229910010413 TiO 2 Inorganic materials 0.000 description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
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- 238000012546 transfer Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 229910052747 lanthanoid Inorganic materials 0.000 description 2
- 150000002602 lanthanoids Chemical class 0.000 description 2
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- 238000006479 redox reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 description 2
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 229910020068 MgAl Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 230000007613 environmental effect Effects 0.000 description 1
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- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
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- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
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- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
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- 229910000859 α-Fe Inorganic materials 0.000 description 1
Images
Classifications
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- G—PHYSICS
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-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
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- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8416—Electrodes adapted for supplying ionic species
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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Definitions
- the present invention relates to an information recording / reproducing apparatus having a high recording density.
- NAND flash memory and small HDD hard disk drive
- PCRAM phase change memory
- a material that can take two states, an amorphous state (ON) and a crystalline state (OFF), as a recording material, and these two states are represented by binary data “0”. , “1” is used to record data.
- an amorphous state is created by applying a high power pulse to the recording material, and a crystalline state is created by applying a small power pulse to the recording material.
- Reading is performed by passing a small read current that does not cause writing / erasing to the recording material and measuring the electrical resistance of the recording material.
- the resistance value of the recording material in the amorphous state is larger than the resistance value of the recording material in the crystalline state, and the ratio is about 10 3 .
- PCRAM Physical Random Access Memory
- Tbpsi terra bit per square inch
- a typical example of a recording material for recording data is nickel oxide, and similarly to PCRAM, a high power pulse and a small power pulse are used for writing / erasing. In this case, it has been reported that the power consumption at the time of writing / erasing is smaller than that of the PCRAM.
- MEMS memories using MEMS (micro-electro-mechanical systems) technology have been proposed (for example, P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz and G. K. Binnig, IEEE Trans. Nanotechnology 1, 39 (2002)).
- a MEMS memory called Millipede has a structure in which a plurality of cantilevers arranged in an array and a recording medium coated with an organic substance face each other, and the probe at the tip of the cantilever is applied to the recording medium with an appropriate pressure. In contact.
- the writing is performed by selectively controlling the temperature of the heater added to the probe. That is, when the temperature of the heater is increased, the recording medium is softened, and the probe is recessed into the recording medium, thereby forming a recess in the recording medium.
- Reading is performed by causing the probe to scan the surface of the recording medium while causing the probe to pass a current that does not soften the recording medium.
- the temperature of the probe decreases and the resistance value of the heater increases. Therefore, data can be sensed by reading the change in resistance value.
- the minimum recording unit is one unit cell of the ferroelectric layer crystal, the recording density becomes a huge value of about 4 Pbpsi (peta bit per square inch).
- the present invention provides a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption.
- the information recording / reproducing apparatus of the present invention includes a recording layer in which two or more states having different electrical resistivity are recorded, and a recording layer on the anode side when a voltage or current is applied to the recording layer to change the state of the recording layer
- a conductive oxide layer disposed at one end of the substrate.
- the electrical resistivity of the conductive oxide layer is smaller than the minimum value of the electrical resistivity of the recording layer.
- the conductive oxide layer is made of (i) a first material as a main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ⁇ s ⁇ 2), In 2 O 3 , IrO 2 , and RuO 2.
- a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
- FIG. 1 is a diagram showing the recording principle.
- FIG. 2 is a diagram showing the recording principle.
- FIG. 3 is a diagram illustrating the recording principle.
- FIG. 4 shows the recording principle.
- FIG. 5 shows the recording principle.
- FIG. 6 is a diagram showing a probe type solid-state memory.
- FIG. 7 is a diagram showing classification of recording media.
- FIG. 8 is a diagram showing a state during recording.
- FIG. 9 is a diagram showing a recording operation.
- FIG. 10 is a diagram showing a reproduction operation.
- FIG. 11 is a diagram showing a cross-point type solid-state memory.
- FIG. 12 is a diagram showing the structure of the memory cell array.
- FIG. 13 is a diagram showing the structure of the memory cell array.
- FIG. 14 is a diagram showing the structure of the memory cell array.
- FIG. 15 is a diagram showing a structure of a memory cell.
- FIG. 16 is a diagram illustrating an application example to a flash memory.
- FIG. 17 is a circuit diagram showing a NAND cell unit.
- FIG. 18 is a diagram showing the structure of the NAND cell unit.
- FIG. 19 is a diagram showing the structure of the NAND cell unit.
- FIG. 20 is a diagram showing the structure of the NAND cell unit.
- FIG. 21 is a circuit diagram showing a NOR cell.
- FIG. 22 is a diagram showing the structure of a NOR cell.
- FIG. 23 is a circuit diagram showing a two-tracell unit.
- FIG. 24 is a diagram illustrating a structure of a two-tracell unit.
- FIG. 25 is a diagram illustrating the structure of a two-tracell unit.
- An information recording / reproducing apparatus includes a recording layer in which two or more states having different electrical resistivity are recorded, and an anode side when a voltage or current is applied to the recording layer to change the state of the recording layer. And a conductive oxide layer disposed at one end of the recording layer.
- the electrode is (i) Ti-N, Ti-Si-N, Ta-N, Ta-Si-N, Si-N, Ti -Nitride, carbide or oxide of material selected from the group of -C, Ta-C, Si-C, (ii) a mixture of nitride and oxide of (i), (iii) of (i) It is composed of a mixture of nitride and carbide, (iv) a mixture of oxide and carbide of (i), or (v) a mixture of nitride, carbide and oxide of (i).
- a x M y X 4 (0.1 ⁇ x ⁇ 2.2,1.8 ⁇ y ⁇ 2), (2) A x M y X 3 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1 ), constituted by (3) a x M y X 4 (0.5 ⁇ x ⁇ 1.1,0.9 ⁇ y ⁇ 1 material selected from the group of).
- A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Elements selected from the group of Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi, M is Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, It is an element selected from the group of Ni, Nb, Ta, Mo, W, Ru, Rh.
- A is an element selected from the group of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, Bi.
- M is an element selected from the group of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, Os.
- a and M are mutually different elements
- X is an element selected from the group of O and N.
- the recording layer is composed of 1. corundum structure, 2. rutile structure, 3. spinel structure, 4. ramsdellite structure, 5. anatase structure, 6. hollandite structure, 7. brookite structure, 8. pyrolose structure, 9. NaCl structure, 10. It has a crystal structure selected from the group of perovskite structure, 11. ilmenite structure, and 12. wolframite structure.
- corundum structure examples include Al 2 O 3 , Cr 2 O 3 , ⁇ -Fe 2 O 3 , ⁇ -GaO 3 , Ti 2 O 3 , and V 2 O 3 .
- Examples of the rutile structure include TiO 2 and SnO 2 .
- the brookite structure, anatase structure and ramsdellite structure are modified structures of the rutile structure.
- the brookite structure is an orthorhombic form of a rutile structure.
- the spinel structure is typified by MgAl 2 O 4 , and other examples include ZnFe 2 O 4 and ZnMnO 3 .
- Cu 2 Mg and Mn 2 O 3 also have a spinel structure.
- Ba 2 Fe 12 O 19 and KFe 11 O 17 have a composite spinel structure.
- a typical example of the hollandite structure and pyroloose structure is MnO 2
- examples of the hollandite structure include ⁇ -MnO 2 and BiVO.
- Ilmenite structure includes FeTiO 3 .
- the perovskite structure which became famous for the discovery of high-temperature oxide superconductors, also has various deformation structures. Examples include BaTiO 3 , CaTiO 3 , GdFeO 3 and the like.
- NaCl structure examples include TiO and NiO.
- CuO can be understood as a modified version of the NaCl structure.
- the base crystal structure may be slightly distorted.
- a distorted spinel structure or a distorted NaCl structure may be used.
- another name called a heterolite structure for example, ZnMn 2 O 4
- ZnMn 2 O 4 ZnMn 2 O 4
- the recording layer is composed of, for example, a composite compound having one kind or two or more kinds of cation elements, and at least one of the cation elements is a transition element having a d orbital incompletely filled with electrons.
- the conductive oxide layer stably changes the electrical resistivity of the recording layer (set / reset operation) and applies a voltage or current to the recording layer to ensure its reproducibility. When changing, it is added to one end of the recording layer which becomes the anode side.
- a change in the electrical resistivity of the conductive oxide layer can be an unstable element of the set / reset operation.
- the electrical resistivity of the conductive oxide layer is made smaller than the minimum value of the electrical resistivity of the recording layer.
- the conductive oxide layer preferably has no change in electrical resistivity. However, if the electrical resistivity of the conductive oxide layer is sufficiently smaller than the minimum value of the electrical resistivity of the recording layer, the set / reset operation is performed. May change the electrical resistivity of the conductive oxide layer.
- the electrical resistivity of the conductive oxide layer is 1 ⁇ 10 ⁇ 1 ⁇ cm or less.
- the conductive oxide layer is (i) a first main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ⁇ s ⁇ 2), In 2 O 3 , IrO 2 , and RuO 2 . 1 material and selected from the group of (ii) Ga 2 O 3 , Al 2 O 3 , Nb 2 O 5 , SnO 2 , Ta 2 O 5 , Sb 2 O 3 , ZnO, TiO s (1 ⁇ s ⁇ 2) It is comprised from the mixture with the 2nd material as a dopant made.
- the proportion of the second material in the conductive oxide layer Is preferably 30 wt% or less, more preferably 20 wt% or less, and even more preferably 5 wt% or less.
- the main point of selecting such a material is to prevent the conductive oxide layer from becoming an unstable element of the set / reset operation.
- the characteristics of strongly correlated systems change in the same way as materials that can be interpreted by band theory such as semiconductors. That is, the electrical characteristics, magnetic characteristics, dielectric characteristics, and the like of the material change depending on the crystal structure, crystal grain size, orientation, impurities, and the like.
- the selection of the above-mentioned materials controls the crystallinity such as crystal grain size and orientation, and stably obtains good device characteristics. It is effective for.
- the material of the conductive oxide layer is composed of electrical resistivity and controllability, adhesion to other films, diffusion prevention, heat resistance, etching property, chemical resistance including gas and solution, crystallinity. , Orientation, and controllability thereof are selected.
- ITO a material in which In 2 O 3 is doped with SnO 2 is known as ITO. Since ITO is a material having a low electrical resistivity, it is advantageous for realizing an electrical resistivity lower than that of the recording layer.
- ZnO is known as a material that is easily oriented. Therefore, it is predicted that a highly oriented film can be easily formed if there is a crystal plane with a close lattice constant or a close lattice spacing.
- the electrical resistivity of ZnO is larger than that of ITO, and since Zn is known as an element that easily volatilizes, simply using only ZnO diffuses Zn into other films, or Zn escapes from the conductive oxide layer, causing problems such as unstable electrical resistivity. In such a case, such a problem can be solved if ZnO contains the second material as a dopant.
- TiO s may be in the range of TiO s (1 ⁇ s ⁇ 2).
- the conductive oxide layer is selected from the group consisting of (I) sphalerite structure, (II) wurtzite structure, (III) C-rare earth structure, (IV) rutile structure, and (V) NaCl structure. It preferably has a crystal structure.
- the recording layer has a thickness of 5 nm or more and 50 nm or less
- the conductive oxide layer has a thickness of 0.5 nm or more and 10 nm or less.
- the recording layer assumes one of two states having different electric resistivity, and a description will be given of a system in which two types of ions exist.
- the initial state of the recording layer is an insulator (high resistance state), for example, a state where the electrical resistivity is 10 3 ⁇ ⁇ cm. Then, by applying a potential difference to both ends of the recording layer, a part of the cation element existing inside the recording layer moves to the cathode (negative electrode) side.
- the recording layer is positioned on the anode (positive electrode) side and the conductive oxide layer is positioned on the cathode side, the cation element discharged from the recording layer is introduced into the conductive oxide layer, and the conductivity is increased.
- the proportion of the cationic element is relatively higher than the proportion of the anionic element.
- the conductive oxide layer receives electrons from the cathode in order to maintain electrical neutrality, and becomes a compound in a low oxidation state as a result of a decrease in the valence of the transition element in the conductive oxide layer.
- the recording layer on the anode side has a relatively lower proportion of the cationic element than the proportion of the anionic element, it emits electrons to the anode and becomes a highly oxidized compound.
- the recording layer is in a low resistance state, for example, a state in which the electrical resistivity is 10 0 ⁇ ⁇ cm.
- the thermal energy returns to the low energy stable state insulator (high resistance state) before setting again.
- the electrical resistivity of the conductive oxide layer does not change when the resistance of the recording layer is changed as described above, but the electrical resistivity of the conductive oxide layer is the minimum of the electrical resistivity of the recording layer. If the value is sufficiently smaller than the value, there is no problem even if the electric resistivity of the conductive oxide layer changes.
- a Pbpsi (Peta per square inch) class can be realized, and further a significant improvement in write disturb resistance can be realized.
- FIG. 1 shows the structure of a recording unit as a premise of the present invention.
- Reference numeral 11 denotes an electrode layer
- 12 denotes a recording layer
- 13A denotes an electrode layer (or a protective layer).
- a small white circle in the recording layer 12 represents a representative element as a diffusion ion
- a small black circle represents a transition element as a cation.
- a large white circle represents a typical element as an anion.
- the initial state of the recording layer 12 is an insulator (high resistance state), and for information recording, the recording layer 12 is phase-changed by a potential gradient to make the recording layer 12 conductive (see FIG. (Low resistance state)
- the high resistance state is defined as a reset state
- the low resistance state is defined as a set state.
- this definition is intended to simplify the following description. Depending on the selection of materials and the manufacturing method, this definition may be reversed, that is, the low resistance state becomes the reset (initial) state.
- the state may be set. That is, it goes without saying that such a case is also included in the scope of the present invention.
- a state in which the potential of the electrode layer 13A is relatively lower than the potential of the electrode layer 11 is created. If the electrode layer 11 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the electrode layer 13A.
- a fixed potential for example, ground potential
- the diffusion ions in the recording layer 12 move to the electrode layer (cathode) 13A side, and the diffusion ions in the recording layer (crystal) 12 decrease relative to the anions.
- the diffused ions that have moved to the electrode layer 13A side receive electrons from the electrode layer 13A and precipitate as metal, so that the metal layer 14 is formed.
- anions become excessive, and as a result, the valence of transition element ions in the recording layer 12 is increased. That is, since the recording layer 12 has electron conductivity by carrier injection, information recording (set operation) is completed.
- Information reproduction can be easily performed by flowing a current pulse through the recording layer 12 and detecting the resistance value of the recording layer 12.
- the current pulse needs to be a minute value that does not cause a phase change in the material constituting the recording layer 12.
- the above process is a kind of electrolysis, and an oxidizing agent is generated by electrochemical oxidation on the electrode layer (anode) 11 side, and a reducing agent is generated by electrochemical reduction on the electrode layer (cathode) 13A side. Can be considered.
- the recording layer 12 is Joule-heated with a large current pulse to promote the oxidation-reduction reaction of the recording layer 12. Just do it. That is, the recording layer 12 returns to the insulator due to the residual heat after the interruption of the large current pulse (reset operation).
- the coordination number of the diffuse ions is reduced (ideally 2 or less), the valence is 2 or more, or the anion valence is increased (ideally 3). This can be done.
- Such a recording layer 12 can be realized by the elements and crystal structure as described above.
- the electrode layer 11 is made of a material that is not easily oxidized (for example, electrically conductive nitride, electrically conductive oxide, etc.). Is preferred.
- the electrode layer 11 is preferably made of a material that does not have ionic conductivity.
- LaNiO 3 can be said to be the most preferable material from the viewpoint of comprehensive performance in consideration of good electrical conductivity and the like.
- ⁇ MN M contains at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta. N is nitrogen.
- ⁇ MO x M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
- the molar ratio x shall satisfy 1 ⁇ x ⁇ 4.
- ⁇ AMO 3 A contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba, and Ln (Lanthanide).
- M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
- O is oxygen
- ⁇ B 2 MO 4 B contains at least one element selected from the group of K, Ca, Sr, Ba, and Ln (Lanthanide).
- M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
- O is oxygen
- the electrode layer 13A preferably has a function of preventing the recording layer 12 from reacting with the atmosphere.
- Examples of such a material include semiconductors such as amorphous carbon, diamond-like carbon, and SnO 2 .
- the electrode layer 13A may function as a protective layer for protecting the recording layer 12, or a protective layer may be provided instead of the electrode layer 13A.
- the protective layer may be an insulator or a conductor.
- FIG. 2 shows the structure of a recording unit according to an example of the present invention.
- 11 is an electrode layer
- 12 is a recording layer
- 13A is an electrode layer (or protective layer)
- 15 is a conductive oxide layer.
- Small white circles in the recording layer 12 represent typical elements as diffusion ions, and small black circles represent transition elements as cations.
- a large white circle represents a typical element as an anion.
- This structure is different from the structure of FIG. 1, which is the premise of the present invention, in that when a voltage or current is applied to the recording layer 12 to change the state of the recording layer 12, specifically, when a set operation is performed.
- the conductive oxide layer 15 is disposed at one end of the recording layer 12 on the anode side.
- the conductive oxide layer 15 may have a cavity site.
- the void site is a site that stores a cation element that has moved from the recording layer 12.
- the conductive oxide layer 15 has void sites, the effect of facilitating the movement of ions in the recording layer 12 is exhibited, and the composition range of the conductive oxide layer 15 is adjusted so that the recording layer 12 Improve electronic conductivity and ensure stability of crystal structure. As a result, the disturb resistance of the recording layer 12 is improved.
- an insulator having a thickness of about several nanometers having a permeability of ions discharged from the recording layer 12 may be inserted between the recording layer 12 and the conductive oxide layer 15.
- This insulator is composed of a compound or composite compound containing at least an ionic element discharged from the recording layer 12 and other typical elements. This lowers the on-resistance of the recording unit.
- FIG. 3 represents the structure of FIG. In the recording layer 12, for example, two states with different electrical resistivity are recorded.
- ⁇ rr is the electrical resistivity of the recording layer 12 in the reset state (high resistance state)
- ⁇ rs is the electrical resistivity of the recording layer 12 in the set state (low resistance state).
- ⁇ or is the electrical resistivity of the conductive oxide layer 15 when the recording layer 12 is in the reset state
- ⁇ os is the electrical resistivity of the conductive recording layer 15 when the recording layer 12 is in the set state.
- FIG. 4 is a modification of the structure of FIG. For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively.
- a conductive oxide layer 15 is added to the end of the recording layer 12-1 on the anode side.
- the conductive oxide layer 15 is also formed on the end of the recording layer 12-2 on the anode side. Added.
- the threshold value for changing the state of the recording layer 12-1 and the threshold value for changing the state of the recording layer 12-2 are set to different values to enable multi-level recording.
- ⁇ rr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ⁇ rs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state).
- ⁇ rr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ⁇ rs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
- the electrical resistivity ⁇ or, ⁇ os of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ⁇ rr1, ⁇ rs1, ⁇ rr2, ⁇ rs2 of the recording layers 12-1, 12-2.
- FIG. 5 is also a modification of the structure of FIG. For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. Further, a conductive oxide layer 15 is disposed between the electrode layer 11 as an anode and the recording layer 12-1.
- the threshold for changing the state of the recording layer 12-1 and the threshold for changing the state of the recording layer 12-2 are set to different values to enable multi-value recording.
- ⁇ rr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ⁇ rs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state).
- ⁇ rr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ⁇ rs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
- the electrical resistivity ⁇ or, ⁇ os of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ⁇ rr1, ⁇ rs1, ⁇ rr2, ⁇ rs2 of the recording layers 12-1, 12-2.
- Probe type solid-state memory A Structure 6 and 7 show a probe type solid state memory according to an example of the present invention.
- An electrode layer 21 is disposed on the semiconductor substrate 20, and a recording unit 22 having a data area and a servo area is disposed on the electrode layer 21.
- the recording unit (recording medium) 22 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG.
- the recording unit 22 is solidly formed at the center of the semiconductor substrate 20.
- the servo area is arranged along the edge of the semiconductor substrate 20.
- the data area and servo area are composed of multiple blocks.
- a plurality of probes 24 are arranged corresponding to a plurality of blocks.
- Each of the plurality of probes 24 has a sharpened shape.
- the plurality of probes 24 constitutes a probe array and is formed on one surface side of the semiconductor substrate 23.
- the plurality of probes 24 can be easily formed on one surface side of the semiconductor substrate 23 by using the MEMS technology.
- the position of the probe 24 on the data area is controlled by a servo burst signal read from the servo area. Specifically, the access operation is executed by causing the driver 27 to reciprocate the semiconductor substrate 20 in the X direction and controlling the position of the plurality of probes 24 in the Y direction.
- the recording medium is formed independently for each block, and the recording medium is configured to rotate in a circle like a hard disk, and each of the plurality of probes 24 is moved in the radial direction of the recording medium, for example, the X direction. You may do it.
- Each of the plurality of probes 24 has a function as a recording / erasing head and a function as a reproducing head.
- the multiplex drivers 25 and 26 supply a predetermined voltage to the plurality of probes 24 at the time of recording, reproduction, and erasing.
- FIG. 8 shows the recording operation (set operation).
- the recording unit (recording medium) 22 is formed on the electrode layer 21 on the semiconductor chip 20.
- the recording unit 22 is covered with the protective layer 13B.
- the tip of the probe 24 is brought into contact with the surface of the protective layer 13B, a voltage pulse is applied to the recording unit 30 of the recording unit (recording medium) 22, and a potential gradient is generated in the recording unit 30 of the recording unit 22.
- a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.
- the voltage pulse may be generated by emitting electrons from the probe 24 toward the electrode layer 21 using, for example, an electron generation source or a hot electron source.
- some of the diffusion ions move to the probe (cathode) 24 side, and the diffusion ions in the crystal are relative to the anions. To decrease.
- the diffused ions that have moved to the probe 24 side receive electrons from the probe 24 and are deposited as metal.
- anions become excessive, and as a result, the valence of the transition element ions left in the recording layer 12 is increased. That is, since the recording unit 30 of the recording layer 12 has electron conductivity due to carrier injection due to phase change, information recording (set operation) is completed.
- the voltage pulse for information recording can be generated by creating a state in which the potential of the probe 24 is relatively higher than the potential of the electrode layer 21.
- the probe type solid-state memory of this example information can be recorded in the recording unit 30 of the recording medium as in the case of the hard disk, and by adopting a new recording material, the conventional solid-state memory or semiconductor memory can be used. High recording density can be realized.
- FIG. 10 shows the reproduction operation.
- the reproduction operation is performed by flowing a voltage pulse to the recording unit 30 of the recording layer 12 and detecting the resistance value of the recording unit 30 of the recording layer 12.
- the voltage pulse is set to a minute value so that the material constituting the recording unit 30 of the recording layer 12 does not cause a phase change.
- the read current generated by the sense amplifier S / A is passed from the probe 24 to the recording unit 30 of the recording layer 12, and the resistance value of the recording unit 30 is measured by the sense amplifier S / A. If the new material already described is adopted, the resistance ratio between the high resistance state and the low resistance state can be secured at 10 3 or more.
- the erasing (reset) operation is performed by heating the recording unit 30 of the recording layer 12 with a large current pulse to promote the oxidation-reduction reaction in the recording unit 30 of the recording layer 12.
- it can also be performed by applying a voltage pulse in the direction opposite to that at the time of setting to the recording layer 12.
- the erasing operation can be performed for each recording unit 30, or can be performed for a plurality of recording units 30 or blocks.
- FIG. 11 shows a cross-point type solid state memory according to an example of the present invention.
- the word lines WL i ⁇ 1 , WL i , WL i + 1 extend in the X direction, and the bit lines BL j ⁇ 1 , BL j , BL j + 1 extend in the Y direction.
- each of the word lines WL i ⁇ 1 , WL i , WL i + 1 is connected to the word line driver & decoder 31 via a MOS transistor RSW as a selection switch, and the bit lines BL j ⁇ 1 , BL j , BL j + 1 One end is connected to a bit line driver & decoder & read circuit 32 via a MOS transistor CSW as a selection switch.
- Selection signals R i ⁇ 1 , R i , and R i + 1 for selecting one word line (row) are input to the gate of the MOS transistor RSW, and one bit line is input to the gate of the MOS transistor CSW.
- Selection signals C j ⁇ 1 , C j , and C j + 1 for selecting (column) are input.
- the memory cell 33 is arranged at the intersection of the word lines WL i ⁇ 1 , WL i , WL i + 1 and the bit lines BL j ⁇ 1 , BL j , BL j + 1 . This is a so-called cross-point cell array structure.
- a diode 34 for preventing a sneak current during recording / reproduction is added to the memory cell 33.
- FIG. 12 shows the structure of the memory cell array portion of the cross-point type solid-state memory shown in FIG.
- word lines WL i ⁇ 1 , WL i , WL i + 1 and bit lines BL j ⁇ 1 , BL j , BL j + 1 are arranged, and memory cells 33 and diodes 34 are arranged at intersections of these wirings. Is done.
- cross-point type cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33.
- FIGS. 13 and 14 it is possible to stack the memory cells 33 to make the memory cell array have a three-dimensional structure.
- the memory cell 33 has a stacked structure of a recording layer 12, a conductive oxide layer 15, and a protective layer 13B.
- One memory cell 33 stores data of 1 bit or more.
- the diode 34 is disposed between the word line WL i and the memory cell 33.
- a barrier metal may be disposed between at least one of the word line WL i and the diode 34 and between the protective layer 13B and the bit line BL j .
- the diode 34 is preferably omitted when the set / reset operation is performed only by the direction of the voltage.
- the potential of the word line WL i is a bit. making a relatively lower than the potential of the line BL j. If the bit line BL j is set to a fixed potential (for example, ground potential), a negative potential may be applied to the word line WL i .
- the diffusion ions in the recording layer 12 are anions. It decreases relative to. Further, the diffused ions that have moved to the word line WL i side receive electrons from the word line WL i and are deposited as metal.
- the non-selected word lines WL i ⁇ 1 and WL i + 1 and the non-selected bit lines BL j ⁇ 1 and BL j + 1 are all biased to the same potential.
- the voltage pulse for recording information may be generated by creating a state in which the potential of the word line WL i is relatively higher than the potential of the bit line BL j .
- the erase (reset) operation uses Joule heat generated by flowing a large current pulse to the selected memory cell 33 and its residual heat, for example, the potential of the word line WL i is set higher than the potential of the bit line BL j . Also make it relatively high. If the bit line BL j is set to a fixed potential (eg, ground potential), a positive potential may be applied to the word line WL i .
- a fixed potential eg, ground potential
- the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
- the erase operation can also be performed by the following method.
- the potential of the word line WL i is made relatively lower than the potential of the bit line BL j .
- Bit lines BL j and a fixed potential e.g., ground potential
- a negative potential may be applied to the word line WL i.
- the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
- the unselected word lines WL i ⁇ 1 , WL i + 1 and the unselected bit lines BL j ⁇ 1 , BL j + 1 are all biased to the same potential.
- the read operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33.
- the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.
- read current generated by the reading circuit (current pulses) to the memory cell 33 surrounded by the dotted line A from the bit line BL j, measure the resistance value of the memory cell 33 by the read circuit. If the new material already explained is adopted, the difference in resistance value between the set / reset states can be secured at 10 3 or more.
- probe type solid-state memory and the cross-point type solid-state memory have been described.
- material and principle proposed in the example of the present invention can be applied to a recording medium such as a current hard disk or DVD. It is.
- FIG. 16 shows a memory cell of the flash memory.
- the memory cell of flash memory is composed of MIS (metal-insulator-semiconductor) transistors.
- a diffusion layer 42 is formed in the surface region of the semiconductor substrate 41.
- a gate insulating layer 43 is formed on the channel region between the diffusion layers 42.
- a recording portion (ReRAM: Resistive RAM) 44 is formed on the gate insulating layer 43.
- a control gate electrode 45 is formed on the recording unit 44.
- the semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types.
- the control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.
- the recording unit 44 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG.
- the difference between the potentials V1 and V2 needs to be large enough for the recording unit 44 to undergo phase change or resistance change, but the direction is not particularly limited.
- V1> V2 or V1 ⁇ V2 may be used.
- the gate insulating layer 43 is substantially thickened, and thus the threshold value of the memory cell (MIS transistor). Get higher.
- the gate insulating layer 43 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is , Get lower.
- the potential V2 is applied to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.
- the reset (erase) operation is performed by applying the potential V1 'to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 ( ⁇ V3) to the other of the diffusion layers 42.
- the potential V1 ' is set to a value exceeding the threshold value of the memory cell in the set state.
- the memory cell is turned on, electrons flow from one side of the diffusion layer 42 to the other side, and hot electrons are generated. Since the hot electrons are injected into the recording unit 44 through the gate insulating layer 43, the temperature of the recording unit 44 rises.
- the recording unit 44 changes from a conductor (low resistance) to an insulator (high resistance)
- the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is , Get higher.
- the information recording / reproducing apparatus can be put into practical use by utilizing the technology of the flash memory.
- FIG. 17 shows a circuit diagram of the NAND cell unit.
- FIG. 18 shows the structure of a NAND cell unit according to an example of the present invention.
- an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
- a NAND cell unit according to an example of the present invention is formed in the P-type well region 41c.
- the NAND cell unit includes a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to both ends thereof.
- the memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
- the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
- the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
- One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.
- the set (write) operation is sequentially performed one by one from the memory cell MC on the source line SL side toward the memory cell on the bit line BL side.
- V1 (plus potential) is applied as a write potential to the selected word line (control gate electrode) WL
- Vpass is applied as a transfer potential (potential at which the memory cell MC is turned on) to the unselected word line WL.
- the select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
- a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording unit 44 of the selected memory cell MC
- the resistance value should not change from a high state to a low state.
- V2 ( ⁇ V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording unit 44 of the selected memory cell MC is changed from a high state to a low state. To change.
- V1 ' is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 ( ⁇ V3) is applied to the source line SL.
- the reset operation is executed collectively for all the memory cells MC in the NAND cell unit.
- a read potential (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL.
- a potential to be turned on without fail is given.
- the two select gate transistors ST are turned on to supply a read current to the NAND string.
- the selected memory cell MC When a read potential is applied to the selected memory cell MC, the selected memory cell MC is turned on or off according to the value of the data stored therein. For example, data can be read by detecting a change in the read current. it can.
- the select gate transistor ST has the same structure as the memory cell MC.
- the select gate transistor ST has a recording portion (recording layer and conductive layer). It is also possible to form a normal MIS transistor without forming the conductive oxide layer.
- FIG. 20 shows a modification of the NAND flash memory.
- This modification is characterized in that the gate insulating layer of the plurality of memory cells MC constituting the NAND string is replaced with a P-type semiconductor layer 47.
- the P-type semiconductor layer 47 is filled with a depletion layer in a state where no voltage is applied.
- a positive write potential for example, 3.5 V
- a positive transfer potential to the control gate electrode 45 of the non-selected memory cell MC. For example, give 1V).
- the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.
- the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.
- reset is performed by applying a negative erase potential (for example, ⁇ 3.5 V) to all the control gate electrodes 45 and applying a ground potential (0 V) to the P-type well region 41 c and the P-type semiconductor layer 47. This can be performed collectively for all the memory cells MC constituting the NAND string.
- a negative erase potential for example, ⁇ 3.5 V
- a positive read potential for example, 0.5 V
- the memory cell MC receives data “0” to the control gate electrode 45 of the non-selected memory cell MC.
- a transfer potential for example, 1 V that is always turned on regardless of “1” is applied.
- the threshold voltage Vth ”1” of the memory cell MC in the “1” state is in the range of 0V ⁇ ⁇ ⁇ Vth ”1” ⁇ 0.5V
- the threshold voltage Vth ”0 of the memory cell MC in the“ 0 ”state “” Shall be in the range of 0.5V0.5 ⁇ Vth ”0” ⁇ 1V.
- the two select gate transistors ST are turned on to supply a read current to the NAND string.
- the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0.5 than that of the P-type well region 41c. It is preferable that the depth is about V.
- the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed.
- the channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
- the diffusion layer 42 and the control gate electrode 45 are not short-circuited.
- FIG. 21 shows a circuit diagram of the NOR cell unit.
- FIG. 22 shows the structure of a NOR cell unit according to an example of the present invention.
- an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
- a NOR cell according to an example of the present invention is formed in the P-type well region 41c.
- the NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
- the memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a control on the recording unit 44. And a gate electrode 45.
- ReRAM recording unit
- the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
- FIG. 23 shows a circuit diagram of a two-tracell unit.
- FIG. 24 shows the structure of a two-tracell unit according to an example of the present invention.
- the 2 tracell unit was recently developed as a new cell structure that combines the features of NAND cell units and NOR cells.
- an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a.
- the two tracell unit according to the example of the present invention is formed in the P-type semiconductor substrate 41a.
- the 2 tracell unit is composed of one memory cell MC and one select gate transistor ST connected in series.
- the memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
- the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
- the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
- the select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.
- the state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
- the select gate transistor ST has the same structure as the memory cell MC.
- the select gate transistor ST has a recording portion (recording layer and conductive oxide).
- a normal MIS transistor can be formed without forming a physical layer.
- Example A description will be given of an embodiment in which several samples are prepared and the resistance difference between the reset (erase) state and the set (write) state is evaluated.
- a device having the system of FIG. 8 and having the recording unit 22 having the structure of FIG. 2 (the recording layer 12 and the conductive oxide layer 15) is used.
- ⁇ Evaluation uses a probe pair whose tip diameter is sharpened to 10nm or less.
- the probe pair is brought into contact with the protective layer 13B, and information recording (writing / erasing) is performed using one of them.
- Writing is performed by applying a voltage pulse of 1 V to the recording unit 22 with a width of 10 nsec, for example.
- Erasing is performed by applying a voltage pulse of 0.2 V to the recording unit 22 with a width of 100 nsec, for example.
- DC evaluation is also possible like a semiconductor parameter analyzer.
- read is executed using the other one of the probe pair between write / erase. Reading is performed by applying a voltage pulse of 0.1 V with a width of 10 nsec to the recording unit 22 and measuring the resistance value of the recording unit (recording bit) 22.
- the recording layer 12 is made of Zn 1.1 Mn 1.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of ZnO doped with 2 wt.% Ga 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the material of the electrode layer 21 is four types of TiN, TiSiN, TaN, and TaSiN.
- the electrode layer 21 SiN, TiC, TaC, SiC or the like is considered suitable.
- Metal materials such as Pt, Ru, and Ir are not preferable as the material of the electrode layer 21 because they are expensive.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the set / reset voltage hardly depends on the thickness of the conductive oxide layer 15. This is thought to be because it is difficult to perfectly match the impedance and measurement error due to ringing or the like is included about 10%. In other words, the influence of the thickness of the conductive oxide layer 15 on the set / reset voltage can be estimated to be about 10%.
- the recording layer 12 is made of Zn 1.1 Mn 2.0 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of ZnO doped with 2.5 wt.% Of Al 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of ZnCo 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of CoO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- Recording layer 12 a TiZn 2 O 4, are prepared three kinds of thickness (10nm, 20nm, 50nm).
- the conductive oxide layer 15 is made of TiO 2 doped with 1 wt.% Of Nb 2 O 5 and has three types of thickness (0.5 nm, 5 nm, and 10 nm).
- the amount of dopant with respect to the conductive oxide layer (TiO 2 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of ZnMnO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is SnO 2 doped with 1 wt.% Of Sb 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant for the conductive oxide layer (SnO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of TiZn 2 O 3.8, and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of In 2 O 3 doped with 1 wt.% Of TiO 2 and ZnO, and three kinds of thicknesses (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (In 2 O 3 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of ZnMoO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of IrO 2 doped with 1% by weight of ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant for the conductive oxide layer (IrO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of ZnFe 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of RuO 2 doped with 1 wt.% ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of Mn 3 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of ZnO doped with 2.6 wt.% Al23, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the recording layer 12 is made of Mn 2.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared.
- the conductive oxide layer 15 is made of TiO 2 + doped with 1.1 wt.% Of Nb2O5, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
- the amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
- the reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
- the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
- the specification of the sample of the comparative example is as follows.
- the recording layer 12 is made of Fe 1.9 O 3 having a thickness of 10 nm and does not use a conductive oxide layer. That is, the recording unit 22 is composed of only the recording layer 12.
- the reset voltage during unipolar operation was + 0.5V
- the set voltage was + 1.5V
- the reset voltage during bipolar operation was + 0.5V
- the set voltage was -0.5V.
- the cycle characteristics were poor and the upper limit of the number of rewrites was about several hundred times.
- the set voltage during the bipolar operation is higher than the set voltage during the unipolar operation.
- the set voltage during the bipolar operation is lower than the set voltage during the unipolar operation.
- the on-state resistance value increases, the on-current decreases, and a set / reset operation with extremely low power consumption becomes possible. This enables simultaneous processing of a large number of cells and realizes extremely high speed operation.
- Table 2 summarizes the verification results of the first to eighth examples and the comparative example.
- the example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention.
- Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.
- the example of the present invention According to the information recording / reproducing apparatus according to the example of the present invention, it is possible to perform information recording at a recording density that cannot be achieved by the prior art, and at the same time to achieve high-speed operation, despite the extremely simple mechanism. become. Therefore, the example of the present invention has a great industrial advantage as a next generation technology that breaks down the recording density barrier of the current nonvolatile memory.
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Abstract
This invention provides a nonvolatile information recording/reproducing device which can realize high-recording density and low-power consumption. The information recording/reproducing device comprises a recording layer on which two or more different electric resistance states are recorded, and an electroconductive oxide layer, disposed at one end of the recording layer, which, when voltage or current is applied to the recording layer to change the state of the recording layer, is on the anode side. The electric resistance of the electroconductive oxide layer is smaller than the minimum value of the electric resistance of the recording layer. The electroconductive oxide layer is formed of a mixture of (i) a first material as a main component, selected from the group consisting of ZnO, SnO2, CoO, TiOs (wherein 1 ≤ s ≤ 2), In2O3, IrO2, and RuO2, and (ii) a second material as a dopant selected from the group consisting of Ga2O3, Al2O3, Nb2O5, SnO2, Ta2O5, Sb2O3, ZnO, and TiOs (wherein 1 ≤ s ≤ 2).
Description
本発明は、高記録密度の情報記録再生装置に関する。
The present invention relates to an information recording / reproducing apparatus having a high recording density.
近年、小型携帯機器が世界的に普及し、同時に、高速情報伝送網の大幅な進展に伴い、小型大容量不揮発性メモリの需要が急速に拡大してきている。その中でも、ＮＡＮＤ型フラッシュメモリ及び小型ＨＤＤ(hard disk drive)は、特に、急速な記録密度の進化を遂げ、大きな市場を形成するに至っている。
In recent years, small portable devices have become widespread worldwide, and at the same time, with the rapid progress of high-speed information transmission networks, the demand for small-sized and large-capacity nonvolatile memories has been rapidly expanding. Among them, NAND flash memory and small HDD (hard disk drive) have achieved a rapid development of recording density, and have formed a large market.
このような状況の下、記録密度の限界を大幅に超えることを目指した新規メモリのアイデアがいくつか提案されている。
In this situation, several new memory ideas have been proposed aiming to greatly exceed the recording density limit.
例えば、ＰＣＲＡＭ(相変化メモリ)は、記録材料として、アモルファス状態（オン）と結晶状態（オフ）の２つの状態をとることができる材料を使用し、この２つの状態を２値データ“０”，“１”に対応させてデータを記録する、という原理を採用する。
For example, PCRAM (phase change memory) uses a material that can take two states, an amorphous state (ON) and a crystalline state (OFF), as a recording material, and these two states are represented by binary data “0”. , “1” is used to record data.
書き込み／消去に関しては、例えば、大電力パルスを記録材料に印加することによりアモルファス状態を作り、小電力パルスを記録材料に印加することにより結晶状態を作る。
Regarding writing / erasing, for example, an amorphous state is created by applying a high power pulse to the recording material, and a crystalline state is created by applying a small power pulse to the recording material.
読み出しに関しては、記録材料に、書き込み／消去が起こらない程度の小さな読み出し電流を流し、記録材料の電気抵抗を測定することにより行う。アモルファス状態の記録材料の抵抗値は、結晶状態の記録材料の抵抗値よりも大きく、その比は、103程度である。
Reading is performed by passing a small read current that does not cause writing / erasing to the recording material and measuring the electrical resistance of the recording material. The resistance value of the recording material in the amorphous state is larger than the resistance value of the recording material in the crystalline state, and the ratio is about 10 3 .
ＰＣＲＡＭの最大の特長は、素子サイズを10nm程度にまで縮小しても動作できるという点にあり、この場合には、約10Tbpsi (terra bit per square inch)の記録密度を実現できるため、高記録密度化への候補の一つとされる（例えば、T. Gotoh, K. Sugawara and K. Tanaka, Jpn. J. Appl. Phys., 43, 6B, 2004, L818を参照）。
The biggest feature of PCRAM is that it can be operated even when the element size is reduced to about 10 nm. In this case, a recording density of about 10 Tbpsi (terra bit per square inch) can be realized. (See, for example, T. Gotoh, K. Sugawara and K. Tanaka, Jpn. J. Appl. Phys., 43, 6B, 2004, L818).
また、ＰＣＲＡＭとは異なるが、これと非常に似た動作原理を有する新規メモリが報告されている（例えば、A.Sawa, T.Fuji, M. Kawasaki and Y. Tokura, Appl. Phys. Lett., 85, 18, 4073 (2004)を参照）。
Also, a new memory has been reported which is different from PCRAM but has a very similar operation principle (for example, A.Sawa, T.Fuji, M. Kawasaki and Y. Tokura, Appl. Phys. Lett. , 85, 18, 4073 (2004)).
この報告によれば、データを記録する記録材料の代表例は、酸化ニッケルであり、ＰＣＲＡＭと同様に、書き込み／消去には、大電力パルスと小電力パルスとを使用する。この場合、ＰＣＲＡＭに比べて、書き込み／消去時の消費電力が小さくなる、という利点が報告されている。
According to this report, a typical example of a recording material for recording data is nickel oxide, and similarly to PCRAM, a high power pulse and a small power pulse are used for writing / erasing. In this case, it has been reported that the power consumption at the time of writing / erasing is smaller than that of the PCRAM.
現在までのところ、この新規メモリの動作メカニズムについては解明されていないが、再現性については確認されており、高記録密度化への候補の他の一つとされる。また、動作メカニズムについても、いくつかのグループが解明を試みている。
So far, the operation mechanism of this new memory has not been elucidated, but reproducibility has been confirmed, and it is considered as another candidate for higher recording density. In addition, several groups have tried to elucidate the operating mechanism.
これらの他、ＭＥＭＳ(micro electro mechanical systems)技術を使ったＭＥＭＳメモリが提案されている（例えば、P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W. Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz and G. K. Binnig, IEEE Trans. Nanotechnology 1, 39(2002)を参照）。
Besides these, MEMS memories using MEMS (micro-electro-mechanical systems) technology have been proposed (for example, P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz and G. K. Binnig, IEEE Trans. Nanotechnology 1, 39 (2002)).
特に、ミリピード(Millipede)と呼ばれるＭＥＭＳメモリは、アレイ状の複数のカンチレバーと有機物質が塗布された記録媒体とが対向する構造を有し、カンチレバーの先端のプローブは、記録媒体に適度な圧力で接触している。
In particular, a MEMS memory called Millipede has a structure in which a plurality of cantilevers arranged in an array and a recording medium coated with an organic substance face each other, and the probe at the tip of the cantilever is applied to the recording medium with an appropriate pressure. In contact.
書き込みに関しては、選択的に、プローブに付加されるヒータの温度を制御することにより行う。即ち、ヒータの温度を上げると、記録媒体が軟化し、プローブが記録媒体にめり込んで、記録媒体に窪みを形成する。
The writing is performed by selectively controlling the temperature of the heater added to the probe. That is, when the temperature of the heater is increased, the recording medium is softened, and the probe is recessed into the recording medium, thereby forming a recess in the recording medium.
読み出しに関しては、記録媒体が軟化しない程度の電流をプローブに流しながら、記録媒体の表面に対し、このプローブをスキャンさせることにより行う。プローブが記録媒体の窪みに落ち込むとプローブの温度が低下し、ヒータの抵抗値が上昇するため、この抵抗値の変化を読み取ることによりデータをセンスできる。
Reading is performed by causing the probe to scan the surface of the recording medium while causing the probe to pass a current that does not soften the recording medium. When the probe falls into the depression of the recording medium, the temperature of the probe decreases and the resistance value of the heater increases. Therefore, data can be sensed by reading the change in resistance value.
ミリピードのようなＭＥＭＳメモリの最大の特長は、ビットデータを記録する各記録部に配線を設ける必要がないため、記録密度を飛躍的に向上できる点にある。現状で、既に、1Tbpsi程度の記録密度を達成している（例えば、P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz, D. Wiesmann and G. K. Binnig, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis and E. Eleftheriou, in Technical Digest, IEDM03 pp.763-766を参照）。
The greatest feature of a MEMS memory such as millipede is that it is not necessary to provide a wiring in each recording unit for recording bit data, so that the recording density can be dramatically improved. At present, recording density of about 1 Tbpsi has already been achieved (for example, P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, M. A. Lants, H. E. Rothuizen, R. Stutz, tzD. Wiesmann and G. K. Binnig, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pandzi, H. Pandzi, E. Eleftheriou, in Technical Digest, IEDM03 pp.763-766).
また、ミリピードの発表を受けて、最近、ＭＥＭＳ技術と新たな記録原理とを組み合わせ、消費電力、記録密度や、動作速度などに関して大きな改善を達成しようという試みがなされている。
In response to the announcement of Millipede, recently, attempts have been made to achieve significant improvements in terms of power consumption, recording density, operating speed, etc. by combining MEMS technology with new recording principles.
例えば、記録媒体に強誘電体層を設け、記録媒体に電圧を印加することにより強誘電体層に誘電分極を引き起こしてデータの記録を行う方式が提案されている。この方式によれば、ビットデータを記録する記録部同士の間隔（記録最小単位）を結晶の単位胞レベルにまで近づけることができる、との理論的予測がある。
For example, there has been proposed a method of recording data by providing a ferroelectric layer on a recording medium and applying a voltage to the recording medium to cause dielectric polarization in the ferroelectric layer. According to this method, there is a theoretical prediction that the interval (recording minimum unit) between the recording units that record bit data can be brought close to the unit cell level of the crystal.
仮に、記録最小単位が強誘電体層の結晶の１単位胞になると、記録密度は、約4Pbpsi(peta bit per square inch)という巨大な値になる。
If the minimum recording unit is one unit cell of the ferroelectric layer crystal, the recording density becomes a huge value of about 4 Pbpsi (peta bit per square inch).
最近では、ＳＮＤＭ(走査型非線形誘電率顕微鏡)を用いた読み出し方式の提案により、この新規メモリは、実用化に向けてかなり進展してきている（例えば、A. Onoue, S. Hashimoto, Y. Chu, Mat. Sci. Eng. B120, 130(2005)を参照）。
Recently, due to the proposal of a readout method using SNDM (Scanning Nonlinear Dielectric Microscope), this new memory has made considerable progress toward practical use (for example, A. Onoue, S. Hashimoto, Y. Chu). , Mat. Sci. Eng. B120, 130 (2005)).
本発明は、高記録密度及び低消費電力の不揮発性の情報記録再生装置を提供する。
The present invention provides a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption.
本発明の情報記録再生装置は、異なる電気抵抗率の２以上の状態が記録される記録層と、記録層に電圧又は電流を与えて記録層の状態を変化させるときに陽極側となる記録層の一端に配置される導電性酸化物層とを備える。導電性酸化物層の電気抵抗率は、記録層の電気抵抗率の最小値よりも小さい。導電性酸化物層は、(i) ZnO、SnO2、CoO、TiOs(1≦s≦2)、In2O3、IrO2、RuO2のグループから選択される主成分としての第１材料と、(ii) Ga2O3、Al2O3、Nb2O5、SnO2、Ta2O5、Sb2O3、ZnO、TiOs(1≦s≦2)のグループから選択されるドーパントとしての第２材料との混合体から構成される。
The information recording / reproducing apparatus of the present invention includes a recording layer in which two or more states having different electrical resistivity are recorded, and a recording layer on the anode side when a voltage or current is applied to the recording layer to change the state of the recording layer A conductive oxide layer disposed at one end of the substrate. The electrical resistivity of the conductive oxide layer is smaller than the minimum value of the electrical resistivity of the recording layer. The conductive oxide layer is made of (i) a first material as a main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ≦ s ≦ 2), In 2 O 3 , IrO 2 , and RuO 2. When, is selected from the group of (ii) Ga 2 O 3, Al 2 O 3, Nb 2 O 5, SnO 2, Ta 2 O 5, Sb 2 O 3, ZnO, TiO s (1 ≦ s ≦ 2) It consists of a mixture with the 2nd material as a dopant.
本発明によれば、高記録密度及び低消費電力の不揮発性の情報記録再生装置を実現できる。
According to the present invention, a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
以下、図面を参照しながら、本発明の例を実施するための最良の形態について詳細に説明する。
Hereinafter, the best mode for carrying out an example of the present invention will be described in detail with reference to the drawings.
１． 概要
本発明の例に係る情報記録再生装置は、異なる電気抵抗率の２以上の状態が記録される記録層と、記録層に電圧又は電流を与えて記録層の状態を変化させるときに陽極側となる記録層の一端に配置される導電性酸化物層とを備える。 1. Overview
An information recording / reproducing apparatus according to an example of the present invention includes a recording layer in which two or more states having different electrical resistivity are recorded, and an anode side when a voltage or current is applied to the recording layer to change the state of the recording layer. And a conductive oxide layer disposed at one end of the recording layer.
本発明の例に係る情報記録再生装置は、異なる電気抵抗率の２以上の状態が記録される記録層と、記録層に電圧又は電流を与えて記録層の状態を変化させるときに陽極側となる記録層の一端に配置される導電性酸化物層とを備える。 1. Overview
An information recording / reproducing apparatus according to an example of the present invention includes a recording layer in which two or more states having different electrical resistivity are recorded, and an anode side when a voltage or current is applied to the recording layer to change the state of the recording layer. And a conductive oxide layer disposed at one end of the recording layer.
導電性酸化物層が記録層と電極との間に配置される場合、電極は、(i) Ti-N、Ti-Si-N、Ta-N、Ta-Si-N、Si-N、Ti-C、Ta-C、Si-Cのグループから選択される材料の窒化物、炭化物若しくは酸化物、(ii) (i)の窒化物と酸化物との混合体、(iii) (i)の窒化物と炭化物との混合体、(iv) (i)の酸化物と炭化物との混合体、又は、(v) (i)の窒化物と炭化物と酸化物との混合体から構成される。
When the conductive oxide layer is disposed between the recording layer and the electrode, the electrode is (i) Ti-N, Ti-Si-N, Ta-N, Ta-Si-N, Si-N, Ti -Nitride, carbide or oxide of material selected from the group of -C, Ta-C, Si-C, (ii) a mixture of nitride and oxide of (i), (iii) of (i) It is composed of a mixture of nitride and carbide, (iv) a mixture of oxide and carbide of (i), or (v) a mixture of nitride, carbide and oxide of (i).
記録層は、(1) AxMyX4 (0.１≦x≦2.2、1.8≦y≦2)、(2) AxMyX3 (0.5≦x≦1.1、0.9≦y≦1)、(3) AxMyX4 (0.5≦x≦1.1、0.9≦y≦1)のグループから選択される材料により構成される。
Recording layer, (1) A x M y X 4 (0.1 ≦ x ≦ 2.2,1.8 ≦ y ≦ 2), (2) A x M y X 3 (0.5 ≦ x ≦ 1.1,0.9 ≦ y ≦ 1 ), constituted by (3) a x M y X 4 (0.5 ≦ x ≦ 1.1,0.9 ≦ y ≦ 1 material selected from the group of).
但し、(1)及び(2)に関し、Aは、Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi のグループから選択される元素、Mは、Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Nb, Ta, Mo, W, Ru, Rh のグループから選択される元素である。
However, regarding (1) and (2), A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Elements selected from the group of Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi, M is Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, It is an element selected from the group of Ni, Nb, Ta, Mo, W, Ru, Rh.
(3)に関し、Aは、Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, Bi のグループから選択される元素、Mは、Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, Os のグループから選択される元素である。
Regarding (3), A is an element selected from the group of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, Bi. , M is an element selected from the group of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, Os.
(1)、(2)及び(3)に関し、AとMは、互いに異なる元素であり、Xは、O, Nのグループから選択される元素である。
Regarding (1), (2), and (3), A and M are mutually different elements, and X is an element selected from the group of O and N.
記録層は、1. コランダム構造、2. ルチル構造、3. スピネル構造、4.ラムスデライト構造、5.アナターゼ構造、6.ホランダイト構造、7. ブルッカイト構造、8. パイロルース構造、9.NaCl構造、10.ペロブスカイト構造、11.イルメナイト構造、12. ウルフラマイト構造のグループから選択される結晶構造を有する。
The recording layer is composed of 1. corundum structure, 2. rutile structure, 3. spinel structure, 4. ramsdellite structure, 5. anatase structure, 6. hollandite structure, 7. brookite structure, 8. pyrolose structure, 9. NaCl structure, 10. It has a crystal structure selected from the group of perovskite structure, 11. ilmenite structure, and 12. wolframite structure.
ここで、コランダム構造の典型例としては、Al2O3、Cr2O3、α-Fe2O3、α-GaO3、Ti2O3、V2O3などが挙げられる。
Here, typical examples of the corundum structure include Al 2 O 3 , Cr 2 O 3 , α-Fe 2 O 3 , α-GaO 3 , Ti 2 O 3 , and V 2 O 3 .
ルチル構造の例としては、TiO2、SnO2などが挙げられる。
Examples of the rutile structure include TiO 2 and SnO 2 .
ブルッカイト構造、アナターゼ構造及びラムスデライト構造は、ルチル構造の変形構造である。例えば、ブルッカイト構造は、ルチル構造を斜方晶にしたものである。
The brookite structure, anatase structure and ramsdellite structure are modified structures of the rutile structure. For example, the brookite structure is an orthorhombic form of a rutile structure.
スピネル構造は、MgAl2O4に代表され、その他、ZnFe2O4、ZnMnO3などがある。Cu2Mg及びMn2O3も、スピネル構造を有する。Ba2Fe12O19及びKFe11O17は、複合スピネル構造を有する。
The spinel structure is typified by MgAl 2 O 4 , and other examples include ZnFe 2 O 4 and ZnMnO 3 . Cu 2 Mg and Mn 2 O 3 also have a spinel structure. Ba 2 Fe 12 O 19 and KFe 11 O 17 have a composite spinel structure.
ホランダイト構造及びパイロルース構造は、MnO2が代表例であり、ホランダイト構造については、α-MnO2、BiVO系などがある。
A typical example of the hollandite structure and pyroloose structure is MnO 2 , and examples of the hollandite structure include α-MnO 2 and BiVO.
イルメナイト構造は、FeTiO3が挙げられる。
Ilmenite structure includes FeTiO 3 .
酸化物の高温超伝導体の発見で一躍有名になったペロブスカイト構造にも、様々な変形構造がある。例としては、BaTiO3、CaTiO3、GdFeO3などが挙げられる。
The perovskite structure, which became famous for the discovery of high-temperature oxide superconductors, also has various deformation structures. Examples include BaTiO 3 , CaTiO 3 , GdFeO 3 and the like.
NaCl構造は、TiO、NiOなどが挙げられる。CuOは、NaCl構造の変形版と理解できる。
Na Examples of NaCl structure include TiO and NiO. CuO can be understood as a modified version of the NaCl structure.
上述の各構造については、ベースとなる結晶構造が若干歪んでいてもよい。例えば、歪んだスピネル構造や、歪んだNaCl構造などであってもよい。前者については、ヘテロライト構造(例えば、ZnMn2O4)と言う別な名称を用いる場合もあるが、ここでは、歪んだスピネル構造又は単にスピネル構造と呼ぶ。
For each of the above structures, the base crystal structure may be slightly distorted. For example, a distorted spinel structure or a distorted NaCl structure may be used. For the former, another name called a heterolite structure (for example, ZnMn 2 O 4 ) may be used, but here it is called a distorted spinel structure or simply a spinel structure.
記録層は、例えば、１種類又は２種類以上の陽イオン元素を有する複合化合物から構成され、陽イオン元素の少なくとも１つは、電子が不完全に満たされたｄ軌道を有する遷移元素である。
The recording layer is composed of, for example, a composite compound having one kind or two or more kinds of cation elements, and at least one of the cation elements is a transition element having a d orbital incompletely filled with electrons.
導電性酸化物層は、記録層の電気抵抗率の変化（セット／リセット動作）を安定して行うと共にその再現性を確保するために、記録層に電圧又は電流を与えて記録層の状態を変化させるときに陽極側となる記録層の一端に付加される。
The conductive oxide layer stably changes the electrical resistivity of the recording layer (set / reset operation) and applies a voltage or current to the recording layer to ensure its reproducibility. When changing, it is added to one end of the recording layer which becomes the anode side.
しかし、記録層に導電性酸化物層を付加する場合、導電性酸化物層の電気抵抗率の変化がセット／リセット動作の不安定要素となり得る。
However, when a conductive oxide layer is added to the recording layer, a change in the electrical resistivity of the conductive oxide layer can be an unstable element of the set / reset operation.
そこで、まず、導電性酸化物層の電気抵抗率は、記録層の電気抵抗率の最小値よりも小さくする。導電性酸化物層は、電気抵抗率の変化がないことが好ましいが、導電性酸化物層の電気抵抗率を記録層の電気抵抗率の最小値よりも十分に小さくすれば、セット／リセット動作により導電性酸化物層の電気抵抗率が変化しても構わない。
Therefore, first, the electrical resistivity of the conductive oxide layer is made smaller than the minimum value of the electrical resistivity of the recording layer. The conductive oxide layer preferably has no change in electrical resistivity. However, if the electrical resistivity of the conductive oxide layer is sufficiently smaller than the minimum value of the electrical resistivity of the recording layer, the set / reset operation is performed. May change the electrical resistivity of the conductive oxide layer.
例えば、導電性酸化物層の電気抵抗率は、1×10-1Ωcm以下とする。
For example, the electrical resistivity of the conductive oxide layer is 1 × 10 −1 Ωcm or less.
また、導電性酸化物層は、(i) ZnO、SnO2、CoO、TiOs(1≦s≦2)、In2O3、IrO2、RuO2のグループから選択される主成分としての第１材料と、(ii) Ga2O3、Al2O3、Nb2O5、SnO2、Ta2O5、Sb2O3、ZnO、TiOs(1≦s≦2)のグループから選択されるドーパントとしての第２材料との混合体から構成する。
In addition, the conductive oxide layer is (i) a first main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ≦ s ≦ 2), In 2 O 3 , IrO 2 , and RuO 2 . 1 material and selected from the group of (ii) Ga 2 O 3 , Al 2 O 3 , Nb 2 O 5 , SnO 2 , Ta 2 O 5 , Sb 2 O 3 , ZnO, TiO s (1 ≦ s ≦ 2) It is comprised from the mixture with the 2nd material as a dopant made.
第１材料は、導電性酸化物層の主成分となるものであり、第２材料は、第１材料にドーパントとして含ませるものであるから、第２材料が導電性酸化物層内に占める割合は、質量比(wt.%)で30 wt.%以下であるのが好ましく、好適には20 wt.%以下、さらに好適には5 wt.%以下とする。
Since the first material is a main component of the conductive oxide layer, and the second material is included in the first material as a dopant, the proportion of the second material in the conductive oxide layer Is preferably 30 wt% or less, more preferably 20 wt% or less, and even more preferably 5 wt% or less.
このような材料を選択する主旨は、導電性酸化物層がセット／リセット動作の不安定要素とならないようにする点にある。
The main point of selecting such a material is to prevent the conductive oxide layer from becoming an unstable element of the set / reset operation.
遷移金属酸化物を主成分とする材料において、電気伝導性を有するが、従来のいわゆるバンド理論では説明できないものを強相関系と呼ぶ。強相関系の特性は、半導体などのバンド理論により解釈できる材料と同様に変化する。即ち、結晶構造、結晶粒径、配向性、不純物などにより、材料の電気特性、磁気特性、誘電特性などが変化する。
A material having a transition metal oxide as a main component, which has electrical conductivity but cannot be explained by the conventional so-called band theory, is called a strongly correlated system. The characteristics of strongly correlated systems change in the same way as materials that can be interpreted by band theory such as semiconductors. That is, the electrical characteristics, magnetic characteristics, dielectric characteristics, and the like of the material change depending on the crystal structure, crystal grain size, orientation, impurities, and the like.
従って、遷移金属酸化物を主成分とする導電性酸化物層に関し、上述の材料を選択することは、結晶粒径、配向性などの結晶性を制御し、良好なデバイス特性を安定に得るために有効である。
Therefore, regarding the conductive oxide layer mainly composed of a transition metal oxide, the selection of the above-mentioned materials controls the crystallinity such as crystal grain size and orientation, and stably obtains good device characteristics. It is effective for.
このように、導電性酸化物層の材料は、電気抵抗率とその制御性、他の膜との密着性、拡散防止性、耐熱性、エッチング性、ガスや溶液含めて耐薬品性、結晶性、配向性、及び、これらの制御性を考慮して選択する。
Thus, the material of the conductive oxide layer is composed of electrical resistivity and controllability, adhesion to other films, diffusion prevention, heat resistance, etching property, chemical resistance including gas and solution, crystallinity. , Orientation, and controllability thereof are selected.
例えば、In2O3にSnO2をドープした材料は、ITOとして知られている。ITOは、低い電気抵抗率を有する材料であるため、記録層の電気抵抗率よりも低い電気抵抗率を実現するのに好都合である。
For example, a material in which In 2 O 3 is doped with SnO 2 is known as ITO. Since ITO is a material having a low electrical resistivity, it is advantageous for realizing an electrical resistivity lower than that of the recording layer.
また、ZnOは、配向し易い材料として知られている。そのため、格子定数が近い、若しくは格子の面間隔として近い結晶面が存在すれば、配向性の高い膜を形成し易い、と予測される。しかし、ZnOの電気抵抗率は、ITOのそれよりも大きく、また、Znは揮発し易い元素として知られているため、単純にZnOのみを用いるだけでは、他の膜にZnが拡散する、若しくは導電性酸化物層からZnが抜けてしまい、電気抵抗率が不安定になる、などの問題点が生じてしまう。このような場合に、ZnOに第２材料をドーパントとして含ませれば、このような問題を解消可能である。
Also, ZnO is known as a material that is easily oriented. Therefore, it is predicted that a highly oriented film can be easily formed if there is a crystal plane with a close lattice constant or a close lattice spacing. However, the electrical resistivity of ZnO is larger than that of ITO, and since Zn is known as an element that easily volatilizes, simply using only ZnO diffuses Zn into other films, or Zn escapes from the conductive oxide layer, causing problems such as unstable electrical resistivity. In such a case, such a problem can be solved if ZnO contains the second material as a dopant.
尚、導電性酸化物層を構成する材料は、組成を化学量論比のみで示したが、実際の組成比は、10%程度変動しても、同じ結晶構造や電気抵抗率を持つ場合がある。例えば、TiOsに関しては、TiOs(1≦s≦2)の範囲内であればよい。
Note that the material constituting the conductive oxide layer shows the composition only in the stoichiometric ratio, but the actual composition ratio may have the same crystal structure and electrical resistivity even if it varies by about 10%. is there. For example, TiO s may be in the range of TiO s (1 ≦ s ≦ 2).
また、導電性酸化物層は、(I) 閃亜鉛鉱構造、(II) ウルツ鉱構造、(III) C-希土構造、(IV) ルチル構造、(V) NaCl構造のグループから選択される結晶構造を有しているのが好ましい。
The conductive oxide layer is selected from the group consisting of (I) sphalerite structure, (II) wurtzite structure, (III) C-rare earth structure, (IV) rutile structure, and (V) NaCl structure. It preferably has a crystal structure.
さらに、記録層は、5nm以上、50nm以下の厚さを有し、導電性酸化物層は、0.5nm以上、10nm以下の厚さを有するのが好ましい。
Furthermore, it is preferable that the recording layer has a thickness of 5 nm or more and 50 nm or less, and the conductive oxide layer has a thickness of 0.5 nm or more and 10 nm or less.
２． 基本原理
本発明に用いられる記録層の記録動作の基本原理について説明する。 2. Basic principle
The basic principle of the recording operation of the recording layer used in the present invention will be described.
本発明に用いられる記録層の記録動作の基本原理について説明する。 2. Basic principle
The basic principle of the recording operation of the recording layer used in the present invention will be described.
以下では、記録層は、電気抵抗率が異なる２つの状態のうちの１つをとるものとし、２種類のイオンが存在する系で説明する。
Hereinafter, the recording layer assumes one of two states having different electric resistivity, and a description will be given of a system in which two types of ions exist.
記録層の初期状態は、絶縁体（高抵抗状態）、例えば、電気抵抗率が103Ω・cmの状態であるものとする。そして、記録層の両端に電位差を与えることにより、記録層の内部に存在する陽イオン元素の一部が陰極（負極）側に移動する。
It is assumed that the initial state of the recording layer is an insulator (high resistance state), for example, a state where the electrical resistivity is 10 3 Ω · cm. Then, by applying a potential difference to both ends of the recording layer, a part of the cation element existing inside the recording layer moves to the cathode (negative electrode) side.
この結果、陽極（正極）側に記録層、陰極側に導電性酸化物層がそれぞれ位置付けられていると、記録層から排出された陽イオン元素が導電性酸化物層内に導入され、導電性酸化物層内では、相対的に陽イオン元素の割合が陰イオン元素の割合よりも多くなる。
As a result, when the recording layer is positioned on the anode (positive electrode) side and the conductive oxide layer is positioned on the cathode side, the cation element discharged from the recording layer is introduced into the conductive oxide layer, and the conductivity is increased. In the oxide layer, the proportion of the cationic element is relatively higher than the proportion of the anionic element.
これと同時に、導電性酸化物層は、電気的中性を保つために陰極から電子を受け取り、導電性酸化物層内の遷移元素の価数が低下する結果として低い酸化状態の化合物になる。
At the same time, the conductive oxide layer receives electrons from the cathode in order to maintain electrical neutrality, and becomes a compound in a low oxidation state as a result of a decrease in the valence of the transition element in the conductive oxide layer.
また、陽極側の記録層は、相対的に陽イオン元素の割合が陰イオン元素の割合よりも少なくなるため、陽極に電子を放出して高い酸化状態の化合物になる。
Also, since the recording layer on the anode side has a relatively lower proportion of the cationic element than the proportion of the anionic element, it emits electrons to the anode and becomes a highly oxidized compound.
これにより、記録層は、低抵抗状態、例えば、電気抵抗率が100Ω・cmの状態になる。
As a result, the recording layer is in a low resistance state, for example, a state in which the electrical resistivity is 10 0 Ω · cm.
これがセット動作である。
This is the set operation.
低抵抗状態の記録層に電流を与えると、低抵抗のために低電位差であっても大電流が流れることになるが、このときに発生するジュール熱は、記録層の温度を上昇させる。
When a current is applied to the recording layer in the low resistance state, a large current flows even if the potential difference is low because of the low resistance. Joule heat generated at this time raises the temperature of the recording layer.
先ほどのセット動作によって引き上げられた高エネルギー準安定状態から、熱エネルギーにより、再びセット前の低エネルギー安定状態である絶縁体（高抵抗状態）に戻ることになる。
From the high energy metastable state pulled up by the previous set operation, the thermal energy returns to the low energy stable state insulator (high resistance state) before setting again.
これがリセット動作である。
This is the reset operation.
ここで、上述のような記録層の抵抗変化に際して、導電性酸化物層の電気抵抗率は、変化しないのが好ましいが、導電性酸化物層の電気抵抗率を記録層の電気抵抗率の最小値よりも十分に小さくしておけば、導電性酸化物層の電気抵抗率が変化しても何ら問題はない。
Here, it is preferable that the electrical resistivity of the conductive oxide layer does not change when the resistance of the recording layer is changed as described above, but the electrical resistivity of the conductive oxide layer is the minimum of the electrical resistivity of the recording layer. If the value is sufficiently smaller than the value, there is no problem even if the electric resistivity of the conductive oxide layer changes.
本発明の導電性酸化物層を有する情報記録再生装置においては、原理的にはPbpsi（Peta bit per square inch）級を実現でき、さらに大幅なライトディスターブ耐性の改善を実現できる。
In the information recording / reproducing apparatus having the conductive oxide layer of the present invention, in principle, a Pbpsi (Peta per square inch) class can be realized, and further a significant improvement in write disturb resistance can be realized.
３． 基本構造
図１は、本発明の前提となる記録部の構造を示している。
１１は、電極層、１２は、記録層、１３Ａは、電極層（又は保護層）である。記録層１２内の小さな白丸は、拡散イオンとしての典型元素(representativeelement)を表し、小さな黒丸は、陽イオンとしての遷移元素(transition element)を表す。また、大きな白丸は、陰イオンとしての典型元素を表す。 3. Basic structure
FIG. 1 shows the structure of a recording unit as a premise of the present invention.
Reference numeral 11 denotes an electrode layer, 12 denotes a recording layer, and 13A denotes an electrode layer (or a protective layer). A small white circle in the recording layer 12 represents a representative element as a diffusion ion, and a small black circle represents a transition element as a cation. A large white circle represents a typical element as an anion.
図１は、本発明の前提となる記録部の構造を示している。
１１は、電極層、１２は、記録層、１３Ａは、電極層（又は保護層）である。記録層１２内の小さな白丸は、拡散イオンとしての典型元素(representativeelement)を表し、小さな黒丸は、陽イオンとしての遷移元素(transition element)を表す。また、大きな白丸は、陰イオンとしての典型元素を表す。 3. Basic structure
FIG. 1 shows the structure of a recording unit as a premise of the present invention.
記録層１２に電圧を印加し、記録層１２内に電位勾配を発生させると、拡散イオンの一部が結晶中を移動する。そこで、本発明の例では、記録層１２の初期状態を絶縁体（高抵抗状態）とし、情報記録に関しては、電位勾配により記録層１２を相変化させ、記録層１２に伝導性を持たせる（低抵抗状態）ことにより行う。
When a voltage is applied to the recording layer 12 to generate a potential gradient in the recording layer 12, some of the diffused ions move in the crystal. Therefore, in the example of the present invention, the initial state of the recording layer 12 is an insulator (high resistance state), and for information recording, the recording layer 12 is phase-changed by a potential gradient to make the recording layer 12 conductive (see FIG. (Low resistance state)
ここで、本明細書では、高抵抗状態をリセット状態とし、低抵抗状態をセット状態と定義する。但し、この定義は、以下の説明を簡単にするためのものであり、材料の選択や製造方法によっては、この定義と逆の場合、即ち、低抵抗状態がリセット（初期）状態となり、高抵抗状態がセット状態となる場合もある。つまり、このような場合も、本発明の範疇に含まれることは言うまでもない。
Here, in this specification, the high resistance state is defined as a reset state, and the low resistance state is defined as a set state. However, this definition is intended to simplify the following description. Depending on the selection of materials and the manufacturing method, this definition may be reversed, that is, the low resistance state becomes the reset (initial) state. The state may be set. That is, it goes without saying that such a case is also included in the scope of the present invention.
まず、例えば、電極層１３Ａの電位が電極層１１の電位よりも相対的に低い状態を作る。電極層１１を固定電位（例えば、接地電位）とすれば、電極層１３Ａに負の電位を与えればよい。
First, for example, a state in which the potential of the electrode layer 13A is relatively lower than the potential of the electrode layer 11 is created. If the electrode layer 11 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the electrode layer 13A.
この時、記録層１２内の拡散イオンの一部が電極層（陰極）１３Ａ側に移動し、記録層（結晶）１２内の拡散イオンが陰イオンに対して相対的に減少する。電極層１３Ａ側に移動した拡散イオンは、電極層１３Ａから電子を受け取り、メタルとして析出するため、メタル層１４を形成する。
At this time, some of the diffusion ions in the recording layer 12 move to the electrode layer (cathode) 13A side, and the diffusion ions in the recording layer (crystal) 12 decrease relative to the anions. The diffused ions that have moved to the electrode layer 13A side receive electrons from the electrode layer 13A and precipitate as metal, so that the metal layer 14 is formed.
記録層１２の内部では、陰イオンが過剰となり、結果的に、記録層１２内の遷移元素イオンの価数を上昇させる。つまり、記録層１２は、キャリアの注入により電子伝導性を有するようになるため、情報記録（セット動作）が完了する。
In the recording layer 12, anions become excessive, and as a result, the valence of transition element ions in the recording layer 12 is increased. That is, since the recording layer 12 has electron conductivity by carrier injection, information recording (set operation) is completed.
情報再生に関しては、電流パルスを記録層１２に流し、記録層１２の抵抗値を検出することにより容易に行える。但し、電流パルスは、記録層１２を構成する材料が相変化を起こさない程度の微小な値であることが必要である。
Information reproduction can be easily performed by flowing a current pulse through the recording layer 12 and detecting the resistance value of the recording layer 12. However, the current pulse needs to be a minute value that does not cause a phase change in the material constituting the recording layer 12.
以上の過程は、一種の電気分解であり、電極層（陽極）１１側では、電気化学的酸化により酸化剤が生じ、電極層（陰極）１３Ａ側では、電気化学的還元により還元剤が生じた、と考えることができる。
The above process is a kind of electrolysis, and an oxidizing agent is generated by electrochemical oxidation on the electrode layer (anode) 11 side, and a reducing agent is generated by electrochemical reduction on the electrode layer (cathode) 13A side. Can be considered.
このため、情報記録の状態（低抵抗状態）を初期状態（高抵抗状態）に戻すには、例えば、記録層１２を大電流パルスによりジュール加熱して、記録層１２の酸化還元反応を促進させればよい。即ち、大電流パルスの遮断後の残留熱により記録層１２は、絶縁体に戻る（リセット動作）。
Therefore, in order to return the information recording state (low resistance state) to the initial state (high resistance state), for example, the recording layer 12 is Joule-heated with a large current pulse to promote the oxidation-reduction reaction of the recording layer 12. Just do it. That is, the recording layer 12 returns to the insulator due to the residual heat after the interruption of the large current pulse (reset operation).
但し、この動作原理を実用化するには、室温でリセット動作が生じないこと（十分に長いリテンション時間の確保）と、リセット動作の消費電力が十分に小さいこととを確認しなければならない。
However, in order to put this operating principle into practical use, it is necessary to confirm that a reset operation does not occur at room temperature (a sufficiently long retention time is ensured) and that the power consumption of the reset operation is sufficiently small.
前者に対しては、拡散イオンの配位数を小さく（理想的には２以下に）する、若しくは、価数を２以上にする、又は、陰イオンの価数を上げる（理想的には３以上にする）ことで対応できる。
For the former, the coordination number of the diffuse ions is reduced (ideally 2 or less), the valence is 2 or more, or the anion valence is increased (ideally 3). This can be done.
また、後者に対しては、結晶破壊を引き起こさないために拡散イオンの価数を２以下にする必要があると共に、記録層（結晶）１２内を移動する拡散イオンの移動パスを数多く有する材料を見つけ出すことにより対応できる。
In addition, for the latter, a material having a large number of diffusion ion movement paths that move through the recording layer (crystal) 12 is necessary in order not to cause crystal breakage, and the valence of diffusion ions needs to be 2 or less. We can cope by finding out.
そのような記録層１２は、既に述べたような元素及び結晶構造により実現できる。
Such a recording layer 12 can be realized by the elements and crystal structure as described above.
ところで、セット動作後の電極層（陽極）１１側には酸化剤が生じるため、電極層１１には、酸化され難い材料（例えば、電気伝導性窒化物、電気伝導性酸化物など）から構成するのが好ましい。
By the way, since an oxidizing agent is generated on the electrode layer (anode) 11 side after the setting operation, the electrode layer 11 is made of a material that is not easily oxidized (for example, electrically conductive nitride, electrically conductive oxide, etc.). Is preferred.
また、電極層１１は、イオン伝導性を有しない材料から構成するのがよい。
The electrode layer 11 is preferably made of a material that does not have ionic conductivity.
そのような材料としては、以下に示されるものがあり、その中でも、電気伝導率の良さなどを加味した総合的性能の点から、LaNiO3は、最も好ましい材料ということができる。
Examples of such a material include those shown below. Among them, LaNiO 3 can be said to be the most preferable material from the viewpoint of comprehensive performance in consideration of good electrical conductivity and the like.
・ MN
Mは、Ti, Zr, Hf, V, Nb, Ta のグループから選択される少なくとも１種類の元素を含む。Nは、窒素である。 ・ MN
M contains at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta. N is nitrogen.
Mは、Ti, Zr, Hf, V, Nb, Ta のグループから選択される少なくとも１種類の元素を含む。Nは、窒素である。 ・ MN
M contains at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta. N is nitrogen.
・ MOx
Mは、Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt のグループから選択される少なくとも１種類の元素を含む。モル比xは、1≦x≦4を満たすものとする。 ・ MO x
M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element. The molar ratio x shall satisfy 1 ≦ x ≦ 4.
Mは、Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt のグループから選択される少なくとも１種類の元素を含む。モル比xは、1≦x≦4を満たすものとする。 ・ MO x
M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element. The molar ratio x shall satisfy 1 ≦ x ≦ 4.
・ AMO3
Aは、La, K, Ca, Sr, Ba, Ln(Lanthanide) のグループから選択される少なくとも１種類の元素を含む。 ・ AMO 3
A contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba, and Ln (Lanthanide).
Aは、La, K, Ca, Sr, Ba, Ln(Lanthanide) のグループから選択される少なくとも１種類の元素を含む。 ・ AMO 3
A contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba, and Ln (Lanthanide).
Mは、Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt のグループから選択される少なくとも１種類の元素を含む。
M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
Oは、酸素である。
O is oxygen.
・ B2MO4
Bは、K, Ca, Sr, Ba, Ln(Lanthanide) のグループから選択される少なくとも１種類の元素を含む。 ・ B 2 MO 4
B contains at least one element selected from the group of K, Ca, Sr, Ba, and Ln (Lanthanide).
Bは、K, Ca, Sr, Ba, Ln(Lanthanide) のグループから選択される少なくとも１種類の元素を含む。 ・ B 2 MO 4
B contains at least one element selected from the group of K, Ca, Sr, Ba, and Ln (Lanthanide).
Mは、Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt のグループから選択される少なくとも１種類の元素を含む。
M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt Containing at least one element.
Oは、酸素である。
O is oxygen.
また、セット動作後の電極層（陰極）１３Ａ側には還元剤が生じるため、電極層１３Ａとしては、記録層１２が大気と反応することを防止する機能を持っていることが好ましい。
In addition, since a reducing agent is generated on the electrode layer (cathode) 13A side after the setting operation, the electrode layer 13A preferably has a function of preventing the recording layer 12 from reacting with the atmosphere.
そのような材料としては、例えば、アモルファスカーボン、ダイヤモンドライクカーボン、SnO2などの半導体がある。
Examples of such a material include semiconductors such as amorphous carbon, diamond-like carbon, and SnO 2 .
電極層１３Ａは、記録層１２を保護する保護層として機能させてもよいし、電極層１３Ａの代わりに保護層を設けてもよい。この場合、保護層は、絶縁体でもよいし、導電体でもよい。
The electrode layer 13A may function as a protective layer for protecting the recording layer 12, or a protective layer may be provided instead of the electrode layer 13A. In this case, the protective layer may be an insulator or a conductor.
図２は、本発明の例に係わる記録部の構造を示している。
１１は、電極層、１２は、記録層、１３Ａは、電極層（又は保護層）、１５は、導電性酸化物層(Conductive oxide layer)である。記録層１２内の小さな白丸は、拡散イオンとしての典型元素を表し、小さな黒丸は、陽イオンとしての遷移元素を表す。また、大きな白丸は、陰イオンとしての典型元素を表す。 FIG. 2 shows the structure of a recording unit according to an example of the present invention.
11 is an electrode layer, 12 is a recording layer, 13A is an electrode layer (or protective layer), and 15 is a conductive oxide layer. Small white circles in therecording layer 12 represent typical elements as diffusion ions, and small black circles represent transition elements as cations. A large white circle represents a typical element as an anion.
１１は、電極層、１２は、記録層、１３Ａは、電極層（又は保護層）、１５は、導電性酸化物層(Conductive oxide layer)である。記録層１２内の小さな白丸は、拡散イオンとしての典型元素を表し、小さな黒丸は、陽イオンとしての遷移元素を表す。また、大きな白丸は、陰イオンとしての典型元素を表す。 FIG. 2 shows the structure of a recording unit according to an example of the present invention.
11 is an electrode layer, 12 is a recording layer, 13A is an electrode layer (or protective layer), and 15 is a conductive oxide layer. Small white circles in the
この構造が本発明の前提となる図１の構造と異なる点は、記録層１２に電圧又は電流を与えて記録層１２の状態を変化させるとき、具体的には、セット動作を行うときに、陽極側となる記録層１２の一端に導電性酸化物層１５を配置した点にある。
This structure is different from the structure of FIG. 1, which is the premise of the present invention, in that when a voltage or current is applied to the recording layer 12 to change the state of the recording layer 12, specifically, when a set operation is performed. The conductive oxide layer 15 is disposed at one end of the recording layer 12 on the anode side.
セット／リセット動作及び材料については、図１の場合と同じであるため、ここでは、その説明を省略する。
Since the set / reset operation and the material are the same as those in FIG. 1, the description thereof is omitted here.
導電性酸化物層１５は、空隙サイト(cavity cite)を有していてもよい。空隙サイトは、記録層１２から移動してきた陽イオン元素を収納するサイトである。
The conductive oxide layer 15 may have a cavity site. The void site is a site that stores a cation element that has moved from the recording layer 12.
導電性酸化物層１５が空隙サイトを有する場合、記録層１２内のイオンの移動を円滑化する効果を発揮すると共に、導電性酸化物層１５の組成範囲を調整することで、記録層１２の電子伝導性を良くし、結晶構造の安定性を確保する。この結果、記録層１２のディスターブ耐性の向上を実現する。
When the conductive oxide layer 15 has void sites, the effect of facilitating the movement of ions in the recording layer 12 is exhibited, and the composition range of the conductive oxide layer 15 is adjusted so that the recording layer 12 Improve electronic conductivity and ensure stability of crystal structure. As a result, the disturb resistance of the recording layer 12 is improved.
また、記録層１２と導電性酸化物層１５との間に、記録層１２から排出されるイオンの透過性を有する数ナノメータ程度の厚さの絶縁体を挿入してもよい。この絶縁体は、少なくとも記録層１２から排出されるイオン元素とそれ以外の典型元素とを含む化合物又は複合化合物から構成される。これにより、記録部のオン抵抗を下げる。
Further, an insulator having a thickness of about several nanometers having a permeability of ions discharged from the recording layer 12 may be inserted between the recording layer 12 and the conductive oxide layer 15. This insulator is composed of a compound or composite compound containing at least an ionic element discharged from the recording layer 12 and other typical elements. This lowers the on-resistance of the recording unit.
図３は、図２の構造を表している。
記録層１２には、例えば、異なる電気抵抗率の２つの状態が記録される。 FIG. 3 represents the structure of FIG.
In therecording layer 12, for example, two states with different electrical resistivity are recorded.
記録層１２には、例えば、異なる電気抵抗率の２つの状態が記録される。 FIG. 3 represents the structure of FIG.
In the
ρrrは、リセット状態（高抵抗状態）の記録層１２の電気抵抗率、ρrsは、セット状態（低抵抗状態）の記録層１２の電気抵抗率である。また、ρorは、記録層１２がリセット状態のときの導電性酸化物層１５の電気抵抗率、ρosは、記録層１２がセット状態のときの導電性記録層１５の電気抵抗率である。
Ρrr is the electrical resistivity of the recording layer 12 in the reset state (high resistance state), and ρrs is the electrical resistivity of the recording layer 12 in the set state (low resistance state). Further, ρor is the electrical resistivity of the conductive oxide layer 15 when the recording layer 12 is in the reset state, and ρos is the electrical resistivity of the conductive recording layer 15 when the recording layer 12 is in the set state.
ρos<<ρrs<ρrr, ρor<<ρrs<ρrrである。
Ρos << ρrs <ρrr, ρor << ρrs <ρrr.
図４は、図３の構造の変形例である。
記録層１２－１，１２－２には、それぞれ、例えば、異なる電気抵抗率の２つの状態が記録される。また、記録層１２－１の陽極側の端部には、導電性酸化物層１５が付加され、同様に、記録層１２－２の陽極側の端部にも、導電性酸化物層１５が付加される。 FIG. 4 is a modification of the structure of FIG.
For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. In addition, aconductive oxide layer 15 is added to the end of the recording layer 12-1 on the anode side. Similarly, the conductive oxide layer 15 is also formed on the end of the recording layer 12-2 on the anode side. Added.
記録層１２－１，１２－２には、それぞれ、例えば、異なる電気抵抗率の２つの状態が記録される。また、記録層１２－１の陽極側の端部には、導電性酸化物層１５が付加され、同様に、記録層１２－２の陽極側の端部にも、導電性酸化物層１５が付加される。 FIG. 4 is a modification of the structure of FIG.
For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. In addition, a
記録層１２－１の状態が変化する閾値と記録層１２－２の状態が変化する閾値とは互いに異なる値に設定し、多値(multi-level)の記録を可能にする。
The threshold value for changing the state of the recording layer 12-1 and the threshold value for changing the state of the recording layer 12-2 are set to different values to enable multi-level recording.
ρrr1は、リセット状態（高抵抗状態）の記録層１２－１の電気抵抗率、ρrs1は、セット状態（低抵抗状態）の記録層１２－１の電気抵抗率である。ρrr2は、リセット状態（高抵抗状態）の記録層１２－２の電気抵抗率、ρrs2は、セット状態（低抵抗状態）の記録層１２－２の電気抵抗率である。
Ρrr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ρrs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state). ρrr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ρrs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
導電性酸化物層１５の電気抵抗率ρor, ρosは、記録層１２－１，１２－２の電気抵抗率ρrr1, ρrs1, ρrr2, ρrs2よりも十分に小さい。
The electrical resistivity ρor, ρos of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ρrr1, ρrs1, ρrr2, ρrs2 of the recording layers 12-1, 12-2.
図５も、図３の構造の変形例である。
記録層１２－１，１２－２には、それぞれ、例えば、異なる電気抵抗率の２つの状態が記録される。また、陽極としての電極層１１と記録層１２－１との間には、導電性酸化物層１５が配置される。 FIG. 5 is also a modification of the structure of FIG.
For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. Further, aconductive oxide layer 15 is disposed between the electrode layer 11 as an anode and the recording layer 12-1.
記録層１２－１，１２－２には、それぞれ、例えば、異なる電気抵抗率の２つの状態が記録される。また、陽極としての電極層１１と記録層１２－１との間には、導電性酸化物層１５が配置される。 FIG. 5 is also a modification of the structure of FIG.
For example, two states having different electrical resistivity are recorded in the recording layers 12-1 and 12-2, respectively. Further, a
記録層１２－１の状態が変化する閾値と記録層１２－２の状態が変化する閾値とは互いに異なる値に設定し、多値の記録を可能にする。
The threshold for changing the state of the recording layer 12-1 and the threshold for changing the state of the recording layer 12-2 are set to different values to enable multi-value recording.
ρrr1は、リセット状態（高抵抗状態）の記録層１２－１の電気抵抗率、ρrs1は、セット状態（低抵抗状態）の記録層１２－１の電気抵抗率である。ρrr2は、リセット状態（高抵抗状態）の記録層１２－２の電気抵抗率、ρrs2は、セット状態（低抵抗状態）の記録層１２－２の電気抵抗率である。
Ρrr1 is the electrical resistivity of the recording layer 12-1 in the reset state (high resistance state), and ρrs1 is the electrical resistivity of the recording layer 12-1 in the set state (low resistance state). ρrr2 is the electrical resistivity of the recording layer 12-2 in the reset state (high resistance state), and ρrs2 is the electrical resistivity of the recording layer 12-2 in the set state (low resistance state).
導電性酸化物層１５の電気抵抗率ρor, ρosは、記録層１２－１，１２－２の電気抵抗率ρrr1, ρrs1, ρrr2, ρrs2よりも十分に小さい。
The electrical resistivity ρor, ρos of the conductive oxide layer 15 is sufficiently smaller than the electrical resistivity ρrr1, ρrs1, ρrr2, ρrs2 of the recording layers 12-1, 12-2.
４． 実施形態
次に、最良と思われるいくつかの実施形態について説明する。
以下では、本発明の例を、プローブ型固体メモリに適用した場合とクロスポイント型固体メモリに適用した場合の２つについて説明する。 4). Embodiment
Next, some embodiments considered to be the best will be described.
Below, the example of this invention is demonstrated about the case where it applies to a probe type solid memory, and the case where it applies to a cross point type solid memory.
次に、最良と思われるいくつかの実施形態について説明する。
以下では、本発明の例を、プローブ型固体メモリに適用した場合とクロスポイント型固体メモリに適用した場合の２つについて説明する。 4). Embodiment
Next, some embodiments considered to be the best will be described.
Below, the example of this invention is demonstrated about the case where it applies to a probe type solid memory, and the case where it applies to a cross point type solid memory.
(1) プローブ型固体メモリ
A. 構造
図６及び図７は、本発明の例に係わるプローブ型固体メモリを示している。 (1) Probe type solid-state memory
A. Structure
6 and 7 show a probe type solid state memory according to an example of the present invention.
A. 構造
図６及び図７は、本発明の例に係わるプローブ型固体メモリを示している。 (1) Probe type solid-state memory
A. Structure
6 and 7 show a probe type solid state memory according to an example of the present invention.
半導体基板２０上には、電極層２１が配置され、電極層２１上には、データエリアとサーボエリアとを有する記録部２２が配置される。記録部（記録媒体）２２は、例えば、図２に示す記録層１２と導電性酸化物層１５とから構成される。記録部２２は、半導体基板２０の中央部にベタに形成される。
An electrode layer 21 is disposed on the semiconductor substrate 20, and a recording unit 22 having a data area and a servo area is disposed on the electrode layer 21. The recording unit (recording medium) 22 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG. The recording unit 22 is solidly formed at the center of the semiconductor substrate 20.
サーボエリアは、半導体基板２０の縁に沿って配置される。
The servo area is arranged along the edge of the semiconductor substrate 20.
データエリア及びサーボエリアは、複数のブロックから構成される。データエリア上及びサーボエリア上には、複数のブロックに対応して複数のプローブ２４が配置される。複数のプローブ２４の各々は、先鋭化された形状を有する。
The data area and servo area are composed of multiple blocks. On the data area and the servo area, a plurality of probes 24 are arranged corresponding to a plurality of blocks. Each of the plurality of probes 24 has a sharpened shape.
複数のプローブ２４は、プローブアレイを構成し、半導体基板２３の一面側に形成される。複数のプローブ２４は、ＭＥＭＳ技術を利用することにより、半導体基板２３の一面側に容易に形成できる。
The plurality of probes 24 constitutes a probe array and is formed on one surface side of the semiconductor substrate 23. The plurality of probes 24 can be easily formed on one surface side of the semiconductor substrate 23 by using the MEMS technology.
データエリア上のプローブ２４の位置は、サーボエリアから読み出されるサーボバースト信号により制御される。具体的には、ドライバ２７により、半導体基板２０をＸ方向に往復運動させ、複数のプローブ２４のＹ方向の位置制御を行うことにより、アクセス動作を実行する。
The position of the probe 24 on the data area is controlled by a servo burst signal read from the servo area. Specifically, the access operation is executed by causing the driver 27 to reciprocate the semiconductor substrate 20 in the X direction and controlling the position of the plurality of probes 24 in the Y direction.
尚、ブロックごとに記録媒体を独立に形成し、記録媒体がハードディスクのように円形で回転するような構造とし、複数のプローブ２４の各々を、記録媒体の半径方向、例えば、Ｘ方向に移動させるようにしてもよい。
The recording medium is formed independently for each block, and the recording medium is configured to rotate in a circle like a hard disk, and each of the plurality of probes 24 is moved in the radial direction of the recording medium, for example, the X direction. You may do it.
複数のプローブ２４は、それぞれ、記録／消去ヘッドとしての機能及び再生ヘッドとしての機能を有する。マルチプレクスドライバ２５，２６は、記録、再生及び消去時に、複数のプローブ２４に対して所定の電圧を供給する。
Each of the plurality of probes 24 has a function as a recording / erasing head and a function as a reproducing head. The multiplex drivers 25 and 26 supply a predetermined voltage to the plurality of probes 24 at the time of recording, reproduction, and erasing.
B. 記録／再生動作
図６及び図７のプローブ型固体メモリの記録／再生動作について説明する。 B. Recording / playback operation
A recording / reproducing operation of the probe type solid-state memory shown in FIGS. 6 and 7 will be described.
図６及び図７のプローブ型固体メモリの記録／再生動作について説明する。 B. Recording / playback operation
A recording / reproducing operation of the probe type solid-state memory shown in FIGS. 6 and 7 will be described.
図８は、記録動作（セット動作）について示している。
記録部（記録媒体）２２は、半導体チップ２０上の電極層２１上に形成される。記録部２２は、保護層１３Ｂにより覆われる。 FIG. 8 shows the recording operation (set operation).
The recording unit (recording medium) 22 is formed on theelectrode layer 21 on the semiconductor chip 20. The recording unit 22 is covered with the protective layer 13B.
記録部（記録媒体）２２は、半導体チップ２０上の電極層２１上に形成される。記録部２２は、保護層１３Ｂにより覆われる。 FIG. 8 shows the recording operation (set operation).
The recording unit (recording medium) 22 is formed on the
情報記録は、プローブ２４の先端を保護層１３Ｂの表面に接触させて、記録部（記録媒体）２２の記録単位３０に電圧パルスを印加し、記録部２２の記録単位３０内に電位勾配を発生させることにより行う。本例では、プローブ２４の電位が電極層２１の電位よりも相対的に低い状態を作る。電極層２１を固定電位（例えば、接地電位）とすれば、プローブ２４に負電位を与えればよい。
For information recording, the tip of the probe 24 is brought into contact with the surface of the protective layer 13B, a voltage pulse is applied to the recording unit 30 of the recording unit (recording medium) 22, and a potential gradient is generated in the recording unit 30 of the recording unit 22. To do. In this example, a state is created in which the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 is set to a fixed potential (for example, ground potential), a negative potential may be applied to the probe 24.
電圧パルスは、例えば、電子発生源又はホットエレクトロン源を使用し、プローブ２４から電極層２１に向かって電子を放出することにより発生させてもよい。
The voltage pulse may be generated by emitting electrons from the probe 24 toward the electrode layer 21 using, for example, an electron generation source or a hot electron source.
この時、例えば、図９に示すように、記録層１２の記録単位３０では、拡散イオンの一部がプローブ（陰極）２４側に移動し、結晶内の拡散イオンが陰イオンに対して相対的に減少する。また、プローブ２４側に移動した拡散イオンは、プローブ２４から電子を受け取ってメタルとして析出する。
At this time, for example, as shown in FIG. 9, in the recording unit 30 of the recording layer 12, some of the diffusion ions move to the probe (cathode) 24 side, and the diffusion ions in the crystal are relative to the anions. To decrease. The diffused ions that have moved to the probe 24 side receive electrons from the probe 24 and are deposited as metal.
記録層１２の記録単位３０では、陰イオンが過剰となり、結果的に、記録層１２内に残された遷移元素イオンの価数を上昇させる。つまり、記録層１２の記録単位３０は、相変化によるキャリアの注入により電子伝導性を有するようになるため、情報記録（セット動作）が完了する。
In the recording unit 30 of the recording layer 12, anions become excessive, and as a result, the valence of the transition element ions left in the recording layer 12 is increased. That is, since the recording unit 30 of the recording layer 12 has electron conductivity due to carrier injection due to phase change, information recording (set operation) is completed.
尚、情報記録のための電圧パルスは、プローブ２４の電位が電極層２１の電位よりも相対的に高い状態を作ることにより発生させることもできる。
Note that the voltage pulse for information recording can be generated by creating a state in which the potential of the probe 24 is relatively higher than the potential of the electrode layer 21.
本例のプローブ型固体メモリによれば、ハードディスクと同様に、記録媒体の記録単位３０に情報記録を行うことができると共に、新規な記録材料を採用することにより、従来のハードディスクや半導体メモリよりも高記録密度が実現できる。
According to the probe type solid-state memory of this example, information can be recorded in the recording unit 30 of the recording medium as in the case of the hard disk, and by adopting a new recording material, the conventional solid-state memory or semiconductor memory can be used. High recording density can be realized.
図１０は、再生動作について示している。
再生動作に関しては、電圧パルスを記録層１２の記録単位３０に流し、記録層１２の記録単位３０の抵抗値を検出することにより行う。但し、電圧パルスは、記録層１２の記録単位３０を構成する材料が相変化を起こさない程度の微小な値とする。 FIG. 10 shows the reproduction operation.
The reproduction operation is performed by flowing a voltage pulse to therecording unit 30 of the recording layer 12 and detecting the resistance value of the recording unit 30 of the recording layer 12. However, the voltage pulse is set to a minute value so that the material constituting the recording unit 30 of the recording layer 12 does not cause a phase change.
再生動作に関しては、電圧パルスを記録層１２の記録単位３０に流し、記録層１２の記録単位３０の抵抗値を検出することにより行う。但し、電圧パルスは、記録層１２の記録単位３０を構成する材料が相変化を起こさない程度の微小な値とする。 FIG. 10 shows the reproduction operation.
The reproduction operation is performed by flowing a voltage pulse to the
例えば、センスアンプＳ／Ａにより発生した読み出し電流をプローブ２４から記録層１２の記録単位３０に流し、センスアンプＳ／Ａにより記録単位３０の抵抗値を測定する。既に説明した新材料を採用すると、高抵抗状態と低抵抗状態との抵抗の比は、103以上を確保できる。
For example, the read current generated by the sense amplifier S / A is passed from the probe 24 to the recording unit 30 of the recording layer 12, and the resistance value of the recording unit 30 is measured by the sense amplifier S / A. If the new material already described is adopted, the resistance ratio between the high resistance state and the low resistance state can be secured at 10 3 or more.
尚、再生動作では、記録媒体上をプローブ２４により走査（スキャン）することで、連続再生が可能となる。
In the reproduction operation, continuous reproduction is possible by scanning the recording medium with the probe 24.
消去（リセット）動作に関しては、記録層１２の記録単位３０を大電流パルスによりジュール加熱して、記録層１２の記録単位３０における酸化還元反応を促進させることにより行う。或いは、セット時とは逆向きの電圧パルスを記録層１２に印加することによっても行うことができる。
The erasing (reset) operation is performed by heating the recording unit 30 of the recording layer 12 with a large current pulse to promote the oxidation-reduction reaction in the recording unit 30 of the recording layer 12. Alternatively, it can also be performed by applying a voltage pulse in the direction opposite to that at the time of setting to the recording layer 12.
消去動作は、記録単位３０ごとに行うこともできるし、複数の記録単位３０又はブロック単位で行うこともできる。
The erasing operation can be performed for each recording unit 30, or can be performed for a plurality of recording units 30 or blocks.
C. まとめ
このようなプローブ型固体メモリによれば、現在のハードディスクやフラッシュメモリよりも高記録密度及び低消費電力を実現できる。 C. Summary
According to such a probe type solid-state memory, higher recording density and lower power consumption can be realized than current hard disks and flash memories.
このようなプローブ型固体メモリによれば、現在のハードディスクやフラッシュメモリよりも高記録密度及び低消費電力を実現できる。 C. Summary
According to such a probe type solid-state memory, higher recording density and lower power consumption can be realized than current hard disks and flash memories.
(2) クロスポイント型固体メモリ
A. 構造
図１１は、本発明の例に係わるクロスポイント型固体メモリを示している。 (2) Cross-point type solid-state memory
A. Structure
FIG. 11 shows a cross-point type solid state memory according to an example of the present invention.
A. 構造
図１１は、本発明の例に係わるクロスポイント型固体メモリを示している。 (2) Cross-point type solid-state memory
A. Structure
FIG. 11 shows a cross-point type solid state memory according to an example of the present invention.
ワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１は、Ｘ方向に延び、ビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１は、Ｙ方向に延びる。
The word lines WL i−1 , WL i , WL i + 1 extend in the X direction, and the bit lines BL j−1 , BL j , BL j + 1 extend in the Y direction.
ワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１の一端は、選択スイッチとしてのＭＯＳトランジスタＲＳＷを経由してワード線ドライバ＆デコーダ３１に接続され、ビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１の一端は、選択スイッチとしてのＭＯＳトランジスタＣＳＷを経由してビット線ドライバ＆デコーダ＆読み出し回路３２に接続される。
One end of each of the word lines WL i−1 , WL i , WL i + 1 is connected to the word line driver & decoder 31 via a MOS transistor RSW as a selection switch, and the bit lines BL j−1 , BL j , BL j + 1 One end is connected to a bit line driver & decoder & read circuit 32 via a MOS transistor CSW as a selection switch.
ＭＯＳトランジスタＲＳＷのゲートには、１本のワード線（ロウ）を選択するための選択信号Ｒｉ－１，Ｒｉ，Ｒｉ＋１が入力され、ＭＯＳトランジスタＣＳＷのゲートには、１本のビット線（カラム）を選択するための選択信号Ｃｊ－１，Ｃｊ，Ｃｊ＋１が入力される。
Selection signals R i−1 , R i , and R i + 1 for selecting one word line (row) are input to the gate of the MOS transistor RSW, and one bit line is input to the gate of the MOS transistor CSW. Selection signals C j−1 , C j , and C j + 1 for selecting (column) are input.
メモリセル３３は、ワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１とビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１との交差部に配置される。いわゆるクロスポイント型セルアレイ構造である。
The memory cell 33 is arranged at the intersection of the word lines WL i−1 , WL i , WL i + 1 and the bit lines BL j−1 , BL j , BL j + 1 . This is a so-called cross-point cell array structure.
メモリセル３３には、記録／再生時における回り込み電流(sneak current)を防止するためのダイオード３４が付加される。
A diode 34 for preventing a sneak current during recording / reproduction is added to the memory cell 33.
図１２は、図１１のクロスポイント型固体メモリのメモリセルアレイ部の構造を示している。
FIG. 12 shows the structure of the memory cell array portion of the cross-point type solid-state memory shown in FIG.
半導体チップ３０上には、ワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１とビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１が配置され、これら配線の交差部にメモリセル３３及びダイオード３４が配置される。
On the semiconductor chip 30, word lines WL i−1 , WL i , WL i + 1 and bit lines BL j−1 , BL j , BL j + 1 are arranged, and memory cells 33 and diodes 34 are arranged at intersections of these wirings. Is done.
このようなクロスポイント型セルアレイ構造の特長は、メモリセル３３に個別にＭＯＳトランジスタを接続する必要がないため、高集積化に有利な点にある。例えば、図１３及び図１４に示すように、メモリセル３３を積み重ねて、メモリセルアレイを３次元構造にすることも可能である。
The feature of such a cross-point type cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33. For example, as shown in FIGS. 13 and 14, it is possible to stack the memory cells 33 to make the memory cell array have a three-dimensional structure.
メモリセル３３は、例えば、図１５に示すように、記録層(Recording layer)１２、導電性酸化物層(Conductive oxide layer)１５及び保護層(Protective layer)１３Ｂのスタック構造から構成される。１つのメモリセル３３により１ビット以上のデータを記憶する。また、ダイオード３４は、ワード線ＷＬｉとメモリセル３３との間に配置される。
For example, as shown in FIG. 15, the memory cell 33 has a stacked structure of a recording layer 12, a conductive oxide layer 15, and a protective layer 13B. One memory cell 33 stores data of 1 bit or more. The diode 34 is disposed between the word line WL i and the memory cell 33.
尚、ワード線ＷＬｉとダイオード３４との間、及び、保護層１３Ｂとビット線ＢＬｊとの間の少なくとも１つにバリアメタルを配置してもよい。また、ダイオード３４は、電圧の向きのみによってセット／リセット動作を行う場合には省略するのが好ましい。
A barrier metal may be disposed between at least one of the word line WL i and the diode 34 and between the protective layer 13B and the bit line BL j . The diode 34 is preferably omitted when the set / reset operation is performed only by the direction of the voltage.
B. 記録／再生動作
図１１、図１２及び図１５を用いて記録／再生動作を説明する。
ここでは、点線Ａで囲んだメモリセル３３を選択し、これについて記録／再生動作を実行するものとする。 B. Recording / playback operation
The recording / reproducing operation will be described with reference to FIG. 11, FIG. 12, and FIG.
Here, it is assumed that thememory cell 33 surrounded by the dotted line A is selected, and the recording / reproducing operation is executed for this.
図１１、図１２及び図１５を用いて記録／再生動作を説明する。
ここでは、点線Ａで囲んだメモリセル３３を選択し、これについて記録／再生動作を実行するものとする。 B. Recording / playback operation
The recording / reproducing operation will be described with reference to FIG. 11, FIG. 12, and FIG.
Here, it is assumed that the
情報記録（セット動作）は、選択されたメモリセル３３に電圧を印加し、そのメモリセル３３内に電位勾配を発生させて電流パルスを流せばよいため、例えば、ワード線ＷＬｉの電位がビット線ＢＬｊの電位よりも相対的に低い状態を作る。ビット線ＢＬｊを固定電位（例えば、接地電位）とすれば、ワード線ＷＬｉに負電位を与えればよい。
In the information recording (set operation), it is only necessary to apply a voltage to the selected memory cell 33 and generate a potential gradient in the memory cell 33 to flow a current pulse. For example, the potential of the word line WL i is a bit. making a relatively lower than the potential of the line BL j. If the bit line BL j is set to a fixed potential (for example, ground potential), a negative potential may be applied to the word line WL i .
この時、点線Ａで囲まれた選択されたメモリセル３３の記録層１２内では、拡散イオンの一部がワード線（陰極）ＷＬｉ側に移動し、記録層１２内の拡散イオンが陰イオンに対して相対的に減少する。また、ワード線ＷＬｉ側に移動した拡散イオンは、ワード線ＷＬｉから電子を受け取ってメタルとして析出する。
At this time, in the recording layer 12 of the selected memory cell 33 surrounded by the dotted line A, a part of the diffusion ions move to the word line (cathode) WL i side, and the diffusion ions in the recording layer 12 are anions. It decreases relative to. Further, the diffused ions that have moved to the word line WL i side receive electrons from the word line WL i and are deposited as metal.
点線Ａで囲まれた選択されたメモリセル３３の記録層１２では、陰イオンが過剰となり、結果的に、記録層１２内における遷移元素イオンの価数を上昇させる。つまり、点線Ａで囲まれた選択されたメモリセル３３は、相変化によるキャリアの注入により電子伝導性を有するようになるため、情報記録（セット動作）が完了する。
In the recording layer 12 of the selected memory cell 33 surrounded by the dotted line A, anions become excessive, and as a result, the valence of transition element ions in the recording layer 12 is increased. That is, since the selected memory cell 33 surrounded by the dotted line A has electron conductivity due to carrier injection due to phase change, information recording (set operation) is completed.
尚、情報記録時には、非選択のワード線ＷＬｉ－１，ＷＬｉ＋１及び非選択のビット線ＢＬｊ－１，ＢＬｊ＋１については、全て同電位にバイアスしておくことが好ましい。
During information recording, it is preferable that the non-selected word lines WL i−1 and WL i + 1 and the non-selected bit lines BL j−1 and BL j + 1 are all biased to the same potential.
また、情報記録前のスタンバイ時には、全てのワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１及び全てのビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１をプリチャージしておくことが好ましい。
In standby before recording information, it is preferable to precharge all the word lines WL i−1 , WL i , WL i + 1 and all the bit lines BL j−1 , BL j , BL j + 1 .
また、情報記録のための電圧パルスは、ワード線ＷＬｉの電位がビット線ＢＬｊの電位よりも相対的に高い状態を作ることにより発生させてもよい。
The voltage pulse for recording information may be generated by creating a state in which the potential of the word line WL i is relatively higher than the potential of the bit line BL j .
消去（リセット）動作は、選択されたメモリセル３３に大電流パルスを流すことにより発生するジュール熱とその残留熱を利用するため、例えば、ワード線ＷＬｉの電位をビット線ＢＬｊの電位よりも相対的に高くする。ビット線ＢＬｊを固定電位（例えば、接地電位）とすれば、ワード線ＷＬｉに正の電位を与えればよい。
Since the erase (reset) operation uses Joule heat generated by flowing a large current pulse to the selected memory cell 33 and its residual heat, for example, the potential of the word line WL i is set higher than the potential of the bit line BL j . Also make it relatively high. If the bit line BL j is set to a fixed potential (eg, ground potential), a positive potential may be applied to the word line WL i .
この時、点線Ａで囲まれた選択されたメモリセル３３の記録層１２内に陽イオンの一部が移動する。このため、導電性酸化物層１５内の陽イオン（遷移元素）の価数が増大し、記録層１２内の陽イオン（遷移元素）の価数が減少する。
At this time, a part of the cation moves into the recording layer 12 of the selected memory cell 33 surrounded by the dotted line A. For this reason, the valence of the cation (transition element) in the conductive oxide layer 15 increases, and the valence of the cation (transition element) in the recording layer 12 decreases.
その結果、メモリセル３３は、低抵抗状態から高抵抗状態に変化し、リセット動作（消去）が完了する。
As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
ここで、消去動作は、以下の方法により行うこともできる。
Here, the erase operation can also be performed by the following method.
但し、この場合には、上述したように、図１１、図１２及び図１５の半導体メモリからダイオード３４を取り除くことが好ましい。
However, in this case, as described above, it is preferable to remove the diode 34 from the semiconductor memory of FIG. 11, FIG. 12, and FIG.
例えば、ワード線ＷＬｉの電位をビット線ＢＬｊの電位よりも相対的に低くする。ビット線ＢＬｊを固定電位（例えば、接地電位）とすれば、ワード線ＷＬｉに負の電位を与えればよい。
For example, the potential of the word line WL i is made relatively lower than the potential of the bit line BL j . Bit lines BL j and a fixed potential (e.g., ground potential) if, a negative potential may be applied to the word line WL i.
この時、点線Ａで囲まれた選択されたメモリセル３３では、導電性酸化物層１５内の陽イオンの一部が記録層１２内に移動する。このため、導電性酸化物層１５内の陽イオン（遷移元素）の価数が増大し、記録層１２内の陽イオン（遷移元素）の価数が減少する。
At this time, in the selected memory cell 33 surrounded by the dotted line A, some of the cations in the conductive oxide layer 15 move into the recording layer 12. For this reason, the valence of the cation (transition element) in the conductive oxide layer 15 increases, and the valence of the cation (transition element) in the recording layer 12 decreases.
その結果、メモリセル３３は、低抵抗状態から高抵抗状態に変化し、リセット動作（消去）が完了する。
As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erase) is completed.
尚、消去時にも、非選択のワード線ＷＬｉ－１，ＷＬｉ＋１及び非選択のビット線ＢＬｊ－１，ＢＬｊ＋１については、全て同電位にバイアスしておくことが好ましい。
Even at the time of erasing, it is preferable that the unselected word lines WL i−1 , WL i + 1 and the unselected bit lines BL j−1 , BL j + 1 are all biased to the same potential.
また、消去前のスタンバイ時には、全てのワード線ＷＬｉ－１，ＷＬｉ，ＷＬｉ＋１及び全てのビット線ＢＬｊ－１，ＢＬｊ，ＢＬｊ＋１をプリチャージしておくことが好ましい。
In standby before erasing, it is preferable to precharge all the word lines WL i−1 , WL i , WL i + 1 and all the bit lines BL j−1 , BL j , BL j + 1 .
読み出し動作は、電流パルスを点線Ａで囲まれた選択されたメモリセル３３に流し、そのメモリセル３３の抵抗値を検出することにより行う。但し、電流パルスは、メモリセル３３を構成する材料が抵抗変化を起こさない程度の微小な値とすることが必要である。
The read operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a minute value that does not cause a resistance change of the material constituting the memory cell 33.
例えば、読み出し回路により発生した読み出し電流（電流パルス）をビット線ＢＬｊから点線Ａで囲まれたメモリセル３３に流し、読み出し回路によりそのメモリセル３３の抵抗値を測定する。既に説明した新材料を採用すれば、セット／リセット状態の抵抗値の差は、103以上を確保できる。
For example, read current generated by the reading circuit (current pulses) to the memory cell 33 surrounded by the dotted line A from the bit line BL j, measure the resistance value of the memory cell 33 by the read circuit. If the new material already explained is adopted, the difference in resistance value between the set / reset states can be secured at 10 3 or more.
C. まとめ
このようなクロスポイント型固体メモリによれば、現在のハードディスクやフラッシュメモリよりも高記録密度及び低消費電力を実現できる。 C. Summary
According to such a cross-point type solid-state memory, higher recording density and lower power consumption can be realized than current hard disks and flash memories.
このようなクロスポイント型固体メモリによれば、現在のハードディスクやフラッシュメモリよりも高記録密度及び低消費電力を実現できる。 C. Summary
According to such a cross-point type solid-state memory, higher recording density and lower power consumption can be realized than current hard disks and flash memories.
(3) その他
本実施形態では、プローブ型固体メモリとクロスポイント型固体メモリの２つについて説明したが、本発明の例で提案する材料及び原理を、現在のハードディスクやＤＶＤなどの記録媒体に適用することも可能である。 (3) Other
In this embodiment, the probe type solid-state memory and the cross-point type solid-state memory have been described. However, the material and principle proposed in the example of the present invention can be applied to a recording medium such as a current hard disk or DVD. It is.
本実施形態では、プローブ型固体メモリとクロスポイント型固体メモリの２つについて説明したが、本発明の例で提案する材料及び原理を、現在のハードディスクやＤＶＤなどの記録媒体に適用することも可能である。 (3) Other
In this embodiment, the probe type solid-state memory and the cross-point type solid-state memory have been described. However, the material and principle proposed in the example of the present invention can be applied to a recording medium such as a current hard disk or DVD. It is.
５． フラッシュメモリへの適用
(1) 構造
本発明の例は、フラッシュメモリに適用することも可能である。 5). Application to flash memory
(1) Structure
The example of the present invention can also be applied to a flash memory.
(1) 構造
本発明の例は、フラッシュメモリに適用することも可能である。 5). Application to flash memory
(1) Structure
The example of the present invention can also be applied to a flash memory.
図１６は、フラッシュメモリのメモリセルを示している。
FIG. 16 shows a memory cell of the flash memory.
フラッシュメモリのメモリセルは、ＭＩＳ(metal-insulator-semiconductor)トランジスタから構成される。
The memory cell of flash memory is composed of MIS (metal-insulator-semiconductor) transistors.
半導体基板４１の表面領域には、拡散層４２が形成される。拡散層４２の間のチャネル領域上には、ゲート絶縁層４３が形成される。ゲート絶縁層４３上には、本発明に係わる記録部(ReRAM: Resistive RAM)４４が形成される。記録部４４上には、コントロールゲート電極４５が形成される。
A diffusion layer 42 is formed in the surface region of the semiconductor substrate 41. A gate insulating layer 43 is formed on the channel region between the diffusion layers 42. On the gate insulating layer 43, a recording portion (ReRAM: Resistive RAM) 44 according to the present invention is formed. A control gate electrode 45 is formed on the recording unit 44.
半導体基板４１は、ウェル領域でもよく、また、半導体基板４１と拡散層４２とは、互いに逆の導電型を有する。コントロールゲート電極４５は、ワード線となり、例えば、導電性ポリシリコンから構成される。
The semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types. The control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.
記録部４４は、例えば、図２の記録層１２及び導電性酸化物層１５から構成される。
The recording unit 44 includes, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG.
(2) 基本動作
図１６を用いて基本動作について説明する。
セット（書き込み）動作は、コントロールゲート電極４５に電位Ｖ１を与え、半導体基板４１に電位Ｖ２を与えることにより実行する。 (2) Basic operation
The basic operation will be described with reference to FIG.
The set (write) operation is performed by applying the potential V1 to thecontrol gate electrode 45 and applying the potential V2 to the semiconductor substrate 41.
図１６を用いて基本動作について説明する。
セット（書き込み）動作は、コントロールゲート電極４５に電位Ｖ１を与え、半導体基板４１に電位Ｖ２を与えることにより実行する。 (2) Basic operation
The basic operation will be described with reference to FIG.
The set (write) operation is performed by applying the potential V1 to the
電位Ｖ１，Ｖ２の差は、記録部４４が相変化又は抵抗変化するのに十分な大きさであることが必要であるが、その向きについては、特に、限定されない。
The difference between the potentials V1 and V2 needs to be large enough for the recording unit 44 to undergo phase change or resistance change, but the direction is not particularly limited.
即ち、Ｖ１＞Ｖ２及びＶ１＜Ｖ２のいずれでもよい。
That is, either V1> V2 or V1 <V2 may be used.
例えば、初期状態（リセット状態）において、記録部４４が絶縁体（抵抗大）であると仮定すると、実質的にゲート絶縁層４３が厚くなったことになるため、メモリセル（ＭＩＳトランジスタ）の閾値は、高くなる。
For example, assuming that the recording unit 44 is an insulator (high resistance) in the initial state (reset state), the gate insulating layer 43 is substantially thickened, and thus the threshold value of the memory cell (MIS transistor). Get higher.
この状態から電位Ｖ１，Ｖ２を与えて記録部４４を導電体（抵抗小）に変化させると、実質的にゲート絶縁層４３が薄くなったことになるため、メモリセル（ＭＩＳトランジスタ）の閾値は、低くなる。
When the potentials V1 and V2 are applied from this state to change the recording portion 44 to a conductor (low resistance), the gate insulating layer 43 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is , Get lower.
尚、電位Ｖ２は、半導体基板４１に与えたが、これに代えて、メモリセルのチャネル領域に拡散層４２から電位Ｖ２を転送するようにしてもよい。
Although the potential V2 is applied to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.
リセット（消去）動作は、コントロールゲート電極４５に電位Ｖ１’を与え、拡散層４２の一方に電位Ｖ３を与え、拡散層４２の他方に電位Ｖ４（＜Ｖ３）を与えることにより実行する。
The reset (erase) operation is performed by applying the potential V1 'to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 (<V3) to the other of the diffusion layers 42.
電位Ｖ１’は、セット状態のメモリセルの閾値を越える値にする。
The potential V1 'is set to a value exceeding the threshold value of the memory cell in the set state.
この時、メモリセルは、オンになり、電子が拡散層４２の他方から一方に向かって流れると共に、ホットエレクトロンが発生する。このホットエレクトロンは、ゲート絶縁層４３を介して記録部４４に注入されるため、記録部４４の温度が上昇する。
At this time, the memory cell is turned on, electrons flow from one side of the diffusion layer 42 to the other side, and hot electrons are generated. Since the hot electrons are injected into the recording unit 44 through the gate insulating layer 43, the temperature of the recording unit 44 rises.
これにより、記録部４４は、導電体（抵抗小）から絶縁体（抵抗大）に変化するため、実質的にゲート絶縁層４３が厚くなったことになり、メモリセル（ＭＩＳトランジスタ）の閾値は、高くなる。
As a result, since the recording unit 44 changes from a conductor (low resistance) to an insulator (high resistance), the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is , Get higher.
このように、フラッシュメモリと類似した原理により、メモリセルの閾値を変えることができるため、フラッシュメモリの技術を利用して、本発明の例に係る情報記録再生装置を実用化できる。
As described above, since the threshold value of the memory cell can be changed based on a principle similar to that of the flash memory, the information recording / reproducing apparatus according to the example of the present invention can be put into practical use by utilizing the technology of the flash memory.
(3) ＮＡＮＤ型フラッシュメモリ
図１７は、ＮＡＮＤセルユニットの回路図を示している。図１８は、本発明の例に係るＮＡＮＤセルユニットの構造を示している。 (3) NAND flash memory
FIG. 17 shows a circuit diagram of the NAND cell unit. FIG. 18 shows the structure of a NAND cell unit according to an example of the present invention.
図１７は、ＮＡＮＤセルユニットの回路図を示している。図１８は、本発明の例に係るＮＡＮＤセルユニットの構造を示している。 (3) NAND flash memory
FIG. 17 shows a circuit diagram of the NAND cell unit. FIG. 18 shows the structure of a NAND cell unit according to an example of the present invention.
Ｐ型半導体基板４１ａ内には、Ｎ型ウェル領域４１ｂ及びＰ型ウェル領域４１ｃが形成される。Ｐ型ウェル領域４１ｃ内に、本発明の例に係るＮＡＮＤセルユニットが形成される。
In the P-type semiconductor substrate 41a, an N-type well region 41b and a P-type well region 41c are formed. A NAND cell unit according to an example of the present invention is formed in the P-type well region 41c.
ＮＡＮＤセルユニットは、直列接続される複数のメモリセルＭＣからなるＮＡＮＤストリングと、その両端に１つずつ接続される合計２つのセレクトゲートトランジスタＳＴとから構成される。
The NAND cell unit includes a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to both ends thereof.
メモリセルＭＣ及びセレクトゲートトランジスタＳＴは、同じ構造を有する。具体的には、これらは、Ｎ型拡散層４２と、Ｎ型拡散層４２の間のチャネル領域上のゲート絶縁層４３と、ゲート絶縁層４３上の記録部(ReRAM)４４と、記録部４４上のコントロールゲート電極４５とから構成される。
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
メモリセルＭＣの記録部４４の状態（絶縁体／導電体）は、上述の基本動作により変化させることが可能である。これに対し、セレクトゲートトランジスタＳＴの記録部４４は、セット状態、即ち、導電体（抵抗小）に固定される。
The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
セレクトゲートトランジスタＳＴの１つは、ソース線ＳＬに接続され、他の１つは、ビット線ＢＬに接続される。
One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.
セット（書き込み）動作前には、ＮＡＮＤセルユニット内の全てのメモリセルは、リセット状態（抵抗大）になっているものとする。
Before the set (write) operation, all the memory cells in the NAND cell unit are in a reset state (resistance is large).
セット（書き込み）動作は、ソース線ＳＬ側のメモリセルＭＣからビット線ＢＬ側のメモリセルに向かって１つずつ順番に行われる。
The set (write) operation is sequentially performed one by one from the memory cell MC on the source line SL side toward the memory cell on the bit line BL side.
選択されたワード線（コントロールゲート電極）ＷＬに書き込み電位としてＶ１（プラス電位）を与え、非選択のワード線ＷＬに転送電位（メモリセルＭＣがオンになる電位）としてＶpassを与える。
V1 (plus potential) is applied as a write potential to the selected word line (control gate electrode) WL, and Vpass is applied as a transfer potential (potential at which the memory cell MC is turned on) to the unselected word line WL.
ソース線ＳＬ側のセレクトゲートトランジスタＳＴをオフ、ビット線ＢＬ側のセレクトゲートトランジスタＳＴをオンにし、ビット線ＢＬから選択されたメモリセルＭＣのチャネル領域にプログラムデータを転送する。
The select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.
例えば、プログラムデータが“１”のときは、選択されたメモリセルＭＣのチャネル領域に書き込み禁止電位（例えば、Ｖ１と同じ程度の電位）を転送し、選択されたメモリセルＭＣの記録部４４の抵抗値が高い状態から低い状態に変化しないようにする。
For example, when the program data is “1”, a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording unit 44 of the selected memory cell MC The resistance value should not change from a high state to a low state.
また、プログラムデータが“０”のときは、選択されたメモリセルＭＣのチャネル領域にＶ２（＜Ｖ１）を転送し、選択されたメモリセルＭＣの記録部４４の抵抗値を高い状態から低い状態に変化させる。
When the program data is “0”, V2 (<V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording unit 44 of the selected memory cell MC is changed from a high state to a low state. To change.
リセット（消去）動作では、例えば、全てのワード線（コントロールゲート電極）ＷＬにＶ１’を与え、ＮＡＮＤセルユニット内の全てのメモリセルＭＣをオンにする。また、２つのセレクトゲートトランジスタＳＴをオンにし、ビット線ＢＬにＶ３を与え、ソース線ＳＬにＶ４（＜Ｖ３）を与える。
In the reset (erase) operation, for example, V1 'is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 (<V3) is applied to the source line SL.
この時、ホットエレクトロンがＮＡＮＤセルユニット内の全てのメモリセルＭＣの記録部４４に注入されるため、ＮＡＮＤセルユニット内の全てのメモリセルＭＣに対して一括してリセット動作が実行される。
At this time, since hot electrons are injected into the recording units 44 of all the memory cells MC in the NAND cell unit, the reset operation is executed collectively for all the memory cells MC in the NAND cell unit.
読み出し動作は、選択されたワード線（コントロールゲート電極）ＷＬに読み出し電位（プラス電位）を与え、非選択のワード線（コントロールゲート電極）ＷＬには、メモリセルＭＣがデータ“０”、“１”によらず必ずオンになる電位を与える。
In the read operation, a read potential (plus potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL. A potential to be turned on without fail is given.
また、２つのセレクトゲートトランジスタＳＴをオンにし、ＮＡＮＤストリングに読み出し電流を供給する。
Also, the two select gate transistors ST are turned on to supply a read current to the NAND string.
選択されたメモリセルＭＣは、読み出し電位が印加されると、それに記憶されたデータの値に応じてオン又はオフになるため、例えば、読み出し電流の変化を検出することにより、データを読み出すことができる。
When a read potential is applied to the selected memory cell MC, the selected memory cell MC is turned on or off according to the value of the data stored therein. For example, data can be read by detecting a change in the read current. it can.
尚、図１８の構造では、セレクトゲートトランジスタＳＴは、メモリセルＭＣと同じ構造を有しているが、例えば、図１９に示すように、セレクトゲートトランジスタＳＴについては、記録部（記録層及び導電性酸化物層）を形成せずに、通常のＭＩＳトランジスタとすることも可能である。
In the structure of FIG. 18, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 19, the select gate transistor ST has a recording portion (recording layer and conductive layer). It is also possible to form a normal MIS transistor without forming the conductive oxide layer.
図２０は、ＮＡＮＤ型フラッシュメモリの変形例である。
FIG. 20 shows a modification of the NAND flash memory.
この変形例は、ＮＡＮＤストリングを構成する複数のメモリセルＭＣのゲート絶縁層がＰ型半導体層４７に置き換えられている点に特徴を有する。
This modification is characterized in that the gate insulating layer of the plurality of memory cells MC constituting the NAND string is replaced with a P-type semiconductor layer 47.
高集積化が進み、メモリセルＭＣが微細化されると、電圧を与えていない状態で、Ｐ型半導体層４７は、空乏層で満たされることになる。
When high integration progresses and the memory cell MC is miniaturized, the P-type semiconductor layer 47 is filled with a depletion layer in a state where no voltage is applied.
セット（書き込み）時には、選択されたメモリセルＭＣのコントロールゲート電極４５にプラスの書き込み電位（例えば、3.5V）を与え、かつ、非選択のメモリセルＭＣのコントロールゲート電極４５にプラスの転送電位（例えば、1V）を与える。
At the time of setting (writing), a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and a positive transfer potential (to the control gate electrode 45 of the non-selected memory cell MC). For example, give 1V).
この時、ＮＡＮＤストリング内の複数のメモリセルＭＣのＰ型ウェル領域４１ｃの表面がＰ型からＮ型に反転し、チャネルが形成される。
At this time, the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.
そこで、上述したように、ビット線ＢＬ側のセレクトゲートトランジスタＳＴをオンにし、ビット線ＢＬから選択されたメモリセルＭＣのチャネル領域にプログラムデータ“０”を転送すれば、セット動作を行うことができる。
Therefore, as described above, the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.
リセット（消去）は、例えば、全てのコントロールゲート電極４５にマイナスの消去電位（例えば、-3.5V）を与え、Ｐ型ウェル領域４１ｃ及びＰ型半導体層４７に接地電位（0V）を与えれば、ＮＡＮＤストリングを構成する全てのメモリセルＭＣに対して一括して行うことができる。
For example, reset (erase) is performed by applying a negative erase potential (for example, −3.5 V) to all the control gate electrodes 45 and applying a ground potential (0 V) to the P-type well region 41 c and the P-type semiconductor layer 47. This can be performed collectively for all the memory cells MC constituting the NAND string.
読み出し時には、選択されたメモリセルＭＣのコントロールゲート電極４５にプラスの読み出し電位（例えば、0.5V）を与え、かつ、非選択のメモリセルＭＣのコントロールゲート電極４５に、メモリセルＭＣがデータ“０”、“１”によらず必ずオンになる転送電位（例えば、1V）を与える。
At the time of reading, a positive read potential (for example, 0.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the memory cell MC receives data “0” to the control gate electrode 45 of the non-selected memory cell MC. A transfer potential (for example, 1 V) that is always turned on regardless of “1” is applied.
但し、“１”状態のメモリセルＭＣの閾値電圧Vth”1”は、0V < Vth”1” < 0.5Vの範囲内にあるものとし、“０”状態のメモリセルＭＣの閾値電圧Vth”0”は、0.5V < Vth”0” < 1Vの範囲内にあるものとする。
However, the threshold voltage Vth ”1” of the memory cell MC in the “1” state is in the range of 0V 範 囲 <Vth ”1” <0.5V, and the threshold voltage Vth ”0 of the memory cell MC in the“ 0 ”state “” Shall be in the range of 0.5V0.5 <Vth ”0” <1V.
また、２つのセレクトゲートトランジスタＳＴをオンにし、ＮＡＮＤストリングに読み出し電流を供給する。
Also, the two select gate transistors ST are turned on to supply a read current to the NAND string.
このような状態にすれば、選択されたメモリセルＭＣに記憶されたデータの値に応じてＮＡＮＤストリングに流れる電流量が変わるため、この変化を検出することにより、データを読み出すことができる。
In such a state, since the amount of current flowing through the NAND string changes according to the value of data stored in the selected memory cell MC, data can be read by detecting this change.
尚、この変形例においては、Ｐ型半導体層４７のホールドープ量がＰ型ウェル領域４１ｃのそれよりも多く、かつ、Ｐ型半導体層４７のフェルミレベルがＰ型ウェル領域４１ｃのそれよりも0.5V程度深くなっていることが好ましい。
In this modification, the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0.5 than that of the P-type well region 41c. It is preferable that the depth is about V.
これは、コントロールゲート電極４５にプラスの電位を与えたときに、Ｎ型拡散層４２間のＰ型ウェル領域４１ｃの表面部分からＰ型からＮ型への反転が開始し、チャネルが形成されるようにするためである。
This is because when a positive potential is applied to the control gate electrode 45, inversion from the P-type to N-type starts from the surface portion of the P-type well region 41c between the N-type diffusion layers 42, and a channel is formed. It is for doing so.
このようにすることで、例えば、書き込み時には、非選択のメモリセルＭＣのチャネルは、Ｐ型ウェル領域４１ｃとＰ型半導体層４７の界面のみに形成され、読み出し時には、ＮＡＮＤストリング内の複数のメモリセルＭＣのチャネルは、Ｐ型ウェル領域４１ｃとＰ型半導体層４７の界面のみに形成される。
Thus, for example, at the time of writing, the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed. The channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
つまり、メモリセルＭＣの記録部４４が導電体（セット状態）であっても、拡散層４２とコントロールゲート電極４５とが短絡することはない。
That is, even if the recording part 44 of the memory cell MC is a conductor (set state), the diffusion layer 42 and the control gate electrode 45 are not short-circuited.
(4) ＮＯＲ型フラッシュメモリ
図２１は、ＮＯＲセルユニットの回路図を示している。図２２は、本発明の例に係るＮＯＲセルユニットの構造を示している。 (4) NOR flash memory
FIG. 21 shows a circuit diagram of the NOR cell unit. FIG. 22 shows the structure of a NOR cell unit according to an example of the present invention.
図２１は、ＮＯＲセルユニットの回路図を示している。図２２は、本発明の例に係るＮＯＲセルユニットの構造を示している。 (4) NOR flash memory
FIG. 21 shows a circuit diagram of the NOR cell unit. FIG. 22 shows the structure of a NOR cell unit according to an example of the present invention.
Ｐ型半導体基板４１ａ内には、Ｎ型ウェル領域４１ｂ及びＰ型ウェル領域４１ｃが形成される。Ｐ型ウェル領域４１ｃ内に、本発明の例に係るＮＯＲセルが形成される。
In the P-type semiconductor substrate 41a, an N-type well region 41b and a P-type well region 41c are formed. A NOR cell according to an example of the present invention is formed in the P-type well region 41c.
ＮＯＲセルは、ビット線ＢＬとソース線ＳＬとの間に接続される１つのメモリセル（ＭＩＳトランジスタ）ＭＣから構成される。
The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
メモリセルＭＣは、Ｎ型拡散層４２と、Ｎ型拡散層４２の間のチャネル領域上のゲート絶縁層４３と、ゲート絶縁層４３上の記録部(ReRAM)４４と、記録部４４上のコントロールゲート電極４５とから構成される。
The memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a control on the recording unit 44. And a gate electrode 45.
メモリセルＭＣの記録部４４の状態（絶縁体／導電体）は、上述の基本動作により変化させることが可能である。
The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
(5) ２トラ型フラッシュメモリ
図２３は、２トラセルユニットの回路図を示している。図２４は、本発明の例に係る２トラセルユニットの構造を示している。 (5) Two-tra type flash memory
FIG. 23 shows a circuit diagram of a two-tracell unit. FIG. 24 shows the structure of a two-tracell unit according to an example of the present invention.
図２３は、２トラセルユニットの回路図を示している。図２４は、本発明の例に係る２トラセルユニットの構造を示している。 (5) Two-tra type flash memory
FIG. 23 shows a circuit diagram of a two-tracell unit. FIG. 24 shows the structure of a two-tracell unit according to an example of the present invention.
２トラセルユニットは、ＮＡＮＤセルユニットの特徴とＮＯＲセルの特徴とを併せ持った新たなセル構造として最近開発されたものである。
The 2 tracell unit was recently developed as a new cell structure that combines the features of NAND cell units and NOR cells.
Ｐ型半導体基板４１ａ内には、Ｎ型ウェル領域４１ｂ及びＰ型ウェル領域４１ｃが形成される。Ｐ型ウェル領域４１ｃ内に、本発明の例に係る２トラセルユニットが形成される。
In the P-type semiconductor substrate 41a, an N-type well region 41b and a P-type well region 41c are formed. In the P-type well region 41c, the two tracell unit according to the example of the present invention is formed.
２トラセルユニットは、直列接続される１つのメモリセルＭＣと１つのセレクトゲートトランジスタＳＴとから構成される。
The 2 tracell unit is composed of one memory cell MC and one select gate transistor ST connected in series.
メモリセルＭＣ及びセレクトゲートトランジスタＳＴは、同じ構造を有する。具体的には、これらは、Ｎ型拡散層４２と、Ｎ型拡散層４２の間のチャネル領域上のゲート絶縁層４３と、ゲート絶縁層４３上の記録部(ReRAM)４４と、記録部４４上のコントロールゲート電極４５とから構成される。
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. And the upper control gate electrode 45.
メモリセルＭＣの記録部４４の状態（絶縁体／導電体）は、上述の基本動作により変化させることが可能である。これに対し、セレクトゲートトランジスタＳＴの記録部４４は、セット状態、即ち、導電体（抵抗小）に固定される。
The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above. On the other hand, the recording portion 44 of the select gate transistor ST is fixed in a set state, that is, a conductor (small resistance).
セレクトゲートトランジスタＳＴは、ソース線ＳＬに接続され、メモリセルＭＣは、ビット線ＢＬに接続される。
The select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.
メモリセルＭＣの記録部４４の状態（絶縁体／導電体）は、上述の基本動作により変化させることが可能である。
The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the basic operation described above.
図２４の構造では、セレクトゲートトランジスタＳＴは、メモリセルＭＣと同じ構造を有しているが、例えば、図２５に示すように、セレクトゲートトランジスタＳＴについては、記録部（記録層及び導電性酸化物層）を形成せずに、通常のＭＩＳトランジスタとすることも可能である。
In the structure of FIG. 24, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 25, the select gate transistor ST has a recording portion (recording layer and conductive oxide). A normal MIS transistor can be formed without forming a physical layer.
６． 実施例
いくつかのサンプルを作成し、リセット（消去）状態とセット（書き込み）状態との抵抗差について評価した実施例を説明する。 6). Example
A description will be given of an embodiment in which several samples are prepared and the resistance difference between the reset (erase) state and the set (write) state is evaluated.
いくつかのサンプルを作成し、リセット（消去）状態とセット（書き込み）状態との抵抗差について評価した実施例を説明する。 6). Example
A description will be given of an embodiment in which several samples are prepared and the resistance difference between the reset (erase) state and the set (write) state is evaluated.
サンプルとしては、図８のシステムを有し、記録部２２が図２の構造（記録層１２及び導電性酸化物層１５）からなるデバイスを使用する。
As a sample, a device having the system of FIG. 8 and having the recording unit 22 having the structure of FIG. 2 (the recording layer 12 and the conductive oxide layer 15) is used.
評価は、先端の径が10nm以下に先鋭化されたプローブ対を使用する。
¡Evaluation uses a probe pair whose tip diameter is sharpened to 10nm or less.
プローブ対を保護層１３Ｂに接触させ、情報記録（書き込み／消去）は、そのうちの１つを用いて実行する。書き込みは、記録部２２に、例えば、10nsec幅で、1Vの電圧パルスを印加することにより行う。消去は、記録部２２に、例えば、100nsec幅で、0.2Vの電圧パルスを印加することにより行う。なお、半導体パラメーターアナライザーのようにDC的な評価も可能である。
The probe pair is brought into contact with the protective layer 13B, and information recording (writing / erasing) is performed using one of them. Writing is performed by applying a voltage pulse of 1 V to the recording unit 22 with a width of 10 nsec, for example. Erasing is performed by applying a voltage pulse of 0.2 V to the recording unit 22 with a width of 100 nsec, for example. DC evaluation is also possible like a semiconductor parameter analyzer.
また、書き込み／消去の合間に、プローブ対の他の１つを用いて読み出しを実行する。読み出しは、記録部２２に、10nsec幅で、0.1Vの電圧パルスを印加し、記録部（記録ビット）２２の抵抗値を測定することにより行う。
Also, read is executed using the other one of the probe pair between write / erase. Reading is performed by applying a voltage pulse of 0.1 V with a width of 10 nsec to the recording unit 22 and measuring the resistance value of the recording unit (recording bit) 22.
(1) 第１実施例
第１実施例のサンプルの仕様は、以下の通りである。 (1) First embodiment
The specifications of the sample of the first embodiment are as follows.
第１実施例のサンプルの仕様は、以下の通りである。 (1) First embodiment
The specifications of the sample of the first embodiment are as follows.
記録層１２は、Zn1.1Mn1.9O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Ga2O3を2wt.%ドープしたZnOとし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(ZnO)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of Zn 1.1 Mn 1.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of ZnO doped with 2 wt.% Ga 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
この場合、記録層１２と導電性酸化物層１５との間で元素が相互拡散し難くなるため、耐熱性、耐環境性、耐久性などの特性が向上する。また、記録層１２の結晶性が向上し、素子間のばらつき、ロット間ばらつきが大幅に低減される。
In this case, since it becomes difficult for the elements to mutually diffuse between the recording layer 12 and the conductive oxide layer 15, characteristics such as heat resistance, environmental resistance, and durability are improved. Further, the crystallinity of the recording layer 12 is improved, and variations between elements and lots are greatly reduced.
また、全てのサンプルにおいて数千回以上の書き換え動作が可能であった。
In addition, rewriting operation several thousand times or more was possible in all samples.
これは、書き換え動作時に、記録層１２とそれに接触する層との間での元素の拡散、記録層１２の内部での偏析などの原子レベルでの変化が小さい、又はそれを相殺する方向に働いている、ということを意味する。
This is because a change at an atomic level such as element diffusion between the recording layer 12 and a layer in contact with the recording layer 12 and segregation inside the recording layer 12 is small or cancels out during the rewriting operation. It means that
電極層２１の材料は、TiN、TiSiN、TaN、TaSiNの４種類とする。
The material of the electrode layer 21 is four types of TiN, TiSiN, TaN, and TaSiN.
また、電極層２１としては、SiN、TiC、TaC、SiCなども好適と考えられる。Pt、Ru、Irなどの金属材料は、高コストであるため、電極層２１の材料としては好ましくない。
Also, as the electrode layer 21, SiN, TiC, TaC, SiC or the like is considered suitable. Metal materials such as Pt, Ru, and Ir are not preferable as the material of the electrode layer 21 because they are expensive.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
これらをまとめて表１に示す。
These are summarized in Table 1.
表１から明らかなように、セット／リセット電圧は、導電性酸化物層１５の厚さにはほとんど依存しない。これは、インピーダンスを完全にマッチングさせることが難しく、リンギングなどによる測定誤差が10%程度含まれるためであると考えられる。言い換えれば、導電性酸化物層１５の厚さがセット／リセット電圧に与える影響は10%程度と見積もることができる。
As is clear from Table 1, the set / reset voltage hardly depends on the thickness of the conductive oxide layer 15. This is thought to be because it is difficult to perfectly match the impedance and measurement error due to ringing or the like is included about 10%. In other words, the influence of the thickness of the conductive oxide layer 15 on the set / reset voltage can be estimated to be about 10%.
(2) 第２実施例
第２実施例のサンプルの仕様は、以下の通りである。 (2) Second embodiment
The specifications of the sample of the second embodiment are as follows.
第２実施例のサンプルの仕様は、以下の通りである。 (2) Second embodiment
The specifications of the sample of the second embodiment are as follows.
記録層１２は、Zn1.1Mn2.0O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Al2O3を2.5wt.%ドープしたZnOとし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(ZnO)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of Zn 1.1 Mn 2.0 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of ZnO doped with 2.5 wt.% Of Al 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(3) 第３実施例
第３実施例のサンプルの仕様は、以下の通りである。 (3) Third embodiment
The sample specifications of the third embodiment are as follows.
第３実施例のサンプルの仕様は、以下の通りである。 (3) Third embodiment
The sample specifications of the third embodiment are as follows.
記録層１２は、ZnCo2O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、CoOとし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。
The recording layer 12 is made of ZnCo 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of CoO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(4) 第４実施例
第４実施例のサンプルの仕様は、以下の通りである。 (4) Fourth embodiment
The sample specifications of the fourth embodiment are as follows.
第４実施例のサンプルの仕様は、以下の通りである。 (4) Fourth embodiment
The sample specifications of the fourth embodiment are as follows.
記録層１２は、TiZn2O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Nb2O5を1wt.%ドープしたTiO2とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(TiO2)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
Recording layer 12, a TiZn 2 O 4, are prepared three kinds of thickness (10nm, 20nm, 50nm). The conductive oxide layer 15 is made of TiO 2 doped with 1 wt.% Of Nb 2 O 5 and has three types of thickness (0.5 nm, 5 nm, and 10 nm). The amount of dopant with respect to the conductive oxide layer (TiO 2 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(5) 第５実施例
第５実施例のサンプルの仕様は、以下の通りである。 (5) Fifth embodiment
The sample specifications of the fifth embodiment are as follows.
第５実施例のサンプルの仕様は、以下の通りである。 (5) Fifth embodiment
The sample specifications of the fifth embodiment are as follows.
記録層１２は、ZnMnO3とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Sb2O3を1wt.%ドープしたSnO2とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(SnO2)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of ZnMnO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is SnO 2 doped with 1 wt.% Of Sb 2 O 3 , and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant for the conductive oxide layer (SnO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(6) 第６実施例
第６実施例のサンプルの仕様は、以下の通りである。 (6) Sixth embodiment
The specifications of the sample of the sixth embodiment are as follows.
第６実施例のサンプルの仕様は、以下の通りである。 (6) Sixth embodiment
The specifications of the sample of the sixth embodiment are as follows.
記録層１２は、TiZn2O3.8とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、TiO2とZnOとをそれぞれ1wt.%ドープしたIn2O3とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(In2O3)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of TiZn 2 O 3.8, and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of In 2 O 3 doped with 1 wt.% Of TiO 2 and ZnO, and three kinds of thicknesses (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (In 2 O 3 ) 15 is determined in consideration of the electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(7) 第７実施例
第７実施例のサンプルの仕様は、以下の通りである。 (7) Seventh embodiment
The sample specifications of the seventh embodiment are as follows.
第７実施例のサンプルの仕様は、以下の通りである。 (7) Seventh embodiment
The sample specifications of the seventh embodiment are as follows.
記録層１２は、ZnMoO3とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、ZnOを1wt.%ドープしたIrO2とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(IrO2)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of ZnMoO 3 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of IrO 2 doped with 1% by weight of ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant for the conductive oxide layer (IrO 2 ) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(8) 第８実施例
第８実施例のサンプルの仕様は、以下の通りである。 (8) Eighth Example
The sample specifications of the eighth embodiment are as follows.
第８実施例のサンプルの仕様は、以下の通りである。 (8) Eighth Example
The sample specifications of the eighth embodiment are as follows.
記録層１２は、ZnFe2O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、ZnOを1wt.%ドープしたRuO2とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(ZnO)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of ZnFe 2 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of RuO 2 doped with 1 wt.% ZnO, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(9) 第9実施例
第9実施例のサンプルの仕様は、以下の通りである。 (9) Ninth embodiment
The specifications of the sample of the ninth embodiment are as follows.
第9実施例のサンプルの仕様は、以下の通りである。 (9) Ninth embodiment
The specifications of the sample of the ninth embodiment are as follows.
記録層１２は、Mn3O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Al23を2.6wt.%ドープしたZnOとし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(ZnO)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of Mn 3 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of ZnO doped with 2.6 wt.% Al23, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(10) 第10実施例
第10実施例のサンプルの仕様は、以下の通りである。 (10) Tenth embodiment
The sample specifications of the tenth embodiment are as follows.
第10実施例のサンプルの仕様は、以下の通りである。 (10) Tenth embodiment
The sample specifications of the tenth embodiment are as follows.
記録層１２は、Mn2.9O4とし、３種類の厚さ(10nm、20nm、50nm)を用意する。導電性酸化物層１５は、Nb2O5を1.1wt.%ドープしたTiO2+とし、３種類の厚さ(0.5nm、5nm、10nm)を用意する。導電性酸化物層(ZnO)１５に対するドーパント量は、その電気抵抗率と、記録層１２を積層したときに発生する微小な電圧降下とを考慮して決定する。
The recording layer 12 is made of Mn 2.9 O 4 and three types of thickness (10 nm, 20 nm, 50 nm) are prepared. The conductive oxide layer 15 is made of TiO 2 + doped with 1.1 wt.% Of Nb2O5, and three types of thickness (0.5 nm, 5 nm, and 10 nm) are prepared. The amount of dopant with respect to the conductive oxide layer (ZnO) 15 is determined in consideration of its electrical resistivity and a minute voltage drop generated when the recording layer 12 is laminated.
導電性酸化物層１５による効果及び電極層２１の材料に関する説明は、第１実施例と同じであるため、ここでは、その説明を省略する。
Since the description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as in the first embodiment, the description thereof is omitted here.
ユニポーラ動作時のリセット電圧は、+0.5～+0.8V、セット電圧は、+1.5～1.7Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+1～+1.3V、セット電圧は、-2.5～-2.7Vを実現できることを確認した。
The reset voltage during unipolar operation was +0.5 to + 0.8V, and the set voltage was +1.5 to 1.7V. It was also confirmed that the reset voltage during bipolar operation can be +1 to + 1.3V, and the set voltage can be -2.5 to -2.7V.
この結果は、第１実施例の結果と同じである。導電性酸化物層１５の厚さがセット／リセット電圧にほとんど影響を与えないことも第１実施例と同じである。
This result is the same as the result of the first example. Similarly to the first embodiment, the thickness of the conductive oxide layer 15 hardly affects the set / reset voltage.
(9) 比較例
比較例のサンプルの仕様は、以下の通りである。
記録層１２は、厚さ10nmのFe1.9O3とし、導電性酸化物層を用いない。即ち、記録部２２は、記録層１２のみから構成する。 (9) Comparative example
The specification of the sample of the comparative example is as follows.
Therecording layer 12 is made of Fe 1.9 O 3 having a thickness of 10 nm and does not use a conductive oxide layer. That is, the recording unit 22 is composed of only the recording layer 12.
比較例のサンプルの仕様は、以下の通りである。
記録層１２は、厚さ10nmのFe1.9O3とし、導電性酸化物層を用いない。即ち、記録部２２は、記録層１２のみから構成する。 (9) Comparative example
The specification of the sample of the comparative example is as follows.
The
この場合、ユニポーラ動作時のリセット電圧は、+0.5V、セット電圧は、+1.5Vという結果が得られた。また、バイポーラ動作時のリセット電圧は、+0.5V、セット電圧は、-0.5Vという結果が得られた。しかし、比較例では、サイクル特性が悪く、書き換え回数の上限は、数百回程度であった。
In this case, the reset voltage during unipolar operation was + 0.5V, and the set voltage was + 1.5V. In addition, the reset voltage during bipolar operation was + 0.5V, and the set voltage was -0.5V. However, in the comparative example, the cycle characteristics were poor and the upper limit of the number of rewrites was about several hundred times.
(10) まとめ
以上、説明したように、第１乃至第８実施例で使用するサンプルでは、バイポーラ動作時のセット電圧は、ユニポーラ動作時のセット電圧に比べて高い。これに対し、比較例で使用するサンプルでは、バイポーラ動作時のセット電圧は、ユニポーラ動作時のセット電圧に比べて低い。これは、本発明をクロスポイント型固体メモリに適用した場合に、書き込みの対象とならない非選択セルの逆バイアス耐性が優れていることを意味する。また、サイクル特性に関しても、第１乃至第８実施例は、比較例よりも優れている。 (10) Summary
As described above, in the samples used in the first to eighth embodiments, the set voltage during the bipolar operation is higher than the set voltage during the unipolar operation. On the other hand, in the sample used in the comparative example, the set voltage during the bipolar operation is lower than the set voltage during the unipolar operation. This means that when the present invention is applied to a cross-point type solid-state memory, the reverse bias resistance of the non-selected cell that is not the object of writing is excellent. Also, regarding the cycle characteristics, the first to eighth examples are superior to the comparative example.
以上、説明したように、第１乃至第８実施例で使用するサンプルでは、バイポーラ動作時のセット電圧は、ユニポーラ動作時のセット電圧に比べて高い。これに対し、比較例で使用するサンプルでは、バイポーラ動作時のセット電圧は、ユニポーラ動作時のセット電圧に比べて低い。これは、本発明をクロスポイント型固体メモリに適用した場合に、書き込みの対象とならない非選択セルの逆バイアス耐性が優れていることを意味する。また、サイクル特性に関しても、第１乃至第８実施例は、比較例よりも優れている。 (10) Summary
As described above, in the samples used in the first to eighth embodiments, the set voltage during the bipolar operation is higher than the set voltage during the unipolar operation. On the other hand, in the sample used in the comparative example, the set voltage during the bipolar operation is lower than the set voltage during the unipolar operation. This means that when the present invention is applied to a cross-point type solid-state memory, the reverse bias resistance of the non-selected cell that is not the object of writing is excellent. Also, regarding the cycle characteristics, the first to eighth examples are superior to the comparative example.
さらに、本発明によれば、オン状態の抵抗値が増大し、オン電流が低減し、極めて小さな消費電力でのセット／リセット動作が可能になる。これは、多数セルの同時並行処理を可能とし、極めて高速な動作を実現できることになる。
Furthermore, according to the present invention, the on-state resistance value increases, the on-current decreases, and a set / reset operation with extremely low power consumption becomes possible. This enables simultaneous processing of a large number of cells and realizes extremely high speed operation.
このようなことから、本発明に係わる導電性酸化物層を用いることで、高記録密度及び低消費電力の不揮発性の情報記録再生装置を実現できる。
Therefore, by using the conductive oxide layer according to the present invention, a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
表２に、第１乃至第８実施例及び比較例の検証結果をまとめたものを示す。
Table 2 summarizes the verification results of the first to eighth examples and the comparative example.
７． むすび
本発明によれば、高記録密度及び低消費電力の不揮発性の情報記録再生装置を実現できる。 7). Conclusion
According to the present invention, a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
本発明によれば、高記録密度及び低消費電力の不揮発性の情報記録再生装置を実現できる。 7). Conclusion
According to the present invention, a nonvolatile information recording / reproducing apparatus with high recording density and low power consumption can be realized.
本発明の例は、上述の実施形態に限定されるものではなく、その要旨を逸脱しない範囲で、各構成要素を変形して具体化できる。また、上述の実施形態に開示されている複数の構成要素の適宜な組み合せにより種々の発明を構成できる。例えば、上述の実施形態に開示される全構成要素から幾つかの構成要素を削除してもよいし、異なる実施形態の構成要素を適宜組み合わせてもよい。
The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.
本発明の例に関わる情報記録再生装置よれば、極めて単純な仕組みであるにもかかわらず、従来技術では到達することのできない記録密度による情報記録を可能とすると同時に高速動作を実現することが可能になる。従って、本発明の例は、現在の不揮発性メモリの記録密度の壁を打ち破る次世代技術として産業上のメリットは多大である。
According to the information recording / reproducing apparatus according to the example of the present invention, it is possible to perform information recording at a recording density that cannot be achieved by the prior art, and at the same time to achieve high-speed operation, despite the extremely simple mechanism. become. Therefore, the example of the present invention has a great industrial advantage as a next generation technology that breaks down the recording density barrier of the current nonvolatile memory.
Claims (10)
- 異なる電気抵抗率の２以上の状態が記録される記録層と、前記記録層に電圧又は電流を与えて前記記録層の状態を変化させるときに陽極側となる前記記録層の一端に配置される導電性酸化物層とを具備し、
前記導電性酸化物層の電気抵抗率は、前記記録層の電気抵抗率の最小値よりも小さく、
前記導電性酸化物層は、
(i) ZnO、SnO2、CoO、TiOs(1≦s≦2)、In2O3、IrO2、RuO2のグループから選択される主成分としての第１材料と、
(ii) Ga2O3、Al2O3、Nb2O5、SnO2、Ta2O5、Sb2O3、ZnO、TiOs(1≦s≦2)のグループから選択されるドーパントとしての第２材料と
の混合体から構成される
ことを特徴とする情報記録再生装置。 A recording layer in which two or more states having different electrical resistivity are recorded, and one end of the recording layer on the anode side when a voltage or current is applied to the recording layer to change the state of the recording layer A conductive oxide layer,
The electrical resistivity of the conductive oxide layer is smaller than the minimum value of the electrical resistivity of the recording layer,
The conductive oxide layer is
(i) a first material as a main component selected from the group consisting of ZnO, SnO 2 , CoO, TiO s (1 ≦ s ≦ 2), In 2 O 3 , IrO 2 , RuO 2 ;
(ii) As a dopant selected from the group of Ga 2 O 3 , Al 2 O 3 , Nb 2 O 5 , SnO 2 , Ta 2 O 5 , Sb 2 O 3 , ZnO, TiO s (1 ≦ s ≦ 2) An information recording / reproducing apparatus comprising: a mixture with the second material. - 前記陽極側の電極をさらに具備し、前記導電性酸化物層は、前記記録層と前記電極との間に配置され、前記電極は、
Ti-N、Ti-Si-N、Ta-N、Ta-Si-N、Si-N、Ti-C、Ta-C、Si-Cのグループから選択される材料の窒化物、炭化物若しくは酸化物、
前記窒化物と前記酸化物との混合体、
前記窒化物と前記炭化物との混合体、
前記酸化物と前記炭化物との混合体、又は、
前記窒化物と前記炭化物と前記酸化物との混合体
から構成されることを特徴とする請求項１に記載の情報記録再生装置。 Further comprising an electrode on the anode side, the conductive oxide layer is disposed between the recording layer and the electrode,
Nitride, carbide or oxide of a material selected from the group of Ti-N, Ti-Si-N, Ta-N, Ta-Si-N, Si-N, Ti-C, Ta-C, Si-C ,
A mixture of the nitride and the oxide;
A mixture of the nitride and the carbide;
A mixture of the oxide and the carbide, or
The information recording / reproducing apparatus according to claim 1, comprising a mixture of the nitride, the carbide, and the oxide. - 前記記録層は、
(I) AxMyX4 (0.１≦x≦2.2、1.8≦y≦2)
(II) AxMyX3 (0.5≦x≦1.1、0.9≦y≦1)
(III) AxMyX4 (0.5≦x≦1.1、0.9≦y≦1)
のグループから選択される材料
但し、(I)及び(II)に関し、Aは、Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi のグループから選択される元素、Mは、Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Nb, Ta, Mo, W, Ru, Rh のグループから選択される元素である。
(III)に関し、Aは、Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, Bi のグループから選択される元素、Mは、Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, Os のグループから選択される元素である。
(I)、(II)及び(III)に関し、AとMは、互いに異なる元素であり、Xは、O, Nのグループから選択される元素である。
により構成されることを特徴とする請求項１に記載の情報記録再生装置。 The recording layer is
(I) A x M y X 4 (0.1 ≦ x ≦ 2.2,1.8 ≦ y ≦ 2)
(II) A x M y X 3 (0.5 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1)
(III) A x M y X 4 (0.5 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1)
However, regarding (I) and (II), A is Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu , Zn, Ge, Ag, Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi An element selected from the group, M is Al, Ga, Ti, Ge, Sn, V, Cr , Mn, Fe, Co, Ni, Nb, Ta, Mo, W, Ru, and Rh.
Regarding (III), A is an element selected from the group consisting of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, and Bi. , M is an element selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, and Os.
Regarding (I), (II), and (III), A and M are different elements, and X is an element selected from the group of O and N.
The information recording / reproducing apparatus according to claim 1, comprising: - 前記記録層は、
1. コランダム構造
2. ルチル構造
3. スピネル構造
4. ラムスデライト構造
5. アナターゼ構造
6. ホランダイト構造
7. ブルッカイト構造
8. パイロルース構造
9. NaCl構造
10. ペロブスカイト構造
11. イルメナイト構造
12. ウルフラマイト構造
のグループから選択される結晶構造を有することを特徴とする請求項１に記載の情報記録再生装置。 The recording layer is
1. Corundum structure 2. Rutile structure 3. Spinel structure 4. Ramsdelite structure 5. Anatase structure 6. Hollandite structure 7. Brookite structure 8. Pyroluth structure 9. NaCl structure 10. Perovskite structure 11. Ilmenite structure 12. Wolframite structure 2. The information recording / reproducing apparatus according to claim 1, wherein the information recording / reproducing apparatus has a crystal structure selected from a group. - 前記第２材料が前記導電性酸化物層内に占める割合は、30 wt.%以下であることを特徴とする請求項１に記載の情報記録再生装置。 2. The information recording / reproducing apparatus according to claim 1, wherein the proportion of the second material in the conductive oxide layer is 30 wt% or less.
- 前記導電性酸化物層は、
(i) 閃亜鉛鉱構造
(ii) ウルツ鉱構造
(iii) C-希土構造
(iv) ルチル構造
(v) NaCl構造
のグループから選択される結晶構造を有することを特徴とする請求項１に記載の情報記録再生装置。 The conductive oxide layer is
A crystal structure selected from the group consisting of (i) sphalerite structure (ii) wurtzite structure (iii) C-rare earth structure (iv) rutile structure (v) NaCl structure The information recording / reproducing apparatus described. - 前記記録層は、5nm以上、50nm以下の厚さを有することを特徴とする請求項１に記載の情報記録再生装置。 2. The information recording / reproducing apparatus according to claim 1, wherein the recording layer has a thickness of 5 nm or more and 50 nm or less.
- 前記導電性酸化物層は、0.5nm以上、10nm以下の厚さを有することを特徴とする請求項１に記載の情報記録再生装置。 2. The information recording / reproducing apparatus according to claim 1, wherein the conductive oxide layer has a thickness of 0.5 nm or more and 10 nm or less.
- 前記導電性酸化物層の電気抵抗率は、1x10-1Ωcm以下であることを特徴とする請求項１に記載の情報記録再生装置。 The information recording / reproducing apparatus according to claim 1, wherein an electrical resistivity of the conductive oxide layer is 1 × 10 −1 Ωcm or less.
- 前記情報記録再生装置は、プローブ型固体メモリ及びクロスポイント型固体メモリのうちの１つを構成することを特徴とする請求項１に記載の情報記録再生装置。 2. The information recording / reproducing apparatus according to claim 1, wherein the information recording / reproducing apparatus constitutes one of a probe type solid memory and a cross point type solid memory.
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| CN105552217A (en) * | 2014-10-30 | 2016-05-04 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and formation method thereof |
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| TWI396281B (en) | 2013-05-11 |
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