TWI396281B - Information recording and reproductive device - Google Patents

Description

Information recording and reproducing device

The present invention relates to an information recording and reproducing apparatus having a high recording density.

In recent years, small-sized portable devices have become more and more popular in the world, and with the rapid development of high-speed information transmission networks, the demand for small-sized and large-capacity non-volatile memories has rapidly expanded. Among them, NAND-type flash memory and small HDD (hard disk drive) have reached the rapid development of recording density, thus forming a vast market.

Under such circumstances, there have been several proposals for the concept of a new type of memory that significantly exceeds the recording density limit.

For example, PCRAM (phase change memory) uses a material that can obtain two states of an amorphous state (on) and a crystalline state (off) on the recording material, and uses the two states to correspond to the binary data. The principle of recording data with "0" and "1".

The writing/deleting is performed in an amorphous state by, for example, applying a large power pulse to a recording material, and a crystal state is produced by applying a small electric power pulse to the recording material.

The reading is performed by measuring the resistance of the recording material by flowing a reading current that does not cause a small degree of writing/deleting into the recording material. The resistance value of the recording material in the amorphous state is larger than the resistance value of the recording material in the crystalline state, and the ratio thereof is about 10 ³ .

The biggest advantage of PCRAM is that it can be operated even if the component size is reduced to 10 nm. In this case, since the recording density of about 10 Tbpsi (10 ¹² terabits per square inch) can be achieved, As a proposal for high recording density (for example, refer to T. Gotoh, K. Sugawara and K. Tanaka, Jpn. J. Appl. Phys., 43, 6B, 2004, L818).

In addition, there has been a report of a new type of memory which is different from PCRAM but has a very similar operating principle (for example, refer to A. Sawa, T. Fuji, M. Kawasaki and Y. Tokura, Appl. Phys. Lett., 85, 18, 4073 (2004)).

According to this report, a representative example of the recording material of the recorded data is nickel oxide, and in the same manner as the PCRAM, when writing/deleting, a large power pulse and a small power pulse are used. A report on the advantage that the power consumption at the time of writing/deleting is smaller than that of the PCRAM has been proposed in this case.

So far, although the mechanism of action of the novel memory has not yet been elucidated, reproducibility has been confirmed as another proposal for high recording density. In addition, even with the action mechanism, there are still several working groups trying to clarify.

In addition to this, there have been proposals for MEMS memory using MEMS (Micro Electro Mechanical Systems) technology (for example, see P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, W). .Haberle, MALants, HERothuizen, R. Stutz and GKBinnig, IEEE Trans. Nanotechnology 1, 39 (2002)).

In particular, a MEMS memory called Millipede has a structure in which a plurality of cantilevers in an array face the recording medium coated with an organic substance, and the probe at the tip of the cantilever contacts the recording medium with a moderate pressure.

The writing is performed by selectively controlling the temperature of the heater attached to the probe. That is, when the temperature of the heater is raised, the recording medium is softened, and the probe is caught in the recording medium to form a recess in the recording medium.

The reading is performed by flowing a current such that the recording medium does not soften into the probe and scanning the probe on the surface of the recording medium. When the probe falls into the recess of the recording medium, the temperature of the probe is lowered, and the resistance value of the heater is increased, so that the data can be sensed by reading the change in the resistance value.

For example, the maximum strength of the MEMS memory of Millipede is that it is not necessary to provide wiring in each recording portion of the recording bit data, so that the recording density can be greatly improved. The current status is that a recording density of 1 Tbpsi has been achieved (see, for example, P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, MALants, HERothuizen , R.Stutz, D.Wiesmann and GKBinnig, P.Bachtold, G. Cherubini, C.Hagleitner, T.Loeliger, A.Pantazi, H.Pozidis and E.Eleftheriou,in Technical Digest,IEDM03 pp.763-766 ).

In addition, the publication of Millipede has recently attempted to combine MEMS technology with novel recording principles to achieve significant improvements in power consumption, recording density, and speed of motion.

For example, there has been proposed a method of providing a ferroelectric layer in a recording medium and recording a material by applying a voltage to the recording medium to cause polarization of the dielectric in the ferroelectric layer. In this way, it is theoretically predicted that the interval (recording minimum unit) of the groups of the recording units of the recorded bit data can be approximated to the unit cell level of the crystal.

Assuming that the minimum unit of recording reaches one unit cell of the crystal of the ferroelectric layer, the recording density reaches a large value of about 4 Pbpsi (10 ¹⁵ bits/square inch).

Recently, the novel memory has been progressing toward practical use by using the SNDM (Scanning Type Non-Linear Dielectric Constant Microscope) reading method (for example, refer to A.Onoue, S.Hashimoto, Y.Chu, Mat). .Sci.Eng.B120, 130 (2005)).

The present invention provides a non-volatile information recording and reproducing apparatus with high recording density and low power consumption.

The information recording and reproducing apparatus of the present invention includes a recording layer that records two or more states of different resistivities, and a conductive oxide layer that is disposed when a voltage or a current is applied to the recording layer to change the state of the recording layer. At one end of the recording layer on the anode side, the resistivity of the conductive oxide layer is smaller than the minimum value of the resistivity of the recording layer, and the conductive oxide layer is selected from (i) selected from the group consisting of ZnO, SnO ₂ , CoO, and TiO _s ( a first material as a main component of 1≦s≦2), a group of In ₂ O ₃ , IrO ₂ , and RuO ₂ ; and (ii) selected from the group consisting of Ga ₂ O ₃ , Al ₂ O ₃ , Nb ₂ O ₅ , and SnO ₂ , a group of Ta ₂ O ₅ , Sb ₂ O ₃ , ZnO, TiO _s (1≦s≦2) and a mixture of the second materials of the dopant.

According to the present invention, a non-volatile information recording and reproducing apparatus with high recording density and low power consumption can be realized.

Hereinafter, the best mode for carrying out the examples of the present invention will be described in detail with reference to the drawings.

1. Summary

An information recording and reproducing apparatus according to an example of the present invention includes: a recording layer that records two or more states of different resistivities; and a recording layer that is disposed on the anode side when a voltage or a current is applied to the recording layer to change the state of the recording layer. A conductive oxide layer at one end.

The conductive oxide layer is disposed between the recording layer and the electrode, and the electrode is made of (i) selected from the group consisting of Ti-N, Ti-Si-N, Ta-N, Ta-Si-N, Si-N, Ti-. C, nitrides, carbides or oxides of materials of the group of Ta-C, Si-C; (ii) a mixture of nitrides and oxides of (i); (iii) nitrides and carbonization of (i) a mixture of the materials; (iv) a mixture of oxides and carbides of (i); or a mixture of (v) (i) nitrides, carbides and oxides.

The recording layer is selected from the group consisting of (1) A _x M _y X ₄ (0.1≦x≦2.2, 1.8≦y≦2), (2) A _x M _y X ₃ (0.5≦x≦1.1, 0.9≦y≦1) And (3) a material of a group of A _x M _y X ₄ (0.5≦x≦1.1, 0.9≦y≦1).

Among them, regarding (1) and (2), A is selected from the group consisting of Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag. Element of group of Au, Cd, Sn, Sb, Pt, Pd, Hg, Tl, Pb, Bi, M is selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, Ni Elements of the group of Nb, Ta, Mo, W, Ru, and Rh.

(3), A is an element selected from the group consisting of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, Tl, Pb, and Bi, M An element selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, and Os.

Regarding (1), (2), and (3), elements A and M are different from each other, and X is an element selected from the group of O and N.

The recording layer has a structure selected from the group consisting of 1. corundum structure, 2. rutile structure, 3. spinel structure, 4. ramsdellite structure, 5. anatase structure, 6. manganese strontite structure, 7 . brookite structure, 8. pyrolusite structure, 9. NaCl structure, 10. perovskite structure, 11. ilmenite structure, 12. crystal structure of the group of wolframite structures.

Here, typical examples of the corundum structure include Al ₂ O ₃ , Cr ₂ O ₃ , α-Fe ₂ O ₃ , α-GaO ₃ , Ti ₂ O ₃ , V ₂ O _{3 ,} and the like.

Examples of the rutile structure include TiO ₂ and SnO ₂ .

The temperate structure, the anatase structure and the deformation structure of the rutile structure of the ore-manganese structure. For example, the brookite structure forms orthorhombic crystals in the rutile structure.

The spinel structure is represented by MgAl ₂ O ₄ , and others include ZnFe ₂ O ₄ and ZnMnO ₃ . Cu ₂ Mg and Mn ₂ O ₃ also have a spinel structure. Ba ₂ Fe ₁₂ O ₁₉ and KFe ₁₁ O ₁₇ have a composite spinel structure.

The representative example of the manganese-niobium ore structure and the soft manganese ore structure is MnO ₂ , and the manganese-niobium ore structure has α-MnO ₂ and BiVO systems.

The ilmenite structure is exemplified by FeTiO ₃ .

There are also various deformation structures in the perovskite structure that has become famous for discovering high-temperature superconductors of oxides. Include, for example, BaTiO _3, CaTiO _3, GdFeO ₃ and the like.

The NaCl structure is exemplified by TiO, NiO, and the like. CuO can be understood as a modified version of the NaCl structure.

With respect to each of the above structures, the basic crystal structure may be skewed. For example, it may be a skewed spinel structure or a skewed NaCl structure. In the former case, a different name called a zinc-manganese structure (for example, ZnMn ₂ O ₄ ) is sometimes used, but it is referred to herein as a skewed spinel structure or a spinel structure alone.

The recording layer is composed of, for example, a composite compound containing one or two or more kinds of cationic elements, and at least one of the cationic elements contains a transition element which does not completely fill the d orbitals of electrons.

In order to stably change the resistivity (set/reset operation) of the recording layer and ensure reproducibility, the conductive oxide layer is applied to the recording layer by applying a voltage or current to change the state of the recording layer. One end of the recording layer on the anode side.

However, when a conductive oxide layer is added to the recording layer, the change in the resistivity of the conductive oxide layer becomes an unstable element of the setting/resetting operation.

Therefore, first, the resistivity of the conductive oxide layer is smaller than the minimum value of the resistivity of the recording layer. The conductive oxide layer preferably has no change in resistivity, but the resistivity of the conductive oxide layer is sufficiently smaller than the minimum value of the resistivity of the recording layer, even if the resistivity of the conductive oxide layer is set/reset by Change is no problem.

For example, the resistivity of the conductive oxide layer is 1 × 10 ^-1 Ωcm or less.

Further, the conductive oxide layer is composed of (i) a first material selected from the group consisting of ZnO, SnO ₂ , CoO, TiO _s (1≦s≦2), In ₂ O ₃ , IrO ₂ , and RuO ₂ as a main component; And (ii) a group selected from the group consisting of Ga ₂ O ₃ , Al ₂ O ₃ , Nb ₂ O ₅ , SnO ₂ , Ta ₂ O ₅ , Sb ₂ O ₃ , ZnO, TiO _s (1≦s≦2) It is composed of a mixture of the second materials of the objects.

Since the first material is a main component of the conductive oxide layer, and the second material is included as a dopant in the first material, the ratio of the second material in the conductive oxide layer is mass ratio (wt .%) is preferably 30 wt.% or less, 20 wt.% or less is suitable, and 5 wt.% or less is more suitable.

The main purpose of selecting such a material is that the conductive oxide layer does not become an unstable element of the set/reset operation.

Electrical conductivity is contained in a material containing a transition metal oxide as a main component, but the previously called energy band theory is not described as a strong phase relationship. The characteristics of the strong phase relationship are similar to those of semiconductors and the like which can be explained by the band theory. That is, the electrical properties, magnetic properties, dielectric properties, and the like of the material vary depending on the crystal structure, crystal grain size, alignment, impurities, and the like.

Therefore, the conductive oxide layer containing the transition metal oxide as a main component is stable in obtaining good device characteristics by controlling crystallinity such as crystal grain size and alignment property, and therefore it is effective to select the above materials.

Therefore, the material of the conductive oxide layer is in consideration of resistivity and controllability, adhesion to other films, diffusion prevention, heat resistance, etching property, gas and solution, chemical resistance, crystallinity, alignment, and These control options are chosen.

For example, a material doped with SnO ₂ in In ₂ O ₃ is known as ITO. Since ITO has a material having a low electrical resistivity, it is suitable to achieve a resistivity lower than that of the recording layer.

In addition, ZnO is known as a material that is easy to align. Therefore, when the lattice constant is close to or the crystal plane which is close to the lattice interval is present, it is predicted that a film having high alignment property is easily formed. However, since it is understood that the resistivity of ZnO is larger than that of ITO, and Zn is an element which is easily volatilized, simply using only ZnO causes Zn to diffuse into another film or Zn to be detached from the conductive oxide layer. Therefore, the problem of unstable resistivity and the like. In this case, when the second material is included as a dopant in the ZnO, such a problem can be eliminated.

Further, the material constituting the conductive oxide layer exhibits a composition only in a stoichiometric ratio, but the actual composition ratio may maintain the same crystal structure and electrical resistivity even if the composition ratio is changed by about 10%. For example, TiO _{s may be} in the range of TiO _s (1 ≦ s ≦ 2).

Further, the conductive oxide layer is preferably a group having (I) sphalerite structure, (II) wurtzite structure, (III) C-rare earth structure, (IV) rutile structure, (V) NaCl structure Crystal structure.

Further, the recording layer preferably has a thickness of 5 nm or more and 50 nm or less, and the conductive oxide layer preferably has a thickness of 0.5 nm or more and 10 nm or less.

2. Basic principles

The basic principle of the recording operation for the recording layer of the present invention will be described.

Hereinafter, the recording layer is described by taking one of two states in which the resistivity is different, and there are two types of ions.

The initial state of the recording layer is an insulator (high resistance state), for example, the resistivity is 10 ³ Ω. The state of cm. Then, by applying a potential difference across the recording layer, a part of the cation element existing inside the recording layer moves to the cathode (negative electrode) side.

As a result, when the recording layer is on the anode (positive electrode) side and the conductive oxide layer is on the cathode side, the cation element discharged from the recording layer is introduced into the conductive oxide layer, and the ratio of the cation element to the anion in the conductive oxide layer is higher. The ratio of elements is relatively large.

At the same time, in order to maintain electrical neutrality, the conductive oxide layer acquires electrons from the cathode, and the valence of the transition element in the conductive oxide layer is lowered, and as a result, a compound having a low oxidation state is formed.

Further, in the recording layer on the anode side, since the ratio of the cation element is relatively smaller than the ratio of the anion element, electrons are emitted to the anode to form a compound having a high oxidation state.

Thereby, the recording layer forms a low resistance state, for example, a resistivity of 10 ⁰ Ω is formed. The state of cm.

This is the setting action.

When a current is applied to the recording layer in a low-resistance state, a large current flows even with a low potential difference due to the low resistance, but the Joule heat generated at this time causes the temperature of the recording layer to rise.

The high-energy quasi-stable state that has been previously increased by the setting operation is returned to the low-energy stable insulator (high-resistance state) before the setting by the thermal energy.

This is a reset action.

Here, when the resistance of the recording layer described above changes, the resistivity of the conductive oxide layer does not change, but the resistivity of the conductive oxide layer is sufficiently smaller than the minimum value of the resistivity of the recording layer, even if the conductive oxide There is still no problem with the resistivity change of the layer.

In the information recording and reproducing apparatus including the conductive oxide layer of the present invention, the Pbpsi (10 ¹⁵ bit/square inch) level can be realized in principle, and the light interference resistance can be further improved.

3. Basic structure

Fig. 1 shows the construction of a recording unit which has been proposed before the present invention.

11-series electrode layer, 12-series recording layer, 13A-based electrode layer (or protective layer). A small open circle in the recording layer 12 represents a representative element as a diffusing ion, and a small solid circle represents a transition element as a cation. Further, a large open circle indicates a typical element as an anion.

When a voltage is applied to the recording layer 12 to cause a potential gradient in the recording layer 12, a part of the diffused ions moves in the crystal. Therefore, in the example of the present invention, the initial state of the recording layer 12 is used as an insulator (high resistance state), and regarding the information recording, the recording layer 12 is phase-changed by the potential gradient, and the recording layer 12 is kept conductive (low resistance state). ) proceed.

Here, the present specification defines a high resistance state as a reset state and a low resistance state as a set state. However, this definition is for the sake of simplicity of the following description, depending on the choice of material and the manufacturing method, as opposed to the definition, that is, the low resistance state is reset (initial) state, and the high resistance state is set state. . In other words, even such a case is of course included in the scope of the present invention.

First, for example, a state in which the potential of the electrode layer 13A is lower than the potential of the electrode layer 11 is made. When the electrode layer 11 has a fixed potential (for example, a ground potential), a negative potential may be applied to the electrode layer 13A.

At this time, a part of the diffused ions in the recording layer 12 is moved to the electrode layer (cathode) 13A side, and the diffused ions in the recording layer (crystal) 12 are less dependent on the anion. The diffusion ions that have moved to the electrode layer 13A side acquire electrons from the electrode layer 13A, and are deposited as a metal to form the metal layer 14.

The anion is excessive inside the recording layer 12, and as a result, the valence of the transition element ions in the recording layer 12 is increased. In other words, since the recording layer 12 has electron conductivity by the implantation of the carrier, the information recording (setting operation) is completed.

Regarding information reproduction, it is easily performed by flowing a current pulse into the recording layer 12 and detecting the resistance value of the recording layer 12. However, the current pulse needs to be a small value that does not cause the phase change of the material constituting the recording layer 12.

The above process is an electrical decomposition, and it is considered that the electrode layer (anode) 11 side is oxidized by electrochemical oxidation, and the electrode layer (cathode) 13A side is electrochemically reduced to produce a reducing agent.

Therefore, when the state of the information recording (low resistance state) is returned to the initial state (high resistance state), for example, the recording layer 12 is heated by Joule by a large current pulse to promote the oxidation-reduction reaction of the recording layer 12. That is, the recording layer 12 returns to the insulator by resetting the residual heat after the large current pulse (reset operation).

However, when the operation principle is put into practical use, it is necessary to confirm that the reset operation is not performed at room temperature (ensure that the storage time is sufficiently long) and the power consumption of the reset operation is sufficiently small.

For the former, it is possible to reduce the coordination number of the diffusion ions (preferably 2 or less), or to form the valence of 2 or more, or to increase the valence of the anion (ideally 3 or more).

Further, in the latter case, it is necessary to find a material which has a valence of diffused ions of 2 or less and a moving path of a plurality of diffused ions moving in the recording layer (crystal) 12 in order to prevent crystal damage.

Such a recording layer 12 can be realized by the elements and crystal structures already described.

Next, since an oxidizing agent is generated on the electrode layer (anode) 11 side after the setting operation, the electrode layer 11 is preferably made of a material that is not easily oxidized (for example, an electrically conductive nitride or an electrically conductive oxide).

Further, the electrode layer 11 may be composed of a material that does not have ion conductivity.

Such a material is as follows, and LaNiO ₃ may be referred to as an optimum material from the viewpoint of comprehensive performance such as a good electrical conductivity.

. MN

M contains at least one element selected from the group consisting of Ti, Zr, Hf, V, Nb, and Ta. N series nitrogen.

. MO _x

M comprises a group selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt At least 1 element. The molar ratio x is equal to 1≦x≦4.

. AMO ₃

A contains at least one element selected from the group consisting of La, K, Ca, Sr, Ba, and Ln (steroidal elements).

M comprises a group selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt At least 1 element.

O system oxygen.

. B ₂ MO ₄

B contains at least one element selected from the group consisting of K, Ca, Sr, Ba, and Ln (steroidal elements).

M comprises a group selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt At least 1 element.

O system oxygen.

Further, since the reducing agent is generated on the electrode layer (cathode) 13A side after the setting operation, the electrode layer 13A should preferably maintain the function of preventing the recording layer 12 from reacting with the air.

Such materials include, for example, amorphous carbon, diamond-like carbon, and semiconductors such as SnO ₂ .

The electrode layer 13A may also function as a protective layer for protecting the recording layer 12, and a protective layer may be provided instead of the electrode layer 13A. In this case, the protective layer may be an insulator or an electrical conductor.

Fig. 2 shows the construction of a recording unit of an example of the present invention.

11-series electrode layer, 12-series recording layer, 13A-based electrode layer (or protective layer), and 15-series conductive oxide layer (Conductive oxide layer). A small open circle in the recording layer 12 indicates a typical element as a diffused ion, and a small solid circle indicates a transition element as a cation. Further, a large open circle indicates a typical element as an anion.

This structure is different from the structure of FIG. 1 which has been proposed in the present invention. When a voltage or a current is applied to the recording layer 12 and the state of the recording layer 12 is changed, specifically, when the setting operation is performed, the anode side is formed. A point of the conductive oxide layer 15 is disposed at one end of the recording layer 12.

Since the setting/reset operation and the material are the same as those in the case of FIG. 1, the description thereof is omitted here.

The conductive oxide layer 15 may also contain a cavity cite. The void portion is a portion that accommodates the cationic element that has moved from the recording layer 12.

When the conductive oxide layer 15 contains a void portion, the effect of smoothly moving ions in the recording layer 12 is exhibited, and by adjusting the composition range of the conductive oxide layer 15, the electron conductivity of the recording layer 12 is ensured. The stability of the crystalline structure. As a result, the interference resistance of the recording layer 12 is improved.

Further, an insulator having a thickness of a few nanometers of the permeability of the ions discharged from the recording layer 12 may be inserted between the recording layer 12 and the conductive oxide layer 15. The insulator is composed of a compound or a composite compound containing at least an ionic element discharged from the recording layer 12 and a typical element other than the ionic element. Thereby, the on-resistance of the recording portion is lowered.

Figure 3 shows the construction of Figure 2.

For example, two states of different resistivities are recorded in the recording layer 12.

The ρrr is the resistivity of the recording layer 12 in the reset state (high resistance state), and the resistivity of the recording layer 12 in the ρrs-set state (low resistance state). Further, the ρor-based recording layer 12 has a resistivity of the conductive oxide layer 15 in the reset state, and the resistivity of the conductive recording layer 15 when the ρ-based recording layer 12 is in the set state.

Ρos<<ρrs<ρrr, ρor<<ρrs<ρrr.

Fig. 4 is a modification of the structure of Fig. 3.

For example, two states of different resistivities are recorded in the recording layers 12-1 and 12-2, respectively. Further, a conductive oxide layer 15 is added to an end portion on the anode side of the recording layer 12-1, and a conductive oxide layer 15 is also added to an end portion on the anode side of the recording layer 12-2.

The threshold value of the state change of the recording layer 12-1 and the threshold value of the state change of the recording layer 12-2 are set to values different from each other, and multi-level recording is possible.

Ρrr1 is the resistivity of the recording layer 12-1 in the reset state (high resistance state), and the resistivity of the recording layer 12-1 in the set state (low resistance state) of ρrs1. Ρrr2 is the resistivity of the recording layer 12-2 in the reset state (high resistance state), and the resistivity of the recording layer 12-2 in the ρrs2 set state (low resistance state).

The resistivities ρor and ρos of the conductive oxide layer 15 are sufficiently smaller than the resistivities ρrr1, ρrs1, ρrr2, and ρrs2 of the recording layers 12-1 and 12-2.

Fig. 5 is also a modification of the configuration of Fig. 3.

For example, two states of different resistivities are recorded in the recording layers 12-1 and 12-2, respectively. Further, a conductive oxide layer 15 is disposed between the electrode layer 11 as an anode and the recording layer 12-1.

The threshold value of the state change of the recording layer 12-1 and the threshold value of the state change of the recording layer 12-2 are set to values different from each other, and can be recorded in multiple values.

Ρrr1 is the resistivity of the recording layer 12-1 in the reset state (high resistance state), and the resistivity of the recording layer 12-1 in the set state (low resistance state) of ρrs1. Ρrr2 is the resistivity of the recording layer 12-2 in the reset state (high resistance state), and the resistivity of the recording layer 12-2 in the ρrs2 set state (low resistance state).

The resistivities ρor and ρos of the conductive oxide layer 15 are sufficiently smaller than the resistivities ρrr1, ρrs1, ρrr2, and ρrs2 of the recording layers 12-1 and 12-2.

4. Implementation

Secondly, the best embodiments are considered to be explained.

Hereinafter, the case where the example of the present invention is applied to a probe type solid memory and the case where it is applied to a cross-point type solid memory will be described.

(1) Probe type solid memory A. Construction

6 and 7 show a probe type solid memory of an example of the present invention.

The electrode layer 21 is disposed on the semiconductor substrate 20, and the recording portion 22 including the data region and the servo region is disposed on the electrode layer 21. The recording unit (recording medium) 22 is composed of, for example, the recording layer 12 and the conductive oxide layer 15 shown in FIG. 2 . The recording unit 22 is formed integrally at the central portion of the semiconductor substrate 20.

The servo area is disposed along the edge of the semiconductor substrate 20.

The data area and the servo area are composed of several blocks. In the data area and the servo area, a plurality of probes 24 are arranged corresponding to a plurality of blocks. Each of the plurality of probes 24 has a sharpened shape.

A plurality of probes 24 constitute a probe array and are formed on one surface side of the semiconductor substrate 23. A plurality of probes 24 can be easily formed on one surface side of the semiconductor substrate 23 by using MEMS technology.

The position of the probe 24 in the data area is controlled by the servo burst signal read from the servo area. Specifically, the semiconductor substrate 20 is moved back and forth in the X direction by the driver 27, and the access operation is performed by controlling the position of the plurality of probes 24 in the Y direction.

Further, the recording medium may be formed independently of each of the blocks, and the recording medium such as a hard disk may be rotated in a circular shape, and each of the plurality of probes 24 may be moved in the radial direction of the recording medium, for example, in the X direction.

The plurality of probes 24 each have a function as a recording/deleting head and a function as a reproducing head. When the multiplex drives 25 and 26 record, reproduce, and delete, a predetermined voltage is supplied to the plurality of probes 24.

B. Recording/regeneration action

The recording/reproduction operation of the probe type solid memory of Figs. 6 and 7 will be described.

Figure 8 shows the recording action (setting action).

A recording portion (recording medium) 22 is formed on the electrode layer 21 on the semiconductor wafer 20. The recording unit 22 is covered by the protective layer 13B.

The information recording is performed by applying a voltage pulse to the recording unit 30 of the recording unit (recording medium) 22 by bringing the tip end of the probe 24 into contact with the surface of the protective layer 13B, and causing a potential gradient to occur in the recording unit 30 of the recording unit 22. . In this example, the potential of the probe 24 is made lower than the potential of the electrode layer 21. When the electrode layer 21 has a fixed potential (for example, a ground potential), a negative potential may be applied to the probe 24.

The voltage pulse can be generated, for example, by using an electron generating source or a hot electron source, or by emitting electrons from the probe 24 to the electrode layer 21.

At this time, for example, as shown in FIG. 9, one portion of the recording unit 30 of the recording layer 12, which is one of the diffused ions, moves to the side of the probe (cathode) 24, and the relative value of the diffused ions in the crystal to the anion is reduced. Further, the diffused ions that have moved to the side of the probe 24 take electrons from the probe 24 and are precipitated as a metal.

In the recording unit 30 of the recording layer 12, the anion is excessive, and as a result, the valence of the transition element ions remaining in the recording layer 12 is increased. In other words, since the recording unit 30 of the recording layer 12 has electron conductivity by the implantation of the phase-changing carrier, the information recording (setting operation) is completed.

Further, the voltage pulse for information recording may be generated by making the potential of the probe 24 relatively higher than the potential of the electrode layer 21.

When the probe type solid memory of the present embodiment is used, information recording can be performed in the recording unit 30 of the recording medium as in the case of the hard disk, and the memory of the hard disk and the semiconductor can be realized by using the new recording material. Recording density of body height.

Figure 10 shows the regeneration action.

The reproducing operation is performed by flowing a voltage pulse into the recording unit 30 of the recording layer 12 and detecting the resistance value of the recording unit 30 of the recording layer 12. However, the voltage pulse is a small value that does not cause a phase change in the material constituting the recording unit 30 of the recording layer 12.

For example, the read current generated by the sense amplifier S/A flows from the probe 24 into the recording unit 30 of the recording layer 12, and the resistance value of the recording unit 30 is measured by the sense amplifier S/A. When using the new material already described, the ratio of the resistance of the high resistance state to the low resistance state ensures more than 10 ³ .

Further, the reproducing operation can be continuously reproduced by scanning the probe 24 on the recording medium.

The deletion (reset) operation is performed by heating the recording unit of the recording layer 12 by 30 Joules by a large current pulse to promote the oxidation-reduction reaction of the recording layer 12 in the recording unit 30. Alternatively, it may be performed by applying a voltage pulse opposite to the set time to the recording layer 12.

The deletion operation may also be performed by each recording unit 30, or may be performed by a plurality of recording units 30 or block units.

C. Summary

When such a probe type solid memory is used, recording density and low power consumption higher than current hard disk and flash memory can be achieved.

(2) Cross-point solid memory A. Construction

Fig. 11 shows a cross-point type solid memory of an example of the present invention.

The word lines WL _i-1 , WL _i , and WL _i+1 extend in the X direction, and the bit lines BL _j-1 , BL _j , and BL _j+1 extend in the Y direction.

One of the word lines WL _i-1 , WL _i , WL _i+1 is connected to the word line driver & decoder 31 via the MOS transistor RSW as a selection switch, and the bit lines BL _j-1 , BL _j , BL _{j+ One} of the terminals ₁ is connected to the bit line driver & decoder & readout circuit 32 via the MOS transistor CSW as a selection switch.

A selection signal R _i-1 , R _i , R _i+1 for selecting one word line (row) is input to the gate of the MOS transistor RSW, and one bit is selected on the gate of the MOS transistor CSW. The line (column) is used to select signals C _j-1 , C _j , C _j+1 .

The memory cell 33 is disposed at an intersection of the word lines WL _i-1 , WL _i , WL _i+1 and the bit lines BL _j-1 , BL _j , and BL _j+1 . The so-called cross-point cell array structure. A diode 34 for preventing a sneak current during recording/regeneration is added to the memory cell 33.

Fig. 12 is a view showing the configuration of a memory cell array portion of the cross-point type solid memory of Fig. 11.

Word lines WL _i-1 , WL _i , WL _i+1 and bit lines BL _j-1 , BL _j , and BL _j+1 are disposed on the semiconductor wafer 30, and memory cells 33 are disposed at intersections of the wirings. Diode 34.

The characteristic point of such a cross-point cell array structure is that the memory cell 33 does not need to be individually connected to the MOS transistor, so that it is advantageous for high integration. For example, as shown in FIGS. 13 and 14, the memory cells 33 may be stacked to form a three-dimensional structure of the memory cell array.

For example, as shown in FIG. 15, the memory cell 33 is composed of a recording layer (Recording layer) 12, a conductive oxide layer 15 and a protective layer 13B. The memory of one bit or more is memorized by one memory cell 33. Further, the diode 34 is disposed between the word line WL _i and the memory cell 33.

Further, at least one barrier metal may be disposed between the word line WL _i and the diode 34 and between the protective layer 13B and the bit line BL _j . Further, the diode 34 should be omitted when the setting/resetting operation is performed only by the direction of the voltage.

B. Recording/regeneration action

The recording/reproduction operation will be described with reference to FIGS. 11 , 12 and 15 .

Here, the memory cell 33 surrounded by the broken line A is selected, and the recording/reproduction operation is performed there.

The information recording (setting operation) is performed by applying a voltage to the selected memory cell 33, so that the potential gradient occurs in the memory cell 33, and the current pulse is allowed to flow. Therefore, for example, the potential of the word line WL _i is made to be larger than the bit line BL. The state in which the potential of _j is relatively low. When the bit line BL _j is a fixed potential (for example, a ground potential), a negative potential may be applied to the word line WL _i .

At this time, in the recording layer 12 of the selected memory cell 33 surrounded by the broken line A, one of the diffused ions is moved to the word line (cathode) WL _i side, and the diffused ions in the recording layer 12 are reduced in relative reactivity with respect to the anion. Furthermore, diffusion of the ions move to the side of the word line WL _i to obtain an electron from the word line WL _i, precipitated as the metal.

The recording layer 12 of the selected memory cell 33 surrounded by the broken line A has an excess of anions, and as a result, the valence of the transition element ions in the recording layer 12 is increased. In other words, the selected memory cell 33 surrounded by the broken line A has electron conductivity by the implantation of the phase-changing carrier, so that the information recording (setting operation) is completed.

In addition, in the information recording, the unselected word lines WL _i-1 , WL _i+1 and the unselected bit lines BL _j-1 and BL _{j+1 are} all biased to the same potential in advance.

In addition, in the standby state before the information recording, all the word lines WL _i-1 , WL _i , WL _i+1 and all the bit lines BL _j-1 , BL _j , BL _{j+1 should} be precharged.

Further, the voltage pulse for information recording may be generated by making the potential of the word line WL _i relatively higher than the potential of the bit line BL _j .

The deletion (reset) operation uses the Joule heat generated by the inflow of the large current pulse in the selected memory cell 33 and the residual heat thereof, so that, for example, the potential of the word line WL _i is higher than the potential of the bit line BL _j . . When the bit line BL _j is a fixed potential (for example, a ground potential), a positive potential may be applied to the word line WL _i .

At this time, one of the cations is moved to the recording layer 12 of the selected memory cell 33 surrounded by the broken line A. Therefore, the valence of the cation (transition element) in the conductive oxide layer 15 is increased, and the valence of the cation (transition element) in the recording layer 12 is reduced.

As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset action (deletion) is completed.

Here, the deletion operation can also be performed by the following method.

However, in this case, as described above, it is preferable to remove the diode 34 from the semiconductor memory of Figs. 11, 12, and 15.

For example, the potential of the word line WL _i is lowered relative to the potential of the bit line BL _j . When the bit line BL _j is a fixed potential (for example, a ground potential), a negative potential may be applied to the word line WL _i .

At this time, the selected memory cell 33 surrounded by the broken line A moves a part of the cation in the conductive oxide layer 15 into the recording layer 12. Therefore, the valence of the cation (transition element) in the conductive oxide layer 15 is increased, and the valence of the cation (transition element) in the recording layer 12 is reduced.

As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset action (deletion) is completed.

In addition, when deleting, the unselected word lines WL _i-1 and WL _i+1 and the unselected bit lines BL _j-1 and BL _{j+1 are} all biased to the same potential in advance.

Further, in the standby state before deletion, it is preferable to precharge all the word lines WL _i-1 , WL _i , WL _i+1 and all the bit lines BL _j-1 , BL _j , BL _j+1 .

The read operation is performed by flowing a current pulse into the selected memory cell 33 surrounded by the broken line A, and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a small value to the extent that the material constituting the memory cell 33 does not cause a change in resistance.

For example, by the occurrence of the readout circuit current (pulse current) flows _J of the memory cell is surrounded by a broken line A 33, measured by readout circuitry 33 of the resistance value of the memory cell from the bit line BL. When using the new material already described, the difference in the resistance value of the set/reset state ensures 10 ³ or more.

C. Summary

When such a cross-point type solid memory is used, recording density and low power consumption higher than current hard disk and flash memory can be achieved.

(3) Others

In the present embodiment, two types of probe type solid memory and cross-point type solid memory are described. However, the materials and principles proposed by the examples of the present invention can be applied to current recording media such as hard disks and DVDs.

5. Application to flash memory (1) Construction

The examples of the present invention are also applicable to flash memory.

Figure 16 shows the memory cells of the flash memory.

The memory cells of the flash memory are composed of MIS (Metal Insulator Semiconductor) transistors.

A diffusion layer 42 is formed on a surface region of the semiconductor substrate 41. A gate insulating layer 43 is formed on the channel region between the diffusion layers 42. A recording portion (ReRAM: Resistive RAM) 44 of the present invention is formed on the gate insulating layer 43. A control gate electrode 45 is formed on the recording portion 44.

The semiconductor substrate 41 may also be a well region, and further, the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types. The gate electrode 45 is controlled to be a word line, and is made of, for example, a conductive polysilicon.

The recording unit 44 is configured by, for example, the recording layer 12 and the conductive oxide layer 15 of FIG. 2 .

(2) Basic actions

The basic operation will be described using FIG. The setting (writing) operation is performed by applying the potential V1 to the control gate electrode 45 and applying the potential V2 to the semiconductor substrate 41.

The difference between the potentials V1 and V2 is required to be sufficient for the phase change or the resistance change of the recording portion 44, but the direction thereof is not particularly limited.

That is, any of V1>V2 and V1<V2 can be used.

For example, in the initial state (reset state), when the recording portion 44 is an insulator (large resistance), since the gate insulating layer 43 is substantially thick, the threshold value of the memory cell (MIS transistor) is improved.

When the potentials V1 and V2 are given from this state and the recording portion 44 is changed to a conductor (small resistance), since the gate insulating layer 43 is substantially thinned, the threshold value of the memory cell (MIS transistor) is lowered.

Further, the potential V2 is applied to the semiconductor substrate 41. Alternatively, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell.

The reset (deletion) operation is performed by applying the potential V1' to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 (<V3) to the other of the diffusion layers 42.

The potential V1' is a value of a threshold value of the memory cell exceeding the set state.

At this time, the memory cell is turned on, electrons flow from the other direction of the diffusion layer 42, and hot electrons occur. Since the hot electrons are implanted in the recording portion 44 via the gate insulating layer 43, the temperature of the recording portion 44 rises.

As a result, since the recording portion 44 changes from the conductor (small resistance) to the insulator (the resistance is large), the gate insulating layer 43 is substantially thicker, and the threshold value of the memory cell (MIS transistor) is improved.

Thus, since the threshold of the memory cell can be changed by a principle similar to that of the flash memory, the information recording and reproducing apparatus of the example of the present invention can be put to practical use by the technique of the flash memory.

(3) NAND type flash memory

Figure 17 shows a circuit diagram of a NAND cell. Fig. 18 shows the construction of a NAND cell unit of an example of the present invention.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NAND cell unit of the example of the present invention is formed in the P-type well region 41c.

The NAND cell is composed of a NAND string including a plurality of memory cells MC connected in series, and a total of two selected gate transistors ST connected to both ends thereof.

The memory cell MC and the selective gate transistor ST have the same configuration. Specifically, the gate insulating layer 43 on the channel region between the N-type diffusion layer 42 and the N-type diffusion layer 42 and the recording portion (ReRAM) 44 on the gate insulating layer 43 and the recording portion 44 are provided. The gate electrode 45 is controlled to be constructed.

The state (insulator/conductor) of the recording portion 44 of the memory cell MC can be changed by the above basic operation. Further, the recording portion 44 for selecting the gate transistor ST is fixed to a set state, that is, fixed to a conductor (small resistance).

One of the selection gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.

All memory cells in the NAND cell form a reset state (high resistance) before the set (write) operation.

The setting (writing) operation is sequentially performed from the memory cell MC on the source line SL side to the memory cell on the bit line BL side.

V1 (positive potential) is applied as a write potential to the selected word line (control gate electrode) WL, and Vpass is applied to the unselected word line WL as a transfer potential (potential at which the memory cell MC is turned on).

The selection gate transistor ST on the source line SL side is turned off, the selection gate transistor ST on the bit line BL side is turned on, and the program data is transferred to the channel region of the memory cell MC selected from the bit line BL.

For example, when the program data is "1", the write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording portion 44 of the selected memory cell MC is not high. Change to a low state.

Further, when the program data is "0", V2 (<V1) is transferred to the channel area of the selected memory cell MC, and the resistance value of the recording portion 44 of the selected memory cell MC is changed from the high state to the low state.

The reset (delete) operation, for example, assigns V1' to all of the word lines (control gate electrodes) WL, and turns on all of the memory cells MC in the NAND cell. Further, two selection gate transistors ST are turned on, V3 is supplied to the bit line BL, and V4 (<V3) is supplied to the source line SL.

At this time, since the hot electrons are implanted in the recording unit 44 of all the memory cells MC in the NAND cell, the reset operation is performed on all the memory cells MC in the NAND cell.

In the read operation, a read potential (positive potential) is applied to the selected word line (control gate electrode) WL, and no data is set to "0" or "1" in the unselected word line (control gate electrode) WL. The memory cell MC must be turned on.

Further, two selection gate transistors ST are turned on, and a read current is supplied in the NAND string.

When the read potential is applied to the selected memory cell MC, it is turned on or off depending on the data value stored therein, so that the data can be read, for example, by detecting a change in the read current.

In addition, the structure selection gate transistor ST of FIG. 18 has the same structure as the memory cell MC, but as shown in FIG. 19, for example, the gate transistor ST may be selected or the recording portion (recording layer and conductive oxide layer) may not be formed. And as a normal MIS transistor.

Fig. 20 is a modification of the NAND type flash memory.

This modification is characterized in that the gate insulating layer constituting the plurality of memory cells MC of the NAND string is replaced with the P-type semiconductor layer 47.

When the high memory is progressing and the memory cell MC is made fine, the P-type semiconductor layer 47 is filled with the depletion layer in a state where no voltage is applied.

At the time of setting (writing), a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and a positive transfer potential is given to the control gate electrode 45 of the unselected memory cell MC. (eg 1 V).

At this time, the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from the P-type to the N-type to form a channel.

Therefore, as described above, when the selection gate transistor ST on the bit line BL side is turned on, and the program data "0" is transferred to the channel region of the memory cell MC selected from the bit line BL, the setting operation can be performed.

Resetting (deleting), for example, a negative erasing potential (for example, -3.5 V) is applied to all of the control gate electrodes 45, and a ground potential (0 V) is applied to the P-type well region 41c and the P-type semiconductor layer 47. All of the memory cells MC constituting the NAND string are performed together.

At the time of reading, a positive read potential (for example, 0.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the data is set to "0" in the control gate electrode 45 of the unselected memory cell MC. , "1", the transfer potential (for example, 1 V) at which the memory cell MC must be turned on.

However, the threshold voltage Vth "1" of the memory cell MC in the "1" state is within the range of 0 V < Vth "1" < 0.5 V, and the threshold voltage Vth of the memory cell MC of the "0" state " 0" is in the range of 0.5 V < Vth "0" < 1 V.

Further, two selection gate transistors ST are turned on to supply a read current to the NAND string.

When such a state is formed, since the amount of current flowing into the NAND string changes depending on the data value stored in the selected memory cell MC, the data can be read by detecting the change.

Further, in this modification, it is preferable that the P-type semiconductor layer 47 has more hole doping amount than the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is deeper than the Fermi level of the P-type well region 41c. 0.5 V level.

When a positive potential is applied to the control gate electrode 45, the surface portion of the P-type well region 41c between the N-type diffusion layers 42 is inverted from the P-type to the N-type to form a channel.

Thereby, for example, when writing, the channel of the unselected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and when read, the channels of the plurality of memory cells MC in the NAND string are formed only. The interface between the P-type well region 41c and the P-type semiconductor layer 47.

In other words, even if the recording portion 44 of the memory cell MC is a conductor (set state), the diffusion layer 42 and the control gate electrode 45 are not short-circuited.

(4) NOR type flash memory

Figure 21 shows a circuit diagram of a NOR cell unit. Fig. 22 shows the construction of a NOR cell unit of an example of the present invention.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NOR cell of the example of the present invention is formed in the P-type well region 41c.

The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.

The memory cell MC is composed of a gate insulating layer 43 on the channel region between the N-type diffusion layer 42 and the N-type diffusion layer 42, a recording portion (ReRAM) 44 on the gate insulating layer 43, and a control gate electrode on the recording portion 44. 45 constitutes.

The state (insulator/conductor) of the recording portion 44 of the memory cell MC can be changed by the above-described basic operation.

(5) 2tr type flash memory

Figure 23 shows a circuit diagram of a 2tr-cell unit. Fig. 24 shows the construction of a 2tr-cell unit of an example of the present invention.

The 2tr-cell unit has recently developed a new cell structure that combines the characteristics of a NAND cell unit with the characteristics of a NOR cell.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A 2tr-cell unit of the example of the present invention is formed in the P-type well region 41c.

The 2tr-cell unit is composed of one memory cell MC connected in series and one selective gate transistor ST.

The memory cell MC and the selective gate transistor ST have the same configuration. Specifically, the gate insulating layer 43 on the channel region between the N-type diffusion layer 42 and the N-type diffusion layer 42 and the recording portion (ReRAM) 44 on the gate insulating layer 43 are in the recording portion 44. The upper gate electrode 45 is controlled.

The state (insulator/conductor) of the recording portion 44 of the memory cell MC can be changed by the above-described basic operation. Further, the recording portion 44 for selecting the gate transistor ST is fixed to a set state, that is, fixed to a conductor (small resistance).

The gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.

The state (insulator/conductor) of the recording portion 44 of the memory cell MC can be changed by the above-described basic operation.

The structure of FIG. 24 selects the gate transistor ST having the same structure as the memory cell MC. However, as shown in FIG. 25, for example, the gate transistor ST may not be formed, and the recording portion (recording layer and conductive oxide layer) may not be formed. The usual MIS transistor is formed.

6. Embodiments

Several samples are prepared to illustrate an embodiment in which the resistance difference between the reset (deleted) state and the set (write) state is evaluated.

The sample system uses the system of Fig. 8, and the recording portion 22 includes the structure of the structure of Fig. 2 (recording layer 12 and conductive oxide layer 15).

Evaluate probe pairs that are sharpened to a depth of 10 nm using the tip diameter.

The probe pair is brought into contact with the protective layer 13B, and one of the information recording (writing/deleting) is performed. The writing is performed by, for example, applying a voltage pulse of 10 nsec and 1 V in the recording unit 22. The deletion is performed by, for example, applying a voltage pulse of 100 nsec and 0.2 V in the recording section 22. Alternatively, the DC evaluation can be performed as a semiconductor parameter analyzer. Further, in the interval of writing/deleting, the other one of the probe pairs is used for reading. The reading is performed by applying a voltage pulse of 10 nsec and a voltage of 0.1 V to the recording unit 22, and measuring the resistance value of the recording unit (recording bit) 22.

(1) First Embodiment

The specifications of the sample of the first embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of Zn _1.1 Mn _1.9 O ₄ . The conductive oxide layer 15 is doped with 2 wt.% of Ga ₂ O ₃ ZnO in three thicknesses (0.5 nm, 5 nm, 10 nm). The amount of dopant of the conductive oxide layer (ZnO) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

In this case, since the element is difficult to diffuse between the recording layer 12 and the conductive oxide layer 15, the properties such as heat resistance, environmental resistance, and durability are improved. Further, the crystallinity of the recording layer 12 is improved, and variations between components and variations between batches are greatly reduced.

In addition, in all the samples, thousands of rewrite operations can be performed.

This indicates that the atomic energy level change of the element between the recording layer 12 and the layer in contact with the recording layer 12 and the segregation inside the recording layer 12 is small, or it is applied to the direction of the offset.

The material of the electrode layer 21 is four kinds of TiN, TiSiN, TaN, and TaSiN.

Further, SiN, TiC, TaC, SiC, or the like is also suitable as the electrode layer 21. Metal materials such as Pt, Ru, and Ir are not suitable as the material of the electrode layer 21 because of their high cost.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

A summary of these is shown in Table 1.

As is apparent from Table 1, the set/reset voltage hardly depends on the thickness of the conductive oxide layer 15. This makes it difficult to completely match the impedance, and the measurement error due to ringing is about 10%. In other words, it can be estimated that the influence of the thickness of the conductive oxide layer 15 on the setting/resetting voltage is about 10%.

(2) Second embodiment

The specifications of the sample of the second embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of Zn _1.1 Mn _2.0 O ₄ . The conductive oxide layer 15 is made of ZnO doped with 2.5 wt.% of Al ₂ O ₃ in three thicknesses (0.5 nm, 5 nm, 10 nm). The amount of dopant of the conductive oxide layer (ZnO) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(3) Third embodiment

The specifications of the sample of the third embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of ZnCo ₂ O ₄ . The conductive oxide layer 15 is available in three thicknesses (0.5 nm, 5 nm, 10 nm) in terms of CoO.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(4) Fourth embodiment

The specifications of the sample of the fourth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of TiZn ₂ O ₄ . The conductive oxide layer 15 is doped with 1 wt.% of Nb ₂ O ₅ TiO _{2 in} three thicknesses (0.5 nm, 5 nm, 10 nm). The amount of dopant of the conductive oxide layer (TiO ₂ ) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(5) Fifth embodiment

The specifications of the sample of the fifth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of ZnMnO ₃ . The conductive oxide layer 15 is made of three kinds of thickness (0.5 nm, 5 nm, 10 nm) of SnO ₂ doped with 1 wt.% of Sb ₂ O ₃ . The amount of dopant of the conductive oxide layer (SnO ₂ ) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(6) Sixth embodiment

The specifications of the sample of the sixth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of TiZn ₂ O _3.8 . The conductive oxide layer 15 is doped with 1 wt.% of TiO ₂ and ZnO of In ₂ O _{3 in} three thicknesses (0.5 nm, 5 nm, 10 nm). The amount of dopant of the conductive oxide layer (In ₂ O ₃ ) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(7) Seventh embodiment

The specifications of the sample of the seventh embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of ZnMoO ₃ . The conductive oxide layer 15 is made of three kinds of thickness (0.5 nm, 5 nm, 10 nm) of IrO ₂ doped with 1 wt.% of ZnO. The amount of dopant of the conductive oxide layer (IrO ₂ ) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(8) Eighth Embodiment

The specifications of the sample of the eighth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of ZnFe ₂ O ₄ . The conductive oxide layer 15 is made of three kinds of thickness (0.5 nm, 5 nm, 10 nm) of RuO ₂ doped with 1 wt.% of ZnO. The amount of dopant of the conductive oxide layer (ZnO) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(9) Ninth Embodiment

The specifications of the sample of the ninth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of Mn ₃ O ₄ . The conductive oxide layer 15 is provided with three thicknesses (0.5 nm, 5 nm, 10 nm) of ZnO doped with 2.6 wt.% of A123. The amount of dopant of the conductive oxide layer (ZnO) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(10) Tenth Embodiment

The specifications of the sample of the tenth embodiment are as follows.

The recording layer 12 is provided with three thicknesses (10 nm, 20 nm, 50 nm) in terms of Mn _2.9 O ₄ . The conductive oxide layer 15 is doped with 1.1 wt.% of Nb ₂ O ₅ TiO _{2 in} three thicknesses (0.5 nm, 5 nm, 10 nm). The amount of dopant of the conductive oxide layer (ZnO) 15 is determined in consideration of the resistivity and a small voltage drop occurring when the recording layer 12 is stacked.

The description of the effect of the conductive oxide layer 15 and the material of the electrode layer 21 is the same as that of the first embodiment, and thus the description thereof is omitted here.

When the unipolar operation is obtained, the reset voltage is +0.5~+0.8 V, and the set voltage is +1.5~1.7 V. In addition, it is confirmed that the reset voltage for bipolar operation is +1~+1.3 V, and the set voltage is -2.5~-2.7 V.

This result is the same as that of the first embodiment. The thickness of the conductive oxide layer 15 hardly affects the setting/resetting voltage, and is also the same as in the first embodiment.

(9) Comparative example

The specifications of the samples of the comparative examples are as follows.

The recording layer 12 is Fe _1.9 O ₃ having a thickness of 10 nm, and no conductive oxide layer is used. That is, the recording unit 22 is constituted only by the recording layer 12.

In this case, the reset voltage is +/- V when the unipolar operation is performed, and the set voltage is +1.5 V. In addition, the reset voltage when the bipolar action is obtained is +0.5 V, and the set voltage is -0.5 V. However, the cycle characteristics of the comparative example are poor, and the upper limit coefficient of the number of rewrites is a hundred times.

(10) Summary

As described above, the sample used in the first to eighth embodiments has a set voltage higher than the set voltage at the time of the unipolar operation. In addition, the sample used in the comparative example has a set voltage lower than the set voltage at the time of the unipolar operation. This indicates that when the present invention is applied to a cross-point type solid memory, the non-selective cells that are not written are excellent in reverse bias resistance. Further, regarding the cycle characteristics, the first to eighth embodiments are also superior to the comparative examples.

Further, according to the present invention, the resistance value of the ON state is increased, the ON current is reduced, and the setting/resetting operation can be performed with extremely small power consumption. This allows simultaneous processing of a large number of cells in parallel, enabling extremely high speed operations.

Thus, by using the conductive oxide layer of the present invention, a non-volatile information recording and reproducing apparatus having high recording density and low power consumption can be realized.

The verification results of the first to eighth embodiments and the comparative examples are shown in Table 2.

7. Conclusion According to the present invention, a non-volatile information recording and reproducing apparatus capable of achieving high recording density and low power consumption can be realized.

The examples of the present invention are not limited to the above-described embodiments, and various constituent elements may be modified and embodied without departing from the scope of the invention. Further, various inventions can be constructed by a plurality of constituent elements disclosed in the above embodiments by a suitable combination. For example, several constituent elements may be deleted from all the constituent elements disclosed in the above embodiment, and constituent elements of different embodiments may be combined as appropriate.

Industrial availability

When the information recording and reproducing apparatus according to the example of the present invention is used, although it has a very simple structure, information can be recorded by the recording density which cannot be achieved by the prior art, and high-speed operation can be realized. Therefore, the example of the present invention has contributed a lot to the industry as a generation of technology that breaks the current recording density limit of non-volatile memory.

11, 21. . . Electrode layer

12, 12-1, 12-2. . . Recording layer

13A. . . Electrode layer (or protective layer)

13B. . . The protective layer

14. . . Metal layer

15. . . Conductive oxide layer

20, 23, 41. . . Semiconductor substrate

22, 44. . . Recording department

twenty four. . . Probe

25, 26. . . Multiplex driver

27. . . driver

30. . . Recording unit

31. . . Word line driver & decoder

32. . . Bit Line Driver & Decoder & Readout Circuit

33, MC. . . Memory cell

34. . . Dipole

41a. . . P-type semiconductor substrate

41b. . . N-well area

41c. . . P-well area

42. . . N type diffusion layer

43. . . Gate insulation

45. . . Control gate electrode

47. . . P-type semiconductor layer

BL, BLj, BLj+1, BLj-1. . . Bit line

Cj, Cj+1, Cj-1, Ri, Ri+1, Ri-1. . . Select signal

CSW, RSW. . . MOS transistor

SL. . . Source line

ST. . . Select gate transistor

WLi, WLi+1, WLi-1. . . Word line

Figure 1 is a diagram showing the principle of recording.

Figure 2 is a diagram showing the principle of recording.

Figure 3 is a diagram showing the principle of recording.

Figure 4 is a diagram showing the principle of recording.

Figure 5 is a diagram showing the principle of recording.

Fig. 6 is a view showing a probe type solid memory.

Fig. 7 is a diagram showing the division of the recording medium.

Fig. 8 is a view showing a state at the time of recording.

Figure 9 is a diagram showing the recording action.

Fig. 10 is a view showing the reproduction operation.

Figure 11 is a diagram showing a cross-point type solid memory.

Figure 12 is a diagram showing the construction of a memory cell array.

Figure 13 is a diagram showing the construction of a memory cell array.

Figure 14 is a diagram showing the construction of a memory cell array.

Fig. 15 is a view showing the construction of a memory cell.

Fig. 16 is a view showing an example of application to a flash memory.

Figure 17 is a circuit diagram showing a NAND cell unit.

Fig. 18 is a view showing the construction of a NAND cell unit.

Fig. 19 is a view showing the construction of a NAND cell unit.

Figure 20 is a diagram showing the construction of a NAND cell unit.

Figure 21 is a circuit diagram showing a NOR cell.

Fig. 22 is a structural diagram showing a NOR cell.

Figure 23 is a circuit diagram showing a 2tr-cell unit.

Fig. 24 is a view showing the construction of a 2tr-cell unit.

Fig. 25 is a view showing the construction of a 2tr-cell unit.

11. . . Electrode layer

12. . . Recording layer

13A. . . Electrode layer (protective layer)

14. . . Metal layer

Claims (10)

An information recording and reproducing apparatus comprising: a recording layer that records two or more states of different resistivities; and a conductive oxide layer that applies a voltage or a current to the recording layer to cause the recording layer to When the state changes, it is disposed at one end of the recording layer on the anode side; the resistivity of the conductive oxide layer is smaller than the minimum value of the resistivity of the recording layer, and the conductive oxide layer is selected from (i) a first material as a main component of ZnO, SnO ₂ , CoO, TiO _s (1≦s≦2), In ₂ O ₃ , IrO ₂ , and RuO ₂ ; and (ii) selected from Ga ₂ O ₃ , Al _{A group of 2} O ₃ , Nb ₂ O ₅ , SnO ₂ , Ta ₂ O ₅ , Sb ₂ O ₃ , ZnO, TiO _s (1≦s≦2) and a second material of the dopant. The information recording and reproducing device of claim 1, further comprising an electrode on the anode side, wherein the conductive oxide layer is disposed between the recording layer and the electrode, and the electrode is selected from the group consisting of Ti-N and Ti- a nitride, a carbide or an oxide of a material of a group of Si-N, Ta-N, Ta-Si-N, Si-N, Ti-C, Ta-C, Si-C; the foregoing nitride and the foregoing oxide a mixture of the nitride and the carbide; a mixture of the oxide and the carbide; or a mixture of the nitride, the carbide, and the oxide. The information recording and reproducing apparatus of claim 1, wherein the recording layer is selected from the group consisting of (I) A _x M _y X ₄ (0.1≦x≦2.2, 1.8≦y≦2), (II) A _x M _y X ₃ (0.5≦x≦1.1, 0.9≦y≦1), (III) A _x M _y X ₄ (0.5≦x≦1.1, 0.9≦y≦1), and (I) And (II), A is selected from the group consisting of Na, K, Rb, Be, Mg, Ca, Sr, Ba, Al, Ga, Mn, Fe, Co, Ni, Cu, Zn, Ge, Ag, Au, Cd, Sn Element of group Sb, Pt, Pd, Hg, Tl, Pb, Bi, M is selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Cr, Mn, Fe, Co, Ni, Nb, Ta, Mo Element of group of W, Ru, Rh, with respect to (III), A is selected from the group consisting of Mg, Ca, Sr, Al, Ga, Sb, Ti, V, Cr, Mn, Fe, Co, Rh, In, Sb, An element of the group of T1, Pb, and Bi, and M is an element selected from the group consisting of Al, Ga, Ti, Ge, Sn, V, Nb, Ta, Cr, Mn, Mo, W, Ir, and Os, and (I) (II) and (III), where A and M are different elements, and X is an element selected from the group consisting of O and N. The information recording and reproducing apparatus of claim 1, wherein the recording layer has a structure selected from the group consisting of 1. corundum structure, 2. rutile structure, 3. spinel structure, 4. ramsdellite structure, 5. anatase structure 6. Manganese ore structure, 7. brookite structure, 8. pyrolusite structure, 9. NaCl structure, 10. perovskite structure, 11. ilmenite structure, 12. wolframite (wolframite) The crystalline structure of the group of structures. The information recording and reproducing apparatus of claim 1, wherein the ratio of the second material in the conductive oxide layer is 30 wt.% or less. The information recording and reproducing apparatus of claim 1, wherein the conductive oxide layer has a structure selected from the group consisting of (i) a sphalerite structure, (ii) a wurtzite structure, (iii) a C-rare earth structure, and (iv) a rutile structure. And (v) the crystal structure of the group of NaCl structures. The information recording and reproducing apparatus of claim 1, wherein the recording layer has a thickness of 5 nm or more and 50 nm or less. The information recording and reproducing device of claim 1, wherein the conductive oxide layer has a thickness of 0.5 nm or more and 10 nm or less. The information recording and reproducing device according to claim 1, wherein the conductive oxide layer has a resistivity of 1 × 10 ^-1 Ωcm or less. The information recording and reproducing device of claim 1, wherein the information recording and reproducing device constitutes one of a probe type solid memory and a cross-point type solid memory.