WO2009105943A1 - 柔性切换电源转换器的同步整流电路 - Google Patents

柔性切换电源转换器的同步整流电路 Download PDF

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Publication number
WO2009105943A1
WO2009105943A1 PCT/CN2008/070976 CN2008070976W WO2009105943A1 WO 2009105943 A1 WO2009105943 A1 WO 2009105943A1 CN 2008070976 W CN2008070976 W CN 2008070976W WO 2009105943 A1 WO2009105943 A1 WO 2009105943A1
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Prior art keywords
signal
circuit
power transistor
power converter
switching
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PCT/CN2008/070976
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English (en)
French (fr)
Inventor
杨大勇
王周昇
徐维利
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崇贸科技股份有限公司
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Publication of WO2009105943A1 publication Critical patent/WO2009105943A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • a conventional flexible switching power converter as shown in FIG. 1, includes a transformer 10 for providing insulation from an input voltage V IN to an output voltage Vo to ensure safety of a power converter, two switches 111, 112 A half bridge circuit 11 is formed to switch between a resonant tank 12 and a transformer 10.
  • the resonant circuit 12 includes an inductor 121 and a capacitor 122.
  • the inductor 121 can be an inductive device or a primary winding N P of the transformer 10.
  • the leakage inductance, the inductance L of the inductor 121, and the capacitance C of the capacitor 122 can be determined by the following formula by the resonance frequency f Q of the resonance circuit 12: i jL XC "The transformer 10 is composed of the primary winding N P to the transformer 10 The secondary windings N S1 , N S2 convert energy, and the two rectifiers 13 , 14 and 15 perform rectification and filtering on the transformer 10 to generate a DC output voltage Vo at the output of the power converter, the part of the flexible switching power converter ( Soft switching power converter) can be found in "Resonant Power Converters” (, Resonant Power Converters, by Marian K. Kazimierczuk and Dariusz Czarkowski , 1995 by John Wiley & Sons, Inc. ) ⁇ ⁇ In the book.
  • the same rectifier circuit of the flexible switching power converter has a transformer, and the same rectifier circuit includes: a current transformer that generates a switching current signal corresponding to a switching state of the transformer;
  • An integrated parallel rectifier which includes:
  • a power transistor coupled to the transformer and an output of the power converter for rectification
  • a controller generating a driving signal according to the switching current signal to control the power transistor; wherein when the switching current signal is greater than a first threshold, the controller generates an activation signal, when the switching current signal is lower than a second The threshold value, the controller generates a stop signal, and the enable signal enables the drive signal to turn on the power transistor, and the stop signal disables the drive signal to turn off the power transistor.
  • the controller includes a pulse width detecting circuit for generating an integrated signal, a ramp signal and a pulse signal, wherein the integrated signal is generated according to the start signal and the period of the stop signal, and the ramp signal is based on The activation signal is generated, and the pulse signal is generated by comparing the integrated signal and the ramp signal to disable the driving signal to turn off the power transistor.
  • the controller includes an internal locking circuit, and the internal locking circuit generates an internal locking signal according to the activation of the driving signal. When the internal locking signal is disabled, the driving signal is initialized.
  • the controller includes a maximum on-time signal for turning off the power transistor to limit the maximum on-time of the power transistor.
  • the above controller contains:
  • a latch circuit for generating the driving signal to control the power transistor; and a plurality of comparators for generating a start signal and a stop signal to set or reset the latch circuit;
  • the driving signal is enabled when the switching current signal is higher than the first threshold, and the driving signal is disabled when the switching current signal is lower than the second threshold.
  • the controller includes a monitoring circuit for generating a reset signal, wherein the reset signal couples and disables the power transistor when the amplitude of the switching current signal is lower than a third threshold voltage.
  • a diode is included to be connected in parallel to the power transistor, and the power transistor is turned on when the diode is activated.
  • the coaxial rectification circuit of the flexible switching power converter of the present invention comprises a power transistor connected to the output end of the power converter by a transformer as a rectification, and the controller has a shackle circuit for corresponding to the switching current.
  • the signal generates a driving signal for controlling the power transistor, and the current transformer generates a switching current signal corresponding to the switching current of the transformer. Therefore, when the switching current signal is lower than the second threshold, the controller turns off the power transistor, and when the switching current signal is higher than At the first threshold, the power converter is turned on, and the pulse width detection circuit generates a pulse signal to couple and disable the drive signal to turn off the power transistor.
  • the invention has the advantages of improving the power conversion efficiency.
  • FIG. 1 is a circuit diagram of a conventional flexible switching power converter.
  • FIG. 2 is a schematic circuit diagram of a first embodiment of a synchronous switching power converter of the flexible switching power converter of the present invention.
  • FIG. 3 is a schematic diagram showing the circuit structure of the integrated parallel rectifiers 21 and 22 in FIG.
  • FIG. 4 is a schematic diagram showing the circuit structure of the preferred embodiment of the controller 30 of FIG.
  • FIG. 5 is a schematic diagram showing the circuit structure of the maximum on-time circuit 39 of FIG.
  • FIG. 6 is a schematic diagram showing the circuit structure of the preferred embodiment of the monitoring circuit 32 of FIG.
  • FIG. 7 is a schematic diagram showing the circuit structure of the internal lock circuit 50 of FIG.
  • FIG. 8 is a schematic diagram showing the circuit structure of the pulse width detecting circuit 33 of FIG.
  • FIG. 9 is a schematic diagram showing the circuit structure of the signal generator 60 of FIG.
  • FIG. 10 is a schematic diagram showing the circuit structure of the click circuits 602 and 604 of FIG.
  • Figure 11 is a waveform diagram of the same-rectification of the present invention.
  • FIG. 12 is a schematic circuit diagram of Embodiment 2 of the same-rectifying circuit of the flexible switching power converter of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A homogenous rectifying circuit of a flexible switching power converter of the present invention is shown in FIG. 2.
  • the power converter includes a transformer 10 having a primary winding NP and a secondary winding NS1, NS2, and a half bridge circuit ( Half bridge circuit) 11, a resonant tank 12, a capacitor 15, a current transformer 20, two integrated coaxial rectifiers 21, 22 and a resistor 23, the half bridge circuit 11 includes two switching switches 111, 112, and the resonant circuit 12 includes There are an inductor 121 and a capacitor 122.
  • the switch 111, 112 switches the primary winding NP of the transformer.
  • the current transformer 20 includes two input windings T1, ⁇ 2 and an output winding ⁇ 3.
  • the integrated synchronous rectifier 21 has a cathode terminal ⁇ connected to the secondary winding NS 1 through the input winding T1 of the current transformer 20, and the anode terminal ⁇ of the integrated synchronous rectifier 21 is connected to the output ground of the power converter.
  • the integrated coaxial rectifier 22 has a cathode terminal K and an anode terminal A. The cathode terminal K is also connected to the secondary winding NS2 through the input winding T2 of the current transformer 20, and the anode terminal A is connected to the output terminal of the power converter.
  • the integrated synchronous rectifiers 21, 22 include an input signal terminal X and an input signal terminal Y, and are connected to the output winding ⁇ 3 of the current transformer 20 to receive the switching current signal VS.
  • the switching current signal VS is generated by the switching currents IS 1 and IS2 of the transformer 23 and the transformer 10, and the switching current signal is related to the switching currents IS1, IS2 of the transformer 10, which can be expressed by the following equation:
  • NT1, NT2 and NT3 are the turns of the windings Tl, T2 and T3, respectively;
  • R23 is the resistance value of the resistor 23.
  • the switching current signal VS is a differential signal whose polarity is determined by the on or off of the integrated parallel rectifiers 21, 22.
  • the integrated parallel rectifiers 21, 22 also generate an internal lock signal SL (not shown) at the internal lock terminal L to prevent the integrated parallel rectifiers 21, 22 from being simultaneously turned on.
  • the amplitude of the switching current signal VS is lower than the threshold voltage or the supply voltage VCC of the integrated parallel rectifiers 21, 22 is lower than the power supply threshold, the integrated synchronous rectifiers 21, 22 are turned off.
  • FIG. 3 is a schematic diagram of the integrated parallel rectifier 21 or 22. As shown in FIG. 3, the integrated parallel rectifier 21 is taken as an example. Since the integrated synchronous rectifiers 22 and 21 are the same, they are not described herein again.
  • the integrated synchronous rectifier 21 includes a power transistor 24, a diode 25, and a controller 30.
  • the diode 25 is connected in parallel to the power transistor 24, and the diode 25 can be a parasitic device of a Schottky diode or a power transistor 24.
  • (Parasitic device) 0 is connected between the cathode terminal K and the anode terminal A, the cathode terminal K is coupled to the secondary winding NS1 or NS2 of the transformer 10, and the anode terminal A is coupled to the output terminal of the power converter, the controller
  • the power transistor 24 is turned on or off by receiving the switching current signal VS through the input signal terminals X and Y.
  • the power terminal VCC is used to supply the power required by the controller 30, and the internal locking terminal L outputs the internal locking signal SL to display the power transistor 24. Turn it on or off.
  • the controller 30 includes resistors 311, 312, 313 and 314, two offset voltage sources 315, 316, three comparators 341, 342 and 343, and AND gates 351, 352. 37, SR flip-flop 36 as a shackle circuit, Pulse Width Detector (PWD) 33, Maximum On-time Circuit (MOT) 39, monitoring Circuit 32 and inverter 38.
  • the resistors 311 and 312 provide a bias terminal of the input signal terminal X
  • the resistors 313 and 314 provide a bias terminal of the other input signal terminal Y
  • the input signal terminal X transmits an offset voltage 315.
  • the 316 is coupled to the positive input of comparator 341, and the offset voltage sources 315, 316 are coupled to each other in series.
  • the input signal terminal X is connected to the negative input terminal of the comparator 342 through the offset voltage source 315, and the input signal terminal Y is connected to the positive input terminal of the comparator 342 and the negative input terminal of the comparator 341, and the offset voltage source 315, 316 Hysteresis occurs.
  • the comparator 343 receives the threshold VTH from the positive input terminal, the negative input terminal is coupled to the cathode terminal K, and the output terminal of the comparator 343 is coupled to the input terminal of the AND gate 351.
  • the output of the comparator 341 generates an enable signal SA to the input of the AND gate 351, the output of the AND gate 351 is coupled to the set input S of the SR flip-flop 36, and the reset terminal R of the SR flip-flop 36 is subjected to the AND gate 352.
  • the output of the comparator 342 generates a stop signal SB.
  • the pulse width detecting circuit 33 generates a pulse signal SC corresponding to the start signal SA and the stop signal SB, and the stop signal SB and the pulse signal SC are transmitted to the input end of the AND gate 352.
  • the output terminal Q of the SR flip-flop 36 and the output terminal of the comparator 343 are both connected to the input terminal of the AND gate 37.
  • the driving signal VG is generated at the output of the AND gate 37 to control the power transistor 24 (see Fig. 3), and the driving signal VG.
  • the maximum on-time is limited by the maximum on-time circuit 39 and is passed to the input of the maximum on-time circuit 39.
  • a maximum on-time signal SM is generated corresponding to the actuation of the driving signal VG, and is transmitted to the clearing terminal CLR of the SR flip-flop 36 through the inverter 38 to clear the SR flip-flop. 36. Therefore, the maximum on-time of the driving signal VG can be limited by the blanking time of the maximum on-time circuit 39.
  • VK is the voltage of the input signal terminal X
  • VY is the voltage input to the signal terminal Y
  • VK is the voltage at the cathode terminal K
  • V315 is to compensate the voltage of voltage source 315
  • V316 is the voltage that compensates for voltage source 316.
  • the start signal SA When the switching current signal VS is lower than the first threshold (V315 + V316), the start signal SA will be enabled. When the switching current signal VS is lower than the second threshold (V315), the stop signal SB will be caused. can.
  • the enable signal SA enables the drive signal VG to turn on the power transistor 24, and the stop signal SB disables the drive signal VG to turn off the power transistor 24.
  • the diode 25 When the diode 25 is turned on and has a forward bias, the voltage at the cathode terminal K is lower than the voltage at the threshold VTH, so that the power transistor 24 can be activated only when the diode 25 is turned on, and the flexible switching power transistor is achieved. twenty four.
  • the driving signal VG is turned off and the power transistor 24 is turned off, and the monitoring circuit 32 detects the internal locking signal SL, the switching current signal VS and the supply voltage VCC to generate the reset signal RST.
  • the reset signal RST is transmitted to the pulse width detecting circuit 33 to generate the pulse signal SC, coupled to the other input terminal of the gate 351 and receiving the reset signal RST. Therefore, when the amplitude of the switching current signal VS is lower than The boundary voltage or supply voltage VCC is below the power supply threshold and the power transistor 24 will be turned off.
  • 5 is a schematic diagram of the maximum on-time circuit 39. As shown in FIG.
  • the maximum on-time circuit 39 includes a current source 391, a capacitor 392, a transistor 393, an AND gate 394 and an inverter 395, and the current source 391 is connected to Capacitor 392 charges capacitor 392, transistor 393 is coupled to capacitor 392 and discharges capacitor 392, drive signal VG is controlled by inverter 395 to control transistor 393, and is coupled to an input of AND gate 394, AND gate 394 The other input is coupled to a capacitor 392.
  • the maximum on-time signal SM is generated at the output of the AND gate 394 after the blanking time to turn off the driving signal VG, and the blanking time is obtained by the current of the current source 391 and the capacitance of the capacitor 392. Decide.
  • the monitoring circuit 32 includes two current sources 321, 322, a capacitor 323, a switch 324, a comparator 325, a threshold voltage 326, and two inversions.
  • the current sources 321, 322 and the capacitor 323 form a debounce circuit, the current source 321 supplies and charges the capacitor 323, and the current source 322 discharges the capacitor 323 through the switch 324, and the switch 324 is turned on/ The control is controlled by the comparator 325.
  • the positive input terminal of the comparator 325 is coupled to the signal input terminal X through the threshold voltage 326, and the negative input terminal of the comparator 325 is connected to the input signal terminal Y to receive the switching current signal VS.
  • the switch 324 is turned off and the capacitor 323 is charged.
  • the reset signal RST will be turned off (logically high).
  • the input terminal of the inverter 327 is connected to the capacitor 323, and the output terminal is connected to one input terminal of the AND gate 328; the output terminal of the AND gate 328 generates a reset signal RST, and the other input terminal thereof is connected to the power source through the inverter 329. Voltage detection circuit 40.
  • the power supply voltage detecting circuit 40 includes transistors 43, 44, Zener diodes 41, 42, resistors 45, 46 and 47, and a capacitor 48.
  • the signal will turn on transistor 43.
  • Resistor 46 and capacitor 48 are used to filter noise.
  • the output of transistor 43 is coupled to the input of inverter 329 and transistor 44.
  • Resistor 45 provides transistor 44 bias, and when transistor 43 is turned on, transistor 44 is turned “on”. Short-circuiting with the Zener diode 41, and then when the power supply voltage VCC is lower than the voltage of the Zener diode 42, the transistor 43 is turned off.
  • the reset signal RST will be turned off (logic high).
  • the other input end of the AND gate 328 receives the output signal SO by the internal lock circuit 50, and the internal lock circuit 50 generates the internal lock signal SL corresponding to the actuation of the drive signal VG, and only when the internal lock signal SL is disabled, the drive The signal VG will be initialized.
  • FIG. 7 is a schematic diagram of the interlock circuit 50.
  • the latch circuit 50 includes a current source 51, a transistor 52, an AND gate 53, and an inverter 54, a current source 51 and a transistor. 52 generates an internal lock signal SL, the drive signal VG controls the transistor 52 and the inverter 54, the output signal SO is generated through the AND gate 53, and the input end of the AND gate 53 is coupled to the output end of the latch L and the inverter 54. .
  • the pulse width detecting circuit 33 includes a signal generator 60, a current source 331, two capacitors 332 and 336, and three switching switches 333, 334 and 335. Buffer amplifier 337, comparator 338 and two resistors 330, 339.
  • the pulse width detecting circuit 33 generates the integrated signal VINT, the ramp signal VRMP and the pulse signal SC; the integrated signal VINT is generated according to the period of the start signal SA and the stop signal SB, and the ramp signal VRMP is generated according to the start signal SA, by comparing
  • the pulse signal SC is generated by integrating the signal VINT and the ramp signal VRMP.
  • the pulse signal SC cuts off the driving signal VG and turns off the power transistor 24 (see FIG. 3).
  • the current source 331 charges the capacitor 332 through the switch 333, and the capacitor 332 is coupled to the other capacitor 336 through the switch 335; When the switch 335 is turned on, the signal of the capacitor 332 is transmitted to the capacitor 336, the ramp signal VRMP is generated at the capacitor 332, and the integrated signal VINT is generated at the capacitor 336.
  • the switch 334 is connected in parallel to the capacitor 332 and is discharged.
  • the signal generator 60 is configured to generate the charging signal CHG, the clear signal CLR and the sampling signal SMP, the charging signal CHG control switch 333, the clear signal CLR control switch 334, and the sampling signal The SMP controls the changeover switch 335.
  • the charging signal CHG is actuated by the start signal SA and is turned off by the stop signal SB. Therefore, the pulse width of the charging signal CHG is proportional to the pulse width of the switching current signal VS, and the maximum amplitude of the ramp signal VRMP is also charged. The pulse width of the signal CHG is proportional.
  • the ramp signal VRMP is generated corresponding to the enable of the charging signal CHG.
  • the sampling signal SMP is generated along with the disable of the charging signal CHG.
  • the ramp signal VRMP is thus transmitted to the capacitor 336 for generating the integrated signal VINT, integrating the signal.
  • the amplitude of VINT is proportional to the period of the start signal SA and the stop signal SB.
  • the integrated signal VINT is coupled to the comparator 338 through the buffer amplifier 337 and the resistors 339, 330.
  • the resistors 339, 330 form a voltage divider to provide attenuation, and the other input of the comparator 338 receives the ramp signal VRMP to generate the pulse signal SC.
  • the ramp signal VRMP is higher than the integrated signal VINT, the pulse signal SC is enabled, and before the stop signal SB is enabled, the pulse signal SC is generated. Before the sampling signal SMP is cut off, the clear signal CLR will be generated and the capacitor 332 will be cleared after sampling.
  • the signal generator 60 includes a flip-flop 601, a one shot circuit 602, 604, two inverters 603, 605, or an OR gate 606.
  • the flip-flop 601 is used to generate the charging signal CHG
  • the start signal SA is transmitted to the set terminal S of the flip-flop 601
  • the stop signal SB is transmitted to the reset terminal R of the flip-flop 601, and the charging signal CHG is inverted.
  • 603 is transferred to click Circuit 602, click circuit 602 generates sample signal SMP through inverter 605 to another click circuit 604, the output of circuit 604 is connected to OR gate 606, and the other input of OR gate 606 receives the reset signal. RST, and the output generates a clear signal CLR.
  • FIG. 10 is a circuit diagram of the click circuits 602, 604.
  • the current source 650 is connected to the capacitor 670 and charges the capacitor 670 according to the high potential of the input signal IN.
  • the input signal IN is transmitted through the inverter 651.
  • Transistor 652 discharges capacitor 670, and input signal IN is again coupled to AND gate 680.
  • the other input of AND gate 680 is coupled to capacitor 670 via inverter 675; therefore, AND gate 680 corresponds to the input signal IN.
  • the click output signal OP is generated by the potential, and the pulse width of the click output signal OP is determined by the current value of the current source 650 and the capacitance value of the capacitor 670.
  • FIG. 11 is a schematic diagram of the waveform of the same rectification.
  • the switching current signal VS is generated corresponding to the switching current IS of the transformer 10 including the currents IS1 and IS2, and the pulse width TPW displays the start signal SA and the stop signal SB.
  • the driving signals VG1 and VG2 are driving signals VG of the integrated parallel rectifiers 21 and 22, respectively.
  • the driving signal is cut off by the pulse signal SC1 by the VG1, and the driving signal VG2 is cut off by the pulse signal SC2, and the pulse width TON of the driving signals VG1 and VG2 is shorter than the pulse width TPW.
  • FIG. 12 is a schematic diagram of another embodiment of the present invention. As shown in FIG. 12, the difference between this embodiment and the first embodiment is: using two current transformers 71, 72, resistors 81, 82 to switch the switching currents IS 1 , IS2 to switch Current signal VS.
  • the coaxial rectifier circuit of the flexible switching power converter of the present invention can achieve the efficiency of power conversion for the flexible switching power converter.

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Description

柔性切换电源转换器的同步整流电路 技术领域 本发明涉及一种电源转换器，特别是指一种柔性切换电源转换器 的同歩整流电路。 背景技术 习知柔性切换电源转换器， 如图 1所示， 包含有变压器 10， 用 以提供由输入电压 VIN至输出电压 Vo 的绝缘来确保电源转换器的 安全性， 两个开关 111、 112构成了一个半桥电路（half bridge circuit) 11来切换谐振电路 （resonant tank) 12与变压器 10， 谐振电路 12包 含电感 121与电容 122， 电感 121可为电感装置或是变压器 10的一 次绕组 NP 的漏电感，电感 121的电感值 L 以及电容 122的电容值 C 可以藉由谐振电路 12的谐振频率 fQ 由下列公式来决定： i jL X C " 变压器 10由一次绕组 NP至变压器 10的二次绕组 NS1、NS2 转换 能量， 两个整流器 13、 14与电容 15针对变压器 10来执行整流与滤 波来于电源转换器的输出端产生直流电输出电压 Vo， 此部份柔性切 换电源转换器 ( soft switching power converter) 可见于 「谐振电源转 换器」 (，， Resonant Power Converters，， by Marian K. Kazimierczuk and Dariusz Czarkowski, 1995 by John Wiley & Sons, Inc. ) ^ ^书中。
尽管电源转换器的柔性切换可以达到高效率以及低电磁波干扰 (electric-magnetic interference; EMI) 的效能， 整流器 13、 14的顺 向电压仍会引起显著的能量损耗。 因此， 使用晶体管作为同歩整流器 乃为高效率的一种趋势， 如美国专利第 7,173,835 号专利， 揭露一种 作为同歩整流顺向电源转换器的具有饱和电感的控制电路 （ Control circuit associated with saturable inductor operated as synchronous rectifier forward power converter) , 然而， 其缺点是饱和电感等组件会 产生额外的能量损耗， 电源转换效率较低。 发明内容 本发明的目的是提供一种可提升电源转换效率的柔性切换电源 转换器的同歩整流电路。
本发明的技术方案是这样的：柔性切换电源转换器的同歩整流电 路， 具有一变压器， 该同歩整流电路包含有： 一电流变压器，对应于该变压器的切换状态而产生一切换电流讯 号； 以及
一集成同歩整流器， 系包含有：
一功率晶体管，耦合于该变压器以及该电源转换器的一输出端作 为整流之用； 以及
一控制器，依据该切换电流讯号产生一驱动讯号来控制该功率晶 体管； 其中当该切换电流讯号大于一第一临界值， 该控制器产生一启 动讯号， 当该切换电流讯号低于一第二临界值， 该控制器产生一停止 讯号， 且该启动讯号致能该驱动讯号用以开启该功率晶体管， 该停止 讯号禁能该驱动讯号用以关闭该功率晶体管。
上述控制器包含有一脉冲宽度侦测电路， 用以产生一整合讯号、 一斜波讯号与一脉冲讯号，其中该整合讯号系依据该启动讯号与该停 止讯号的期间而产生， 该斜波讯号依据该启动讯号而产生， 该脉冲讯 号依据比较整合讯号与斜波讯号而产生并禁能该驱动讯号来关闭该 功率晶体管。
上述控制器包含有一内锁电路，该内锁电路依据该驱动讯号的致 能而产生一内锁讯号，其中当内锁讯号禁能时，会初始化该驱动讯号。
上述控制器包含有最大导通时间讯号，用以关闭该功率晶体管来 限制功率晶体管的最大导通时间。
上述控制器包含有：
一拴锁电路， 用以产生该驱动讯号来控制该功率晶体管； 以及 复数个比较器，用以产生一启动讯号与一停止讯号来设定或重置 该拴锁电路；
其中当该切换电流讯号高于该第一临界值， 该驱动讯号被致能， 当该切换电流讯号低于该第二临界值， 该驱动讯号被禁能。
上述控制器包含有一监控电路， 用以产生一复位讯号， 其中当切 换电流讯号的振幅低于一第三临界电压时，该复位讯号耦合并禁能该 功率晶体管。
包含有一二极管， 以并联的方式连接于该功率晶体管， 且当该二 极管启动时， 该功率晶体管会被开启。
采用上述方案后， 本发明的柔性切换电源转换器的同歩整流电 路，包含有由变压器连接至电源转换器的输出端的功率晶体管作为整 流之用，控制器具有拴锁电路用来对应于切换电流讯号产生控制功率 晶体管的驱动讯号，电流变压器对应于变压器的切换电流产生切换电 流讯号， 因此， 当切换电流讯号低于第二临界值时， 控制器会关闭功 率晶体管， 而当切换电流讯号高于第一临界值时， 功率转换器会被开 启，且脉冲宽度侦测电路产生脉冲讯号来耦合并禁能驱动讯号以关闭 功率晶体管。本发明与现有技术相比， 具有可提升电源转换效率的优 点 附图说明 图 1为一种习知柔性切换电源转换器的电路示意图。
图 2 为本发明柔性切换电源转换器的同歩整流电路实施例一电 路示意图。
图 3为图 2中集成同歩整流器 21、 22的电路结构示意图。
图 4为图 3中控制器 30的较佳实施例的电路结构示意图。
图 5为图 4中最大导通时间电路 39的电路结构示意图。
图 6为图 4中监控电路 32的较佳实施例的电路结构示意图。 图 7为图 6中内锁电路 50的电路结构示意图。
图 8为图 4中脉冲宽度侦测电路 33的电路结构示意图。
图 9为图 8中讯号产生器 60的电路结构示意图。
图 10为图 9中单击电路 602、 604的电路结构示意图。
图 11为本发明的同歩整流的波形示意图。
图 12为本发明柔性切换电源转换器的同歩整流电路实施例二的 电路示意图。 具体实施方式 本发明柔性切换电源转换器的同歩整流电路，实施例一如图 2所 示， 电源转换器包含有变压器 10， 其具有一次绕组 NP与二次绕组 NS1、 NS2、半桥电路（half bridge circuit) 11、谐振电路（resonant tank) 12、 电容 15、 电流变压器 20、 两集成同歩整流器 21、 22与电阻 23， 半桥电路 11包含有两切换开关 111、 112， 谐振电路 12包含有电感 121与电容 122， 切换开关 111、 112切换变压器的一次绕组 NP ， 电 流变压器 20包含有两输入绕阻 Tl、 Τ2 与一输出绕阻 Τ3。 集成同歩 整流器 21具有阴极端 Κ, 透过电流变压器 20的输入绕阻 T1 而连接 至二次绕组 NS 1 , 而集成同歩整流器 21的阳极端 Α连接于电源转换 器的输出地端。 集成同歩整流器 22具有阴极端 K与阳极端 A， 阴极 端 K亦透过电流电压器 20的输入绕阻 T2而连接至二次绕组 NS2, 阳 极端 A连接至电源转换器的输出地端， 集成同歩整流器 21、 22包含 有输入讯号端 X与输入讯号端 Y， 连接到电流变压器 20的输出绕阻 Τ3 来接收切换电流讯号 VS。 切换电流讯号 VS透过电阻 23与变压 器 10的切换电流 IS 1、 IS2 来产生， 且切换电流讯号系与变压器 10 的切换电流 IS1、 IS2 相关， 其可以下列方程式表示：
Figure imgf000006_0001
其中， NT1、 NT2 与 NT3分别为绕阻 Tl、 T2 与 T3 的匝数； 及
R23为电阻 23的电阻值。
切换电流讯号 VS 系为差动讯号 （differential signal) , 其极性乃 由集成同歩整流器 21、 22的开启或关闭来决定。集成同歩整流器 21、 22亦在内锁端 L产生内锁讯号 SL (inner-lock signal; 图中未示） 来 避免集成同歩整流器 21、 22同时开启。 当切换电流讯号 VS 的振幅 低于临界值电压或集成同歩整流器 21、 22的供应电压 VCC 低于电 源临界值时， 集成同歩整流器 21、 22会被截止。
图 3为集成同歩整流器 21或 22的示意图， 如图 3所示， 在此图 以集成同歩整流器 21为例， 由于集成同歩整流器 22与 21相同， 在 此不再赘述。 集成同歩整流器 21 包含有功率晶体管 24、 二极管 25 以及控制器 30， 二极管 25以并联的方式连接于功率晶体管 24， 且二 极管 25可为萧特基二极管（Schottky diode)或功率晶体管 24的寄生 装置 （parasitic device )0 功率晶体管 24连接于阴极端 K与阳极端 A 之间，阴极端 K耦合于变压器 10的二次绕组 NS1 或 NS2,阳极端 A 耦合于电源转换器的输出地端， 控制器 30透过输入讯号端 X、 Y接 收切换电流讯号 VS 来开启或关闭功率晶体管 24， 电源端 VCC用以 供应控制器 30所需电源， 内锁端 L输出内锁讯号 SL来显示功率晶 体管 24的开启或关闭。
图 4为控制器 30的较佳实施例的示意图。 如图 4所示， 控制器 30包含有电阻 311、 312、 313与 314、 两偏移电压源 315、 316、 三 个比较器 341、 342与 343、 三与门 (AND gate) 351、 352与 37、 SR 触发器 （SR flip-flop) 36作为一拴锁电路、 脉冲宽度侦测电路 (Pulse Width Detector, PWD )33、 最大导通时间电路 （Maximum-on-time circuit, MOT) 39、 监控电路 32与反相器 （inverter) 38。 电阻 311、 312提供输入讯号端 X的偏压终端， 电阻 313、 314提供另一个输入 讯号端 Y的偏压端点 （bias terminal), 输入讯号端 X透过偏移电压源 ( offset voltage)315, 316耦合于比较器 341的正输入端， 偏移电压源 315、 316以串联方式相互耦合。 输入讯号端 X透过偏移电压源 315 连接于比较器 342的负输入端， 输入讯号端 Y连接于比较器 342的 正输入端与比较器 341的负输入端， 偏移电压源 315、 316产生磁滞 现象 （hysteresis)。 比较器 343由正输入端接收临界值 VTH, 负输入 端耦合于阴极端 K， 比较器 343的输出端耦合于与门 351的输入端， 比较器 341 的输出端产生启动讯号 SA到与门 351 的输入端， 与门 351的输出端连接于 SR触发器 36的设定输入端 S, 而 SR触发器 36 的复位端 R受到与门 352的输出端的控制。比较器 342的输出端产生 停止讯号 SB,脉冲宽度侦测电路 33对应于启动讯号 SA与停止讯号 SB 而产生脉冲讯号 SC, 且停止讯号 SB与脉冲讯号 SC传送至与门 352的输入端。
SR触发器 36的输出端 Q与比较器 343的输出端皆连接于与门 37的输入端，驱动讯号 VG 于与门 37的输出端产生来控制功率晶体 管 24 (见图 3 )， 驱动讯号 VG 的最大导通时间藉由最大导通时间电 路 39来限制， 且传送至最大导通时间电路 39的输入端。在一段遮没 时间 （blanking time) 后， 对应于驱动讯号 VG 的致动而产生最大导 通时间讯号 SM,且透过反相器 38传送至 SR触发器 36的清除端 CLR 来清除 SR触发器 36， 因此，驱动讯号 VG 的最大导通时间可以藉由 最大导通时间电路 39的遮没时间来加以限制， 当满足下列两方程式 时， 驱动讯号将会开启功率晶体管 24:
Figure imgf000007_0001
VK < VTH (5)其 中， VX系为输入讯号端 X的电压；
VY系为输入讯号端 Y的电压；
VK系为阴极端 K的电压；
V315系为补偿电压源 315的电压； 以及
V316系为补偿电压源 316的电压。
当切换电流讯号 VS低于时 V315 , 驱动讯号 VG将会关闭功率 晶体管 24， 如下方程序所示：
Figure imgf000007_0002
当切换电流讯号 VS 低于第一临界值 （V315 + V316) 时， 启动 讯号 SA将会被致能， 当切换电流讯号 VS 低于第二临界值 （V315 ) 时， 停止讯号 SB 将会被致能。 请参阅图 3， 启动讯号 SA致能驱动 讯号 VG来开启功率晶体管 24， 停止讯号 SB 禁能驱动讯号 VG来 关闭功率晶体管 24。 当二极管 25导通且具有顺向偏压时， 阴极端 K 的电压会低于临界值 VTH 的电压， 因此， 只有在二极管 25开启时， 功率晶体管 24才可以被启动， 而达到柔性切换功率晶体管 24。 更进 一歩来说， 当二极管 25逆向偏压时， 驱动讯号 VG 被截止且功率晶 体管 24被关闭，监控电路 32侦测内锁讯号 SL、切换电流讯号 VS 与 供应电压 VCC 来产生复位讯号 RST, 且复位讯号 RST被传送到脉 冲宽度侦测电路 33而来产生脉冲讯号 SC,与门 351的另一个输入端 耦合并接收复位讯号 RST, 因此， 当切换电流讯号 VS 的振幅低于临 界电压或供应电压 VCC低于电源临界值，功率晶体管 24将会被截止。 图 5为最大导通时间电路 39的示意图， 如图 5所示， 最大导通 时间电路 39包含有电流源 391、 电容 392、 晶体管 393、 与门 394与 反相器 395， 电流源 391连接至电容 392并对电容 392进行充电， 晶 体管 393连接到电容 392并对电容 392进行放电， 驱动讯号 VG透 过反相器 395控制晶体管 393， 且传送到与门 394的一个输入端， 与 门 394的另一个输入端耦合于电容 392。 当驱动讯号 VG致能， 在遮 没时间之后与门 394的输出端产生最大导通时间讯号 SM来截止驱 动讯号 VG, 而遮没时间乃藉由电流源 391的电流与电容 392的电容 值来决定。
图 6为监控电路 32的较佳实施例示意图， 如图 6所示， 监控电 路 32包含有两电流源 321、 322、 电容 323、 切换开关 324、 比较器 325、 临界值电压 326、 两反相器 327、 329、 与门 328、 内锁电路 50 与电源电压侦测电路 40。 电流源 321、 322与电容 323形成一反跳电 路（debounce circuit) , 电流源 321供应并对电容 323进行充电， 而电 流源 322透过切换开关 324对电容 323进行放电，切换开关 324的开 启 /关闭受到比较器 325的控制， 比较器 325的正输入端透过临界电 压 326耦合于讯号输入端 X， 比较器 325的负输入端连接到输入讯号 端 Y来接收切换电流讯号 VS , 因此， 当切换电流讯号 VS 低于临界 电压 326的电压（第三临界值电压） 时， 切换开关 324会关闭， 而电 容 323会进行充电。 当到达反跳期间 （debounce peroid) 时， 复位讯 号 RST将会被截止（逻辑上 high)。 反相器 327的输入端连接于电容 323， 输出端连接于与门 328的一个输入端； 与门 328的输出端产生 复位讯号 RST,而其另一个输入端透过反相器 329连接于电源电压侦 测电路 40。 电源电压侦测电路 40系包含晶体管 43、 44、 齐纳二极管 41、 42、 电阻 45、 46与 47以及电容 48， 当供应电压 VCC高于齐纳 二极管 41、 42的电压时， 在电阻 47上的讯号将会开启晶体管 43。 电阻 46与电容 48用以滤波噪声， 晶体管 43的输出端连接于反相器 329的输入端与晶体管 44， 电阻 45提供晶体管 44偏压， 且当晶体管 43开启时， 晶体管 44会被导通来与齐纳二极管 41短路， 之后当电 源供应电压 VCC 低于齐纳二极管 42的电压时，晶体管 43会被关闭。 因此，当切换电流讯号 VS 低于临界电压 326的电压或电源供应电压 VCC 低于齐纳二极管 42的电压时， 复位讯号 RST将会被截止 （逻 辑上 high)。 与门 328的另一个输入端由内锁电路 50接收输出讯号 SO, 且内锁电路 50对应于驱动讯号 VG 的致动而产生内锁讯号 SL， 而只有在内锁讯号 SL禁能时， 驱动讯号 VG才会被初始化。
图 7为内锁电路 50的示意图。如图 7所示， 内锁电路 50包含有 电流源 51、 晶体管 52、 与门 53以及反相器 54， 电流源 51与晶体管 52产生内锁讯号 SL， 驱动讯号 VG控制晶体管 52与反相器 54， 输 出讯号 SO透过与门 53而产生， 与门 53 的输入端耦合于内锁端 L 与反相器 54的输出端。
图 8为脉冲宽度侦测电路 33的示意图， 如图 8所示， 脉冲宽度 侦测电路 33包含讯号产生器 60、 电流源 331、 两电容 332、 336、 三 个切换开关 333、 334与 335、 缓冲放大器 337、 比较器 338与两个电 阻 330、 339。 脉冲宽度侦测电路 33产生整合讯号 VINT、 斜波讯号 VRMP 与脉冲讯号 SC; 整合讯号 VINT根据启动讯号 SA与停止讯 号 SB 的期间而产生， 斜波讯号 VRMP根据启动讯号 SA而产生， 透过比较整合讯号 VINT与斜波讯号 VRMP而产生脉冲讯号 SC。脉 冲讯号 SC 截止驱动讯号 VG 并关闭功率晶体管 24 (见图 3 )， 电流 源 331透过切换开关 333对电容 332进行充电，且电容 332透过切换 开关 335耦合于另一个电容 336; 因此， 当切换开关 335开启时， 电 容 332的讯号会传送到电容 336， 斜波讯号 VRMP会于电容 332产 生，而整合讯号 VINT会于电容 336产生。切换开关 334并联于电容 332并对其放电， 讯号产生器 60用以产生充电讯号 CHG、 清除讯号 CLR与取样讯号 SMP, 充电讯号 CHG控制切换开关 333， 清除讯号 CLR控制切换开关 334， 而取样讯号 SMP控制切换开关 335。 充电 讯号 CHG藉由启动讯号 SA而致动， 并藉由停止讯号 SB 而截止， 因此， 充电讯号 CHG的脉冲宽度与切换电流讯号 VS 的脉冲宽度成 比例，斜坡讯号 VRMP 的最大振幅也会与充电讯号 CHG的脉冲宽度 成比例。斜坡讯号 VRMP会对应于充电讯号 CHG的致能而产生，取 样讯号 SMP会伴随着充电讯号 CHG的禁能而产生，斜波讯号 VRMP 会因此而传送到电容 336用以产生整合讯号 VINT, 整合讯号 VINT 的振幅会与启动讯号 SA与停止讯号 SB 的期间成比例，此意味着整 合讯号 VINT 的振幅也会与切换电流讯号 VS 的期间成比例， 因此， 整合讯号 VINT 也可以表示先前的切换信息。 整合讯号 VINT透过 缓冲放大器 337与电阻 339、 330耦合于比较器 338， 电阻 339、 330 形成一分压器来提供衰减，比较器 338的另一个输入端接收斜波讯号 VRMP来产生脉冲讯号 SC， 当斜波讯号 VRMP高于整合讯号 VINT 时， 脉冲讯号 SC 会被致能， 而在停止讯号 SB 致能之前， 脉冲讯号 SC 就会产生。 在取样讯号 SMP截止前， 清除讯号 CLR会产生， 电 容 332会在取样后被清除。
图 9为讯号产生器 60的示意图， 如图 9所示， 讯号产生器 60包 含有触发器 601、 两单击电路（ one shot circuit )602、 604、 两反相器 603、 605、 或门 606， 触发器 601用以产生充电讯号 CHG, 启动讯号 SA被传送到触发器 601的设定端 S, 停止讯号 SB 则会被传送到触 发器 601的重置端 R， 充电讯号 CHG透过反相器 603传送到单击电 路 602， 单击电路 602会透过反相器 605产生取样讯号 SMP到另一 个单击电路 604， 单击电路 604的输出端连接于或门 606， 或门 606 的另一个输入端接收复位讯号 RST, 而输出端产生清除讯号 CLR。
图 10为单击电路 602、 604的电路示意图， 如图 10所示， 电流 源 650连接于电容 670并对应输入讯号 IN的高电位而对电容 670充 电， 输入讯号 IN透过反相器 651与晶体管 652而对电容 670放电， 且输入讯号 IN又传送到与门 680， 与门 680的另一个输入端透过反 相器 675连接到电容 670; 因此， 与门 680对应于输入讯号 IN的高 电位而产生单击输出讯号 OP, 单击输出讯号 OP的脉冲宽度系透过 电流源 650的电流值与电容 670的电容值来决定。
图 11 为同歩整流的波形示意图， 如图 11 所示， 切换电流讯号 VS 对应于包含有电流 IS1、 IS2 的变压器 10的切换电流 IS 而产生， 脉冲宽度 TPW显示启动讯号 SA与停止讯号 SB 的期间， 驱动讯号 VG1、 VG2 分别为集成同歩整流器 21、 22的驱动讯号 VG。 驱动讯 号藉 VG1 由脉冲讯号 SC1 来截止，而驱动讯号 VG2 藉由脉冲讯号 SC2 来截止， 驱动讯号 VG1、 VG2 的脉冲宽度 TON会短于脉冲宽 度 TPW。
图 12为本发明另一实施例示意图， 如图 12所示， 本实施例与实 施例一的区别在于： 使用两电流变压器 71、 72、 电阻 81、 82来转换 切换电流 IS 1、 IS2 至切换电流讯号 VS。
藉由上述， 本发明的柔性切换电源转换器的同歩整流电路， 可达 到针对柔性切换电源转换器提升其电源转换的效率。
虽然本发明以前述的较佳实施例揭露如上，然其并非用以限定本 发明， 任何熟习此技艺者， 在不脱离本发明的精神和范围内， 当可作 些许的更动与润饰，因此本发明之保护范围当视后附之权利要求书所 界定者为准。

Claims

1、 柔性切换电源转换器的同歩整流电路， 具有一变压器， 其特 征在于： 该同歩整流电路包含有：
一电流变压器，对应于该变压器的切换状态而产生一切换电流讯 号； 以及
一集成同歩整流器， 系包含有：
一功率晶体管，耦合于该变压器以及该电源转换器釣一输出端作 为整流之用； 以及
一控制器，依据该切换电流讯号产生一驱动讯号来控制该功率晶 体管； 其中当该切换电流讯号大于一第一临界值， 该控制器产生一启 动讯号， 当该切换电流讯号低于一第二临界值， 该控制器产生一停止 讯号， 且该启动讯号致能该驱动讯号用以开启该功率晶体管， 该停止 讯号禁能该驱动讯号用以关闭该功率晶体管。
2、根据权利要求 1所述的柔性切换电源转换器的同歩整流电路， 其特征在于： 其中该控制器包含有一脉冲宽度侦测电路， 用以产生一 整合讯号、一斜波讯号与一脉冲讯号， 其中该整合讯号系依据该启动 讯号与该停止讯号的期间而产生， 该斜波讯号依据该启动讯号而产 生，该脉冲讯号依据比较整合讯号与斜波讯号而产生并禁能该驱动讯 号来关闭该功率晶体管。
3、根据权利要求 1所述的柔性切换电源转换器的同歩整流电路， 其特征在于： 其中该控制器包含有一内锁电路， 该内锁电路依据该驱 动讯号的致能而产生一内锁讯号， 其中当内锁讯号禁能时， 会初始化 该驱动讯号。
4、根据权利要求 1所述的柔性切换电源转换器的同歩整流电路， 其特征在于： 其中该控制器包含有最大导通时间讯号， 用以关闭该功 率晶体管来限制功率晶体管的最大导通时间。
5、根据权利要求 1所述的柔性切换电源转换器的同歩整流电路， 其特征在于： 其中该控制器包含有：
一拴锁电路， 用以产生该驱动讯号来控制该功率晶体管； 以及 复数个比较器，用以产生一启动讯号与一停止讯号来设定或重置 该拴锁电路；
其中当该切换电流讯号高于该第一临界值， 该驱动讯号被致能， 当该切换电流讯号低于该第二临界值， 该驱动讯号被禁能。
6、根据权利要求 1所述的柔性切换电源转换器的同歩整流电路， 其特征在于：其中该控制器包含有一监控电路，用以产生一复位讯号， 其中当切换电流讯号的振幅低于一第三临界电压时，该复位讯号耦合 并禁能该功率晶体管。
7、根据权利要求 1所述的柔性切换电源转换器的同歩整流电 其特征在于：更包含有一二极管，以并联的方式连接于该功率晶体 且当该二极管启动时， 该功率晶体管会被开启。
PCT/CN2008/070976 2008-02-25 2008-05-15 柔性切换电源转换器的同步整流电路 WO2009105943A1 (zh)

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