WO2009094805A1 - Appareil de communication radio et procédé d'entrelacement - Google Patents

Appareil de communication radio et procédé d'entrelacement Download PDF

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Publication number
WO2009094805A1
WO2009094805A1 PCT/CN2008/000187 CN2008000187W WO2009094805A1 WO 2009094805 A1 WO2009094805 A1 WO 2009094805A1 CN 2008000187 W CN2008000187 W CN 2008000187W WO 2009094805 A1 WO2009094805 A1 WO 2009094805A1
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WIPO (PCT)
Prior art keywords
bits
parity
radio communication
column
communication apparatus
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PCT/CN2008/000187
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English (en)
Inventor
Kenichi Kuri
Kenichi Miyoshi
Akihiko Nishio
Shinsuke Takaoka
Hao Jiang
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Panasonic Corporation
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Priority to PCT/CN2008/000187 priority Critical patent/WO2009094805A1/fr
Publication of WO2009094805A1 publication Critical patent/WO2009094805A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Definitions

  • the present invention relates to a radio communication apparatus and interleaving method.
  • IMT-Advanced a fourth-generation mobile communication system called IMT-Advanced has been studied by the ITU-R (International Telecommunication Union Radio Communication Sector), and an LDPC (Low-Density Parity-Check) code is one of error correcting codes for implementing a downlink speed of up to 1 Gbps.
  • LDPC Low-Density Parity-Check
  • Use of an LDPC code as an error correcting code enables decoding processing to be parallelized, allowing decoding processing to be speeded up compared with the use of a turbo code that requires repeated serial execution of decoding processing.
  • LDPC encoding is performed using a parity check matrix containing a large number of Os and a small number of Is.
  • a transmitting-side radio communication apparatus encodes a transmission bit sequence using a parity check matrix, and obtains an LDPC codeword comprising systematic bits and parity bits.
  • a receiving- s ide radio communication apparatus decodes received data by iteratively executing passing of the likelihood of individual bits in the parity check matrix row direction and the parity check matrix column direction, and obtains a received bit sequence.
  • the number of Is contained in each column in a parity check matrix is called the column degree
  • the number of Is contained in each row in a parity check matrix is called the row degree.
  • a parity check matrix can be represented by a Tanner graph, which is a two-part graph comprising rows and columns.
  • a Tanner graph each row of a parity check matrix is called a check node, and each column of a parity check matrix is called a variable node.
  • Variable nodes and check nodes of a Tanner graph are connected in accordance with the arrangement of Is in the parity check matrix, and a receiving- side radio communication apparatus decodes receive data by iteratively executing passing of likelihoods between connected nodes, and obtains a received bit sequence.
  • Puncturing is a technology whereby specific bits of a codeword are thinned out. This enables a coding rate higher than the mother coding rate to be set.
  • an E 2 RC (Efficiently Encodable Rate Compatible) -LDPC code is available as an LDPC code which takes into consideration minimization of error rate performance degradation due to puncturing (see Non- Patent Document 1) .
  • the E 2 RC-LDPC code is comprised of a sub matrix corresponding to systematic bits and a sub matrix corresponding to parity bits. Furthermore, the sub matrix corresponding to parity bits is designed using a definition called "SR (Step-Recoverable)." SR is expressed by a tree structure where variable nodes and check nodes are connected in accordance with the arrangement of Is in the sub matrix corresponding to parity bits.
  • a variable node is expressed as an SR node based on the number of steps (order) from the end of the tree structure.
  • a variable node of order n is expressed as an "n-SR node.”
  • E 2 RC-LDPC code a parity bit corresponding to an SR node of higher order has a stronger relationship with parity bits corresponding to other SR nodes. Therefore, the E 2 RC-LDPC code can minimize degradation of the error rate performances by puncturing in order from a parity bit corresponding to an SR node of lower order.
  • a parity bit corresponding to a column closer to a column corresponding to a systematic bit becomes an SR node of lower order and has higher priority ranking of puncturing .
  • HARQ Hybrid ARQ
  • a receiving-side radio communication apparatus feeds back an ACK (Acknowledgment) signal as a response signal to the transmitting- side radio communication apparatus if there are no errors in receive data, and feeds back a NACK (Negative Acknowledgment) signal if there is an error.
  • the receiving-side radio communication apparatus combines retransmitted data from the transmitting-side radio communication apparatus with received data in the past, and decodes the combined data.
  • HARQ forms transmissiondata (e.g., RV: redundancy version) of each transmission.
  • transmissiondata e.g., RV: redundancy version
  • the use of a circular buffer i s under study to facilitate the configuration of transmission data of each transmission (see Non-Patent Document 2) .
  • the transmitting- side radio communication apparatus consecutively reads out transmission data that satisfies a desired coding rate (or desired code length) from the circular buffer in which the codeword is stored by changing the reading out start position for every retransmission.
  • a circular structured buffer circular buffer
  • Non-Patent Document 1 J. Kim, et al . "Design of Efficiently-Encodable Rate-Compatible Irregular LDPC Codes", ICC2006 pp.1131-1136
  • Non-Patent Document 2 Rl-072604, Ericsson, et al . "Way forward on HARQ rate matching for LTE", 3GPP TSG RAN WGl #49, Kobe, Japan, May 7-11, 2007
  • the transmitting- side radio communication apparatus may be unable to consecutively read out the LDPC codeword from the circular buffer and may read out the LDPC codeword intermittently.
  • the transmitting-side radio communication apparatus punctures two parity bits out of 12 bits of the LDPC codeword. That is, parity bits Pl and P2 with higher puncturing priority ranking are punctured. Therefore, the transmitting-side radio communication apparatus reads out systematic bits Sl to S 4 from the circular buffer, and sequentially skips parity bits Pl and P2 and reads out parity bits P3 to P8 from the circular buffer. In this way, when the LDPC codeword is stored in the circular buffer, the transmitting-side radio communication apparatus may be required to intermittently read out the LDPC codeword from the circular buffer. When the LDPC codeword is read out from the circular buffer intermittently, the transmitt ing- side radio communication apparatus needs to manage not only the reading start address but also addresses showing the positions of parity bits to be skipped. Therefore, reading processing at the circular buffer becomes complicated .
  • HARQ involves proces sing of reading out LDPC codewords corresponding to the number of retransmissions from the circular buffer. Therefore, HARQ involves processing of skipping parity bits to be punctured a plurality of times, which further complicates the reading processing in the circular buffer. [0012] Consequently, even when parity bit s are punctured, a technique of consecutively reading out LDPC codewords from the circular buffer is strongly demanded. [0013] 11 i s therefore an obj ect of the present invent ion to provide a radio communication apparatus and interleaving method capable of consecutively reading out LDPC codewords from a circular buffer.
  • a radio communication apparatus of the present invention employs a configuration having: an encoding section that performs LDPC coding on a transmission bit sequence using a parity check matrix to obtain a plurality of systematic bits and a plurality of parity bits; an interleaving section that sorts the plurality of parity bits according to a puncturing order; and a circular buffer that stores the plurality of systematic bits and the plurality of sorted parity bits.
  • FIG.l is a block diagram showing a transmi tting-side radio communication apparatus according to Embodiment 1 of the present invention.
  • FIG.2 shows a parity check matrix according to Embodiment 1 of the present invention
  • FIG.3 shows a Tanner graph of a sub matrix corresponding to parity bits according to Embodiment 1 of the present invention
  • FIG.4 shows a tree structure of the sub matrix corresponding to parity bits according to Embodiment 1 of the present invention
  • FIG.5 shows storing processing according to Embodiment 1 of the present invention
  • FIG.6 shows reading processing according to Embodiment 1 of the present invention
  • FIG.7 is a block diagram showing a configuration of a receiving-side radio communication apparatus according to Embodiment 1 of the present invention.
  • FIG.8 shows received data generation processing according to Embodiment 1 of the present invention (when transmission data is received for the first time);
  • FIG.9 shows received data generation processing according to Embodiment 1 of the present invention (when transmission data is received for the second time);
  • FIG.10 shows column conversion of a parity check matrix according to Embodiment 2 of the present invention;
  • FIG.11 shows storing processing and reading processing according to Embodiment 2 of the present invention.
  • FIG.12 shows column conversion of a parity check matrix according to Embodiment 3 of the present invention.
  • FIG.13 shows storing processing and reading processing according to Embodiment 3 of the present invent ion.
  • a plurality of parity bits are sorted according to orders of SR nodes corresponding to the parity bits.
  • FIG.l shows the configuration of transmitting- s ide radio communication apparatus 100 according to the present embodiment.
  • a transmission bit sequence is input to CRC (Cyclic Redundancy Check) section 101.
  • CRC section 101 performs error detecting encoding on the transmission bit sequence using CRC and outputs the transmission bit sequence to which CRC parity bits are added, to encoding section 102.
  • Encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using a parity check matrix to obtain an LDPC codeword comprised of a plurality of systematic bits and parity bits.
  • an E 2 RC-LDPC code is used as the LDPC code.
  • encoding section 102 outputs the LDPC codeword to interleaver 103.
  • Interleaver 103 sorts the LDPC codeword inputted from encoding section 102 according to the puncturing order. More specifically, interleaver 103 sorts a plurality of parity bits according to orders of SR nodes corresponding to the parity bits. Furthermore, interleaver 103 sorts the plurality of systematic bits in reverse order and outputs the sorted LDPC codeword to transmission circular buffer 104. The sorting processing at interleaver 103 will be described later in detail.
  • Transmission circular buffer 104 stores the LDPC codeword inputted from interleaver 103 in a memory of a cyclic reading type buffer. Furthermore, transmission circular buffer 104 reads out the LDPC codeword from the memory according to a coding rate of the read LDPC codeword and an RV parameter showing the reading start position inputted from control section 112 , and outputs the read LDPC codeword to modulation section 105. The storing processing and reading processing at transmission circular buffer 104 will be described later in detail. [0024] Modulation section 105 modulates the LDPC codeword inputted from transmission circular buffer 104 to generate data symbols and outputs the data symbols to multiplexing section 106.
  • Multiplexing section 106 multiplexes the data symbols, a pilot signal and a control signal inputted from control section 112 and outputs the generated multiplexed signal to radio transmitting section 107.
  • Radio transmitting section 107 performs transmission processing such as D/A conversion, ampIi fi cat ion and up-conversion on the multiplexed signal and transmits the signal from antenna 108 to a receiving-side radio communication apparatus.
  • radio receiving section 109 receives a control signal transmitted from the receiving- side radio communication apparatus through antenna 108, performs reception processing such as down-conversion and A/D conversion on the control signal and outputs the control signal to demodulation section 110.
  • This control signal includes a CQI (Channel Quality Indicator) and response signal generated by the receiving-side radio communication apparatus.
  • CQI Channel Quality Indicator
  • Demodulation section 110 demodulates the control signal and outputs the demodulated signal to decoding s e c t i on 1 1 1 .
  • Decoding section 111 decodes the control signal and outputs the CQI and response signal included in the control signal to control section 112.
  • Control section 112 controls the systematic bit length of the read LDPC codeword, read coding rate and RV parameter according to the CQI. Control section 112 then determines the systematic bit length, coding rate and RV parameter corresponding to the inputted CQI and outputs control information showing the determined systematic bit length, coding rate and RV parameter to transmission circular buffer 104 and multiplexing section 106. Control section 112 determines a lower coding rate for a CQI corresponding to channel quality with a lower inputted CQI . Furthermore, control section 112 controls retransmission of transmission data based on the response signal inputted from decoding section 111. [0031] Next, the sorting processing at interleaver 103 and storing processing at transmission circular buffer 104 will be described in detail.
  • FIG.2 shows an 8-rows * 12-columns parity check mat rix as an example .
  • a pari ty check matrix is represented by a matrix of M rows * N columns, and comprises Os and Is.
  • sub matrix Hi corresponding to systematic bits
  • sub matrix H 2 corresponding to parity bits
  • decription of sub matrix Hi corresponding to systematic bits will be omitted.
  • Each column of the parity checkmatrix correspond to a coded bit of the LDPC codeword. That is, when LDPC encoding is performed using the parity check matrix shown in FIG.2, a 12-bit LDPC codeword (systematic bits Sl to S4 and parity bits Pl to P8) is generated. [0034] Further, in sub matrix H 2 of the parity check matrix shown in FIG.2, the column degree of the fifth column (parity bit Pl) is the number of Is on the fifth column, that is, two, and the column degree of the sixth column (parity bit P2) is the number of Is on the sixth column, that is, two. The same will apply to the seventh column to twelfth column (parity bits P3 to P8) .
  • the row degree of the first row is the number of Is, that is, one
  • the row degree of the second row is the number of Is, that is, one. The same will apply to the third to eighth rows.
  • the parity check matrix shown in FIG.2 can be expressed by a Tanner graph comprised of rows and columns of the parity check matrix.
  • FIG.3 shows a Tanner graph corresponding to sub matrix H 2 of the parity check matrix in FIG.2.
  • the Tanner graph comprises check nodes corresponding to the rows of the parity check matrix and variable nodes corresponding to the columns of the parity check matrix. That is, the Tanner graph corresponding to an 8-rows x 8-columns sub matrix H 2 is a two-part graph comprising eight check nodes and eight variable nodes.
  • each variable node of the Tanner graph corresponds to each coded bit of the LDPC codeword.
  • variable nodes and check nodes of the Tanner graph are connected in accordance with the arrangement of Is in the parity check matrix.
  • the column degree of the fifth column of the parity check matrix is two, and the rows in which a 1 is located in the fifth column are the first row and fifth row. Therefore, there are two connections at variable node Pl ; check node 1 and check node 5.
  • the column degree of the sixth column of the parity check matrix is two, and the rows in which a 1 is located in the sixth column are the second row and sixth row. Therefore, there are two connections at variable node P2; check node 2 and check node 6. The same will apply to variable node P3 to variable node P8.
  • the row degree of the first row of sub matrix H 2 of the parity check matrix is one, and the column in which a 1 is located in the first row is the first column. Therefore, there is one connection at check node 1 ; variable node Pl.
  • the row degree of the second row of sub matrix H 2 of the parity check matrix is one, and the column in which a 1 is located in the second row is the second column. Therefore, there is one connection at check node 2; variable node P2.
  • check node 3 to check node 8.
  • variable nodes and check nodes are connected in accordance with the arrangement of Is in a parity check matrix. That is, the number of check nodes connected to each variable node in a Tanner graph is equal to the column degree of each column in a parity check matrix.
  • check nodes to which each variable node is connected in a Tanner graph are check nodes corresponding to rows in which a 1 is located in each column of a parity check matrix.
  • the number of variable nodes connected to each check node in a Tanner graph is equal to the row degree of each row in a parity check matrix
  • variable nodes to which each check node is connected in a Tanner graph are variable nodes corresponding to columns in which a 1 is located in each row of a parity check matrix.
  • the Tanner graph corresponding to sub matrix H 2 shown in FIG.3 can be expressed by a tree structure .
  • FIG.4 shows a tree structure corresponding to the Tanner graph shown in FIG.3.
  • the tree structure is different from the Tanner graph in notation, they are equivalent to each other. That is, the tree structure shown in FIG.4 is comprised of check nodes corresponding to rows of the parity check matrix and variable nodes corresponding to columns of the parity check matrix in the same way as the Tanner graph shown in FIG.3. [0046] Furthermore, in the tree structure, the variable node corresponding to each parity bit is defined as an SR node.
  • paritybits Pl to P4 located at the end of the tree structure are defined as 1-SR nodes. Furthermore, parity bit P5 connected to parity bit Pl corresponding to the 1-SR node through check node 5 i s de fined as a 2-SR node . Inaddition, parity bit P6 connected to parity bit P2 corresponding to the 1-SR node through check node 6 is defined as a 2-SR node.
  • parity bit P7 connected to parity- bit P5 corresponding to the 2-SR node through check node 7 is defined as a 3-SR node
  • parity bit P8 connected to parity bit P7 corresponding to the 3-SR node through check node 8 is defined as a 4-SR node.
  • error correcting decoding is performed in order from a parity bit corresponding to an SR node of lower order.
  • error-correcting decoding is performed on parity bit P6 corresponding to the 2-SR node shown in FIG.4, parity bit P2 corresponding to the 1-SR node is subjected to error correcting decoding through check node 2 (first step) .
  • parity bit P6 corresponding to the 2-SR node is subjected to error correcting decoding through check node 6 (second step) .
  • a parity bit corresponding to an SR node of higher order has a higher degree of relativity with other parity bits.
  • a parity bit corresponding to a lower order SR node has a lower degree of relativity with other parity bits.
  • transmission circular buffer 104 cyclically reads out an LDPC codeword sequentially from the head of a buffer as transmission data to be transmitted to a receiving-side radio communication apparatus. That is, transmission circular buffer 104 can hardly transmit an LDPC codeword stored in the tail end of the buffer with fewer transmissions. In other words, transmission circular buffer 104 can easily puncture an LDPC codeword stored in the tail end of the buffer. Therefore, when an E 2 RC-LDPC codeword is stored in transmission circular buffer 104, it is preferable to store in the tail end of the buffer parity bits with less degradation of the error rate performances due to puncturing, that is, parity bits corresponding to lower order SR nodes.
  • interleaver 103 sorts a plurality of parity bits according to orders of SR nodes corresponding to parity bits. [0052] This will be described below more specifically.
  • the transmission bit sequence length is 4 bits
  • LDPC codeword length N is twelve bits
  • systematic bit length K determined by control section 112 is 4 bits and coding rate R is 1/2.
  • int erleaver 103 sort s a plurality of parity bits of an LDPC codeword such that parity bits corresponding to SR nodes of lower order are arranged closer to the tail end. That is, interleaver 103 sorts parity bits in descending order of SR node order. More specifically, interleaver 103 compares orders of corresponding SR nodes between parity bits Pl to P8 (fifth column to twelfth column of the parity check matrix shown in FIG.2) of the tree structure shown in FIG.4.
  • interleaver 103 makes comparisons between order 1 of SR node (1-SR) corresponding to parity bit Pl, order 1 of SR node (1-SR) corresponding to parity bit P2, order 1 of SR node (1-SR) corresponding to parity bit P3, order
  • variable node P8 (twelfth column) is first
  • variable node P7 (eleventh column)
  • variable node P6 tenth column
  • variable node 5 (ninth column)
  • variable nodes P4 to Pl (eighth column to fifth column) are fifth.
  • parity bits Pl to P8 puncturing priority ranking
  • parity bits Pl to P4 parity bits Pl to P4 (fifth column to eighth column) are first
  • parity bit P5 noth column
  • parity bit P6 tenth column
  • parity bit P7 extracth column
  • parity bit P8 twelfth column
  • interleaver 103 sorts systematic bits of an LDPC codeword in reverse order. More specifically, as shown in FIG.5, interleaver 103 sorts the order of systematic bits Sl to S4 (first column to fourth column) to systematic bits S4 to Sl (fourth column to first column) .
  • interleaver 103 sorts the order of the 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bits Pl to P8 to systematic bits S4 to Sl and parity bits P8 to Pl.
  • transmission circular buffer 104 stores the LDPC codeword sorted in order of systematic bits S4 to Sl and parity bits P8 to Pl.
  • parity bits stored closer to the tail end of the buffer have higher puncturing priority ranking.
  • first retransmission data are comprised of four systematic bits and four parity bits.
  • transmission circular buffer 104 reads out an 8-bit LDPC codeword in order from systematic bit S4 which is the initial bit of the buffer as the first transmission data (initial transmission data) at the first transmission (initial transmission) . More specifically, transmission circular buffer 104 outputs the 8-bit LDPC codeword comprised of four systematic bits S4 to Sl and four parity bits P8 to P5, to modulation sect ion 105.
  • transmission circular buffer 104 reads out the 8-bit LDPC codeword in order from parity bit P4 following parity bit P5, which is the last bit of the first transmission data (initial transmission data) as the second transmission data (first retransmission data) . More specifically, transmission circular buffer 104 outputs the 8-bit LDPC codeword comprised of four parity bits P4 to Pl and four systematic bits S4 to Sl, to modulation section 105. [0059] Here, as shown in FIG.6, the bits not transmitted at the first transmission (initial transmission) are four parity bits Pl to P4.
  • parity bits Pl to P4 are punctured at the first transmission (initial transmission) .
  • the bits not transmitted at the second transmission (first retransmission) are four parity bits P5 to P8. That is, four parity bits P5 to P8 are punctured at the second transmission (first retransmission) .
  • transmission circular buffer 104 punctures in order from parity bits Pl to P8, that is, in order from a parity bit having the highest puncturing priority ranking, at the first transmission (initial transmission) and the second transmission (first retransmission).
  • transmission circular buffer 104 can generate an LDPC codeword with sequentially punctured parity bits in order from a parity bit with higher puncturing priority ranking by only cyclically reading out eight consecutive bits from the head of the buffer at the first transmission (initial transmission) .
  • transmission circular buffer 104 can generate an LDPC codeword with parity bits punctured according to puncturing priority ranking by only cyclically reading out eight consecutive bits in order from the bit following the last bit of the first transmission data (initial transmission data) at the second transmission (first retransmission) .
  • transmitting-side radio communication apparatus 100 sorts a plurality of parity bits such that a parity bit having higher puncturing priority ranking is stored in the tail end of transmission circular buffer 104. Therefore, according to the E 2 RC-LDPC code, parity bits located closer to systematic bits have higher puncturing priority ranking, and so parity bits are sorted in reverse order. Furthermore, transmitting-side radio communication apparatus 100 also sorts a plurality of systematic bits in reverse order. By this means, although the bits of an LDPC codeword are sorted in reverse order, it is possible to store the bits in transmission circular buffer 104 while keeping the order of Sl to S4 and Pl to P8.
  • FIG.7 shows the configuration of receiving- side radio communication apparatus 200 according to this embodiment.
  • radio receiving section 202 receives a multiplexed signal transmitted from transmitting- side radio communication apparatus 100 (FIG.l) through antenna 201 , performs reception processing such as down-conversion and A/D conversion on the received signal and outputs the signal subjected to reception processing to separation section 203.
  • This received signal includes a control signal specifying data symbols, pilot signal, and systematic bit length, coding rate and RV parameter determined by transmitting-side radio communication apparatus 100.
  • Separation section 203 separates the received signal into the data symbols, the pilot signal and the control signal. Further, separation section 203 outputs the data symbols to demodulation section 204, the pilot signal to channel quality estimation section 209 and the control signal to reception circular buffer 205 and deinterleaver 206.
  • Demodulation section 204 demodulates the data symbols to obtain received data comprised of a plurality of bits and outputs the received data to reception circular buffer 205.
  • Reception circular buffer 205 stores likelihood information of a plurality of bits forming received data inputted from demodulation section 204 in a memory of a cyclic reading type buffer similar to transmission circular buffer 104 (shown in FIG.l) in accordance with the coding rate and RV parameter specified by control information inputted from separation section 203.
  • reception circular buffer 205 pads bit positions in which no received data has been stored with padding bits where an LLR (Log-Likelihood Ratio) is zero. Further, reception circular buffer 205 reads out likelihood information of all the bit positions in which received data has been stored and outputs the read likelihood information to deinterleaver 206.
  • LLR Log-Likelihood Ratio
  • reception circular buffer 205 specifies received bits forming the received data based on the control information (i.e., coding rate and RV parameter) inputted from separation section 103, combines the received data with the saved data, saves the obtained data and outputs the data to deinterleaver 206. Furthermore, when an ACK signal is received from error detecting section 208, that is, when the received data includes no error, reception circular buffer 205 discards the saved received data. Storing processing and reading processing at reception circular buffer 205 will be described later in detail. [0067] Deinterleaver 206 sorts likelihood information inputted from reception circular buffer 205 according to the puncturing order.
  • the control information i.e., coding rate and RV parameter
  • deinterleaver 206 sorts a plurality of parity bits according to orders of SR nodes corresponding to parity bits in the same way as interleaver 103 (shown in FIG.l) . Furthermore, deinterleaver 206 sorts likelihood information of a plurality of systematic bits in reverse order, and outputs the likelihood information of the sorted plurality of bits to decoding section 201. The sorting processing at deinterleaver 206 will be described later in detail .
  • Decoding section 207 performs LDPC decoding on the likelihood information inputted from deinterleaver 206 using the same parity check matrix as the parity check matrix (shown in FIG .2 ) used by encoding section 102 (shown in FIG.l) to obtain a decoded bit sequence.
  • Decoding section 207 outputs the decoded bit sequence to error detecting section 208.
  • Error detecting section 208 performs error detecting on the decoded bit sequence inputted from decoding section 207.
  • error detecting section 208 When the error detecting result shows that decoded bits contain error, error detecting section 208 generates a NACK signal as a response signal and outputs the NACK signal to reception circular buffer 205 and control signal generation section 210, and, when the decoded bits contain no errors, generates an ACK signal as a response signal and outputs the ACK signal to reception circular buffer 205 and control signal generation section 210. Furthermore, when the decoded bits contain no errors , error detecting section 208 outputs the decoded bit sequence as a received bit sequence.
  • channel quality estimation section 209 estimates channel quality using a pilot signal inputted from separation section 203.
  • channel quality estimation section 209 estimates an SINR (Signal to Interference and Noise Ratio) of the pilot signal as channel quality and outputs the estimated SINR to control signal generation section 210.
  • SINR Signal to Interference and Noise Ratio
  • Control signal generation section 210 generates a CQI corresponding to the SINR inputted from channel quality estimation section 209. Further, control signal generation section 210 outputs to encoding section 211 a control signal including the generated CQI and the response signal inputted from error detecting section 208. [0072] Encoding section 211 encodes on the control signal and outputs the encoded control signal to modulation section 212.
  • Modulation section 212 modulates the control signal and outputs the modulated control signal to radio transmitting section 213.
  • Radio transmitting section 213 performs transmission processing such as D/A conversion, amplification and up-conversion on the control signal and transmits the control signal from antenna 201 to transmitting- side radio communication apparatus 100 (shown in FIG.1 ) .
  • reception circular buffer 205 identifies that thebuffer size is 12 (Kx ( 1/R m ) ) bits and the received data length is 8 (Kx (1/R)) bits.
  • the start position of the received data in the circular buffer specified by an RV parameter at which the first transmission data (initial transmission data) is received is the first position of the buffer and the start position of the received data in the circular buffer specified by the RV parameter at which the second transmission data (first retransmission data) is received is the ninth position of the buffer .
  • reception circular buffer 205 pads the ninth to twelfth bit positions of the buffer with 4 padding bits Pad.
  • 12 bits of Rl to R8, Pad, Pad, Pad, Pad, Pad, that is, S4, S3, S2, Sl, P8, P7, P6, P5, Pad, Pad, Pad, Pad, Pad are stored in reception circular buffer 205.
  • the received data read out from reception circular buffer 205 are S4, S3, S2, Sl, P8, P7, P6, P5, Pad, Pad, Pad, Pad.
  • deinterleaver 206 sorts the 12 -bit received data inputted from reception circular buffer 205 in reverse order from the fourth bit of the received data. More specifically, as shown in FIG.8, deinterleaver 206 sorts systematic bit Sl (which is the first position in the sorting order) located at the fourth position of the buffer to parity bit P8 (which is the twelfth position in the sorting order) located at the fifth position in reverse order.
  • Sl which is the first position in the sorting order
  • parity bit P8 which is the twelfth position in the sorting order
  • this 12-bit data comprised of Sl, S2, S3, S4, Pad, Pad, Pad, Pad, P5, P6, P7, P8 is inputted to decoding section 207.
  • the received data length specified by the control information is eight bits and the start position of the received data specified by the RV parameter is the ninth position, so that reception circular buffer 205 stores received data Rl to R8 (P4 to Pl, S4 to Sl) sequentially from the ninth bit pos it ion of the buffer .
  • reception circular buffer 205 stores Rl to R4 in the ninth to twelfth bit positions of the buffer, respectively, and stores R5 to R8 in the first to fourth bit positions of the buffer, respectively.
  • reception circular buffer 205 combines R5 to R8 stored in the first to fourth bit positions of the buffer with S4 to Sl already saved at the first to fourth bit positions of the buffer.
  • 12 bits of S4, S3, S2, Sl, P8, P7, P ⁇ , P5, P4, P3, P2, Pl are stored in reception circular buffer 205.
  • the transmitting-side radio communication apparatus stores parity bits with higher puncturing priority ranking in positions closer to the tail end of the transmission circular buffer. That is, when an LDPC codeword is retransmitted, the LDPC codeword is punctured in order from parity bits with higher puncturing priority ranking.
  • the transmitt ing-side radio communication apparatus sorts a plurality of systematic bits in reverse order. This makes rules for sorting of systematic bits and parity bits, that is, the entire LDPC codeword, the same.
  • the receiving-side radio communication apparatus identifies the start bit of systematic bits and sorts bits in reverse order from the start bit, so that it is possible to obtain the LDPC codeword generated by the transmitting-side radio communication apparatus. Thatis, the receiving-side radio communication apparatus can sort without distinguishing between systematic bits and parity bits of the received data stored in the reception circular buffer.
  • Embodiment 2 in a parity check matrix, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to likelihoods of including errors in systematic bits.
  • Embodiment 1 While a case has been described with Embodiment 1 where a read coding rate is higher than a mother coding rate, a case will be taken into consideration with the present embodiment where the read coding rate is lower than the mother coding rate.
  • One of methods of setting a coding rate lower than the mother coding rate is repetition. Repetition is a technique of generating a plurality of identical bits by replicating (repeating) a specific bit of an LDPC codeword. By this means, it is possible to set a coding rate lower than the mother coding rate. Furthermore, the receiving side can obtain a diversity effect by bit-combining those identical bits.
  • the receiving-side radio communication apparatus transfers likelihoods between variable nodes through check nodes and decodes received data by iteratively updating the likelihood of each variable node,
  • variable nodes connected to more check nodes that is, variable nodes having larger column degrees have a larger number of likelihoods received from checknodes. That is, when the column degrees of variable nodes become larger, the effect of updating likelihood becomes larger, so that the error rate performances improve.
  • variable nodes when the column degrees of variable nodes become smaller, the effect of updating likelihood becomes smaller, and consequently the error rate performances degrade. Therefore, when variable nodes are repeated, it is preferable to repeat variable nodes which have smaller column degrees and which are likely to include errors preferentially to complement and improve likelihoods . Thatis, when the column degrees of variable nodes become smaller, the effect of improving likelihoods becomes larger through repetition. [0089] With the present embodiment, column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits in a parity check matrix according to column degrees of systematic bits.
  • Encoding section 102 (shown in FIG.l) of transmitting- side radio communication apparatus 100 according to the present embodiment performs column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix according to column degrees of systematic bits. Further, encoding section 102 performs LDPC coding on a transmission bit sequence inputted from CRC section 101 using the parity check matrix subjected to column conversion .
  • encoding section 102 serves as an encoding section for encoding a transmission bit sequence and as a conversion section for performing column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix.
  • Encoding sect ion 102 compares column degrees (i.e. the number of connections to check nodes) among the first to fourth columns corresponding to systematic bits Sl to S4 of the parity check matrix shown in the upper part of FIG.10. That is, encoding section 102 makes comparisons between column degree 3 (where the number of connections to check nodes in variable node 1 is 3) of the first column, column degree 3 (where the number of connections to check nodes in variable node 2 is 3) of the second column, column degree 4 (where the number of connections to check nodes in variable node 3 is 4) of the third column and column degree 4 (where the number of connections to check nodes in variable node 4 is 4) of the fourth column.
  • Encoding section 102 then performs column conversion in such a way that columns are arranged in descending order of column degrees of systematic bits. That is, encoding section 102 converts the third column and fourth column shown in the upper part of FIG.10 to the first column and second column as shown in the lower part of FIG.10, respectively, and converts the first column and second column shown in the upper part of FIG.10 to the third column and fourth column as shown in the lower part of FIG .10 , respectively.
  • encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix shown in the lower part of FIG.10, to obtain a 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bit s Pl to P8.
  • interleaver 103 sorts the LDPC codeword in the same way as Embodiment 1. More specifically, as shown in FIG.11, interleaver 103 sorts systematic bits S4 to Sl andparitybits P8 to Pl in that order. Therefore, as shown in FIG.11, transmission circular buffer 104 stores in the head of the buffer a plurality of systematic bits in ascending order of column degrees from systematic bit S4, and stores in the buffer a plurality of parity bits in ascending order of the puncturing priority ranking from parity bit P8. [0097] Next, the reading processing in transmission circular buffer 104 will be described in detail.
  • LDPC codeword length N I 2.
  • systematic bit length K of the first transmission data is four bits and coding rate R is 2/7.
  • systematic bit length K of second transmission data is two bits and coding rate R is 1/4. That is, the first transmission data (initial transmission data) is comprised of four systematic bits and ten parity bits (including two repetition bits) , and the second transmission data (first retransmission data) is comprised of two systematic bits and six parity bits.
  • circular buffer 104 reads out a 14-bit LDPC codeword in order from systematic bit S4 which is the start bit of the buffer as the first transmission data (initial transmission data) . More specifically, transmission circular buffer 104 outputs to modulation section 105 a 14 -bit LDPC codeword comprised of four systematic bits S4 to Sl, eight parity bits P8 to Pl and two systematic bits S4 and S3 as repetition bits.
  • transmission circular buffer 104 reads out an 8-bit LDPC codeword in order from systematic bit S2 which is the bit following systematic bit S3 at the tail end of the first transmission data (initial transmission data) as the second transmission data (first retransmission data) . More specifically, transmission circular buffer 104 outputs to modulation section 105 an 8 -bit LDPC codeword comprised of two systematic bits S2 and Sl and six parity bits P8 to P3.
  • decoding section 207 (shown in FIG.7) of receiving-side radio communication apparatus 200 performs column conversion on the parity check matrix in the same way as encoding section 102 and decodes the received data using the parity check matrix subjected to the column conversion. That is, according to the present embodiment, decoding section 207 serves as a decoding section that decodes the received data and as a conversion section that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits in the parity check matrix.
  • interleaver 103 may also sort systematic bits of the LDPC codeword instead of performing column conversion on the parity check matrix More specifically, interleaver 103 sorts a plurality of systematic bits of the LDPC codeword obtained through LDPC coding using the parity check matrix shown in the upper part of FIG.10 in descending order of column degrees . By this means, transmission circular buffer 104 stores systematic bits in ascending order of column degrees, so that it is possible to obtain effects similar to those in the present embodiment. [0103] (Embodiment 3)
  • Embodiment 2 where column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to column degrees of systematic bits
  • a case will be described with the present embodiment where column conversion is performed on a plurality of columns corresponding to a plurality of systematic bits according to total row degrees .
  • variable nodes having a smaller total number of connections to variable nodes through check nodes that is, variable nodes having smaller total row degrees may be repeated preferentially to complement and increase likelihoods. That is, when the total row degrees of variable nodes become smaller, the effect of improving likelihoods becomes larger through repetition.
  • Encoding section 102 (shown in FIG.l) of transmitting-side radio communication apparatus 100 according to the present embodiment performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix according to total row degrees. Furthermore, encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix subjected to the column conversion.
  • encoding section 102 serves as an encoding section that performs encoding on the transmission bit sequence and as a conversion section that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix.
  • Encoding section 102 compares total row degrees (i.e., the total number of connections to variable nodes connected through check nodes) in the first column to fourth column corresponding to systematic bits Sl to S4 of the parity check matrix shown in the upper part of FIG.12.
  • encoding section 102 makes comparisons among a total number of Is (eleven) located in the third row, fifth row and seventh row in which a 1 is located in the first column in FIG.12 (i.e., total number of connections (eleven connections) to variable nodes connected to variable node 1 through check node 3, check node 5 and check node 7) , a total number of Is (nine) located in the second row, third row and sixth row in which a 1 is located in the second column (i.e., total number of connections (nine connections) to variable nodes connected to variable node 2 through check node 2, check node 3 and check node 6), a total number of Is (eight) located in the first row, second row and fourth row in which a 1 is located in the third column (i.e., total number of connections (eight connections) to variable nodes connected to variable node 3 through check node 1, check node 2 and check node 4) , and a total number of Is (thirteen) located on a
  • encoding section 102 performs column conversion on the parity check matrix such that columns are arranged in descending order of total row degrees of systematic bits. That is, encoding section 102 converts the fourth column shown in the upper part of FIG.12 to the first column as shown in the lower part of FIG.12 and converts the first column to third column shown in the upper part of FIG.12 to the second column to fourth column as shown in the lower part of FIG.12.
  • the column degrees of the first column to fourth column in the parity check matrix subjected to the column conversion shown in the lower part of FIG.12 are (13, 11, 9, 8), that is, the total degrees are arranged in descending order of total row degrees.
  • encoding section 102 performs LDPC coding on the transmission bit sequence inputted from CRC section 101 using the parity check matrix shown in the lower part of FIG.12 to obtain a 12-bit LDPC codeword comprised of four systematic bits Sl to S4 and eight parity bits Pl to P8.
  • the total row degree of systematic bit Sl is thirteen
  • the total row degree of systematic bit S2 is eleven
  • the total row degree of systematic bit S3 is nine
  • the total row degree of systematic bit S4 is eight .
  • interleaver 103 sorts an LDPC codeword in order from systematic bits S4 to Sl and parity bits P8 to Pl. Therefore, as shown in FIG.13, transmission circular buffer 104 stores a plurality of systematic bits in the head of the buffer in order from systematic bit S4 having a smaller total row degree, and stores a plurality of parity bits in order from parity bit P8 with lower puncturing priority ranking.
  • transmission circular buffer 104 outputs to modulation section 105 a 14-bit LDPC codeword comprised of four systematic bits S4 to Sl and eight parity bits P8 to Pl, and two systematic bits S4 and S3 as repetition bits at the first transmission (initial transmission) . Furthermore, as shown in FIG.13, similar to Embodiment 2, transmission circular buffer 104 outputs to modulation section 105 an 8-bit LDPC codeword comprised of two systematic bits S2 and Sl and six parity bits P8 to P3 at the second transmission (first retransmission) .
  • decoding section 207 (shown in FIG.7) of receiving-side radio communication apparatus 200 performs column conversion on the parity check matrix in the same way as encoding section 102 and decodes the received data using the parity check matrix subjected to the column conversion. That is, with the present embodiment, in the same way as Embodiment 2, decoding section 207 serves as a decoding section that decodes received data and as a conversion section that performs column conversion on a plurality of columns corresponding to a plurality of systematic bits of the parity check matrix .
  • interleaver 103 can also sort systematic bits of an LDPC codeword instead of performing column conversion on the parity check matrix. More specifically, interleaver 103 sorts a plurality of systematic bits of an LDPC codeword obtained through LDPC coding using the parity check matrix shown in the upper part of FIG.12 in descending order of total row degrees. By this means, systematic bits are stored in transmission circular buffer 104 in ascending order of total row degrees, so that it is possible to obtain effects similar to those in the present embodiment.
  • a padding bit used in the above embodiments may be either a 1 or a 0, as long as this is known (common) to both the transmitting-side radio communication apparatus and receiving-side radio communication apparatus.
  • a padding bit sequence may be a sequence of all 0s, a sequence of all Is, or a common sequence comprising Os and Is.
  • the error detecting codes for the transmitting-side radio communication apparatus are not limited to CRC codes.
  • the RV parameter may not be used. For example, when the first transmission data (initial transmission data) is received, the receiving- side radio communication apparatus may sequentially store received data from the head of the buffer and sequentially store received data starting from the bit position following the bit position in the tail end of the received data stored upon receiving the first transmission data (initial transmission data) .
  • the receiving- s ide radio communication apparatus can specify the position for storing the received data without using control information from the transmitting-side radio communication apparatus.
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • the present invention is implemented in a TDD system.
  • correlativity between uplink propagation path characteristics and downlink propagation path characteristics is extremely high, and therefore t ransmitt ing-s ide radio communication apparatus 100 can estimate reception quality in receiving-side radio communication apparatus 200 using a signal from receiving-side radio communication apparatus 200. Therefore, in the case of a TDD system, channel quality may be estimated by transmitting-side radio communication apparatus 100 without having receiving-side radio communication apparatus 200 issue a channel quality notification by means of a CQI..
  • parity check matrixes of FIG.2, FIG.10 and FIG.12 are shown as examples, and the parity check matrixes that can be used for the present embodiments are not limited to the parity check matrixes shown in FIG.2, FIG.10 and FIG.12.
  • the systernatic bit length and coding rate set by control section 112 of transmitting- side radio communication apparatus 100 are not limited to those determined according to channel quality and may also be fixed to certain values.
  • SINR is estimated as channel quality, but SNR, SIR, CINR, received power, interference power, bit error rate, throughput, an MCS
  • CQI Channel State Information
  • variable nodes may also be referred to as "bit nodes.”
  • transmitting-side radio communication apparatus 100 can be provided in a radio communication base station apparatus, and receiving- side radio communication apparatus 200 can be provided in a radio communication mobi Ie stat ion apparatus .
  • transmitting- side radio communication apparatus 100 can be provided in a radio communication mobile station apparatus, and receiving-side radio communication apparatus 200 can be provided in a radio communication base station apparatus.
  • a radio communication base station apparatus and radio communication mobile station apparatus can be implemented that offer the same kind of operation and effects as described above.
  • the radio communication mobile station apparatus may also be referred to as a "UE," and radio communication base station apparatus may also be referred to as "Node B.”
  • each function block employed in the description of each of the aforementioned embodiments may typically be implemented as an LSI constituted by an integrated circuit. These may be individual chips or partially or totally contained on a single chip. "LSI” is adopted here but this may also be referred to as "IC,” “system LSI,” “super LSI,” or “ultra LSI” depending on differing extents of integration.
  • the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. After LSI manufacture, utilization of an FPGA (Field Programmable Gate Array) or a reconfigurable processor where connections and settings of circuit cells in an LSI can be reconfigured is also possible. [0136] Further, if integrated circuit technology comes out to replace LSI 1 S as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Application of biotechnology is also possible.
  • the present invention is applicable to a mobile communication system or the like.

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Abstract

La présente invention concerne un appareil de communication radio pouvant extraire consécutivement un mot de code LDPC d'une mémoire tampon circulaire. Dans cet appareil, une section de codage 102 réalise le codage LDPC sur une séquence binaire de transmission entrée depuis une section CRC 101 à l'aide d'une matrice de contrôle de parité pour obtenir un mot de code LDPC composé d'une pluralité de bits systématiques et d'une pluralité de bits de parité. Un entrelaceur 103 trie le mot de code LDPC entré depuis la section de codage 102 selon un ordre de perforation. La mémoire tampon circulaire de transmission 104 stocke le mot de code LDPC entré depuis l'entrelaceur 103 dans une mémoire d'une mémoire tampon à lecture cyclique.
PCT/CN2008/000187 2008-01-25 2008-01-25 Appareil de communication radio et procédé d'entrelacement WO2009094805A1 (fr)

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