WO2009093285A1

WO2009093285A1 - Plasma display unit and method for controlling the same

Info

Publication number: WO2009093285A1
Application number: PCT/JP2008/000083
Authority: WO
Inventors: Nobuyoshi Kondo; Takashi Sasaki; Tetsuya Sakamoto
Original assignee: Hitachi, Ltd.
Priority date: 2008-01-24
Filing date: 2008-01-24
Publication date: 2009-07-30

Abstract

A plasma display unit has a plasma display panel (PDP) having a first substrate and a second substrate which face each other via a discharge space, and a drive section for driving the PDP. The first substrate has a holding electrode (XE), a scanning electrode (YE), and an address electrode (AE). The drive section has an address electrode voltage applying section (ADRC) including a first transistor (PM1) for applying the supply voltage (Vadd) to the address electrode (AE) on the basis of the address control signal (ACNT) during an addressing period and a second transistor (NM1) for applying the ground voltage (GND) to the address electrode (AE) when the first transistor (PM1) turns off during the addressing period. The drive section also has a power supply shutoff section (PS110) to shut off the ground voltage (GND) to be supplied to the address electrode voltage applying section (ADRC) during a sustain period, thereby allowing power consumption to be reduced.

Description

Plasma display device and method for controlling plasma display device

The present invention relates to a plasma display device and a control method for the plasma display device.

A plasma display panel (PDP) is formed by bonding two glass substrates together, and displays an image by generating discharge light in a space formed between the glass substrates. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

In the PDP, in order to display an image with multiple gradations, a field for displaying one screen includes, for example, a plurality of subfields having a reset period, an address period, and a sustain period. For example, a three-electrode PDP displays an image by generating a sustain discharge between the scan electrode and the sustain electrode during the sustain period. A cell that generates a sustain discharge (a cell to be lit) is selected, for example, by generating an address discharge between the scan electrode and the address electrode in the address period.

In a general PDP, sustain electrodes and scan electrodes are disposed on a front glass substrate, and address electrodes are disposed on a rear glass substrate. In recent years, a PDP in which three electrodes, that is, a sustain electrode, a scan electrode, and an address electrode, are arranged on a front glass substrate has been proposed (for example, see Patent Document 1).
JP 2006-259516 A

In the PDP in which the three electrodes are arranged on the front glass substrate, the address electrodes are arranged at positions close to the sustain electrodes and the scan electrodes. For example, in a PDP (general PDP) in which address electrodes are arranged on a rear glass substrate, the distances between the sustain electrodes, the scan electrodes, and the address electrodes are about 100 μm. In contrast, in a PDP in which three electrodes are arranged on the front glass substrate, the distances between the sustain electrode, the scan electrode, and the address electrode are about 10 to 30 μm.

Since the distance between the sustain electrode / scan electrode and the address electrode is short, a large interelectrode capacitance is formed between the sustain electrode / scan electrode and the address electrode. As a result, in the PDP in which the three electrodes are arranged on the front glass substrate, between the sustain electrode and the scan electrode and the address electrode through the interelectrode capacitance (ground-address electrode-interelectrode capacitance-sustain electrode and scan electrode-ground). A large current (for example, a current about 3 to 10 times that of a general PDP) flows in the loop. In other words, a PDP device having a PDP in which three electrodes are provided on the front glass substrate consumes more power than a PDP device having a PDP in which address electrodes are arranged on the rear glass substrate.

An object of the present invention is to reduce power consumption in a PDP device having a PDP in which three electrodes are provided on a front glass substrate.

The plasma display device has a plasma display panel (PDP) having a first substrate and a second substrate facing each other through a discharge space, and a drive unit for driving the PDP. The first substrate has sustain electrodes, scan electrodes, and address electrodes. One field for displaying one screen has a plurality of address periods for generating an address discharge between the scan electrodes and the address electrodes, and a sustain period for generating a sustain discharge between the sustain electrodes and the scan electrodes. Has subfields. For example, the driving unit receives a power supply voltage in the address period, and grounds when the first transistor for applying the power supply voltage to the address electrode based on the address control signal and the first transistor in the address period are off. An address electrode application unit including a second transistor for receiving a voltage and applying a ground voltage to the address electrode based on an address control signal is provided. Furthermore, the drive unit includes a power supply cutoff unit that cuts off either the power supply voltage or the ground voltage supplied to the address electrode application unit during the sustain period.

In the present invention, power consumption can be reduced in a PDP device having a PDP in which three electrodes are provided on a front glass substrate.

It is a figure which shows the PDP apparatus in one Embodiment. It is a figure which shows the principal part of PDP shown in FIG. It is a figure which shows the structural example of the field for displaying the image of 1 screen. It is a figure which shows the outline | summary of the circuit part shown in FIG. 5 shows an example of the address electrode driver shown in FIG. It is a figure which shows an example of the power supply part and switch which were shown in FIG. It is a figure which shows an example of discharge operation of the subfield shown in FIG. It is a figure which shows the address electrode drive part and driver control part of the PDP apparatus in another embodiment. FIG. 9 is a diagram illustrating an example of a subfield discharge operation by the address electrode driver illustrated in FIG. 8. It is a figure which shows the address electrode drive part and control part of the PDP apparatus in another embodiment. It is a figure which shows the address electrode drive part of the PDP apparatus in another embodiment, a driver control part, and a switch control part. It is a figure which shows an example of the switch shown in FIG. It is a figure which shows the address electrode drive part of the PDP apparatus in another embodiment, a driver control part, and a switch control part. It is a figure which shows the address electrode drive part of the PDP apparatus in another embodiment, a driver control part, and a switch control part. FIG. 15 is a diagram showing an example of a subfield discharge operation by the address electrode driver shown in FIG. 14. FIG. 6 is a diagram illustrating a modification of the address electrode driving unit illustrated in FIG. 5.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A plasma display device (hereinafter also referred to as a PDP device) includes a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, A front housing 30 disposed on the image display surface 16 side of the PDP 10, a rear housing 40 and a base chassis 50 disposed on the back surface 18 side of the PDP 10, and attached to the rear housing 40 side of the base chassis 50 to drive the PDP 10. A double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure.

The PDP 10 includes a front substrate portion 12 that constitutes the image display surface 16 and a rear substrate portion 14 that faces the front substrate portion 12. A discharge space (cell) (not shown) is formed between the front substrate portion 12 and the rear substrate portion 14. The front substrate unit 12 and the back substrate unit 14 are formed of, for example, a glass substrate. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

FIG. 2 shows details of the main part of the PDP 10 shown in FIG. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. As described above, the discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, the concave portion of the rear substrate portion 14).

The front substrate portion 12 (first substrate) is formed in parallel along the first direction D1 on the glass substrate FS (lower side in the figure), and is alternately formed along the second direction D2. Xb and Y bus electrodes Yb are provided. An X transparent electrode Xt extending in the second direction D2 from the X bus electrode Xb to the Y bus electrode Yb is connected to the X bus electrode Xb. A Y transparent electrode Yt extending in the second direction D2 from the Y bus electrode Yb to the X bus electrode Xb is connected to the Y bus electrode Yb. In the illustrated example, the X transparent electrode Xt and the Y transparent electrode Yt face each other along the second direction D2.

Here, the X bus electrode Xb and the Y bus electrode Yb are opaque electrodes formed of a metal material or the like, and the X transparent electrode Xt and the Y transparent electrode Yt transmit visible light formed of an ITO film or the like. It is a transparent electrode. The X electrode XE (sustain electrode) is composed of the X bus electrode Xb and the X transparent electrode Xt, and the Y electrode YE (scanning electrode) is composed of the Y bus electrode Yb and the Y transparent electrode Yt. Paired. A discharge (sustain discharge) is repeatedly generated at the electrode pair (more specifically, between the X transparent electrode Xt and the Y transparent electrode Yt) constituted by the X electrode XE and the Y electrode YE.

Further, the transparent electrodes Xt and Yt may be disposed on the entire surface between the bus electrodes Xb and Yb to which the transparent electrodes Xt and Yt are connected and the glass substrate FS. Note that an electrode integral with the bus electrodes Xb and Yb may be formed in place of the transparent electrodes Xt and Yt, using the same material (metal material or the like) as the bus electrodes Xb and Yb.

The electrodes Xb, Xt, Yb, Yt are covered with the dielectric layer DL1. For example, the dielectric layer DL1 is an insulating film such as a silicon dioxide film formed by a CVD method. A plurality of address electrodes AE extending in a direction orthogonal to the bus electrodes Xb and Yb (second direction D2) are provided on the dielectric layer DL1 (lower side in the drawing). For example, the address electrode AE is an opaque electrode made of a metal material or the like. Thus, the PDP of this embodiment has three electrodes (electrodes XE, YE, AE) on the front substrate portion 12. The address electrode AE and the dielectric layer DL1 are covered with a protective layer PL. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collision in order to easily generate discharge.

The rear substrate portion 14 (second substrate) facing the front substrate portion 12 through the discharge space DS has partition walls (barrier ribs) BR formed in parallel with each other on the glass base RS. For example, the barrier ribs BR extend in a direction (second direction D2) orthogonal to the bus electrodes Xb and Yb, and are arranged along the address electrodes AE. In other words, the address electrode AE extends in the second direction D2 and is disposed along the partition wall BR. A partition wall BR constitutes a side wall of the cell. Further, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall BR and the glass substrate RS between the adjacent partition walls BR by being excited by ultraviolet rays. Phosphors PHr, PHg, and PHb are respectively applied.

One pixel of the PDP 10 is composed of three cells that generate red, green, and blue light. Here, one cell (one color pixel) is formed in a region surrounded by the bus electrodes Xb and Yb and the partition wall BR1. As described above, the PDP 10 is configured by arranging cells in a matrix to display an image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes Xb and Yb.

The PDP 10 is configured by bonding the front substrate portion 12 and the rear substrate portion 14 so that the protective layer PL and the partition wall BR are in contact with each other, and enclosing a discharge gas such as Ne or Xe in the discharge space DS. The bus electrodes Xb and Yb and the address electrode AE are respectively connected to an X electrode driving unit XDR (sustain electrode driving unit), a Y electrode driving unit YDR (scanning electrode driving unit) and an address electrode driving unit ADR shown in FIG. Connected.

FIG. 3 shows a configuration example of the field FLD for displaying an image of one screen. The length of one field FLD is 1/60 second (about 16.7 ms), and is composed of, for example, eight subfields SF (SF1-SF8). In this example, each subfield SF has a reset period RST, an address period ADR, and a sustain period SUS.

For example, in the reset period RST, the amounts of wall charges accumulated in the electrodes XE, YE, and AE are adjusted in order to match the discharge start voltages (voltages at which address discharge in the address period ADR starts to occur) of all cells. It is a period. Here, the wall charges are, for example, plus charges and minus charges accumulated on the surface of the protective layer PL such as MgO shown in FIG. 2 in each cell. The address period ADR is a period for selecting a cell to be lit during the sustain period SUS. A cell to be lit in the sustain period SUS is selected by, for example, selectively generating an address discharge between the scan electrode YE and the address electrode AE in the address period as shown in FIG. The sustain period SUS is a period in which discharge (sustain discharge) is generated in the cell selected in the address period ADR.

The length of the sustain period SUS varies depending on the subfield SF and depends on the number of discharges (luminance) of the cell. For this reason, it becomes possible to display an image with multiple gradations by changing the combination of the subfields SF to be lit. In this example, the number of discharge cycles preset in the subfields SF1 to SF8 is 4, 8, 16, 32, 64, 128, 256, and 512, respectively. As shown in FIG. 7 described later, the cell is discharged twice during one discharge cycle (star mark in the figure).

FIG. 4 shows an outline of the circuit unit 60 shown in FIG. A capacitance Cax in the figure indicates a parasitic capacitance (interelectrode capacitance) formed between the address electrode AE and the sustain electrode XE, and a capacitance Cay is a parasitic capacitance (between electrodes) formed between the address electrode AE and the scan electrode YE. Capacity). Hereinafter, the interelectrode capacitances Cax and Cay are collectively referred to as interelectrode capacitance Caxy.

The circuit unit 60 includes a voltage generation unit PWR, an X electrode driving unit XDR (sustain electrode driving unit), a Y electrode driving unit YDR (scanning electrode driving unit), an address electrode driving unit ADR, and a control unit CNT. The voltage generator PWR generates power supply voltages Vs / 2, −Vs / 2, Vsc, etc. to be supplied to the electrode drivers YDR and XDR. The electrode drive units XDR, YDR, and ADR operate as drive units that drive the PDP 10. For example, the sustain electrode driver XDR applies a common pulse to the sustain electrode XE, the scan electrode driver YDR selectively applies a pulse to the scan electrode YE, and the address electrode driver ADR applies to the address electrode AE. A pulse is selectively applied.

In the example shown in the figure, the address electrode drive unit ADR includes a power cutoff unit PSI10 and an address driver AD (address electrode application unit, address voltage application unit) provided for each address electrode AE. For example, the power shutoff unit PSI10 supplies the ground voltage to the address driver AD during the reset period RST and the address period ADR shown in FIG. 3 described above, and shuts off the ground voltage supplied to the address driver AD during the sustain period SUS. To do. The address driver AD selectively applies an address pulse APL shown in FIG. 7 to be described later to the address electrode AE. In this figure, the description of the power supply for supplying the power supply voltage to the address driver AD is omitted.

The control unit CNT includes a driver control unit ADCN that generates a control signal ACNT (address control signal) for controlling the address driver AD, and a switch control unit SWCN that generates a control signal SCNT for controlling the power cutoff unit PSI10. have. Then, the control unit CNT selects a subfield to be used based on the image data R0-7, G0-7, B0-7, and outputs control signals YCNT, XCNT, and ACNT to the electrode drive units YDR, XDR, and ADR. . A multi-gradation image is displayed by selecting a subfield to be used for each cell constituting a pixel. The image data R0-7, G0-7, and B0-7 are 8-bit data for displaying red, green, and blue, respectively, and are sequentially sent from the tuner unit or external input (not shown) to the control unit CNT. Entered.

FIG. 5 shows an example of the address electrode driver ADR shown in FIG. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. Hereinafter, the voltage of the ground line GND is also referred to as a ground voltage GND.

The address electrode driver ADR includes an address driver AD (ADa, ADb) provided for each address electrode AE (AEa, AEb) and an isolator IS1 (IS1a, IS1b) provided for each address driver AD (ADa, ADb). And a power supply unit PS1 (internal power supply) and a power supply cutoff unit PSI10. A circuit group of the address electrode drive unit ADR (a circuit group including the address driver AD and the power supply unit PS1) excluding the power supply cutoff unit PSI10 is also referred to as an address drive circuit ADRC.

For example, the address driver AD (ADa, ADb) includes a first transistor PM1 (PM1a, PM1b) and a second transistor NM1 (NM1a, NM1b) connected in series between the internal power supply line LN10 and the reference power supply line LN20. Have. The common node ND1 (ND1a, ND1b) connecting the transistor PM1 and the transistor NM1 is connected to the address electrode AE (AEa, AEb).

For example, the transistor PM1 is a power pMOS transistor (P-channel FET) capable of flowing a large current, and has a parasitic diode whose anode is connected to the drain of the transistor PM1 and whose cathode is connected to the source of the transistor PM1. Yes. Generally, in a power pMOS transistor, a threshold voltage between a drain and a gate to which an anode of a parasitic diode is connected is larger than a threshold voltage between a source and a gate to which a cathode of the parasitic diode is connected. Therefore, the power P-channel FET is turned on (off) based on the voltage between the source and the gate shown in the drawing.

The transistor NM1 is a power nMOS transistor (N-channel FET) capable of flowing a large current, and has a parasitic diode whose anode is connected to the source of the transistor NM1 and whose cathode is connected to the drain of the transistor NM1. Yes. In the power nMOS transistor, the threshold voltage between the drain and the gate to which the cathode of the parasitic diode is connected is larger than the threshold voltage between the source and the gate to which the anode of the parasitic diode is connected. Therefore, the power N-channel FET is turned on (off) based on the voltage between the source and the gate shown in the drawing.

In the illustrated example, the source of the transistor PM1 is connected to the internal power supply line LN10, and the source of the transistor NM1 is connected to the reference power supply line LN20. That is, the cathode of the parasitic diode of the transistor PM1 is connected to the internal power supply line LN10, and the anode of the parasitic diode of the transistor NM1 is connected to the reference power supply line LN20. As a result, leakage current can be prevented from flowing from the internal power supply line LN10 to the reference power supply line LN20 via the parasitic diode.

The gates of the transistors PM1 and NM1 are connected to each other and are connected to the driver control unit ADCN via the isolator IS1. For example, the isolator IS1 includes a light emitting diode and a phototransistor, and maintains an galvanic isolation between the driver control unit ADCN and the address driver AD, and the address control signal ACNT (ACNTa) from the driver control unit ADCN to the address driver AD. , ACNTb).

In the example of the figure, the isolator IS1 shifts the reference level of the address control signal ACNT from the ground voltage GND to the voltage of the reference power supply line LN20, and transmits the address control signal ACNT to the gates of the transistors PM1 and NM1. Thereby, the logic level (H level and L level) of address control signal ACNT is reliably transmitted to transistors PM1 and NM1. For example, when the address control signal ACNT is at a high logic level (H level), the transistor PM1 is turned off, the transistor NM1 is turned on, and when the address control signal ACNT is at a low logic level (L level), the transistor PM1 is turned on. To do.

The power supply unit PS1 is connected to the ground line GND via the reference power supply line LN20 and the power supply cutoff unit PSI10, and supplies the power supply voltage Vadd to the internal power supply line LN10 to which the transistor PM1 is connected. That is, the power supply unit PS1 maintains the voltage between the reference power supply line LN20 and the internal power supply line LN10 at the voltage Vadd. An example of the configuration of the power supply unit PS1 will be described later with reference to FIG.

The power cutoff unit PSI10 has a switch SW10 disposed between the reference power supply line LN20 and the ground line GND. On / off of the switch SW10 is controlled by a control signal SCNT output from the switch control unit SWCN. For example, the switch SW10 is configured such that no leakage current flows between the reference power supply line LN20 and the ground line GND when the switch SW10 is off.

For example, the switch SW10 is configured by an IGBT (Insulated Gate Bipolar Transistor) or a power MOS transistor. The IGBT is a bipolar transistor in which a MOSFET is incorporated in the gate. Unlike a power MOS transistor, an IGBT does not have a parasitic diode between a collector and an emitter. For this reason, in the switch SW10 constituted by the IGBT, no leakage current flows between the reference power supply line LN20 and the ground line GND when the switch SW10 is off. Details of the switch SW10 formed of a power MOS transistor having a parasitic diode will be described later with reference to FIG.

As described above, the switch SW10 is turned on to supply the ground voltage GND from the ground line GND to the reference power supply line LN20 in the address period ADR shown in FIG. That is, switch SW10 electrically connects address drive circuit ADRC having power supply unit PS1 and address driver AD and ground line GND in address period ADR. In other words, in the address period ADR, the ground voltage GND is supplied to the reference power supply line LN20, and the power supply voltage Vadd based on the ground voltage GND is supplied to the internal power supply line LN10. Thus, the transistor NM1 can apply the ground voltage GND to the address electrode AE when the address control signal ACNT is at a high logic level (H level). Further, the transistor PM1 can apply the power supply voltage Vadd based on the ground voltage GND to the address electrode AE when the address control signal ACNT is at a low logic level (L level).

Further, the switch SW10 is turned off to bring the reference power supply line LN20 into a floating state during the sustain period SUS. That is, the switch SW10 electrically disconnects the address drive circuit ADRC and the ground line GND during the sustain period SUS. As described above, no leakage current flows between the reference power supply line LN20 and the ground line GND when the switch SW10 is off. Therefore, in this embodiment, it is possible to prevent a leak current from flowing between the address electrode AE and the ground line GND during the sustain period SUS.

That is, in this embodiment, in the sustain period SUS, the sustain electrode XE and the scan electrode YE and the address electrode AE are connected via the interelectrode capacitance Caxy (the ground line GND-address electrode AE-interelectrode capacitance Caxy-sustain electrode XE). In addition, it is possible to prevent a leak current from flowing through the scan electrode YE and the loop of the ground line GND. As a result, in this embodiment, power consumption can be reduced.

FIG. 6 shows an example of the power supply unit PS1 and the switch SW10 shown in FIG. The power supply unit PS1 includes, for example, a part of the transformer T1 (coil L2), a rectifier circuit (diode D1 in the figure), a smoothing circuit (capacitor C1 in the figure), and a voltage stabilization circuit VS1. For example, the transformer T1 has a configuration in which two coils L1 and L2 are coupled by a core, and the primary side (coil L1) and the secondary side (coil L2) are galvanically insulated, and one coil L1 is The applied change (AC voltage Vadd1 in the figure) is transmitted to the other coil L2.

For example, one terminal of the coil L1 is connected to the ground line GND, and the AC voltage Vadd1 is applied to the other terminal. The coil L2 has one terminal connected to the reference power line LN20 and the other terminal connected to the anode of the diode D1, and transmits a voltage change applied to the coil L1 to the diode D1. The cathode of the diode D1 is connected to one terminal of the capacitor C1 and the voltage stabilizing circuit VS1, and the other terminal of the capacitor C1 is connected to the reference power supply line LN20. As a result, a voltage rectified and smoothed with reference to the reference power supply line LN20 is supplied to the node where the diode D1 and the capacitor C1 are connected.

The voltage stabilization circuit VS1 stabilizes the voltage rectified and smoothed with reference to the reference power supply line LN20 as the power supply voltage Vadd and supplies it to the internal power supply line LN10. Thereby, even when the reference power supply line LN20 is in a floating state, the power supply unit PS1 can maintain the voltage between the reference power supply line LN20 and the internal power supply line LN10 at the voltage Vadd.

The switch SW10 of the power shut-off unit PSI10 is composed of, for example, a pair of power nMOS transistors NM10 and NM20 (N channel FET) connected in series between the reference power supply line LN20 and the ground line GND. In the power nMOS transistors NM10 and NM20, the common node that connects the gates of the transistors NM10 and NM20 to each other is connected to the switch control unit SWCN, and the control signal SCNT is received by the gate.

The nMOS transistor NM10 has a drain connected to the reference power supply line LN20 and a source connected to the source of the nMOS transistor NM20. The nMOS transistor NM20 has a drain connected to the ground line GND. That is, the pair of power nMOS transistors NM10 and NM20 are connected in the direction in which the anodes of the parasitic diodes formed in the transistors NM10 and NM20 are connected to each other.

When the transistors NM10 and NM20 are in the off state, the parasitic diode of the transistor NM10 prevents a leakage current from flowing from the reference power supply line LN20 to the ground line GND, and the parasitic diode of the transistor NM20 is connected from the ground line GND to the reference power supply line LN20. To prevent leakage current from flowing through. As a result, when the switch SW10 (transistors NM10 and NM20) is off, leakage current can be prevented from flowing between the reference power supply line LN20 and the ground line GND.

FIG. 7 shows an example of the discharge operation of the subfield SF shown in FIG. The star in the figure indicates the occurrence of discharge. The shaded portion of the waveform of the address electrode AE in the figure indicates that the address electrode AE is in a floating state. Note that the switch SW10 shown in FIG. 5 is turned on when receiving a control signal SCNT at a high logic level (H level) and turned off when receiving a control signal SCNT at a low logic level (L level). .

First, in the reset period RST, a positive write voltage is applied to the sustain electrode XE (the bus electrode Xb and the transparent electrode Xt), and a positive write voltage is applied to the scan electrode YE (the bus electrode Yb and the transparent electrode Yt) ( FIG. 7 (a)). Then, the sustain electrode XE is maintained at a positive write voltage, and a positive write voltage (write obtuse wave) that gradually increases is applied to the scan electrode YE (FIG. 7B). Thus, wall charges are accumulated in the sustain electrode XE, the scan electrode YE, and the address electrode AE, respectively, while suppressing the light emission of the cell. For example, negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively, and positive wall charges are accumulated in the address electrode AE.

Next, the sustain electrode XE is maintained at a positive write voltage, and a negative adjustment voltage (adjustment blunt wave) is applied to the scan electrode YE (FIG. 7C). As a result, the amount of negative and positive wall charges accumulated in the sustain electrode XE, the scan electrode YE, and the address electrode AE is reduced, and the amount of wall charges in all cells is adjusted. For example, the positive adjustment voltage applied to the sustain electrode XE is a voltage lower than the voltage Vs / 2, and the minimum value of the negative adjustment voltage applied to the scan electrode YE is higher than the voltage −Vs / 2. It is a voltage (small voltage value as an absolute value).

In the reset period RST, since the control signal SCNT is maintained at the H level, the ground voltage GND is supplied to the reference voltage line LN20 illustrated in FIG. 5 via the switch SW10. Since the control signal ACNT is maintained at the H level, the transistor PM1 shown in FIG. 5 is turned off, the transistor NM1 is turned on, and the transistor NM1 applies the ground voltage GND to the address electrode AE.

In the address period ADR, the control signal SCNT is maintained at the H level by the switch control unit SWCN illustrated in FIG. 5, and the switch SW10 is maintained in the ON state. In the address period ADR, a bias voltage serving as an anode during address discharge is applied to the sustain electrode XE, and a scan pulse SPL (voltage −Vs / 2) serving as a cathode during address discharge is applied to the scan electrode YE, and during address discharge. An address pulse APL (voltage Vadd) serving as an anode is applied to the address electrode AE corresponding to the lighted cell (FIG. 7D). In the cell selected by the scan pulse SPL and the address pulse APL, a discharge (address discharge) is temporarily generated between the scan electrode YE and the address electrode AE. Thereby, a cell to be lit in the sustain period SUS is selected.

For example, by setting the address control signal ACNT corresponding to the lighted cell to L level, in the address driver AD connected to the address electrode AE corresponding to the lighted cell, the transistor PM1 is turned on and the transistor NM1 is turned off. That is, when the address control signal ACNT is at the L level, the transistor PM1 applies the power supply voltage Vadd to the address electrode AE. In other words, the transistor PM1 applies the power supply voltage Vadd to the address electrode AE based on the address control signal ACNT.

Further, in the address driver AD that has received the address control signal ACNT at the H level, the transistor PM1 is turned off, the transistor NM1 is turned on, and the transistor NM1 applies the ground voltage GND to the address electrode AE. That is, the transistor NM1 applies the ground voltage GND to the address electrode AE based on the address control signal ACNT when the transistor PM1 in the address period ADR is off. Note that the second address pulse APL shown in the waveform of the address electrode AE is applied to select a cell of another display line (FIG. 7E).

In the sustain period SUS, negative and positive sustain pulses (voltages Vs / 2, −Vs / 2) are applied to the sustain electrode XE and the scan electrode YE, respectively (FIG. 7 (f, g)). Thereby, the discharge state of the lighted cell is maintained. Sustain pulses having different polarities are repeatedly applied to the sustain electrode XE and the scan electrode YE, so that the discharge of the cells lit in the sustain period SUS (sustain discharge) is repeatedly performed. As described in FIG. 3, two discharges are performed during one discharge cycle (for example, FIG. 7 (f, g)). For example, the subfield SF4 is composed of 32 discharge cycles, and 64 discharges are performed.

In the sustain period SUS, the control signal SCNT is set to L level by the switch control unit SWCN shown in FIG. 5, and the switch SW10 is turned off. That is, in the sustain period SUS, as described above, the address drive circuit ADRC and the ground line GND are electrically disconnected. That is, in this embodiment, in the sustain period SUS, the address electrode AE can be in a floating (high impedance) state, and the average voltage of the sustain electrode XE and the scan electrode YE to which the sustain pulse is applied and the voltage of the address electrode AE The difference can be reduced.

Thereby, the displacement current (leakage current) between the sustain electrode XE, the scan electrode YE, and the address electrode AE generated by the difference between the average voltage of the sustain electrode XE and the scan electrode YE and the voltage of the address electrode AE can be reduced. In this embodiment, as described with reference to FIG. 5 described above, when the switch SW10 is off, it is possible to prevent a leakage current from flowing between the address electrode AE and the ground line GND, thereby reducing power consumption. . In the example shown in the figure, the address control signal ACNT is maintained at the H level during the sustain period SUS. Note that, in the sustain period SUS, the address drive circuit ADRC and the ground line GND are not electrically connected, so the address control signal ACNT may be at the L level.

As described above, in this embodiment, during the sustain period SUS, the switch SW10 (power cutoff unit PSI10) disposed between the reference power supply line LN20 and the ground line GND is turned off, and the ground voltage GND supplied to the reference power supply line LN20. Shut off. As a result, leakage current can be prevented from flowing between the reference power supply line LN20 and the ground line GND during the sustain period SUS, and power consumption can be reduced.

FIG. 8 shows an address electrode driver ADR2 and a driver controller ADCN2 of a PDP device according to another embodiment. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. In this embodiment, the address electrode drive unit ADR2 includes a 2-input OR circuit OR1 (OR1a, OR1b) added to the address electrode drive unit ADR shown in FIG. 5 described above, and the power cut-off unit PSI10 shown in FIG. Instead, a power cutoff unit PSI20 is provided. In the address electrode driver ADR2, the power supply unit PS1 and the isolator IS1 are omitted from the address electrode driver ADR shown in FIG. The other configuration of the address electrode driver ADR2 is the same as that in FIG.

Further, the driver control unit ADCN2 of this embodiment is different from the driver control unit ADCN shown in FIG. 5 in that the address control signal SS is generated in addition to the address control signal ACNT. Other configurations of the driver control unit ADCN2 are the same as those in FIGS. The same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The source of the transistor NM1 (NM1a, NM1b) of the address driver AD (ADa, ADb) is connected to the ground line GND, and the source of the transistor PM1 (PM1a, PM1b) of the address driver AD (ADa, ADb) is a power cutoff unit The PSI 20 is connected to the first power supply line LN12. For example, the power supply voltage Vadd is supplied to the first power supply line LN12 from the voltage generation unit PWR shown in FIG. 4 described above.

For example, the power cutoff unit PSI20 is configured by a power nMOS transistor NM30 having a source connected to the first power supply line LN12, a drain connected to the source of the transistor PM1, and a gate connected to the switch control unit SWCN. That is, in the transistor NM30, the anode of the parasitic diode of the transistor NM30 is connected to the first power supply line LN12, and the cathode of the parasitic diode is connected to the source of the transistor PM1, between the first power supply line LN12 and the transistor PM1. Placed in.

The transistor NM30 is turned on during the reset period RST and the address period ADR shown in FIG. 3 described above, supplies the power supply voltage Vadd to the transistor PM1, turns off during the sustain period SUS, and cuts off the power supply voltage Vadd supplied to the transistor PM1. To do. That is, the transistor NM30 of the power cutoff unit PSI20 functions as a switch.

In this embodiment, since the anode of the parasitic diode of the transistor NM30 is connected to the first power supply line LN12 and the cathode of the parasitic diode is connected to the source of the transistor PM1, when the transistor NM30 is in the off state, Leakage current can be prevented from flowing through one power supply line LN12. The power cutoff unit PSI20 may be configured using a power pMOS transistor, IGBT, or the like instead of the power nMOS transistor NM30. In this case, the power pMOS transistor and the IGBT function as a switch.

The two-input OR circuit OR1 (OR1a, OR1b) receives the address control signal SS at one input terminal, receives the address control signal ACNT (ACNTa, ACNT1b) at the other input terminal, and receives the logic of the address control signals SS and ACNT. The sum is output to the gate of the transistor PM1 (PM1a, PM1b). An address control signal ACNT (ACNTa, ACNT1b) is supplied to the gate of the transistor NM1 (NM1a, NM1b).

For example, the driver control unit ADCN2 simultaneously turns off the transistors PM1 and NM1 by setting the address control signals SS and ACNT to the H level and the L level, respectively, during the sustain period SUS. Note that a logic circuit for simultaneously turning off the transistors PM1 and NM1 may be configured by using a negative logical sum, a logical product, a negative logical product, or the like instead of the two-input logical sum circuit OR1. The two-input OR circuit OR1 may be provided in the driver control unit ADCN2.

Here, a configuration in which the transistors PM1 and NM1 are turned off during the sustain period SUS without providing the power cutoff unit PSI20 (transistor NM30) was considered in the process of the present invention. In this configuration, the address electrodes AE can be in a floating (high impedance) state by simultaneously turning off the transistors PM1 and NM1. As a result, the difference between the average voltage of the sustain electrode XE and the scan electrode YE to which the sustain pulse is applied and the voltage of the address electrode AE can be reduced, and the displacement current between the sustain electrode XE, the scan electrode YE, and the address electrode AE ( (Leakage current) can be reduced.

However, in this configuration, when the voltage of the address electrode AE in the high impedance state is higher than the power supply voltage Vadd, a leakage current flows from the address electrode AE to the first power supply line LN12 via the parasitic diode of the transistor PM1. For example, when the voltage of the sustain electrode XE or the scan electrode YE is higher than the power supply voltage Vadd, the voltage of the address electrode AE in the high impedance state may be higher than the power supply voltage Vadd. That is, in the configuration in which the transistors PM1 and NM1 are turned off during the sustain period SUS without providing the power cutoff unit PSI20 (transistor NM30), when the voltage of the sustain electrode XE or the scan electrode YE is higher than the power supply voltage Vadd, the address electrode There is a possibility that a leakage current flows from the AE to the first power supply line LN12 through the parasitic diode of the transistor PM1.

On the other hand, in this embodiment, even when the voltage of the address electrode AE in the high impedance state is higher than the power supply voltage Vadd, by turning off the transistor NM30, as described above, from the transistor PM1 to the first power supply line LN12. Leakage current can be prevented from flowing. That is, in this embodiment, by turning off the transistors PM1 and NM30, it is possible to prevent a leakage current from flowing between the address electrode AE and the first power supply line LN12. Note that by turning off the transistor PM1 of the address driver AD, it is possible to prevent a leak current from flowing from the first power supply line LN12 to the address electrode AE. Further, by turning off the transistor NM1 of the address driver AD, it is possible to prevent a leak current from flowing from the address electrode AE to the ground line GND.

Therefore, in this embodiment, as shown in FIG. 9 described later, in the sustain period SUS, the transistors PM1, NM1, and NM30 can be turned off, and the sustain electrode XE, the scan electrode YE, and the address electrode AE are connected via the interelectrode capacitance Caxy. It is possible to prevent leakage current from flowing between them. As a result, in this embodiment, power consumption can be reduced.

FIG. 9 shows an example of the discharge operation of the subfield SF by the address electrode driver ADR2 shown in FIG. Detailed description of the same operations as those in FIG. 7 described above will be omitted. The waveform shown in FIG. 9 is different from FIG. 7 in that the waveform of the address control signal SS is added. Other waveforms are the same as those in FIG. The meanings of stars and shaded portions in the figure are the same as those in FIG.

In the reset period RST and the address period ADR, the address control signal SS is maintained at the L level. Thus, when the address control signal ACNT is at the L level, the transistor PM1 shown in FIG. 8 described above can apply the power supply voltage Vadd to the address electrode AE, and when the address control signal ACNT is at the H level, the transistor NM1 A ground voltage GND can be applied to the electrode AE.

In the sustain period SUS, the address control signal SS is maintained at the H level, and the address control signal ACNT is maintained at the L level. Thereby, the transistors PM1 and NM1 are turned off. Further, since the control signal SCNT is set to the L level, the transistor NM30 is turned off. Thus, in this embodiment, since the transistors PM1, NM1, and NM30 are turned off during the sustain period SUS, the sustain electrode XE and the scan electrode YE are connected via the interelectrode capacitance Caxy as described above with reference to FIG. It is possible to prevent a leak current from flowing between the address electrode AE. As described above, also in this embodiment, power consumption can be reduced.

FIG. 10 shows an address electrode drive unit ADR3 and a control unit CNT2 of a PDP device in another embodiment. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. Further, the control unit CNT2 in the figure omits the description of the image data R0-7, G0-7, B0-7 and the control signals XCNT, YCNT. In this embodiment, the address electrode driver ADR3 is provided with a power cutoff unit PSI22 instead of the power cutoff unit PSI20 shown in FIG. The other configuration of the address electrode driver ADR3 is the same as that in FIG.

Also, the control unit CNT2 of this embodiment is configured by omitting the switch control unit SWCN from the control unit CNT shown in FIG. 4 described above. Further, the control unit CNT2 is provided with the driver control unit ADCN2 shown in FIG. 8 described above instead of the driver control unit ADCN shown in FIG. The other configuration of the control unit CNT2 is the same as that in FIG.

In this embodiment, the discharge operation of the subfield SF is the same as the waveform obtained by omitting the control signal SCNT from the waveform shown in FIG. That is, the waveforms of the electrodes XE, YE, AE and the control signals ACNT, SS are the same as those in FIG. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The power cutoff unit PSI22 is configured by a diode D10 having an anode connected to the first power supply line LN12 and a cathode connected to the source of the transistor PM1. For example, when the transistor PM1 is on, the power supply voltage Vadd is supplied from the first power supply line LN12 to the transistor PM1 via the diode D10. Specifically, a voltage that is lowered from the power supply voltage Vadd by the forward voltage of the diode D10 is supplied to the transistor PM1.

For example, when the transistor PM1 is turned off, no current flows from the first power supply line LN12 to the address electrode AE, so that the power supply voltage Vadd is not supplied to the transistor PM1. That is, the diode D10 cuts off the power supply voltage Vadd supplied to the transistor PM1 by turning off the transistor PM1 during the sustain period SUS shown in FIG. Further, the diode D10 prevents a leakage current from flowing from the address electrode AE to the first power supply line LN12 through the parasitic diode of the transistor PM1 when the transistor PM1 is turned off.

For example, in this embodiment, in the sustain period SUS, the address control signals SS and ACNT are set to the H level and the L level, respectively, and the transistors PM1 and NM1 are turned off. Accordingly, the diode D10 can prevent a leak current from flowing from the address electrode AE to the first power supply line LN12 through the parasitic diode of the transistor PM1 during the sustain period SUS. In this case, since the transistor PM1 is off, it is possible to prevent a leak current from flowing from the first power supply line LN12 to the address electrode AE. Further, since the transistor NM1 is off, it is possible to prevent a leak current from flowing from the address electrode AE to the ground line GND.

That is, in this embodiment, the leakage current flows between the sustain electrode XE, the scan electrode YE, and the address electrode AE through the interelectrode capacitance Caxy by turning off the transistors PM1 and NM1 during the sustain period SUS. Can be prevented. As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 8 and 9 can be obtained.

FIG. 11 shows an address electrode driver ADR4, a driver controller ADCN, and a switch controller SWCN of a PDP device in another embodiment. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. In this embodiment, the address electrode driver ADR4 is configured by adding switches SW20 (SW20a, SW20b) to the address electrode driver ADR shown in FIG. Further, in the address electrode driver ADR4, the power supply cutoff unit PSI10, the power supply unit PS1, and the isolator IS1 are omitted from the address electrode driver ADR shown in FIG. The other configuration of the address electrode driver ADR4 is the same as that in FIG.

The configurations of the driver control unit ADCN and the switch control unit SWCN are the same as those in FIG. 5 except for the output destinations of the control signals ACNT and SCNT. In this embodiment, the discharge operation of the subfield SF is the same as that in FIG. The same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The source of the transistor NM1 (NM1a, NM1b) of the address driver AD (ADa, ADb) is connected to the ground line GND, and the source of the transistor PM1 (PM1a, PM1b) of the address driver AD (ADa, ADb) is the internal power supply line Connected to LN10. For example, the power supply voltage Vadd is supplied to the internal power supply line LN10 from the voltage generation unit PWR shown in FIG. 4 described above. The gates of the transistors PM1 and NM1 are connected to each other and to the driver control unit ADCN.

The switch SW20 (SW20a, SW20b) is provided between the address driver AD (ADa, ADb) and the address electrode AE (AEa, AEb) for each address electrode AE (AEa, AEb). ON / OFF of the switch SW20 is controlled by a control signal SCNT output from the switch control unit SWCN. For example, the switch SW20 is configured such that no leak current flows between the address driver AD and the address electrode AE when the switch SW20 is off. For example, by turning off the switch SW20 during the sustain period SUS, the current flowing from the transistor PM1 to the address electrode AE and the current flowing from the address electrode AE to the transistor NM1 are cut off.

For example, the switch SW10 is configured by an IGBT or a power MOS transistor. As described above, since the IGBT does not have a parasitic diode between the collector and the emitter, in the switch SW20 configured by the IGBT, when the switch SW20 is off, a leakage current is generated between the address driver AD and the address electrode AE. Does not flow. Details of the switch SW20 formed of a power MOS transistor having a parasitic diode will be described later with reference to FIG.

For example, as shown in FIG. 7 described above, the driver control unit ADCN turns off the switch SW20 by setting the control signal SCNT to the L level during the sustain period SUS. As described above, when the switch SW20 is turned off, no leak current flows between the address driver AD and the address electrode AE. Therefore, in this embodiment, it is possible to prevent a leak current from flowing between the address electrode AE and the ground line GND and between the internal power supply line LN10 and the address electrode AE during the sustain period SUS.

That is, in this embodiment, by turning off the switch SW20 during the sustain period SUS, it is possible to prevent a leakage current from flowing between the sustain electrode XE, the scan electrode YE, and the address electrode AE via the interelectrode capacitance Caxy. . As a result, in this embodiment, power consumption can be reduced. In this embodiment, since the switch SW20 is turned off during the sustain period SUS, the address control signal ACNT during the sustain period SUS may be H level or L level.

FIG. 12 shows an example of the switch SW20 shown in FIG. The switch SW20 includes, for example, a pair of power nMOS transistors NM40 connected in series between the node ND1 (the common node ND1 connecting the transistor PM1 and the transistor NM1 shown in FIG. 11 described above) and the address electrode AE. NM50 (N channel FET). In the power nMOS transistors NM40 and NM50, a common node that connects the gates of the transistors NM40 and NM50 is connected to the switch control unit SWCN, and the control signal SCNT is received by the gate.

The nMOS transistor NM40 has a drain connected to the node ND1 and a source connected to the source of the nMOS transistor NM50. The nMOS transistor NM50 has a drain connected to the address electrode AE. That is, the pair of power nMOS transistors NM40 and NM50 are connected in the direction in which the anodes of the parasitic diodes formed in the transistors NM40 and NM50 are connected to each other.

When the transistors NM40 and NM50 are off, the parasitic diode of the transistor NM40 prevents a leakage current from flowing from the node ND1 to the address electrode AE, and the parasitic diode of the transistor NM50 has a leakage current from the address electrode AE to the node ND1. Prevent it from flowing. Thereby, when the switch SW20 is off, it is possible to prevent a leak current from flowing between the node ND1 (the address driver AD shown in FIG. 11 described above) and the address electrode AE. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 9 can be obtained.

FIG. 13 shows an address electrode driver ADR5, a driver controller ADCN2, and a switch controller SWCN of a PDP device in another embodiment. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. In this embodiment, the address electrode driver ADR5 is configured by adding a two-input OR circuit OR1 (OR1a, OR1b) and an isolator IS2 to the address electrode driver ADR shown in FIG. The other configuration of the address electrode driver ADR5 is the same as that in FIG.

Further, the driver control unit ADCN2 of this embodiment is different from the driver control unit ADCN shown in FIG. 5 in that the address control signal SS is generated in addition to the address control signal ACNT. Other configurations of the driver control unit ADCN2 are the same as those in FIGS. In this embodiment, the discharge operation of the subfield SF is the same as that in FIG. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Note that one input terminal of the two-input OR circuit OR1 (OR1a, OR1b) is connected to the driver control unit ADCN2 via the isolator IS2, and the other input terminal is a driver via the isolator IS1 (IS1a, IS1b). It is connected to the control unit ADCN2. The output terminal of the 2-input OR circuit OR1 is connected to the gate of the transistor PM1 of the address driver AD.

That is, the 2-input OR circuit OR1 (OR1a, OR1b) outputs the logical sum of the address control signals SS and ACNT to the gate of the transistor PM1 (PM1a, PM1b). The gate of the transistor NM1 of the address driver AD is connected to one input terminal of a two-input OR circuit OR1 (OR1a, OR1b), and is connected to the driver control unit ADCN2 via the isolator IS1.

For example, as shown in FIG. 9 described above, the driver control unit ADCN2 simultaneously turns off the transistors PM1 and NM1 by setting the address control signals SS and ACNT to the H level and the L level, respectively, during the sustain period SUS. . Note that a logic circuit for simultaneously turning off the transistors PM1 and NM1 may be configured by using a negative logical sum, a logical product, a negative logical product, or the like instead of the two-input logical sum circuit OR1. The two-input OR circuit OR1 may be provided in the driver control unit ADCN2.

By simultaneously turning off the transistors PM1 and NM1, the internal power supply line LN10 and the address electrode AE and the address electrode AE and the reference power supply line LN20 can be in a high impedance state. Thereby, the difference between the average voltage of the sustain electrode XE and the scan electrode YE to which the sustain pulse is applied and the voltage of the address electrode AE can be reliably reduced, and the displacement between the sustain electrode XE, the scan electrode YE, and the address electrode AE The current (leakage current) can be reliably reduced.

In the sustain period SUS, since the switch SW10 is off, a leakage current flows between the reference power supply line LN20 and the ground line GND, as in the embodiment described with reference to FIGS. Can be prevented and power consumption can be reduced. As described above, also in this embodiment, the same effects as those of the embodiment described with reference to FIGS. 1 to 9 can be obtained.

FIG. 14 shows an address electrode drive unit ADR6, a driver control unit ADCN3, and a switch control unit SWCN of a PDP device in another embodiment. In the figure, the interelectrode capacitance Caxy between the address electrode AEb, the sustain electrode XE, and the scan electrode YE is omitted. In this embodiment, the address electrode driver ADR6 is configured by omitting the two-input OR circuit OR1 (OR1a, OR1b) from the address electrode driver ADR2 shown in FIG. The configuration of the power cutoff unit PSI20 of the address electrode driver ADR6 is provided with a switch SW30 instead of the transistor NM30 shown in FIG. The other configuration of the address electrode driver ADR6 is the same as that in FIG.

Further, the driver control unit ADCN3 of this embodiment is different from the driver control unit ADCN2 shown in FIG. 8 in that the address control signal SS shown in FIG. 8 is not generated. Other configurations of the driver control unit ADCN3 are the same as those in FIG. The same elements as those described in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The power shut-off unit PSI20 is configured by a switch SW30 that is turned on during the reset period RST and the address period ADR shown in FIG. 3 and turned off during the sustain period SUS. For example, in the switch SW30, the leakage current does not flow between the first power supply line LN12 and the transistor PM1 when the switch SW30 is turned off by the IGBT or the pair of power nMOS transistors shown in FIGS. 6 and 12 described above. Configured as follows.

The gates of the transistors PM1 and NM1 are connected to each other and to the driver control unit ADCN3. For example, as shown in FIG. 15 described later, the driver control unit ADCN3 turns off the transistor NM1 by setting the address control signal ACNT to the L level during the sustain period SUS. In this embodiment, by turning off the transistor NM1, it is possible to prevent a leak current from flowing between the address electrode AE and the reference power supply line LN20.

Further, in this embodiment, since the switch SW30 is turned off during the sustain period SUS, it is possible to prevent a leak current from flowing between the first power supply line LN12 and the transistor PM1. That is, in this embodiment, by turning off the switch SW30 and the transistor NM1 during the sustain period SUS, a leakage current flows between the sustain electrode XE, the scan electrode YE, and the address electrode AE via the interelectrode capacitance Caxy. Can be prevented. As a result, power consumption can be reduced.

FIG. 15 shows an example of the discharge operation of the subfield SF by the address electrode driver ADR6 shown in FIG. Detailed description of the same operations as those in FIG. 9 described above will be omitted. The waveform shown in FIG. 15 is different from FIG. 9 in that the waveform of the address control signal SS is omitted. Other waveforms are the same as those in FIG. The meanings of stars and shaded parts in the figure are the same as those in FIG.

In the reset period RST and the address period ADR, the control signal SCNT is maintained at the H level. Thus, when the address control signal ACNT is at the L level, the transistor PM1 shown in FIG. 14 described above can apply the power supply voltage Vadd to the address electrode AE, and when the address control signal ACNT is at the H level, the transistor NM1 A ground voltage GND can be applied to the electrode AE.

In the sustain period SUS, the address control signal ACNT and the control signal SCNT are set to L level, respectively, and the transistor NM1 and the switch SW30 are turned off. As described above, the switch SW30 is configured such that no leakage current flows between the first power supply line LN12 and the transistor PM1 when the switch SW30 is turned off. For this reason, in the sustain period SUS, it is possible to prevent a leak current from flowing between the first power supply line LN12 and the transistor PM1 even if the transistor PM is turned on.

Thus, in this embodiment, since the transistor NM1 and the switch SW30 are turned off during the sustain period SUS, a leakage current flows between the sustain electrode XE, the scan electrode YE, and the address electrode AE via the interelectrode capacitance Caxy. Can be prevented. As a result, power consumption can be reduced. As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 8 and 9 can be obtained.

In the above-described embodiment, an example in which one pixel includes three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), Cells that generate colors other than blue (B) may be included.

In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, the example in which the voltage −Vs / 2 and the voltage Vs / 2 are alternately applied to the sustain electrode XE and the scan electrode YE in the sustain period SUS has been described. The present invention is not limited to such an embodiment. For example, the ground voltage GND and the voltage Vs may be alternately applied to the sustain electrode XE and the scan electrode YE during the sustain period SUS. In this case, since the voltages of the sustain electrode XE and the scan electrode YE during the sustain period SUS are always equal to or higher than the ground voltage GND, the address electrode AE can be prevented from becoming lower than the ground voltage GND during the sustain period SUS. Thereby, when the transistor NM1 is off, it is possible to reliably prevent leakage current from flowing from the ground line GND to the address electrode AE via the parasitic diode of the transistor NM1. As a result, power consumption can be reliably reduced. Also in this case, the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, the example in which the address driver AD is configured by the pMOS transistor PM1 and the nMOS transistor NM1 has been described. The present invention is not limited to such an embodiment. For example, the address driver AD may be composed of a PNP bipolar transistor and an NPN bipolar transistor instead of the pMOS transistor PM1 and the nMOS transistor NM1. Alternatively, as illustrated in FIG. 16, the address driver AD may be configured using an nMOS transistor NM2 instead of the pMOS transistor PM1. In this case, the gate of the nMOS transistor NM2 receives, for example, a control signal whose logic level (high logic and low logic) is opposite to the control signal received by the gate of the pMOS transistor PM1 shown in FIG.

FIG. 16 shows a modification of the address electrode driver ADR shown in FIGS. 5 and 6 described above. The address electrode driver ADR7 shown in FIG. 16 is provided with an address driver AD2 (AD2a) instead of the address driver AD shown in FIG. Further, in the address electrode driver ADR7, a power supply unit PS2 (PS2a), an inverter INV1 (INV1a), and a level shifter LS1 (LS1a) provided for each address driver AD2 are added to the address electrode driver ADR shown in FIG. Configured. Other configurations are the same as those in FIG. 5 (the configuration of the power supply unit PS1 is the same as that in FIG. 6). The same elements as those described in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. Note that a circuit group (a circuit group including the address driver AD2 and the power supply unit PS1) of the address electrode drive unit ADR7 excluding the power supply cutoff unit PSI10 is also referred to as an address drive circuit ADRC3.

For example, the transistor NM2 of the address driver AD2 has a source connected to the node ND1 (address electrode AE and the drain of the transistor NM1), a drain connected to the internal power supply line LN10, and a gate connected to the output of the inverter INV1. That is, the cathode of the parasitic diode of the transistor NM2 is connected to the internal power supply line LN10, and the anode of the parasitic diode of the transistor NM2 is connected to the node ND1. As a result, leakage current can be prevented from flowing from the internal power supply line LN10 to the reference power supply line LN20 via the parasitic diode.

The configuration of the power supply unit PS2 (PS2a) is the same as that of the power supply unit PS1 except that the coil L2 and the capacitor C1 are connected to the node ND1 (ND1a). Based on the AC voltage Vadd2 applied to the coil L1 of the transformer T1 of the power supply unit PS2, the power supply unit PS2 generates the power supply voltage Vadd3 using the voltage of the node ND1 as a reference (minimum voltage). The power supply voltage Vadd3 is supplied to the inverter INV1 as the power supply voltage of the inverter INV1. For example, the voltage Vadd3 is a voltage higher than the threshold voltage of the transistor NM2. Further, the voltage of the node ND1 is supplied to the inverter INV1 as the reference voltage (minimum voltage) of the inverter INV1. Note that the transformer T1 of the power supply unit PS1 and the transformer T1 of the power supply unit PS2 may be configured to share the coil L1.

The input terminal of the inverter INV1 is connected to the driver control unit ADCN via the level shifter LS1 and the isolator IS1. The level shifter LS1 is a circuit that shifts the input (output of the isolator IS1) signal to a level that matches the input range of the inverter INV1, and outputs the shifted signal to the inverter INV1.

Thereby, regardless of the state of the reference power supply line LN20, the inverter INV1 can output a voltage higher than the voltage of the node ND1 by the voltage Vadd3 to the transistor NM2 when the address control signal ACNT is at the L level. At this time, the transistor NM2 is turned on because the voltage Vadd3 larger than the threshold voltage is applied between the gate and the source. Further, regardless of the state of the reference power supply line LN20, the inverter INV1 can output the voltage of the node ND1 to L level and output it to the transistor NM2 when the address control signal ACNT is at H level. At this time, the transistor NM2 is turned off because a voltage (0 V) smaller than the threshold voltage is applied between the gate and the source.

The gate of the transistor NM1 of the address driver AD2 is connected to the level shifter LS1 and to the driver control unit ADCN via the isolator IS1. Therefore, even in the configuration of FIG. 16, the discharge operation of subfield SF can be made the same as in FIG. For example, the address drive circuit ADRC3 and the ground line GND can be electrically disconnected by setting the control signal SCNT to the L level during the sustain period SUS. Even when the address driver AD2 is configured by the nMOS transistors NM1 and NM2, it is possible to obtain the same effect as that of the embodiment described with reference to FIGS. In the embodiment described with reference to FIG. 8 to FIG. 15, even when the address driver AD2 is used instead of the address driver AD, the same effect as that of the embodiment described with reference to FIG. 8 to FIG. Can be obtained.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modification are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

The present invention can be applied to a plasma display device and a method for controlling the plasma display device.

Claims

A plasma display panel that generates a sustain discharge between the sustain electrode and the scan electrode and generates an address discharge between the scan electrode and the address electrode; and a driving unit that drives the plasma display panel,
The plasma display panel includes a first substrate having the sustain electrodes, the scan electrodes, and the address electrodes, and a second substrate facing the first substrate through a discharge space,
One field for displaying one screen includes a plurality of subfields having an address period for generating an address discharge and a sustain period for generating a sustain discharge.
The drive unit is
A first transistor for receiving a power supply voltage during the address period and applying the power supply voltage to the address electrode based on an address control signal, and a ground voltage when the first transistor during the address period is off. An address electrode applying unit including a second transistor for applying the ground voltage to the address electrode based on the address control signal;
A plasma display apparatus comprising: a power cutoff unit that cuts off either the power supply voltage or the ground voltage supplied to the address electrode application unit during the sustain period.
The plasma display device according to claim 1, wherein
The power shut-off unit is disposed between a reference power line connected to the second transistor and a ground line, and is turned on to supply the ground voltage from the ground line to the reference power line during the address period, A switch that is turned off during the sustain period;
The drive unit is
A plasma display device comprising: a power supply unit connected to a ground line through the reference power supply line and the power supply cutoff unit, and supplying the power supply voltage to an internal power supply line to which the first transistor is connected. .
The plasma display device according to claim 2, wherein
The drive unit includes a switch control unit that turns on the switch during the address period and turns off the switch during the sustain period;
The switch is composed of a pair of N-channel FETs connected in series between the reference power line and the ground line,
The pair of N-channel FETs are connected in a direction in which the anodes of the parasitic diodes formed in the N-channel FET are connected to each other, and a common node that connects the gates of the pair of N-channel FETs to each other is the switch control unit A plasma display device connected to the plasma display device.
The plasma display device according to claim 2, wherein
The plasma display apparatus, wherein the driving unit includes a driver control unit that generates the address control signal for turning off the first and second transistors during the sustain period.
The plasma display device according to claim 1, wherein
The driving unit includes a driver control unit that generates the address control signal for turning off the first and second transistors during the sustain period,
The power cutoff unit is disposed between a first power supply line to which the power supply voltage is supplied and the first transistor, and is turned on to supply the power supply voltage to the first transistor in the address period, Consists of switches that turn off during the sustain period,
The plasma display apparatus, wherein the second transistor is connected to a ground line to receive the ground voltage.
The plasma display device according to claim 5, wherein
The drive unit includes a switch control unit that turns on the switch during the address period and turns off the switch during the sustain period;
2. The plasma display device according to claim 1, wherein the switch includes an N-channel FET having a source, a drain, and a gate connected to the first power line, the first transistor, and the switch control unit, respectively.
The plasma display device according to claim 1, wherein
The driving unit includes a driver control unit that generates the address control signal for turning off the first and second transistors during the sustain period,
The power shut-off unit is disposed between a first power supply line to which the power supply voltage is supplied and the first transistor, an anode is connected to the first power supply line, and a cathode is connected to the first transistor. Composed of diodes,
The plasma display apparatus, wherein the second transistor is connected to a ground line to receive the ground voltage.
A plasma display panel that generates a sustain discharge between the sustain electrode and the scan electrode and generates an address discharge between the scan electrode and the address electrode; and a driving unit that drives the plasma display panel,
The plasma display panel includes a first substrate having the sustain electrodes, the scan electrodes, and the address electrodes, and a second substrate facing the first substrate through a discharge space,
One field for displaying one screen includes a plurality of subfields having an address period for generating an address discharge and a sustain period for generating a sustain discharge.
The drive unit is
A first transistor for receiving a power supply voltage during the address period and applying the power supply voltage to the address electrode based on an address control signal, and a ground voltage when the first transistor during the address period is off. An address electrode applying unit including a second transistor for applying the ground voltage to the address electrode based on the address control signal;
A switch disposed between the address electrode application unit and the address electrode and configured to cut off a current flowing from the first transistor to the address electrode and a current flowing from the address electrode to the second transistor during the sustain period. And a plasma display device.
The plasma display device according to claim 8, wherein
The drive unit includes a switch control unit that turns on the switch during the address period and turns off the switch during the sustain period;
The switch includes a pair of N-channel FETs connected in series between the address electrode application unit and the address electrode,
The pair of N-channel FETs are connected in a direction in which the anodes of the parasitic diodes formed in the N-channel FET are connected to each other, and a common node that connects the gates of the pair of N-channel FETs to each other is the switch control unit A plasma display device connected to the plasma display device.
A plasma display panel for generating a sustain discharge between the sustain electrode and the scan electrode provided on the first substrate and generating an address discharge between the scan electrode and the address electrode provided on the first substrate; and the address electrode An address driving circuit for selectively applying a pulse, wherein the address driving circuit includes an internal power source for generating the pulse,
One field for displaying one screen includes a plurality of subfields having an address period for generating an address discharge and a sustain period for generating a sustain discharge.
In the plasma display apparatus, the address driving circuit and the ground line are electrically connected in the address period, and the address driving circuit and the ground line are electrically disconnected in the sustain period. Control method.
A plasma display panel for generating a sustain discharge between the sustain electrode and the scan electrode provided on the first substrate and generating an address discharge between the scan electrode and the address electrode provided on the first substrate; and the address electrode An address voltage application unit that selectively applies a pulse, and the address voltage application unit includes a first transistor and a second transistor connected in series between a power supply line and a ground line, A control method of a plasma display apparatus, wherein a common node connecting the first transistor and the second transistor to each other is connected to the address electrode,
One field for displaying one screen includes a plurality of subfields having an address period for generating an address discharge and a sustain period for generating a sustain discharge.
In the address period, supply a power supply voltage to the power supply line,
A method of controlling a plasma display device, wherein a power supply voltage supplied to the power supply line is cut off and the second transistor is turned off during the sustain period.