JP2011257620A - Driving method of plasma display device and plasma display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate ramp waveform voltage while reducing power consumption by plasma display device.SOLUTION: The plasma display device has a scan electrode driving circuit which comprises: a clamping part; a power recovery section having inductor L51; and a switching section for applying an intermediate voltage (Vs1+Vs2)/2 between a first voltage Vs1 and a second voltage Vs2 to a scanning electrode. In a first period T11, an interelectrode capacity Cp and the inductor L51 are caused to resonate to reduce the voltage of the scanning electrode, which has a voltage higher than an intermediate voltage (Vs1+Vs2)/2 between a first voltage Vs1 and a second voltage Vs2, to a predetermined voltage higher than the intermediate voltage (Vs1+Vs2)/2. In a second period T12, the switching section is closed to reduce the voltage on the scanning electrode from the predetermined voltage to an intermediate voltage (Vs1+Vs2)/2. In a third period T13, the switching section is opened to cause the interelectrode capacity Cp and the inductor L51 to resonate again to thereby reduce the voltage of the scanning electrode to a voltage lower than the intermediate voltage (Vs1+Vs2)/2.

Description

  The present invention relates to a driving method of an AC surface discharge type plasma display device and a plasma display device.

  A typical plasma display panel (hereinafter abbreviated as “panel”) as a display device includes a front substrate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed, and a plurality of data electrodes. A plurality of discharge cells are formed between the rear substrate and the rear substrate. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays to perform color display.

  As a method for driving the panel, a subfield method in which one field period is divided into a plurality of subfields and gray levels are displayed by a combination of subfields to emit light is generally used. Each subfield has an initialization period, an address period, and a sustain period. During the initialization period, a slowly changing ramp waveform voltage is applied to the scan electrodes to generate a weak initialization discharge, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. To display an image.

  Here, the sustain pulse applied to the display electrode pair in the sustain period is a so-called power recovery circuit that drives the display electrode pair by resonating the interelectrode capacitance of the display electrode pair and the inductor in order to reduce power consumption. (See, for example, Patent Document 1).

  Further, the ramp waveform voltage applied to the scan electrodes in the initialization period is generated using a Miller integrating circuit (see, for example, Patent Document 2).

JP 11-242458 A Japanese Patent Laid-Open No. 11-133914

  However, when the ramp waveform voltage is generated using the Miller integration circuit, there is a problem that the power consumption increases when the Miller integration circuit is operated over a wider voltage range than necessary. Furthermore, with the recent increase in screen size of panels, this increase in power consumption cannot be ignored. Since the Miller integrating circuit uses semiconductor elements in the active region, it cannot be used to disperse power consumption by connecting the semiconductor elements in parallel unless semiconductor elements having completely the same characteristics are used. Therefore, when power is increased, usable semiconductor elements are limited, and the heat dissipation design becomes difficult.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a plasma display device driving method and a plasma display device including a driving circuit capable of generating a ramp waveform voltage while suppressing power consumption. To do.

  In order to achieve the above object, the present invention applies a sustain pulse having a first voltage and a second voltage to a scan electrode of a panel in which a plurality of discharge cells each having a scan electrode and a sustain electrode are arranged. A driving method of a plasma display apparatus for generating a sustain discharge to display an image, comprising: a clamp unit that clamps a sustain pulse voltage to a first voltage or a second voltage; an inductor; and a scan electrode and a sustain electrode A power recovery unit that causes the interelectrode capacitance and the inductor to resonate to rise or fall the sustain pulse, and a switch unit to apply an intermediate voltage between the first voltage and the second voltage to the scan electrode A scan electrode drive circuit is provided, and the interelectrode capacitance and the inductor are caused to resonate, and the voltage of the scan electrode that is higher than the intermediate voltage between the first voltage and the second voltage is referred to as the intermediate voltage. A first period in which the voltage is lowered to a higher predetermined voltage, a second period in which the switch unit is closed and the voltage of the scan electrode is decreased from a predetermined voltage to an intermediate voltage, and the switch unit is opened and the interelectrode capacitance and the inductor are And a third period in which the scan electrode voltage is lowered to a voltage lower than the intermediate voltage. By this method, it is possible to provide a driving method for a plasma display device including a driving circuit capable of generating a ramp waveform voltage while suppressing power consumption.

  The present invention also applies a sustain pulse having a first voltage and a second voltage to a scan electrode of a panel in which a plurality of discharge cells each having a scan electrode and a sustain electrode are arranged to generate a sustain discharge in the discharge cell. A plasma display device for displaying an image, comprising: a clamp unit that clamps a sustain pulse voltage to a first voltage or a second voltage; an inductor; an interelectrode capacitance between the scan electrode and the sustain electrode; and an inductor A scan electrode driving circuit having a power recovery unit that resonates and causes the sustain pulse to rise or fall, and a switch unit for applying an intermediate voltage between the first voltage and the second voltage to the scan electrode; The drive circuit resonates the interelectrode capacitance and the inductor so that the voltage of the scan electrode, which is higher than the intermediate voltage between the first voltage and the second voltage, is higher than the intermediate voltage. The voltage of the scan electrode is lowered from the predetermined voltage to the intermediate voltage by closing the switch unit, and the resonance between the interelectrode capacitance and the inductor is resumed by opening the switch unit and the voltage of the scan electrode is set to the intermediate voltage. The voltage is lowered to a lower voltage. With this configuration, it is possible to provide a plasma display device including a drive circuit that can generate a ramp waveform voltage while suppressing power consumption.

  Moreover, the switch part of this invention may have the structure which has a switching element and a diode connected in series, and flows an electric current only in one direction.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the drive method and plasma display apparatus of a plasma display apparatus provided with the drive circuit which can generate a ramp waveform voltage, suppressing power consumption.

It is a disassembled perspective view of the panel of the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel of the plasma display apparatus. It is a drive voltage waveform figure of the plasma display apparatus. It is a circuit block diagram of the plasma display device. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a timing chart which shows the detail of the sustain pulse of the same plasma display apparatus. It is a timing chart which shows the detail of the downward gradient waveform voltage of the plasma display apparatus. It is a circuit diagram of the switch part of the scan electrode drive circuit of the plasma display apparatus in Embodiment 2 of this invention. It is a timing chart which shows the detail of the downward gradient waveform voltage of the plasma display apparatus.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. In the present embodiment, a discharge gas with a xenon partial pressure of 10% is used to improve luminance. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  As described above, the panel in the present embodiment has a configuration in which a plurality of discharge cells each having scan electrode 12 and sustain electrode 13 are arranged. The panel 10 is not limited to the one described above, and may be provided with, for example, striped partition walls.

  FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 13 in FIG. 1) that are long in the row direction. M data electrodes D1 to Dm (data electrodes 22 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi (i = 1 to n) intersects with one data electrode Dj (j = 1 to m). , M × n discharge cells are formed in the discharge space. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode. There is a large interelectrode capacitance Cp between SUn.

  Next, a driving method for driving the panel 10 will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  During the initialization period, at least one of a slowly increasing ramp waveform voltage and a slowly decreasing ramp waveform voltage is applied to the scan electrode to generate a weak initialization discharge, and wall charges necessary for the subsequent address discharge are applied to each electrode. Form on top. The initializing operation at this time includes a forced initializing operation for forcibly generating an initializing discharge in all the discharge cells and a selective initializing operation for generating an initializing discharge in the discharge cells that have generated a sustain discharge. . In the address period, a scan pulse is applied to scan electrode SC1 to scan electrode SCn, and an address pulse is selectively applied to data electrode D1 to data electrode Dm to generate an address discharge selectively in the discharge cells to be lit. Form wall charges. In the sustain period, a number of sustain pulses corresponding to the luminance weight are applied to scan electrode SC1 through scan electrode SCn, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light. At this time, a pulse voltage synchronized with the sustain pulse is also applied to the data electrodes D1 to Dm. In the present embodiment, sustain pulse is applied only to scan electrode SC1 through scan electrode SCn, and no sustain pulse is applied to sustain electrode SU1 through sustain electrode SUn.

  In the present embodiment, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is, for example, (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). Further, the subfield SF1 is a subfield for performing a forced initialization operation, and the subsequent subfields SF2 to SF10 are subfields for performing a selective initialization operation. However, in the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  FIG. 3 is a drive voltage waveform diagram of the plasma display device in accordance with the exemplary embodiment of the present invention, and shows the drive voltage waveform applied to each electrode of panel 10 in each subfield.

  In the first half of the initialization period of subfield SF1, 0 (V) is applied to data electrode D1 through data electrode Dm, and 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. Then, a ramp waveform voltage that gradually increases toward positive voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrode SC1 through scan electrode SCn, sustain electrode SU1 through sustain electrode SUn, and data electrode D1 through data electrode Dm. Wall voltage is accumulated in Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the second half of the initialization period, a ramp waveform voltage that gradually decreases toward negative voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn. Then, a weak initializing discharge occurs again during this period, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  Thus, in the initializing period of subfield SF1, a forced initializing operation for forcibly generating initializing discharge in all the discharge cells is performed.

  In the address period of subfield SF1, voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

  Next, a scan pulse of negative voltage Va is applied to scan electrode SC1 in the first row. Then, an address pulse of a positive voltage Vd is applied to the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which no address pulse is applied. In this way, the write operation is selectively performed.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk of the discharge cell to be emitted in the second row among data electrodes D1 to Dm. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  Although details will be described later in the sustain period of subfield SF1, first voltage Vs1 (hereinafter simply referred to as “voltage”) is applied to scan electrode SC1 through scan electrode SCn while 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn. A sustain pulse (abbreviated as “Vs1”) is applied. Further, the pulse of the voltage Vd is also applied to the data electrodes D1 to Dm. Then, a sustain discharge is generated in the discharge cell that has caused the address discharge in the address period.

  Next, a sustain pulse of second voltage Vs2 (hereinafter simply referred to as “voltage Vs2”) is applied to scan electrode SC1 through scan electrode SCn while applying 0 (V) to sustain electrode SU1 through sustain electrode SUn. . Further, 0 (V) is also applied to the data electrodes D1 to Dm. Then, a sustain discharge is generated in the discharge cell that has caused the address discharge in the address period.

  Similarly, the sustaining pulse of positive voltage Vs1 and the sustaining pulse of negative voltage Vs2 are applied to scan electrode SC1 through scan electrode SCn by the number set in accordance with the luminance weight, and data electrode D1 through data electrode are applied. The same number of pulse voltages are applied to Dm. As a result, the sustain discharge is continuously generated in the discharge cells that have caused the address discharge in the address period.

  The reason for applying the pulse voltage to the data electrodes D1 to Dm is as follows. Assuming that a constant voltage is applied to data electrode D1 to data electrode Dm in the sustain period, the sustain pulse amplitude (Vs2−Vs1) is large, so that data electrode D1 to data electrode Dm There is a risk of discharge occurring between scan electrode SC1 and scan electrode SCn. When discharge occurs regardless of the presence or absence of address discharge, images cannot be displayed normally. Therefore, in the present embodiment, a pulse voltage having the same phase as the sustain pulse is also applied to data electrode D1 to data electrode Dm, and discharge between data electrode D1 to data electrode Dm and scan electrode SC1 to scan electrode SCn is performed. It is suppressed.

  In the subsequent initializing period of subfield SF2, the ramp waveform voltage gently decreasing toward voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn, as will be described in detail later. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge is performed in the sustain period of subfield SF1, and the wall voltage on each electrode is adjusted to a value suitable for the address operation. As described above, in the initialization period of the subfield SF2, the selective initialization operation for generating the initialization discharge in the discharge cells in which the sustain discharge has been performed is performed.

  The subsequent address period and sustain period are substantially the same as the address period and sustain period of the subfield SF1, and the description thereof is omitted. The subsequent subfield SF3 to subfield SF10 are similar to the operation of subfield SF2 except for the number of sustain pulses.

  As described above, in the present embodiment, a sustain pulse having the first voltage Vs1 and the second voltage Vs2 is applied to generate a sustain discharge in the discharge cells, thereby displaying an image.

  Note that the voltage values applied to the electrodes in this embodiment are, for example, the voltage Vi2 = 350 (V), the voltage Vi4 = −300 (V), the voltage Vc = −170 (V), and the voltage Va = −320 ( V), voltage Vs1 = 200 (V), voltage Vs2 = −200 (V), and voltage Vd = 60 (V). However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate according to the characteristics of the panel, the specifications of the plasma display device 30, and the like.

  FIG. 4 is a circuit block diagram of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 32 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuit blocks. Scan electrode drive circuit 33 drives each of scan electrode SC1 through scan electrode SCn based on the timing signal. In the present embodiment, sustain electrode drive circuit 34 applies 0 (V) to sustain electrode SU1 through sustain electrode SUn.

  FIG. 5 is a circuit diagram of scan electrode drive circuit 33 of plasma display device 30 in accordance with the exemplary embodiment of the present invention. FIG. 5 also shows the interelectrode capacitance Cp of the panel 10 for later explanation. Scan electrode drive circuit 33 includes sustain pulse generator 50, ramp waveform voltage generator 55, ramp waveform voltage generator 56, reference potential setting unit 57, switch unit 58, and scan pulse generator 59. .

  Sustain pulse generating unit 50 includes capacitor C51, power recovery unit 51 including switching element Q51, switching element Q52, diode D51, diode D52, and inductor L51, and clamp unit 53 including switching element Q53 and switching element Q54. Is provided.

  The power recovery unit 51 causes the sustain pulse to rise or fall by resonating the interelectrode capacitance Cp between the scan electrode SC1 to the scan electrode SCn and the sustain electrode SU1 to the sustain electrode SUn and the inductor L51. At the rising edge of the sustain pulse, a current is passed from the capacitor C51 via the switching element Q51, the diode D51, and the inductor L51 to move the charge to the interelectrode capacitance Cp. When the sustain pulse falls, the charge stored in the interelectrode capacitance Cp is returned to the capacitor C51 via the inductor L51, the diode D52, and the switching element Q52. Thus, the power recovery unit 51 includes the inductor L51 and resonates the interelectrode capacitance Cp between the scan electrode SC1 to the scan electrode SCn and the sustain electrode SU1 to the sustain electrode SUn, and the inductor L51, so that the negative polarity is generated from the positive voltage Vs1. The rising and falling of the sustain pulse that changes to the voltage Vs2 is performed. As described above, since the power recovery unit 51 drives the scan electrodes SC1 to SCn by resonance without being supplied with power from the power source, the power consumption is ideally “0”. The capacitor C51 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to an intermediate potential between the voltage Vs1 and the voltage Vs2, that is, the voltage ((Vs1 + Vs2) / 2). Work as.

  Clamp unit 53 clamps scan electrode SC1 through scan electrode SCn to positive voltage Vs1 through switching element Q53, and clamps scan electrode SC1 through scan electrode SCn to negative voltage Vs2 through switching element Q54. . In this way, the clamp unit 53 clamps the sustain pulse voltage to the voltage Vs1 or Vs2. Therefore, the impedance at the time of voltage application by the clamp part 53 is small, and a large discharge current due to strong sustain discharge can flow stably.

  Then, the power recovery unit 51 and the clamp unit 53 output a sustain pulse to the node P59 which is a reference potential of the scan pulse generator 59, and the interelectrode capacitance is passed through the scan pulse generator 59 (becomes a short circuit during the sustain period). A sustain pulse is applied to scan electrode SC1 through scan electrode SCn, which is one end of Cp.

  The ramp waveform voltage generation unit 55 is configured by a Miller integrating circuit having an FET, a capacitor, and a resistor, generates an up ramp waveform voltage that rises to a positive voltage Vr, and outputs it to the node P59. The ramp waveform voltage generation unit 56 is configured by a Miller integrating circuit having an FET, a capacitor, and a resistor, generates a ramp waveform voltage that decreases to a negative voltage Vi4, and outputs the voltage to the node P59. The reference potential setting unit 57 includes a switching element Q57 that sets the voltage at the node P59 to the negative voltage Va.

  The switch unit 58 includes a switching element Q58 that sets the voltage at the node P59 to a voltage ((Vs1 + Vs2) / 2). Thus, the switch unit 58 can apply the intermediate voltage ((Vs1 + Vs2) / 2) between the first voltage Vs1 and the second voltage Vs2 to the scan electrodes SC1 to SCn.

  Scan pulse generator 59 is a switching element that applies power supply E59 of positive voltage Vq superimposed on the reference potential of scan pulse generator 59 and a high-voltage side voltage of power supply E59 to scan electrode SC1 through scan electrode SCn. Q5H1 to switching element Q5Hn, and switching element Q5L1 to switching element Q5Ln for applying the voltage on the low voltage side of power supply E59 to scan electrode SC1 to scan electrode SCn. Then, a scan pulse is applied to each scan electrode SC1 to scan electrode SCn.

  In this embodiment, voltage Vq = 150 (V), voltage Vc is equal to voltage (Vq + Va), and voltage Vi2 is equal to voltage (Vr + Vq).

  First, details of sustain pulses applied to scan electrode SC1 through scan electrode SCn in the sustain period will be described. FIG. 6 is a timing chart showing details of the sustain pulse of plasma display device 30 in the first exemplary embodiment of the present invention, and also shows the current flowing through inductor L51 at that time.

  Here, one repetition period of the sustain pulse is divided into four periods indicated by T1 to T4, and each period will be described in detail.

(Period T1)
At time t1, switching element Q51 of power recovery unit 51 is turned on. Then, a current starts to flow from capacitor C51 to scan electrode SC1 through scan electrode SCn through switching element Q51, diode D51, and inductor L51, and the voltage of scan electrode SC1 through scan electrode SCn begins to rise. Then, after 1/2 of the resonance period of inductor L51 and interelectrode capacitance Cp, the voltage of scan electrode SC1 through scan electrode SCn rises to approximately voltage Vs1, and the current flowing through inductor L51 becomes “0”.

(Period T2)
At time t2 after the current flowing through the inductor L51 becomes “0”, the switching element Q53 of the clamp unit 53 is turned on. Then, scan electrode SC1 to scan electrode SCn are clamped to voltage Vs1. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn exceeds the discharge start voltage, and a sustain discharge occurs.

  After the sustain discharge converges, switching elements Q51 and Q53 of sustain pulse generating unit 50 are turned off.

(Period T3)
At time t3, the switching element Q52 of the power recovery unit 51 is turned on. Then, current starts to flow from scan electrode SC1 to scan electrode SCn to capacitor C51 through inductor L51, diode D52, and switching element Q52, and the voltage of scan electrode SC1 to scan electrode SCn starts to drop. Then, after ½ of the resonance period of inductor L51 and interelectrode capacitance Cp, the voltage of scan electrode SC1 through scan electrode SCn drops substantially to voltage Vs2, and the current flowing through inductor L51 becomes “0”.

(Period T4)
At time t4 after the current flowing through the inductor L51 becomes “0”, the switching element Q54 of the clamp unit 53 is turned on. Then, the voltage of scan electrode SC1 through scan electrode SCn is clamped at voltage Vs2. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn exceeds the discharge start voltage, and sustain discharge occurs.

  After the sustain discharge converges, switching elements Q52 and Q54 of sustain pulse generating unit 50 are turned off.

  By repeating the operations in period T1 to period T4, sustain pulse generating unit 50 in the present embodiment applies the necessary number of sustain pulses to scan electrode SC1 to scan electrode SCn.

  In the present embodiment, the resonance period of the inductor L51 and the interelectrode capacitance Cp is set to 1200 nsec, and the lengths of the periods T1 and T3 are set to 700 nsec. The lengths of the period T2 and the period T4 are set to 1800 nsec.

  Next, details of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn in the initialization period of subfield SF2 to subfield SF10 in which selective initialization is performed will be described. FIG. 7 is a timing chart showing details of the downward ramp waveform voltage of the plasma display device 30 according to the first exemplary embodiment of the present invention, and also shows the current flowing through the inductor L51 at that time.

  Here, the initialization period of subfield SF2 to subfield SF10 is divided into a first period T11 to a fourth period T14, and each period will be described in detail.

  Immediately before the initialization period of subfield SF2 to subfield SF10, that is, at the end of the sustain period of subfield SF1 to subfield SF9, voltage Vs1 is applied to scan electrode SC1 to scan electrode SCn.

(Period T11)
At time t11, the switching element Q52 of the power recovery unit 51 is turned on. Then, current starts to flow from scan electrode SC1 to scan electrode SCn to capacitor C51 through inductor L51, diode D52, and switching element Q52, and the voltage of scan electrode SC1 to scan electrode SCn starts to drop.

  Thus, in the first period T11, the interelectrode capacitance Cp and the inductor L51 resonate, and the scan electrodes SC1 to SC1 having a voltage higher than the intermediate voltage (Vs1 + Vs2) / 2 between the first voltage Vs1 and the second voltage Vs2. The voltage of scan electrode SCn is lowered to a predetermined voltage higher than intermediate voltage (Vs1 + Vs2) / 2.

(Period T12)
After ¼ of the resonance period of the inductor L51 and the interelectrode capacitance Cp, as indicated by a dotted line in FIG. 7, the absolute value of the current flowing through the inductor L51 becomes maximum, and the voltage of scan electrode SC1 to scan electrode SCn. Drops to approximately voltage (Vs1 + Vs2) / 2. However, in the present embodiment, the switching element Q58 of the switch unit 58 is turned on when the voltage of the scan electrode SC1 to the scan electrode SCn drops to a predetermined voltage at time t12 before ¼ of the resonance period. . Then, the voltage of scan electrode SC1 through scan electrode SCn rapidly decreases to the voltage ((Vs1 + Vs2) / 2).

  As described above, in the second period T12, the switch unit 58 is closed, and the voltage of the scan electrodes SC1 to SCn is decreased from a predetermined voltage to an intermediate voltage (Vs1 + Vs2) / 2.

(Period T13)
Switching element Q58 is turned off at time t13. Then, again, current flows from scan electrode SC1 to scan electrode SCn to capacitor C51 through inductor L51, diode D52, and switching element Q52, and the voltage of scan electrode SC1 to scan electrode SCn begins to drop to voltage (Vs1 + Vs2) / 2 or less. Then, when the current flowing through inductor L51 becomes “0”, the voltage drop of scan electrode SC1 through scan electrode SCn stops. The ultimate voltage Vx of scan electrode SC1 through scan electrode SCn at this time is determined by the timing at which switching element Q58 is turned on. If the switching element Q58 is turned on early, the current flowing through the inductor L51 decreases and the ultimate voltage Vx increases. Conversely, if the timing for turning on the switching element Q58 is late, the current flowing through the inductor L51 increases, and the ultimate voltage Vx decreases.

  As described above, the power recovery unit 51 is used to change the voltage of scan electrode SC1 to scan electrode SCn to desired desired voltage Vx within the range of voltage (Vs1 + Vs2) / 2 to voltage Vs2 at the timing when switching element Q58 is turned on. Can be set to Here, the ultimate voltage Vx is set to a voltage that does not reach the voltage at which the initialization discharge starts, that is, a voltage that is higher than the voltage at which the initialization discharge starts.

  In this way, in the third period T13, the switch unit 58 is opened, the resonance between the interelectrode capacitance Cp and the inductor L51 is resumed, and the voltage of the scan electrode SC1 to the scan electrode SCn is changed from the intermediate voltage (Vs1 + Vs2) / 2. Is also reduced to a low voltage Vx.

(Period T14)
The ramp waveform voltage generator 56 is operated at time t14. Then, the voltage of scan electrode SC1 through scan electrode SCn gently drops from ultimate voltage Vx toward voltage Vi4. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge is performed in the sustain period of subfield SF1, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  Thus, in the present embodiment, by setting the ultimate voltage Vx to a voltage that does not reach the voltage at which the initializing discharge starts and is as low as possible, the Miller integrating circuit of the ramp waveform voltage generator 56 is The operating voltage range can be narrowed, and the power consumption of the ramp waveform voltage generator 56 can be suppressed. Therefore, according to the present embodiment, a compact ramp waveform voltage generation unit 56 can be realized using a general-purpose semiconductor element.

  In the present embodiment, when the positive voltage Vs1 and the negative voltage Vs2 have the same absolute value, that is, when the voltage Vs2 = the voltage (−Vs1), the capacitor C51 is omitted and the ground potential ( That is, you may connect directly to 0 (V).

(Embodiment 2)
The circuit block diagram of panel 10 and plasma display device 30 used in the second exemplary embodiment is the same as the circuit block diagram of panel 10 and plasma display device 30 used in the first exemplary embodiment. Components similar to those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted. The difference between the second embodiment and the first embodiment is the circuit configuration of the switch unit 58 of the scan electrode drive circuit 33.

  FIG. 8 is a circuit diagram of switch unit 58 of scan electrode drive circuit 33 of plasma display device 30 in the second exemplary embodiment of the present invention. For the sake of explanation, FIG. 8 shows the interelectrode capacitance Cp of the panel 10, a part of the power recovery unit 51, and the ramp waveform voltage generation unit 56. However, the clamp unit 53, the ramp waveform voltage generation unit 55, the reference potential setting unit 57, and the scan pulse generation unit 59 are omitted.

  In the second embodiment, the absolute values of the positive voltage Vs1 and the negative voltage Vs2 of the sustain pulse are set equal. That is, Vs2 = (− Vs1). As a result, ((Vs1 + Vs2) / 2) = 0, the capacitor C51 of the power recovery unit 51 is omitted, and is directly connected to the ground potential.

  The switch unit 58 includes a switching element Q71 and a diode D71 that constitute a switch for setting the voltage at the node P59 to voltage ((Vs1 + Vs2) / 2) = 0 (V).

  When switching element Q71 is turned on, a current can flow from node P59 toward the ground potential. However, no current can flow from the ground potential toward the node P59. As described above, the switching element Q71 and the diode D71 constitute a switch circuit capable of flowing a current only in one direction.

  The switching element Q99 and the diode D99 are separation switches, and are provided to prevent a current from flowing back through the parasitic diode of the transistor that constitutes the scan electrode driving circuit 33.

  Next, details of the downward ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn in the initialization period of subfield SF2 to subfield SF10 in which selective initialization is performed will be described. FIG. 9 is a timing chart showing details of the downward ramp waveform voltage of the plasma display device 30 in the second exemplary embodiment of the present invention, and also shows the current flowing through the inductor L51 at that time.

  Again, the initialization period of subfield SF2 to subfield SF10 is divided into four periods T21 to T24, and each period will be described in detail.

  Immediately before the initialization period of subfield SF2 to subfield SF10, that is, at the end of the sustain period of subfield SF1 to subfield SF9, voltage Vs1 is applied to scan electrode SC1 to scan electrode SCn. The switching element Q99 is on.

(Period T21)
At time t21, the switching element Q52 of the power recovery unit 51 is turned on. Then, current starts to flow from scan electrode SC1 to scan electrode SCn to the ground potential through inductor L51, diode D52, and switching element Q52, and the voltage of scan electrode SC1 to scan electrode SCn starts to decrease.

(Period T22)
After ¼ of the resonance period of the inductor L51 and the interelectrode capacitance Cp, as indicated by a dotted line in FIG. 9, the absolute value of the current flowing through the inductor L51 becomes maximum, and the voltage of scan electrode SC1 to scan electrode SCn. Drops to approximately 0 (V). However, in the second embodiment as well, the switching element Q58 of the switch unit 58 is turned on at time t22 before 1/4 of the resonance period. Then, current flows to ground potential from scan electrode SC1 to scan electrode SCn through diode D71 switching element Q71, and the voltage of scan electrode SC1 to scan electrode SCn rapidly decreases to 0 (V).

(Period T23)
When the voltage of scan electrode SC1 through scan electrode SCn drops to 0 (V) at time t23, diode D71 is turned off. Therefore, a current again flows from scan electrode SC1 to scan electrode SCn to the ground potential through inductor L51, diode D52, and switching element Q52, and the voltage of scan electrode SC1 to scan electrode SCn starts to drop below 0 (V). Then, when the current flowing through inductor L51 becomes “0”, the voltage drop of scan electrode SC1 through scan electrode SCn stops. The ultimate voltage Vx of scan electrode SC1 to scan electrode SCn at this time is determined by the timing at which switching element Q71 is turned on, and the ultimate voltage Vx is high when the switching element Q71 is turned on early and the current flowing through inductor L51 is small. When the switching element Q71 is turned on late and the current flowing through the inductor L51 increases, the ultimate voltage Vx decreases.

  As described above, the power recovery unit 51 is used to change the voltage of scan electrode SC1 to scan electrode SCn to a desired ultimate voltage Vx in the range of voltage (Vs1 + Vs2) / 2 to voltage Vs2 at the timing when switching element Q71 is turned on. Can be set to Here too, the ultimate voltage Vx is set to a voltage that does not reach the voltage at which the initialization discharge starts, that is, a voltage that is higher than the voltage at which the initialization discharge starts.

(Period T24)
At time t24, switching element Q99 is turned off, and ramp waveform voltage generator 56 is operated. Then, the voltage of scan electrode SC1 through scan electrode SCn gently drops from ultimate voltage Vx toward voltage Vi4. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has been performed in the sustain period of the immediately preceding subfield, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  As described above, also in the second embodiment, by setting the ultimate voltage Vx to a voltage that does not reach the voltage at which the initializing discharge starts and is as low as possible, the Miller integrating circuit of the ramp waveform voltage generating unit 56 is set. Can be narrowed, and the power consumption of the ramp waveform voltage generator 56 can be suppressed. Therefore, also in the present embodiment, a compact ramp waveform voltage generator 56 can be realized using a general-purpose semiconductor element.

  Furthermore, in Embodiment 2, the switch part 58 has the switching element Q71 and the diode D71 which were connected in series, and is a structure which sends an electric current only to one direction. Since the diode D71 is automatically turned on when the voltage at the node P59 is reduced to 0 (V) or lower, the time corresponding to the period T12 in the first embodiment can be made substantially “0”.

  It should be noted that the specific numerical values used in the first and second embodiments are merely examples, and it is desirable to appropriately set optimal values in accordance with panel characteristics, plasma display device specifications, and the like. .

  The driving circuit of the present invention can generate a ramp waveform voltage while suppressing power consumption, and is useful as a driving method of a plasma display device and a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 50 Sustain pulse generation part 51 Electric power Recovery unit 53 Clamp unit 55, 56 Ramp waveform voltage generation unit 57 Reference potential setting unit 58 Switch unit 59 Scan pulse generation unit Cp Interelectrode capacitance L51 Inductor

Claims (3)

An image is generated by applying a sustain pulse having a first voltage and a second voltage to the scan electrode of a plasma display panel in which a plurality of discharge cells having scan electrodes and sustain electrodes are arranged to generate a sustain discharge in the discharge cells. A method of driving a plasma display device for displaying
The sustain pulse is clamped to the first voltage or the second voltage, and includes an inductor, and an interelectrode capacitance between the scan electrode and the sustain electrode and the inductor are caused to resonate to maintain the sustain. A scan electrode drive circuit having a power recovery unit that performs rising or falling of a pulse, and a switch unit for applying an intermediate voltage between the first voltage and the second voltage to the scan electrode;
Resonating the interelectrode capacitance and the inductor to reduce the voltage of the scan electrode at a voltage higher than the intermediate voltage between the first voltage and the second voltage to a predetermined voltage higher than the intermediate voltage. 1 period,
A second period in which the switch unit is closed to reduce the voltage of the scan electrode from the predetermined voltage to the intermediate voltage;
A third period in which the switch unit is opened to resonate the resonance between the interelectrode capacitance and the inductor to reduce the voltage of the scan electrode to a voltage lower than the intermediate voltage. Driving method of plasma display apparatus. An image is generated by applying a sustain pulse having a first voltage and a second voltage to the scan electrode of a plasma display panel in which a plurality of discharge cells having scan electrodes and sustain electrodes are arranged to generate a sustain discharge in the discharge cells. A plasma display device for displaying
The sustain pulse is clamped to the first voltage or the second voltage, and includes an inductor, and an interelectrode capacitance between the scan electrode and the sustain electrode and the inductor are caused to resonate to maintain the sustain. A scan electrode drive circuit having a power recovery unit that performs rising or falling of a pulse, and a switch unit for applying an intermediate voltage between the first voltage and the second voltage to the scan electrode;
The scan electrode driving circuit includes:
Resonating the interelectrode capacitance and the inductor to reduce the voltage of the scan electrode at a voltage higher than the intermediate voltage between the first voltage and the second voltage to a predetermined voltage higher than the intermediate voltage; The switch unit is closed to reduce the voltage of the scan electrode from the predetermined voltage to the intermediate voltage, and the switch unit is opened to resume the resonance between the interelectrode capacitance and the inductor, thereby reducing the voltage of the scan electrode. A plasma display apparatus, wherein the voltage is lowered to a voltage lower than the intermediate voltage. The plasma display apparatus according to claim 2, wherein the switch unit includes a switching element and a diode connected in series, and a current flows only in one direction.

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