WO2009092209A1

WO2009092209A1 - Pdp driving method

Info

Publication number: WO2009092209A1
Application number: PCT/CN2008/071855
Authority: WO
Inventors: Xiong Zhang; Jiajia Wen; Lanlan Yang; Yan TU; Lifeng Zhu; Baoping Wang; Qingyuan Lin
Original assignee: Nanjing Huaxian High Technology Co., Ltd.
Priority date: 2008-01-24
Filing date: 2008-08-01
Publication date: 2009-07-30
Also published as: CN101226718A; CN100530300C

Abstract

A shadow mask type PDP driving method is provided. At least one subfield is set during displaying one frame image. Each subfield comprises an address period, a sustain period and an erase period. Each sustain period comprises three phases. In the first phase an opposed discharge is performed between the scan electrode and the address electrode. In the second phase a surface discharge is performed between the scan electrode and the sustain electrode. In the third phase an opposed discharge is performed between the sustain electrode and the address electrode.

Description

Method for driving plasma display panel

Technical field

The invention relates to a driving method of a plasma display panel, in particular to a cyclic display driving method which combines the advantages of the prior art opposite discharge driving method and surface discharge driving method, in particular to a shadow mask plasma The cyclic display driving method of the display panel. Background technique

The structure of the shadow mask type plasma display panel currently used mainly includes a front substrate, a rear substrate, and a shadow mask. The front substrate is a scan electrode, a dielectric layer and a protective layer formed on the surface of the dielectric layer from the glass substrate; the rear substrate is an address electrode perpendicular to the scan electrode from the glass substrate, and the dielectric layer and the dielectric layer are formed on the dielectric layer. The protective layer sandwiched between the front and rear substrates is a thin metal mesh plate comprising a mesh array processed from a conductive material such as iron or an alloy thereof. The front substrate, the shadow mask and the rear substrate are assembled and sealed, and then filled with a predetermined working gas, such as various inert gases, to form a shadow mask plasma display panel. At present, the shadow mask type plasma display panel mainly adopts two working principles of a counter discharge and a surface discharge. The working principle of the counter-discharge is as follows: first, a high-voltage narrow pulse or a ramp pulse erase signal is applied between the address electrode group and the scan electrode to erase the wall charge accumulated in the last discharge; and then add a scan electrode The high pulse addressing voltage selects the row, and simultaneously applies a data pulse of the row on the address electrode. The difference between the voltage amplitude of the data pulse and the scan voltage is higher than the ignition voltage between the scan electrode and the address electrode, and the trigger discharge is controlled. Thereby, a wall charge distribution corresponding to the desired display information is formed in the row; after the initial discharge of the entire screen image is completed line by line, a sustain pulse is applied between the scan electrode group and the address electrode to display the frame image. This cycle allows you to display the image frame by frame. The working principle of the surface discharge is as follows: First, a positive pulse is applied to the address electrode, and a negative pulse is applied to the scan electrode. When the voltage between the address electrode and the scan electrode is greater than the ignition voltage, discharge occurs first, and the sustain discharge is accumulated. The required wall charge, while the unit is in a lit state, and then a positive sustain pulse is alternately applied to the sustain electrode and the scan electrode, and the lit discharge cell is kept lit by the combination of the wall charge and the sustain pulse. State until the arrival of the erase pulse. However, there are some problems in the above-mentioned counter-discharge or surface-discharge shadow mask type plasma display panel: the counter-discharge structure is adopted, the discharge path is short, and the discharge area is far from the phosphor, so the discharge efficiency is low; the surface discharge is adopted. Structure, although the discharge path becomes long and the discharge efficiency is improved, the brightness of the surface discharge is weaker than that of the opposite discharge, and the sustain voltage required for the surface discharge is relatively high. In summary, the existing surface discharge shadow mask plasma display panel and the opposite discharge shadow mask plasma display panel have some disadvantages. The object of the present invention is to solve the problem that the conventional shadow mask plasma display panel has low parallel discharge efficiency, low surface discharge brightness and high maintenance voltage, and a combination of three electrodes is formed. A cycle display driving method of a new shadow mask type plasma display panel which has advantages of discharge and surface discharge, and improved luminous efficiency and brightness.

The technical solution of the present invention is:

A cyclic display driving method for a shadow mask type plasma display panel, which is characterized in that a memory display mode is adopted, and a plurality of subfields are arranged in a time period for displaying one frame of image, each subfield consisting of an address period, a sustain period, and an erasure The composition of the period, the addressing period completes the ignition of the pixels of the full screen in turn, each sustain period consists of three stages, the first stage mainly performs the opposite discharge between the scan electrode and the address electrode, and the second stage mainly scans. The surface discharge between the electrode and the sustain electrode, the third stage mainly performs the opposite discharge between the sustain electrode and the address electrode, and realizes a cyclic discharge in a sustain period to maintain the gas discharge state at the pixel point that is ignited during the address period. And illuminating, the erasing period uses an erase pulse to complete the neutralization of the charged particles in the discharge space and the erasing of the wall charges on the surface of the medium.

A positive voltage pulse is applied to the address electrode during the address period, and a negative voltage pulse is applied to the scan electrode and the sustain electrode, wherein the voltage amplitude of the scan electrode is either the same as or different from the voltage amplitude of the sustain electrode.

During the sustain period, each sustain period consists of three stages. The first stage scan electrode applies a positive voltage pulse, and the sustain electrode and the address electrode remain in a ground state, mainly performing a counter discharge between the scan electrode and the address electrode; The two-stage sustain electrode applies a positive voltage pulse, the scan electrode and the address electrode remain in a ground state, mainly performing surface discharge between the scan electrode and the sustain electrode; the third stage sustain electrode and the scan electrode apply a negative voltage pulse, and the address electrode remains grounded The state mainly performs the opposite discharge between the sustain electrode and the address electrode, wherein the voltage amplitudes of the sustain electrode and the scan electrode are either the same or different.

The voltage pulse width of the first phase of each sustain period, the voltage pulse width of the second phase, and the voltage pulse width of the third phase are either the same or different.

The shadow mask can serve as a fourth electrode on which a voltage pulse waveform is applied.

The beneficial effects of the invention:

Since the image display driving waveform of the existing shadow mask type plasma display panel adopts only the form of the opposite discharge or the surface discharge during the sustain period, the brightness and the efficiency cannot be optimized. According to the characteristics of the opposite discharge and the surface discharge, the present invention proposes to use a shadow mask type cyclic discharge driving waveform to optimize the brightness and efficiency. Opposite discharge, surface discharge The experimental results of the cyclic discharge show that the discharge intensity of the cyclic discharge is higher, and the discharge efficiency is between the surface discharge and the opposite discharge. The discharge is expanded by the cyclic discharge, and the distance from the phosphor becomes smaller, thereby making the luminous efficiency and The brightness is optimized. DRAWINGS

1 is a schematic view showing the structure of a three-electrode shadow mask type plasma display panel.

Fig. 2 is a schematic diagram showing a conventional storage timing mode with eight subfields showing 256 levels of gray.

Fig. 3 is a schematic view showing the operation waveforms of the electrodes of the shadow mask type three-electrode surface discharge in a single subfield.

Fig. 4 is a schematic diagram showing the working waveforms of the respective electrodes of the shadow mask type three-electrode cyclic discharge in a single subfield.

Fig. 5 is a schematic diagram showing the working waveform of each electrode of a shadow mask type three-electrode cyclic discharge in a single subfield.

The invention will now be further described with reference to the accompanying drawings and embodiments.

As shown in Figure 1-5.

A cyclic display driving method for a shadow mask type plasma display panel adopts a memory display mode, and at least one subfield is arranged in a time for displaying one frame of image, and each subfield is composed of an address period, a sustain period and an erasing period. The addressing period sequentially completes the ignition of each pixel of the full screen. Each sustain period consists of three phases. The first phase performs the opposite discharge between the scan electrode and the address electrode, and the second phase performs the scan electrode and the sustain electrode. In the third stage, the opposite phase between the sustain electrode and the address electrode is performed, and a cyclic discharge is realized in a sustain period, so that the pixel point that is ignited during the address period maintains the gas discharge state and emits light, and erases The neutralization of the charged particles in the discharge space and the erasing of the wall charges on the surface of the medium are performed by using an erase pulse.

Example 1:

As shown in Figure 1, 3.

1 is a three-electrode shadow mask plasma display panel including a front substrate 1, a rear substrate 2, and a shadow mask 3, wherein the shadow mask 3 is packaged between the front and rear substrates 1, 2, and the front substrate 1 is mainly Formed by the front substrate glass substrate 4, the first electrode pair 5, 6, the dielectric layer 7, and the protective film 8, wherein the first electrode pairs 5, 6 are arranged in parallel on the front substrate glass substrate 4, which may be transparent conductive An electrode composed of a film IT0, the electrode 5 is referred to as a sustain electrode, the electrode 6 is referred to as a scan electrode, the dielectric layer 7 is overlaid on the first electrode pair 5, 6, and the protective film 8 is overlying the dielectric layer 7; 2 is mainly composed of a rear substrate glass substrate 9, a second electrode 10, and a dielectric layer 11, wherein the second electrode 10 is on the rear substrate glass substrate 9, the dielectric layer 11 is covered on the second electrode 10, and the second electrode 10 is usually The column electrode group or the address electrode is perpendicular to the first electrode pair 5 on the front substrate 1 in a space; the shadow mask 3 has a thickness d 0. 1~1. Omm includes a conductive plate of an array of funnel-shaped mesh holes 12, and the upper opening 13 of the funnel-shaped mesh hole 12 opposite to the front substrate 1 has a lower opening 14 opposite to the rear substrate 2. 10 to 20 times the area, the opening width 15 of each funnel-shaped mesh hole 12 is 2 to 4 times the width of the lower opening 16; the first electrode pairs 5, 6 are arranged in parallel, respectively, and the funnel shape on the shadow mask 3 The two ends of the upper opening 13 of the mesh hole 12 correspond to each other, and the second electrode 10 corresponds to the lower opening 14 of the funnel-shaped mesh hole 12 on the shadow mask 3, and the lower opening width 16 of each mesh hole 12 is The second electrode 10 has a width 17 of 1 to 2 times, the upper opening length 19 is 1. 5 to 2 times of the lower opening length 18, the electrode width 20 of the first electrode pair 5, 6 is the same, and the upper opening length 20 is the first electrode pair. Between 1.5 and 5 times the parallel spacing 21 between the two, the grid holes 12 intersect the first electrode pairs 5, 6 and the second electrode 10 perpendicularly. The shadow mask 3, the first electrode pair 5, 6 covering the dielectric layer 7 and the protective layer 8, and the second electrode 10 covered with the dielectric layer 11 constitute a basic unit of a dielectric barrier type AC composite discharge type, in which the medium is blocked A visible light emitting region is provided in the basic unit of the AC composite discharge type.

For plasma driving operation, a write pulse exceeding the ignition voltage is required to discharge the discharge space at the intersection of the surface electrode and the address electrode, that is, the selected pixel generates a gas discharge, and then is maintained by applying a continuous AC voltage. The discharge state of the pixel, during which the discharge gas continuously emits ultraviolet light, and the phosphor on the wall of the shadow mask mesh around the discharge discharge space emits light of a corresponding color, and the AC voltage itself is insufficient to sustain other discharges to cause other undischarged pixels. A discharge is generated. If a three-electrode shadow mask plasma display is desired to perform a full-color motion picture such as a television or computer display terminal, a gray scale display mode is required. Figure 2 shows a memory timing scheme with eight subfields that can display 256 levels of gray. According to the usual video display requirements, the motion picture is displayed at a speed of 60 frames per second, that is, one frame of still image is displayed every 16.6 milliseconds. The storage timing mode with eight subfields divides the display time of one frame into eight subfields, each of which contains an address period, a sustain period, and an erase period.

Figure 3 shows the working waveform of each electrode of a shadow mask type three-electrode surface discharge in a single subfield.

During the address period, the scan electrode is applied with a negative scan pulse V „, the positive data voltage V _AW is applied to the address electrode, and the voltage difference between the two electrodes exceeds the ignition voltage, so that the selected pixel of the row enters the ignited state. The sustain electrode is kept in a grounded state, and all the rows are scanned to complete the addressing of the entire screen pixel. All the illuminated cells accumulate wall charges in the discharge space to prepare for sustaining the discharge; during the maintenance period, during maintenance A positive sustain pulse V _s is alternately applied to the electrode and the scan electrode, and the address electrode maintains a ground state, and an alternating current sustaining action is generated for the discharge space of each pixel, and a sustain discharge is performed for the cell that is lit during the address period, and the address period is not. The bright unit is still in a non-discharged state because it does not accumulate wall charges; during the erasing period, the space-charged particles in the last state of the discharge are neutralized by an erase pulse, which does not cause discharge of the unlit unit, and simultaneously wipes In addition to illuminating the wall charge accumulated on the lighting unit, the shadow mask can maintain the floating potential throughout the process, and the shadow mask can also be used as the fourth electrode to apply appropriate electric power. Waveform thereof.

Example 2: As shown in Figure 1, 4.

The three-electrode shadow mask plasma display panel shown in FIG. 1 includes a front substrate 1, a rear substrate 2, and a shadow mask 3, wherein the shadow mask 3 is packaged between the front and rear substrates 1, 2, and the front substrate 1 is mainly composed of The front substrate glass substrate 4, the first electrode pair 5, 6, the dielectric layer 7, and the protective film 8 are composed, wherein the first electrode pair 5, 6 is arranged in parallel on the front substrate glass substrate 4, which may be a transparent conductive film. The electrode composed of IT0, the electrode 5 is referred to as a sustain electrode, the electrode 6 is referred to as a scan electrode, the dielectric layer 7 is overlaid on the first electrode pair 5, 6, and the protective film 8 is overlying the dielectric layer 7; Mainly composed of the rear substrate glass substrate 9, the second electrode 10, and the dielectric layer 11, wherein the second electrode 10 is located on the rear substrate glass substrate 9, the dielectric layer 11 is covered on the second electrode 10, and the second electrode 10 is generally called 1〜 1. 0毫米的含角网, the first electrode pair 5 on the front substrate 1 is perpendicular to the space; the shadow mask 3 is a thickness d is 0. 1~ 1. 0mm including a funnel-shaped net Conductive plate of array of cells 12, said funnel-shaped net The area of the upper opening 13 of the hole 12 opposite to the front substrate 1 is 10 to 20 times the area of the lower opening 14 opposite to the rear substrate 2, and the opening width 15 of each of the funnel-shaped mesh holes 12 is 2 to the width of the lower opening 16. 4 times; the first electrode pairs 5, 6 are arranged in parallel, respectively corresponding to the two ends of the upper opening 13 of the funnel-shaped mesh hole 12 on the shadow mask 3, and the second electrode 10 and the funnel-shaped net on the shadow mask 3 5〜2倍。 The lower opening length 18 is 1. 5~2 times the length of the lower opening 18 is 1 to 2 times the width of the second electrode 10 The first electrode pair 5, 6 has the same electrode width 20, and the upper opening length 20 is 1.25~5 times the parallel spacing 21 between the first electrode pairs 5, 6. The mesh holes 12 and the first electrode pair 5, 6 and the second electrode 10 intersect perpendicularly. The shadow mask 3, the first electrode pair 5, 6 covering the dielectric layer 7 and the protective layer 8, and the second electrode 10 covered with the dielectric layer 11 constitute a basic unit of a dielectric barrier type AC composite discharge type, in which the medium is blocked A visible light emitting region is provided in the basic unit of the AC composite discharge type.

A driving waveform as shown in FIG. 4 is applied to the scan electrodes and the sustain electrodes of the front substrate 1 and the address electrodes of the rear substrate 2. During the address period, the scan electrode applies a negative voltage pulse V _wy , the sustain electrode applies a negative voltage pulse V _wx , and the address electrode applies a positive voltage pulse V _a to generate a scan electrode and an address between the sustain electrode and the address electrode. At the address discharge, positive wall charges are accumulated on the dielectric layer near the scan electrode and the dielectric layer near the sustain electrode in the discharge space, and negative wall charges are accumulated on the dielectric layer near the address electrode, and the wall voltage formed by the wall charge is maintained. Prepare for sustain discharge. During the sustain period, each sustain period consists of three phases P1, P2, and P3. The voltage pulse width of the PI phase is tl. The scan electrodes apply positive voltage pulses V _ys , _pl , and the sustain electrodes and the address electrodes remain grounded. The opposite discharge between the scan electrode and the address electrode is performed, negative wall charges are accumulated on the dielectric layer near the scan electrode, and positive wall charges are accumulated on the dielectric layer near the address electrode; the voltage pulse width of the P2 phase is t2, The sustain electrode applies a positive voltage pulse V _xs , _p2 , and the scan electrode and the address electrode remain in a ground state, mainly performing surface discharge between the scan electrode and the sustain electrode, and a negative wall charge is accumulated on the dielectric layer near the sustain electrode, near the scan electrode. The positive wall charge accumulates on the dielectric layer; the voltage pulse width of the P3 phase is t3, the address electrode remains grounded, the sustain electrode applies a negative voltage pulse _Vxs , _p3 , and the scan electrode The negative voltage pulse v _ys , _p3 is applied to mainly perform the opposite discharge between the sustain electrode and the address electrode, the positive wall charge is accumulated on the dielectric layer near the sustain electrode, and the negative wall charge is accumulated on the dielectric layer near the address electrode. After the end of the maintenance period, the discharge space still accumulates wall charges and enters the erasing period. During the erasing period, the space-charged particles in the last state of the discharge are neutralized by an erase pulse, and the discharge of the unlit unit is not caused. Where tl, t2, and t3 have the same value. The shadow mask maintains a floating potential throughout the process, and the shadow mask can also be used as a fourth electrode to apply a suitable voltage waveform thereon.

Example 3:

As shown in Figures 1 and 5.

A driving waveform as shown in FIG. 5 is applied to the scanning electrodes and the sustain electrodes of the front substrate 1 and the address electrodes of the rear substrate 2, and the shadow mask employs a floating potential. During the address period, the scan electrode applies a negative voltage pulse V _wy , the sustain electrode applies a negative voltage pulse V _wx , and the address electrode applies a positive voltage pulse V _a to generate a scan electrode and an address electrode, between the sustain electrode and the address electrode. The address discharge, the positive wall charge is accumulated on the dielectric layer near the scan electrode and the dielectric layer near the sustain electrode in the discharge space, and the negative wall charge is accumulated on the dielectric layer near the address electrode, and the wall voltage formed by the wall charge is maintained. Prepare for sustain discharge. During the sustain period, each sustain period consists of three phases P1, P2, and P3. The voltage pulse width of the PI phase is tl. The scan electrode applies a positive voltage pulse V _ys , _pl , and the sustain electrode and the address electrode remain grounded. The opposite discharge between the scan electrode and the address electrode is performed, negative wall charges are accumulated on the dielectric layer near the scan electrode, and positive wall charges are accumulated on the dielectric layer near the address electrode; the voltage pulse width of the P2 phase is t2, The sustain electrode applies positive voltage pulses V _xs , _p2 , and the scan electrode and the address electrode remain in a ground state, mainly performing surface discharge between the scan electrode and the sustain electrode, and a negative wall charge is accumulated on the dielectric layer near the sustain electrode, near the scan electrode. The positive wall charge is accumulated on the dielectric layer; the voltage pulse width of the P3 phase is t3, the address electrode remains grounded, the sustain electrode applies a negative voltage pulse _Vxs , _p3 , and the scan electrode applies a negative voltage pulse _Vys , _p3 , mainly The opposite discharge between the sustain electrode and the address electrode, the positive wall charge accumulated on the dielectric layer near the sustain electrode, near the address electrode The negative wall charge accumulates on the dielectric layer, and the wall space charges still accumulate in the discharge space after the end of the sustain period, entering the erasing period. During the erasing period, the space-charged particles in the last state of the discharge are neutralized by an erase pulse, and the discharge of the unlit unit is not caused. The values of tl, t2, and t3 are different. The shadow mask maintains a floating potential throughout the process, and the shadow mask can also be used as a fourth electrode to apply a suitable voltage waveform thereon.

Claims

The invention relates to a method for driving a shadow mask type plasma display panel, which is characterized in that a memory display mode is adopted, at least one subfield is arranged in a time when one frame of image is displayed, and each subfield is addressed by an address period and a sustain period. And the erasing period consists of, the addressing period completes the ignition of each pixel of the full screen in turn, each maintenance period consists of three stages, the first stage performs the opposite discharge between the scan electrode and the address electrode, and the second stage performs The surface discharge between the scan electrode and the sustain electrode, the third stage performs the opposite discharge between the sustain electrode and the address electrode, and achieves a cyclic discharge during a sustain period, so that the pixel point that is ignited during the address period maintains the gas discharge state. And illuminating, the erasing period uses an erase pulse to complete the neutralization of the charged particles in the discharge space and the erasing of the wall charges on the surface of the medium.

A cycle display driving method of a shadow mask type plasma display panel according to claim 1, wherein the voltage pulses applied by the scan electrodes and the sustain electrodes during the address period are negative pulses.

A cyclic display driving method of a shadow mask type plasma display panel according to claim 1, wherein in the three stages of each sustain period, the first stage scan electrode applies a positive voltage pulse to sustain the electrode and seek The address electrode remains in the ground state, and the opposite discharge between the scan electrode and the address electrode is performed; the second stage sustain electrode also applies a positive voltage pulse, and the scan electrode and the address electrode remain in a ground state, and between the scan electrode and the sustain electrode Surface discharge; a third stage sustain electrode and a scan electrode apply a negative voltage pulse, the address electrode remains in a ground state, and a counter discharge between the sustain electrode and the address electrode is performed, wherein the voltage amplitudes of the sustain electrode and the scan electrode are the same, Or different.

The cyclic display driving method of a shadow mask type plasma display panel according to claim 1, wherein the widths of the voltage pulses of the first stage, the second stage, and the third stage of each sustain period are the same, or For the difference. A cycle display driving method of a shadow mask type plasma display panel according to claim 1, wherein the shadow mask is used as a fourth electrode to which a voltage pulse waveform is applied.