WO2009078514A1 - Appareil et procede de creation de matrice de controle de parite pour code ldpc et appareil de codage/decodage ldpc associe - Google Patents

Appareil et procede de creation de matrice de controle de parite pour code ldpc et appareil de codage/decodage ldpc associe Download PDF

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WO2009078514A1
WO2009078514A1 PCT/KR2008/003197 KR2008003197W WO2009078514A1 WO 2009078514 A1 WO2009078514 A1 WO 2009078514A1 KR 2008003197 W KR2008003197 W KR 2008003197W WO 2009078514 A1 WO2009078514 A1 WO 2009078514A1
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parity check
check matrix
basic
matrixes
parity
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PCT/KR2008/003197
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Jong-Ee Oh
Chanho Yoon
Cheol-Hui Ryu
Sok-Kyu Lee
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Electronics And Telecommunications Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6356—Error control coding in combination with rate matching by repetition or insertion of dummy data, i.e. rate reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
    • H03M13/6393—Rate compatible low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel

Definitions

  • the present invention relates to a technology for an error correction code of a wired/ wireless communication system; and, more particularly, to an apparatus and method for generating a parity check matrix of a low density parity check (LDPC) code having a simple coding structure, a fast decoding convergence speed, a variable information length, and a variable coding rate, and a LDPC encoding/decoding apparatus using the same.
  • LDPC low density parity check
  • a receiving end may have difficulty to demodulate a transmitted signal due to noise, interference, and fading on a transmission channel.
  • serial or partial parallel decoding method As a method for decoding the LDPC code, a serial or partial parallel decoding method and a parallel decoding method were introduced. Since the serial or partial parallel decoding method repeatedly uses the small number of common blocks for processing a variable node and a check node, it is possible to advantageously reduce a hardware size. However, the serial or partial parallel decoding method cannot support high speed decoding. On the contrary, the parallel decoding method can advantageously support high speed decoding by exchanging information in parallel through variable node processing blocks and check node processing blocks, which are optimized to each parity check matrix. However, the parallel decoding method also has a disadvantage of a large hardware size. That is, the larger the hardware size increases, the more various code rates are supported.
  • a wired/wireless communication system must use an error correction code having a variable information length and a variable code rate in order to adaptively use modulation and coding scheme (MCS) according to a channel state or in order to perform hybrid automatic repeat request (H-ARQ). Therefore, various decoding methods for supporting various MCS levels were introduced, for example, a method for embodying independent decoders according to each of information lengths and code rates or a method for applying an information shortening scheme or a puncturing scheme although one hardware is used.
  • the former method has a shortcoming of a large hardware size
  • the later method has a disadvantage that error correction performance of a LDPC code significantly deteriorates because of randomly using one of the information shortening scheme and the parity puncturing scheme.
  • the parallel decoding method is better for a high speed wireless communication system supporting a fast processing speed of several giga bits per second. Lately, it has been required to use a LDPC code having a variable information length and a variable code rate having excellent error correction performance in order to effectively apply an adaptive modulation and demodulation scheme. It has been also required that the complexity of encoding and decoding of the LDPC code must be low. However, it is not easy to process entire LDPC codes in parallel due to high complexity of random connection of variable nodes and check nodes.
  • An embodiment of the present invention is directed to providing an apparatus and method for generating a parity check matrix of a LDPC code and a LDPC encoding/ decoding apparatus using the same in order to provide a LDPC code having constraint for having a simple encoding structure and a fast decoding convergence speed, a variable information length, and a variable coding rate.
  • Another embodiment of the present invention is directed to providing an apparatus and method for generating a parity check matrix of a LDPC code and a LDPC encoding/decoding apparatus using the same in order to provide a LDPC code having low encoding/decoding complexity, a fast decoding convergence speed, a variable information length, and a variable coding rate with excellent error correction per- formance.
  • an apparatus for generating a parity check matrix of a low density parity check (LDPC) code including a first parity check matrix generating unit for generating a first parity check matrix formed of a first information block and a parity block; and a q parity check matrix generating means for generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • LDPC low density parity check
  • the apparatus may further include an information shortening means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by applying information shortening on at least one of the first to q parity check matrixes.
  • the apparatus may further include a puncturing means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by puncturing at least one of the first to q parity check matrixes.
  • an apparatus for generating a parity check matrix for a low density parity check (LDPC) code including a basic parity check matrix generating unit for generating at least one of basic parity check matrixes; and an expanded parity check matrix generating unit for generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.
  • LDPC low density parity check
  • the apparatus may further include an information shortening unit for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix.
  • the apparatus may further include a puncturing unit for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.
  • an apparatus for encoding a low density parity code including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding unit for encoding an information word based on the selected parity check matrix from the parity check matrix selecting unit.
  • the plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block, and a q parity check matrix formed by adding a q information block to a q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer is greater than 2.
  • an apparatus for encoding a low density parity check (LDPC) code including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding unit for encoding an information word based on the selected parity check matrix from the parity check matrix selecting unit.
  • the plurality of parity check matrixes include at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by expanding a parity block of the basic parity check matrix by applying row splitting on an information block of the basic parity check matrix.
  • an apparatus for decoding a low density parity check (LDPC) code including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrix; and a decoding unit for decoding a received codeword based on the selected parity check matrix from the parity check matrix selecting unit.
  • the plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block and a q parity check matrix generated by adding a q information block to a q-1 parity check matrix wherein l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • an apparatus for decoding a low density parity check (LDPC) code including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrixes; and a decoding unit for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting unit.
  • the plurality of parity check matrixes includes at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by applying row splitting on an information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.
  • a method for generating a parity check matrix of a low density parity check (LDPC) code including: generating a first parity check matrix formed of a first information block and a parity block; and generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • LDPC low density parity check
  • a method for generating a parity check matrix of a low density parity check (LDPC) code including: generating at least one of basic parity check matrixes; and generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.
  • LDPC low density parity check
  • LDPC low density parity check
  • LDPC decoder and to simply embody hardware performing high speed decoding.
  • the present invention provides a LDPC code of a variable information length and a variable code rate, which has a low complexity for encoding/decoding and provides excellent error correction and error detection performance.
  • Fig. 1 is a diagram structurally illustrating relation among parity check matrices exemplary shown in Table 1.
  • Fig. 2 is a diagram for describing an information shortening scheme and a puncturing scheme in a parity check matrix in accordance with an embodiment of the present invention.
  • FIG. 3 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with another embodiment of the present invention.
  • Fig. 5 is a diagram illustrating a LDPC encoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • Fig. 6 is a diagram illustrating a LDPC decoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • Fig. 7 is a flowchart illustrating a method for generating a parity check matrix in accordance with an embodiment of the present invention.
  • Fig. 8 is a flowchart illustrating a method for generating a parity check matrix in accordance with another embodiment of the present invention.
  • FIG. 9 is a flowchart illustrating a LDPC encoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • Fig. 10 is a flowchart illustrating a LDPC decoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • a LDPC code was introduced by Gallager.
  • the LDPC code is defined as a matrix formed of Is and Os as elements. In the matrix, most elements are Os and few elements are Is.
  • the LDPC code is classified into a regular LDPC code and an irregular LDPC code.
  • the regular LDPC code is a LDPC code introduced by Gallager.
  • a parity check matrix of the regular LDPC code all rows have the same number of Is and all columns also have the same number of Is.
  • a parity check matrix of the irregular LDPC code includes rows having the different number of Is and columns having the different number of Is. In general, it was widely known that the error correction performance of the irregular LDPC code is better than that of the regular LDPC code.
  • Quasi-cyclic LDPC code was introduced by Fossorier in an article entitled "Quasi-cyclic low density parity check codes from circulant permutation matrices", IEEE Trans. Inform. Theory, vol. 50, pp. 1788-1794, Aug. 414.
  • elements of a parity check matrix are cyclic- shifted identity matrices and 0 matrices instead of Os and Is on GF(2).
  • the present invention also relates to a method for changing a length of a n x n sub-matrix, a method for changing the number of sub-matrices, and a method for obtaining an information length and a coding rate changed through information bit row splitting according to variation of degree distribution of a parity check matrix.
  • Eq. 1 shows 5x5 cyclic-permutation i ⁇ atrices.
  • the sub- matrix is a cyclic permutation matrix, which is obtained by cyclic-shifting a 38x38 identify matrix or a 38x38 0 matrix.
  • Table 1 shows LDPC parity check matrices according to an embodiment of the present invention.
  • 20 LDPC parity check matrices are generated by a method for generating a parity check matrix according to the present invention.
  • the 20 LDPC parity check matrices have 456, 912, 1368, 1824, and 2280 bits of information lengths, and 456, 912, 1368, and 1824 bits of parity lengths. Therefore, it is possible to embody an encoder/decoder supporting 20 variable information lengths and code rates based on combination of the information lengths and parity lengths shown in Table 1.
  • Fig. 1 is a diagram structurally illustrating relation among parity check matrices exemplary shown in Table 1.
  • a small square denotes a 456 x 456 matrix.
  • C 1 J blocks and P blocks denote information block and parity block, which are parts of each parity check matrix.
  • a parity check matrix with excellent error correction performance is generated through optimizing degree distribution of a parity check matrix and cyclic distribution on a factor graph. Since the parity check matrices used in the present embodiment are related to each others, optimization is not independently performed for each of the parity check matrices. That is, optimization is performed simultaneously for all of the parity check matrices. Furthermore, optimization is performed using constraints of simple encoding and fast decoding convergence.
  • Eq.2 is an equation exemplary showing a parity check matrix having a parity length of 456 bits and supporting 5 code rates. That is, Eq.2 is H 1 of Fig.1. J
  • Eq.3 is an equation exemplary showing a matrix P 1 which is a parity block in a parity check matrix of Eq.2.
  • the parity block P 1 includes m mod 38 cyclic permutation matrices at (0,0), (6,0), (11,0), and (m, m-1) and (m, m) where l ⁇ m ⁇ l 1, and 0 matrices at remaining positions. That is, in case of a cyclic permutation matrix, remaining after dividing a row value of a basic matrix by 38 is used as elements of a cyclic permutation matrix.
  • the parity check matrix is designed as described above because of constraint for making values of cyclic permutation matrices in the same column of a basic matrix not to be equal. Such a constraint is commonly applied to parity blocks and information blocks. Also, a parity check matrix having simple encoding and fast decoding convergence characteristics can be obtained by the constraint.
  • the parity check matrix is also designed to make remaining values after dividing the values by 19 to be different as well as making values of cyclic permutation matrices in the same column to be different. Such a constraint may be useful if a convergence speed of a decoder increases two times while complexity increases two times or if a size of a sub-matrix increases or decreases two times.
  • parity block P 1 Since such a parity block P 1 is a dual-diagonal sub-matrix, it can be used to embody a partial block based parallel LDPC encoder. If the parity block having a form of a dual diagonal sub-matrix, encoding complexity can be minimized. Although the parity block P 1 is a matrix satisfying linearly independent condition, the parity block P 1 according to the present embodiment may be divided into independent 38 matrices satisfying linearly independent condition. If the parity blocks shown in Eq. 3 are used, it is possible to embody an encoder having low complexity and a decoder having a fast decoding convergence speed.
  • Eq. 4 to Eq. 8 are equations exemplary showing the first to fifth information blocks C
  • integers denote cyclic permutation matrices obtained by cyclic- shifting 38x38 identify matrices to the right as much as the integer itself.
  • "-" denotes a 38x38 0 matrix like Eq. 3.
  • 37 1 denotes cyclic permutation matrix S 37 .
  • exponents are used to generate information blocks included in parity check matrices H 2 , H 3 , and H 4 of Eq. 9 to Eq. 11, which are generated by applying row splitting at first to fifth information blocks of Eq. 2.
  • the row splitting will be described in later with reference to Eq. 12.
  • the first information block O 0 in Eq. 4 and the parity check matrix [C 1 O P 1 ] formed of a parity block P 1 in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 456 bits and a code rate of 1/2.
  • the first and second information blocks O 0 andC'i in Eq. 4 and Eq. 5 and a parity check matrix [C 1 I O 0 P 1 ] formed of parity block P 1 shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 912-bits and a code rate of 2/3.
  • the first to third blocks C 1 O, C 1 I1 and O 2 shown in Eq. 4 to Eq. 6 and a parity check matrix [O 2 C 1 I O 0 P 1 ] formed of parity block P 1 shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 1368 bits and a code rate of 3/4.
  • the first to fourth blocks C 1 O, C 1 I, C 2, and O 3 shown in Eq. 4 to Eq. 7 and a parity check matrix [O 3 O 2 C 1 I C 1 O P 1 ] formed of parity block P 1 shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 1824 bits and a code rate of 4/5.
  • the first to fifth blocks C 1 O, C 1 I, C 2, C 3, and O 4 shown in Eq. 4 to Eq. 8 and a parity check matrix [O 4 O 3 O 2 C 1 I C 1 O P 1 ] formed of parity block P 1 shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 2280 bits and a code rate of 5/6.
  • the parity check matrices designed for obtaining a fast decoding convergence speed is an example of design that makes values of cyclic permutation matrices in the same column not to be the same and makes remaining values after dividing the values by 19 not to be the same. As described above, such restriction may be useful when a convergence speed of a decoder increases two times while complexity increases two times.
  • the matrices in Eq. 3 to Eq. 8 are examples for describing a technical aspect of the present invention. It is obvious to those skilled in the art that various matrices having matrix sizes of Eq. 3 to Eq. 8 may be generated through optimization of degree distribution and cycle distribution beside the matrices in Eq. 3 to Eq. 8.
  • Eq. 9 to Eq. 11 show parity check matrices having parity lengths of 912 bits, 1368 bits, and 1824 bits, and supporting five code rates. That is, Eq. 9 to Eq. 11 denote H 2 , H 3 , and H 4 in Fig. 1.
  • the parity blocks H 2 , H 3 , and H 4 are generated by expanding a parity block H 1 with the same structure. That is, the parity block P 2 of Eq. 9 includes m mode 38 cyclic permutation matrices at (0, 0), (12, 0), and (23, 0) and (m, m-1) and (m, m) where l ⁇ m ⁇ 23 and 0 matrices at other positions. Therefore, the parity block p 2 has the same structure of the parity block P 1 in Eq. 3. Also, a parity block P 3 of Eq.
  • a parity block P 4 of Eq. 11 includes m mode 38 cyclic permutation matrices at (0, 0), (24, 0), (47, 0), and (m, m-1), and (m, m) where l ⁇ m ⁇ 47 and 0 matrices at remaining positions. Therefore, the parity block P 4 has the same structure of the parity block P 1 shown in Eq. 3.
  • a parity block P 4 of Eq. 11 includes m mode 38 cyclic permutation matrices at (0, 0), (24, 0), (47, 0), and (m, m-1), and (m, m) where l ⁇ m ⁇ 47 and 0 matrices at remaining positions. Therefore, the parity block P 4 has the same structure of the parity block P 1 shown in Eq. 3.
  • the parity check matrices [C 2 0 P 2 ], [C 2 ! C 2 0 P 2 ], [C 2 2 C 2 ! C 2 0 P 2 ], [C 2 3 C 2 2 C 2 ! C 2 0 P 2 ] and [C 2 4 C 2 3 C 2 2 C 2 i C 2 0 P 2 ] can support information lengths and code rates shown in Table 1.
  • Eq. 4 to Eq. 8 are used to generate each information block of parity check matrices H 2 , H 3 , and H 4 by applying row splitting to each of information blocks of the parity check matrix H 1 .
  • the row splitting according to the present embodiment is performed using Eq. 12.
  • Eq. 12 is an equation expressing row splitting according to the present embodiment.
  • "-1" denotes 0 sub-matrix.
  • the first embodiment generates a new parity check matrix by adding a second information block to a parity check matrix formed of a first information block and a parity block, which is different from the parity check matrix in an information length or a code rate.
  • the second embodiment generates a new parity check matrix different from a basic parity check matrix in an information length or a code rate by generating an expanded information block through applying row splitting to the base information block and by generating an expanded parity block having the same structure of the base parity block when a parity check matrix formed of the basic information block and the basic parity block is provided.
  • the third embodiment is combination of the first and third embodiments.
  • a target information block for row splitting is a basic information block
  • an expanded information block is an information block obtained by applying row splitting to the basic information block.
  • a target parity block for expanding is a basic parity block
  • an expanded parity block is a result parity block of expanding the basic parity block.
  • parity check matrices are generated by expanding information blocks with a parity block fixed, and an information block is expanded in order to generate an excellent parity check matrix in a view of degree distribution and cycle distribution.
  • an expanded parity check matrix is generated to be different from a basic parity check matrix through performing row splitting on an information block having a basic parity check matrix.
  • a row splitting scheme is applied to generate a parity check matrix good in degree distribution and cycle distribution.
  • a large parity check matrix is generated first. Then, a small parity check matrix may be generated by removing a part of an information block in the generated large parity check matrix.
  • a large basic parity check matrix is generated first. Then, a small parity check matrix may be generated by applying row combining, which is an inverse operation of row splitting, to the information block of the generated basic parity check matrix and applying parity part switching that uses a predetermined part of a parity block of the generated basic parity check matrix.
  • row combining can be expressed parity combining of parity part.
  • the parity part switching can be expressed as parity combining of a parity part.
  • FIG. 2 is a diagram for describing an information shortening scheme and a puncturing scheme in a parity check matrix in accordance with an embodiment of the present invention.
  • Fig. 2 shows an example of shortening information as much as K-K eff bits and puncturing n p parity bits in a k x n parity check matrix shown in a right upper corner.
  • a k x n parity check matrix basically supports a k/n code rate and a k information length.
  • a vector shown in a left upper corner, is a k x 1 input message vector.
  • the vector includes an information word formed of k eff information bits and k-k eff Os filled by information shortening. That is, an information length according to the present embodiment is k eff .
  • a n-bits code word is generated by multiplying such an input message vector with a parity check matrix. Then, n p parity bits are punctured from the generated code ward, and k-k eff Os are deleted. As a result, a length of a final code word becomes n-k+k efr n p .
  • a k eff information length and a k eff /(n-k+k efr n p ) code rate may be provided, which are different from a k/n code rate and a k information length that are basically provided by a parity check matrix.
  • Fig. 2 shows examples of information shortening and puncturing for parity bits, it is possible to apply only one of information shortening and puncturing. Further various information lengths and code rates may be supported if information shortening and puncturing are effectively applied.
  • information shortening and puncturing are performed without a parity check matrix changed by performing 0 fading before multiplying an input message vector and a parity check matrix and performing puncturing after multiplying an input message vector and a parity check matrix.
  • a code word having a n-k+k eff -n p length may be generated by generating a parity check matrix having a new size k eff X(n-k+k eff -n p ) by applying information shortening and puncturing to a parity check matrix itself and multiplying the generated parity check matrix with an input message vector having a length of keffxl.
  • a parity check matrix having a size of k eff X(n-k+k eff -n p ) is obtained by removing the left most k eff columns, the right most n p columns, and the upper most k eff rows.
  • FIG. 3 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with an embodiment of the present invention.
  • an apparatus for generating a parity check matrix includes a first parity check matrix generator 31 for generating a first parity check matrix and q parity check matrix generators 32 to 35 for generating q parity check matrices by adding an q information block to the generated q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • the parity check matrix generating apparatus further includes an information shortening unit 36 for generating the first to Q parity check matrices and at least one of parity check matrices by applying information shortening at least one of the first to Q parity check matrices.
  • the parity check matrix generating apparatus further includes a puncturing unit 37 for generating at least one of parity check matrices different from the first to Q parity check matrices by applying puncturing on at least one of the first to Q parity check matrices.
  • the q parity check matrix generators 32 to 35 generates a q parity check matrix by performing degree distribution and cycle distribution with constraints for a simple encoding structure and a fast decoding convergence speed.
  • the first parity check matrix generator 31 generates a first parity matrix [O 0 P 1 ] formed of a first information block O 0 shown in Eq. 4 and a parity block P 1 shown in Eq. 3.
  • the second parity check matrix generator 32 generates a second parity check matrix [C 1 I CO P 1 ] by adding a second information block C 1 I of Eq. 5 to the first parity check matrix [C 0 P 1 ] generated by the first parity check matrix generator 31.
  • the third parity check matrix generator 33 generates a second parity check matrix [C l 2 C 1 I CO P 1 ] by adding a third information block O 2 of Eq. 6 to the second parity check matrix [C 1 I O 0 P 1 ] generated by the second parity check matrix generator 32.
  • the fourth parity check matrix generator 34 generates a third parity check matrix [O 3 O 2 C 1 I C 1 O P 1 ] by adding a fourth information block O 3 of Eq. 7 to the third parity check matrix [O 2 C 1 I C 1 O P 1 ] generated by the third parity check matrix generator 33.
  • the fifth parity check matrix generator 35 generates a fifth parity check matrix [O 4 C ! 3 C 2 C 1 I C 1 O P 1 ] by adding a fifth information block O 4 of Eq. 8 to the fourth parity check matrix [O 3 O 2 C 1 I C 1 O P 1 ] generated by the fourth parity check matrix generator 34.
  • the information shortening unit 36 generates at least one of parity check matrices different from the first to fifth parity check matrices by applying information shortening to at least one of the first to fifth parity check matrices generated by the first to fifth parity check matrices 31 to 35.
  • the puncturing unit 37 generates at least one of parity check matrices different from the first to fifth parity check matrices by applying puncturing scheme on at least one of the first to fifth parity check matrices generated by the first to fifth parity check matrix generators 31 to 35.
  • FIG. 4 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with another embodiment of the present invention.
  • the apparatus for generating a parity check matrix includes a basic parity check matrix generator 41 for generating at least one of basic parity check matrices and an expanded parity check matrix generator 42 for generating at least one of expanded parity check matrices by applying row splitting on an information block of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.
  • the apparatus for generating a parity check matrix further includes an information shortening unit 43 for generating at least one of parity check matrices different from the expanded parity check matrix by applying information shortening to at least one of the basic parity check matrix and the expanded parity check matrix.
  • the apparatus for generating a parity check matrix further includes a puncturing unit 44 for generating at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by applying a puncturing scheme on at least one of the basic parity check matrix and the expanded parity check matrix.
  • the basic parity check matrix generator 41 generates a first basic parity check matrix formed of a first basic information block and a basic parity block, and generates a q basic parity check matrix by adding a q basic information block to the generated q- 1 basic parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • the expanded parity check matrix generator 42 generates an expanded parity block by expanding the basic parity block, generates a q expanded information block by applying row splitting on the q basic information block, and generates a q expanded parity check matrix formed of the expanded parity block and the first to Q expanded information blocks.
  • the expanded parity check matrix generator 42 generates an expanded parity block having the same structure of the basic parity block.
  • the basic parity block and the expanded parity block has a form of a dual diagonal matrix in order to have a simple encoder and a fast decoding convergence speed.
  • the basic parity check matrix generator 41 generates a basic parity check matrix by optimizing constraints for having simple encoding and fast decoding convergence characteristics, degree distribution, and cycle distribution.
  • the expanded parity check matrix generator 42 generates an expanded parity check matrix by optimizing constraints for having simple encoding and fast decoding convergence characteristics, degree distribution, and cycle distribution.
  • the apparatus for generating a parity check matrix according to the present embodiment shown in Fig. 4 generates matrices H 2 , H 3 , and H 4 of Eq. 9 to Eq. 11 from the matrix H 1 of Eq. 2.
  • the basic parity check matrix generator 41 generates at least one of basic parity check matrices.
  • the basic parity check matrix generator 41 shown in Fig. 4 will be described with assumption that the basic parity check matrix generator 41 generates one basic parity matrix [C 1 P 1 ].
  • the expanded parity check matrix generator 42 generates C 2 by applying row splitting on the information block C 1 of the basic parity check matrix [C 1 P 1 ], and generates a parity block P 2 having the same structure of the P 1 by expanding the parity block P 1 of the basic parity check matrix [C 1 P 1 ]. As a result, an expanded parity check matrix [C 2 P 2 ] is generated.
  • the information shortening unit 43 generates at least one of parity check matrices different from the basic parity check matrix [C 1 P 1 ] and the expanded parity check matrix [C 2 P 2 ] by applying information shortening on at least one of the basic parity check matrix [C 1 P 1 ] and the expanded parity check matrix [C 2 P 2 ].
  • the puncturing unit 44 generates at least one of parity check matrices different from the basic parity check matrix [C 1 P 1 ] and the expanded parity check matrix [C 2 P 2 ] by puncturing at least one of the basic parity check matrix [C 1 P 1 ] and the expanded parity check matrix [C 2 P 2 ].
  • the expanded parity check matrix generator 42 may generates expanded parity check matrices [C 2 0 P 2 ], [C 2 ! C 2 0 P 2 ], [C 2 2 C 2 ! C 2 0 P 2 ], [C 2 3 C 2 2 C 2 ! C 2 0 P 2 ], and [C 2 4 C 2 3 C 2 2 C 2 !
  • FIG. 5 is a diagram illustrating a LDPC encoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • the LDPC encoding apparatus supporting a variable information length and a variable code rate includes a parity check matrix selector 51 for selecting a parity check matrix corresponding to inputted coding parameter among a plurality of parity check matrices, and an encoder for encoding inputted information word based on the parity check matrix selected by the parity check matrix selector 51.
  • the plurality of parity check matrices include a first parity check matrix formed of a first information block and a parity block and a q parity check matrix formed by adding a q information block to a q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • the inputted coding parameter includes a code rate and a length of the inputted information word.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the first to Q parity check matrices.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the first to Q parity check matrices.
  • a LDPC encoding apparatus supporting a variable information length and a variable code rate includes a parity check matrix selector 51 for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrices and an encoder for encoding an inputted information word based on the parity check matrix selected by the parity check matrix selector 51.
  • the plurality of parity check matrices includes at least one of expanded parity check matrices generated by applying row splitting on at least one of the basic parity check matrix and the basic parity check matrix and expanding a parity block of the basic parity check matrix.
  • the inputted coding parameter includes a code rate and a length of the inputted information word.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on the basic parity check matrix and the expanded parity check matrix.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.
  • the parity check matrix selector 51 selects a parity check matrix corresponding to an inputted coding parameter among the plurality of parity check matrices.
  • the plurality of parity check matrices denote parity check matrices generated the apparatuses shown in Figs. 3 and 4.
  • the inputted coding parameters are a parameter used for selecting a parity check matrix, such as an information length and a coding rate.
  • the parity check matrix is not limited thereto.
  • the encoder 52 encodes an inputted information word based on the selected parity check matrix from the parity check matrix selector 51 and outputs a code word.
  • FIG. 6 is a diagram illustrating a LDPC decoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • the LDPC decoding apparatus includes a parity check matrix selector 61 for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrices and a decoder 62 for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61.
  • the plurality of parity check matrices includes a first parity check matrix formed of a first information block and a parity block and a q parity check matrix formed by adding a q information block into a q-1 parity check matrix where l ⁇ q ⁇ Q and Q is an integer greater than 2.
  • the inputted decoding parameter includes a code rate and an information length of the received codeword.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the first to Q parity check matrices.
  • the decoder 62 performs decoding by setting a probability that the information shortening bit is 0 to 1 if the selected parity check matrix is a matrix with information shortening applied.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the first to Q parity check matrices, and the decoder 62 performs decoding by setting a probability that the information shortening bit is 0 to 1/2 if the selected parity check matrix is a matrix with puncturing applied.
  • a LDPC decoding apparatus supporting a variable information length and a variable code rate includes a parity check matrix selector 61 for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrices, and a decoder for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61.
  • the plurality of parity check matrices include at least one of expanded parity check matrices by applying row splitting on an at least one of the basic parity check matrix and the information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.
  • the inputted decoding parameters includes a code rate and an information length of the receive codeword.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix.
  • the decoder 62 performs decoding by setting a probability that an information shortening bit is 0 to 1 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening applied.
  • the plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix, and the decoder 62 performs decoding by setting a probability that an information shortening bit is 1 to 1/2 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening applied.
  • the parity check matrix selector 61 selects a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices.
  • a plurality of parity check matrices denote parity check matrices generated by the apparatuses shown in Figs. 3 and 4.
  • the inputted decoding parameter is a parameter used to select a parity check matrix, for example, a code rate and an information length of a received codeword.
  • the inputted decoding parameter is not limited thereto.
  • the decoder 62 decodes a received codeword based on the parity check matrix selected by the parity check matrix selector 61.
  • a message passing algorithm MPA
  • the decoder 62 performs decoding by setting a probability that an information shortening bit is 0 to 1 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening scheme applied.
  • the decoder 62 performs decoding by setting a probability that an information shortening bit is 1 to 1/2 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with the puncturing scheme applied.
  • Fig. 7 is a flowchart illustrating a method for generating a parity check matrix in accordance with an embodiment of the present invention.
  • the method for generating a parity check matrix according to the present embodiment includes steps performed in a time domain in the apparatus for generating a parity check matrix shown in Fig. 3. Therefore, the description of the apparatus for generating a parity check matrix of Fig. 3 is also applied to a method for generating a parity check matrix according to the present embodiment although some parts of detail description of the method may be omitted.
  • the first parity check matrix generates a first parity check matrix formed of a first information block and a parity block.
  • the second parity check matrix generates a second parity check matrix by adding a second information block to the generated first parity check matrix.
  • the third parity check matrix generates a third parity check matrix by adding a third information block to the generated second parity check matrix.
  • the fourth parity check matrix generates a fourth parity check matrix by adding a fourth information block to the generated third parity check matrix.
  • the fifth parity check matrix generates a fifth parity check matrix by adding a fifth information block to the generated fourth parity check matrix.
  • the information storing unit 36 additionally generates at least one of parity check matrices different from the first to fifth parity check matrices by applying information shortening on at least one of the generated first to fifth parity check matrices
  • the puncturing unit 37 additionally generates at least one of parity check matrices different from the first to fifth parity check matrices by puncturing at least one of the first to fifth parity check matrices.
  • Fig. 8 is a flowchart illustrating a method for generating a parity check matrix in accordance with another embodiment of the present invention.
  • the method for generating a parity check matrix according to another embodiment includes steps performed in a time domain by the apparatus for generating a parity check matrix shown in Fig. 4. Therefore, the description of the apparatus for generating a parity check matrix of Fig. 4 is also applied to a method for generating a parity check matrix according to the present embodiment although a part of detail description of the method is omitted.
  • the basic parity check matrix generator 41 generates at least one of basic parity check matrices.
  • the expanded parity check matrix generator 42 generates at least one of expanded parity check matrices by applying row splitting on an information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.
  • the information shortening unit 43 generates at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the generated basic parity check matrix and the expanded parity check matrix
  • the puncturing unit 44 generates at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the generated basic parity check matrix and the expanded parity check matrix.
  • FIG. 9 is a flowchart illustrating a LDPC encoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • the LDPC encoding method supporting a variable information length and a variable code rate includes steps performed in time series by the LDPC encoding apparatus supporting a variable information length and a variable code rate of Fig. 5. Therefore, the description of the LDPC encoding apparatus of Fig. 5 is also applied to the LDPC encoding method according to the present embodiment although a part of detail description of the method is omitted.
  • the parity check matrix selector 51 selects a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrices.
  • the plurality of parity check matrices denote parity check matrices generated the apparatuses shown in Figs. 3 and 4.
  • the encoder 52 encodes an inputted information word based on the selected parity check matrix.
  • Fig. 10 is a flowchart illustrating a LDPC decoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.
  • the LDPC decoding method supporting a variable information length and a variable code rate according to the present embodiment includes steps performed in time series by the LDPC decoding apparatus supporting a variable information length and a variable code rate of Fig. 6. Therefore, the description of the LDPC decoding apparatus of Fig. 6 is also applied to the LDPC decoding method according to the present embodiment although a part of detail description of the method is omitted.
  • the parity check matrix selector 61 selects a parity check matrix corresponding to an inputted decoding parameter from the plurality of parity check matrices.
  • the plurality of parity check matrices denote parity check matrices generated by the apparatuses shown in Figs. 3 and 4.
  • the decoder 62 decodes a received codeword based on the selected parity check matrix.
  • the methods of the present invention may be programmed in a computer language. Codes and code segments constituting the computer program may be easily inferred by a computer programmer skilled in the art. Furthermore, the computer program may be stored in a computer-readable recording medium including all kinds of media such as CD-ROM, RAM, ROM, floppy disk, hard disk and magneto-optical disk, and read and executed by a computer to embody the methods.

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Abstract

L'invention concerne un appareil et un procédé de création d'un code de contrôle de parité à faible densité (LDPC) présentant une structure de codage simple, une vitesse de convergence de décodage élevée, une longueur d'informations variable et une vitesse de codage variable, ainsi qu'un appareil de codage/décodage LDPC associé. L'appareil de création de code LDPC selon l'invention comprend : une première unité de création de matrice de contrôle de parité destinée à générer une première matrice de contrôle de parité constituée d'un premier bloc d'informations et d'un bloc de parité ; et une unité de création de matrice de contrôle de parité q destinée à générer une matrice de contrôle de parité q par l'ajout d'un bloc d'informations q à la matrice de contrôle de parité q-1, 1<q≤Q et Q étant un entier supérieur à 2.
PCT/KR2008/003197 2007-12-17 2008-06-09 Appareil et procede de creation de matrice de controle de parite pour code ldpc et appareil de codage/decodage ldpc associe WO2009078514A1 (fr)

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