WO2008069460A1 - Procédé de génération d'une matrice de contrôle de parité, procédé de codage/décodage pour un code de contrôle de parité à faible densité à longueur d'informations variable et à vitesse de codage variable, appareil utilisant ce dernier - Google Patents

Procédé de génération d'une matrice de contrôle de parité, procédé de codage/décodage pour un code de contrôle de parité à faible densité à longueur d'informations variable et à vitesse de codage variable, appareil utilisant ce dernier Download PDF

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Publication number
WO2008069460A1
WO2008069460A1 PCT/KR2007/005478 KR2007005478W WO2008069460A1 WO 2008069460 A1 WO2008069460 A1 WO 2008069460A1 KR 2007005478 W KR2007005478 W KR 2007005478W WO 2008069460 A1 WO2008069460 A1 WO 2008069460A1
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WIPO (PCT)
Prior art keywords
parity
check matrix
check
information
block
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PCT/KR2007/005478
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English (en)
Inventor
Jong-Ee Oh
Chanho Yoon
Minho Cheong
Yu-Ro Lee
Sok-Kyu Lee
Heejung Yu
Seung-Chan Bang
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Electronics And Telecommunications Research Institute
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Priority claimed from KR1020070021965A external-priority patent/KR100833515B1/ko
Application filed by Electronics And Telecommunications Research Institute filed Critical Electronics And Telecommunications Research Institute
Priority to US12/517,763 priority Critical patent/US20100325511A1/en
Publication of WO2008069460A1 publication Critical patent/WO2008069460A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/618—Shortening and extension of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields

Definitions

  • the present invention relates to an error correction code of a wired/wireless communication system, and more particularly, to a method of generating a parity-check matrix, an encoding/decoding method for a low density parity-check (hereinafter, abbreviated to LDPC) code with a variable information length and a variable code rate, and an apparatus using the same.
  • LDPC low density parity-check
  • a transmitted signal in a wired/wireless communication system suffers noise, interference, and fading in a transmission channel. Thus, a case occurs where a receiving end cannot demodulate the transmitted signal.
  • a typical technique from among various techniques used to reduce an occurrence rate of an error which increases as a transmission speed increases is the use of an error correction code.
  • the error correction code has been applied to most wireless communication systems.
  • a low density parity-check (LDPC) code has been spotlighted for a next generation high capacity wireless communication system, because the LDPC code has high-performance error correction and can embody a high speed decoder with low complexity.
  • Methods of decoding the LDPC code include a decoding method which employs a serial or partially parallel processing technique and a decoding method which employs a parallel processing technique.
  • the former method has an advantage in that the size of hardware is reduced by repeatedly using a few variable node processing blocks for common use and a few check node processing blocks for common use, but has a dis- advantage in that the method cannot support high speed decoding.
  • the latter method can support high speed decoding by performing a parallel information exchange by including a variable node processing block and a check node processing block optimized for each parity-check matrix.
  • the latter method has a disadvantage in that the size of hardware is big and a disadvantage in that the hardware size increases as various code rates are supported.
  • the wired/wireless communication system needs to use an error correction code with a variable information length and a variable code rate so as to perform a hybrid automatic repeat request (H-ARQ) or to apply a modulation and coding scheme (hereinafter, abbreviated to MCS) that is adaptive for a channel state.
  • MCS modulation and coding scheme
  • Conventional decoding methods used to support various MCS levels so as to meet the aforementioned needs include a method of separately embodying decoders optimized for information lengths and code rates and a method of using a piece of hardware and using information shortening or puncturing techniques.
  • the former method has a disadvantage in that the size of the hardware increases.
  • the latter method has a disadvantage in that a random application of the information shortening or parity puncturing techniques causes a serious deterioration of the error correction performance of the LDPC code.
  • a parallel processing decoding method is advantageous for a super high speed wireless communication system that requires a processing speed of gigabytes.
  • the LDPC code is required, with high-performance error correction which supports a variable information length and a variable code rate.
  • the encoding/decoding complexity of the LDPC code has to be low. Disclosure of Invention Technical Problem
  • the LDPC code is required, with high-performance error correction, which can easily embody a decoder with a variable information length and a variable code rate by using only a piece of parallel processing hardware and can reduce encoding complexity.
  • a method of generating a parity-check matrix corresponding to the LDPC code, an encoding/decoding method, and an apparatus using the same are required.
  • the present invention provides a low density parity-check (LDPC) code having high- performance error correction, which supports low encoding/decoding complexity, high speed decoding, a variable information length, and a variable code rate, a method of generating a parity-check matrix of the LDPC code, an encoding/decoding method, and apparatus using the same.
  • LDPC low density parity-check
  • FIG. 1 illustrates examples of 5x5 cyclic-permutation matrices
  • FIG. 2 illustrates a table including low density parity-check (LDPC) matrices according to an embodiment of the present invention
  • FIG. 3 schematically illustrates relations among parity-check matrices exemplified in the table of FIG. 2
  • FIG. 4 illustrates an example of a parity-check matrix with a parity length of 456 bits which supports five code rates
  • FIG. 5 illustrates an example of a matrix P that is a parity block included in the parity-check matrix of FIG. 4
  • FIGS. 6 to 10 respectively illustrate examples of first to five information blocks C ,
  • FIGS. 11 to 13 respectively illustrate examples of parity-check matrices with parity lengths of 912, 1368, and 1824 bits which support five code rates;
  • FIG. 14 illustrates an equation which represents a row-splitting technique according to an embodiment of the present invention;
  • FIG. 15 illustrates a concept whereby an information shortening technique and a puncturing technique are applied to a parity-check matrix;
  • FIGS. 16 and 17 are block diagrams illustrating structures of an apparatus for generating a parity-check matrix according to an embodiment of the present invention; [25] FIG.
  • FIG. 18 is a block diagram illustrating an LDPC encoding apparatus which supports a variable information length and a variable code rate according to an embodiment of the present invention
  • FIG. 19 is a block diagram illustrating an LDPC decoding apparatus which supports a variable information length and a variable code rate according to an embodiment of the present invention
  • FIGS. 20 and 21 are flowcharts illustrating a method of generating a parity-check matrix according to an embodiment of the present invention
  • FIG. 22 is a flowchart illustrating an LDPC encoding method which supports a variable information length and a variable code rate according to an embodiment of the present invention.
  • FIG. 23 is a flowchart illustrating an LDPC decoding method which supports a variable information length and a variable code rate according to an embodiment of the present invention. Best Mode
  • a method of generating a parity-check matrix of an LDPC (low density parity-check) code with a variable information length and a variable code rate comprising: a first parity-check matrix generation process of generating a first parity-check matrix constructed with a first information block and a parity block; and an m-th parity-check matrix generation process of generating an m-th parity-check matrix by adding an m-th information block to a generated (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the m-th (1 ⁇ m ⁇ M) parity-check matrix generation process may include a process of generating the m-th parity-check matrix by performing optimization of degree distribution and cycle distribution.
  • the method may further comprise an information shortening process of generating at least one parity-check matrix which is different from the first to M-th parity-check matrices by applying an information shortening technique to at least one of the first to M-th parity-check matrices.
  • the method may further comprise a puncturing process of generating at least one parity-check matrix which is different from the first to M-th parity-check matrices by applying a puncturing technique to at least one of the first to M-th parity-check matrices.
  • the puncturing process may include a process of performing the puncturing technique with respect to an information block.
  • the puncturing process may include a process of performing the puncturing technique with respect to the parity block.
  • a method of generating a parity-check matrix of an LDPC (low density parity-check) code with a variable information length and a variable code rate comprising: a basic parity-check matrix generation process of generating at least one basic parity-check matrix; and an extended parity-check matrix generation process of generating at least one extended parity-check matrix by applying a row-splitting technique to an in- formation block of the basic parity-check matrix and extending a parity block of the basic parity-check matrix.
  • the basic parity-check matrix generation process may include a process of generating an m-th basic parity-check matrix by generating the first basic parity-check matrix constructed with a first basic information block and a basic parity block and by adding an m-th basic information block to a generated (m-l)-th basic parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two), and wherein the extended parity-check matrix generation process includes a process of generating an m-th extended information block constructed with an extended parity block and first to m-th extended information blocks by generating an extended parity block by extending the basic parity block and by generating the m-th extended information block by applying the row-splitting technique to the m-th basic information block (1 ⁇ m ⁇ M).
  • the extended parity-check matrix generation process may include a process of generating the extended parity block with the same structure as the basic parity block.
  • the basic parity block and the extended parity block may have a double diagonal matrix form.
  • the basic parity-check matrix generation process may include a process of generating the basic parity-check matrix by performing optimization of degree distribution and cycle distribution, and wherein the extended parity-check matrix generation process includes a process of generating the extended parity-check matrix by performing the optimization of the degree distribution and the cycle distribution.
  • the method may further comprise an information shortening process of generating at least one parity-check matrix which is different from the basic parity-check matrix and the extended parity-check matrix by applying an information shortening technique to at least one of the basic parity-check matrix and the extended parity-check matrix.
  • the method may further comprise a puncturing process of generating at least one parity-check matrix which is different from the basic parity-check matrix and the extended parity-check matrix by applying a puncturing technique to at least one of the basic parity-check matrix and the extended parity-check matrix.
  • the puncturing process may include a process of performing the puncturing technique with respect to an information block.
  • the puncturing process may include a process of performing the puncturing technique with respect to the parity block.
  • an LDPC encoding method which supports a variable information length and a variable code rate
  • the LDPC encoding method comprising: a parity-check matrix selection process of selecting a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity-check matrices; and an encoding process of encoding an input information word based on the selected parity-check matrix, wherein the plurality of parity-check matrices include a first parity-check matrix, which is constructed with a first information block and a parity block, and an m-th parity-check matrix, which is obtained by adding an m-th information block to an (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the input encoding parameter may include a code rate and a length of the input information word.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices.
  • an LDPC encoding method which supports a variable information length and a variable code rate
  • the LDPC encoding method comprising: a parity-check matrix selection process of selecting a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity-check matrices; and an encoding process of encoding an input information word based on the selected parity-check matrix, wherein the plurality of parity-check matrices include at least one basic parity-check matrix and at least one extended parity-check matrix generated by applying a row-splitting technique to an information block of the basic parity-check matrix and extending a parity block of the basic parity-check matrix.
  • the input encoding parameter may include a code rate and a length of the input information word.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying an information shortening technique to at least one of the basic parity-check matrix and the extended parity-check matrix.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying a puncturing technique to at least one of the basic parity- check matrix and the extended parity-check matrix.
  • an LDPC decoding method which supports a variable information length and a variable code rate
  • the LDPC decoding method comprising: a parity-check matrix selection process of selecting a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity-check matrices; and a decoding process of decoding a received codeword based on the selected parity-check matrix, wherein the plurality of parity-check matrices include a first parity-check matrix, which is constructed with a first information block and a parity block, and an m-th parity-check matrix, which is obtained by adding an m-th information block to an (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the input decoding parameter may include a code rate and a length of the received codeword.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices, and wherein the decoding process includes a process of performing decoding by setting a probability that an information-shortened bit has a value of 0 to a value of 1, when the selected parity-check matrix is a matrix to which the information shortening technique is applied.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices, and wherein the decoding process includes a process of performing decoding by setting a probability that a punctured bit has a value of 0 to a value of 0.5, when the selected parity-check matrix is a matrix to which the puncturing technique is applied.
  • an LDPC decoding method which supports a variable information length and a variable code rate
  • the LDPC decoding method comprising: a parity-check matrix selection process of selecting a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity-check matrices; and an encoding process of decoding a received codeword based on the selected parity-check matrix, wherein the plurality of parity-check matrices include at least one basic parity-check matrix and at least one extended parity-check matrix generated by applying a row-splitting technique to an information block of the basic parity-check matrix and extending a parity block of the basic parity-check matrix.
  • the input decoding parameter may include a code rate and a length of the received codeword.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices, and wherein the decoding process includes a process of performing decoding by setting a probability that an information-shortened bit has a value of 0 to a value of 1, when the selected parity-check matrix is a matrix to which the information shortening technique is applied.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices, and wherein the decoding process includes a process of performing decoding by setting a probability that a punctured bit has a value of 0 to a value of 0.5, when the selected parity-check matrix is a matrix to which the puncturing technique is applied.
  • an apparatus for generating a parity-check matrix of an LDPC (low density parity-check) code with a variable information length and a variable code rate comprising: a first parity-check matrix generation unit generating a first parity-check matrix constructed with a first information block and a parity block; and an m-th parity-check matrix generation unit generating an m-th parity-check matrix by adding an m-th information block to a generated (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the m-th (1 ⁇ m ⁇ M) parity-check matrix generation unit may include a unit generating the m-th parity-check matrix by performing optimization of degree distribution and cycle distribution.
  • the apparatus may further comprise an information shortening unit generating at least one parity-check matrix which is different from the first to M-th parity-check matrices by applying an information shortening technique to at least one of the first to M-th parity-check matrices.
  • the apparatus may further comprise a puncturing unit generating at least one parity- check matrix which is different from the first to M-th parity-check matrices by applying a puncturing technique to at least one of the first to M-th parity-check matrices.
  • the puncturing unit may include a unit performing the puncturing technique with respect to an information block.
  • the puncturing unit may include a unit performing the puncturing technique with respect to the parity block.
  • an apparatus for generating a parity-check matrix of an LDPC (low density parity-check) code with a variable information length and a variable code rate comprising: a basic parity-check matrix generation unit generating at least one basic parity-check matrix; and an extended parity-check matrix generation unit generating at least one extended parity-check matrix by applying a row-splitting technique to an information block of the basic parity-check matrix and extending a parity block of the basic parity- check matrix.
  • the basic parity-check matrix generation unit may include a unit generating an m-th basic parity-check matrix by generating the first basic parity-check matrix constructed with a first basic information block and a basic parity block and by adding an m-th basic information block to a generated (m-l)-th basic parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two), and wherein the extended parity-check matrix generation unit includes a unit generating an m-th extended information block constructed with an extended parity block and first to m-th extended information blocks by generating an extended parity block by extending the basic parity block and by generating the m-th extended information block by applying the row- splitting technique to the m-th basic information block (1 ⁇ m ⁇ M).
  • the extended parity-check matrix generation unit may include a unit generating the extended parity block with the same structure as the basic parity block.
  • the basic parity block and the extended parity block may have a double diagonal matrix form.
  • the basic parity-check matrix generation unit may include a unit generating the basic parity-check matrix by performing optimization of degree distribution and cycle distribution, and wherein the extended parity-check matrix generation unit includes a unit generating the extended parity-check matrix by performing the optimization of the degree distribution and the cycle distribution.
  • the unit may further comprise an information shortening unit generating at least one parity-check matrix which is different from the basic parity-check matrix and the extended parity-check matrix by applying an information shortening technique to at least one of the basic parity-check matrix and the extended parity-check matrix.
  • the unit may further comprise a puncturing unit generating at least one parity-check matrix which is different from the basic parity-check matrix and the extended parity- check matrix by applying a puncturing technique to at least one of the basic parity- check matrix and the extended parity-check matrix.
  • the puncturing unit may include a unit performing the puncturing technique with respect to an information block.
  • the puncturing unit may include a unit performing the puncturing technique with respect to the parity block.
  • an LDPC encoding apparatus which supports a variable information length and a variable code rate
  • the LDPC encoding apparatus comprising: a parity-check matrix selection unit selecting a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity-check matrices; and an encoding unit encoding an input information word based on the selected parity-check matrix, wherein the plurality of parity-check matrices include a first parity-check matrix, which is constructed with a first information block and a parity block, and an m-th parity-check matrix, which is obtained by adding an m-th information block to an (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the input encoding parameter may include a code rate and a length of the input information word.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices.
  • an LDPC encoding apparatus which supports a variable information length and a variable code rate
  • the LDPC encoding apparatus comprising: a parity-check matrix selection unit selecting a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity-check matrices; and an encoding unit encoding an input information word based on the selected parity-check matrix, wherein the plurality of parity-check matrices include at least one basic parity-check matrix and at least one extended parity-check matrix generated by applying a row-splitting technique to an information block of the basic parity-check matrix and extending a parity block of the basic parity-check matrix.
  • the input encoding parameter may include a code rate and a length of the input information word.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying an information shortening technique to at least one of the basic parity-check matrix and the extended parity-check matrix.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying a puncturing technique to at least one of the basic parity- check matrix and the extended parity-check matrix.
  • an LDPC decoding apparatus which supports a variable information length and a variable code rate
  • the LDPC decoding apparatus comprising: a parity-check matrix selection unit selecting a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity-check matrices; and a decoding unit decoding a received codeword based on the selected parity-check matrix, wherein the plurality of parity- check matrices include a first parity-check matrix, which is constructed with a first information block and a parity block, and an m-th parity-check matrix, which is obtained by adding an m-th information block to an (m-l)-th parity-check matrix (1 ⁇ m ⁇ M, where M is a natural number equal to or greater than two).
  • the input decoding parameter may include a code rate and a length of the received codeword.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices, and wherein the decoding unit includes a unit performing decoding by setting a probability that an information- shortened bit has a value of 0 to a value of 1, when the selected parity-check matrix is a matrix to which the information shortening technique is applied.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices, and wherein the decoding unit includes a unit performing decoding by setting a probability that a punctured bit has a value of 0 to a value of 0.5, when the selected parity-check matrix is a matrix to which the puncturing technique is applied.
  • an LDPC decoding apparatus which supports a variable information length and a variable code rate
  • the LDPC decoding apparatus comprising: a parity-check matrix selection unit selecting a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity-check matrices; and an encoding unit decoding a received codeword based on the selected parity-check matrix, wherein the plurality of parity- check matrices include at least one basic parity-check matrix and at least one extended parity-check matrix generated by applying a row-splitting technique to an information block of the basic parity-check matrix and extending a parity block of the basic parity- check matrix.
  • the input decoding parameter may include a code rate and a length of the received codeword.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the information shortening technique to at least one of the first to M-th parity-check matrices, and wherein the decoding unit includes a unit performing decoding by setting a probability that an information- shortened bit has a value of 0 to a value of 1, when the selected parity-check matrix is a matrix to which the information shortening technique is applied.
  • the plurality of parity-check matrices may further include at least one parity-check matrix generated by applying the puncturing technique to at least one of the first to M- th parity-check matrices, and wherein the decoding unit includes a unit performing decoding by setting a probability that a punctured bit has a value of 0 to a value of 0.5, when the selected parity-check matrix is a matrix to which the puncturing technique is applied.
  • a low density parity-check (LDPC) code is introduced by Gallager.
  • the LDPC code is defined as a parity-check matrix in which a few elements have l's, and the rest of the elements have O's.
  • the LDPC code is largely classified into a regular LDPC code and an irregular
  • the regular LDPC code is suggested by Gallager. All the rows in the parity-check matrix have the same number of l's, and all the columns also have the same number of l's. Unlike the regular LDPC code, in the parity-check matrix of the irregular LDPC code, there exist rows having different numbers of l's, or there exist columns having different numbers of l's. In general, it is known that the error correction performance of the irregular LDPC code is higher than that of the regular LDPC code.
  • FIG. 1 illustrates examples of 5x5 cyclic-permutation matrices.
  • a sub-matrix Si is obtained by cyclically shifting columns of the identity matrix by i in the right side.
  • the sub-matrices include a matrix obtained by applying a cyclic shift to a 38 x 38 identity matrix and a 38 x 38 zero matrix.
  • FIG. 2 illustrates a table including LDPC matrices according to an embodiment of the present invention.
  • Twenty LDPC matrices included in the table of FIG. 2 are generated by using a method of generating a parity-check matrix according to the current embodiment of the present invention. It is possible to use combinations of in- formation lengths and parity lengths so as to embody an encoder/decoder that supports twenty types of variable information lengths and variable code rates by using 456, 912, 1368, 1824 and 2280 bits as the information lengths and by using 456, 912, 1368, and 1824 bits as the parity lengths.
  • FIG. 3 schematically illustrates relations among parity-check matrices exemplified in the table of FIG. 2.
  • FIG. 3 a small square is a 456 x 456 matrix.
  • a C 1 block and a P 1 block illustrated in FIGS. 2 and 3 respectively indicate an information block and a parity block which constructs the parity-check matrix. A detailed description of this will be given with reference to FIG. 4 and Equation 1.
  • the parity-check matrix with high- performance error correction is generated by using a design optimized for the degree distribution of the parity-check matrix and a design optimized for the cycle distribution on a factor graph.
  • Parity-check matrices used in the present invention will be described later. However, since the parity-check matrices have correlation with one another, designs optimized for all the parity-check matrices have to be concurrently performed, instead of individually performing designs optimized for the parity-check matrices.
  • FIG. 4 illustrates an example of a parity-check matrix H with a parity length of 456 bits, which supports five code rates.
  • the parity-check matrix H is the parity-check matrix H illustrated in FIG. 3.
  • FIG. 5 illustrates an example of a matrix P that is a parity block included in the parity-check matrix of FIG. 4.
  • a parity block P illustrated in FIG. 5 includes zero cyclic -permutation matrices as elements at locations of (0, 0), (6, 0), and (11, 0) and locations of (m, m-1) and (m, m) in a range of 1 ⁇ m ⁇ 11.
  • the parity block P includes zero matrices at the other locations.
  • the aforementioned parity block P can be used to embody a parallel processing LDPC encoder in units of partial blocks as a special case of a double diagonal parity block, it is possible to minimize the encoding complexity, when this type of parity block is used. That is, when the parity block P satisfies a linearly independent condition, it is possible to use the parity block P . Particularly, when the parity block with a type illustrated in FIG. 5 is used, it is possible to embody an encoder with lower complexity.
  • FIGS. 6 to 10 respectively illustrate examples of first to five information blocks C , C 1 1 , C 1 2 , C 1 3 , and C 1 4 of FIG. 4.
  • Integers that are largely represented in the right sides of FIGS. 6 to 10 indicate cyclic -permutation matrices obtained by cyclically shifting the 38 x 38 identity matrix by the integers in the right side. As described in relation to FIG. 5, '-' indicates a 38 x 38 zero matrix. For example, in FIG. 6, 37 indicates a cyclic-permutation matrix S .
  • exponents in the right sides of FIGS. 6 to 10 are used to generate information blocks included in the parity-check matrices H , H , and H respectively illustrated in FIGS. 11 to 13 by applying a row-splitting technique to first to fifth information blocks of FIG. 4 according to an embodiment of the present invention. This row- splitting technique will be described later with reference to Equation 1.
  • a parity-check matrix [C P ] constructed with the first information block C illustrated in FIG. 6 and the parity block P illustrated FIG. 5 is used to encode/decode the LDPC code with information length of 456 bits and a code rate of 0.5.
  • a parity-check matrix [C C P ] constructed with the first and second information blocks C and C respectively illustrated in FIGS. 6 and 7 and the parity block P illustrated in FIG. 5 is used to encode/decode the LDPC code with information length of 912 bits and a code rate of 2/3.
  • a parity-check matrix [C C C P ] constructed with the first to third information blocks C 0 , C 1 , and C 2 res r pectively J illustrated in FIGS. 6 to 8 and the parity block P illustrated in FIG. 5 is used to encode/decode the LDPC code with information length of 1368 bits and a code rate of 3/4.
  • a parity-check matrix [C C C C P ] constructed with the first to fourth information blocks C , C , C , and C respectively illustrated in FIGS. 6 to 9 and the parity block P illustrated in FIG. 5 is used to encode/decode the LDPC code with information length of 1824 bits and a code rate of 4/5.
  • the matrices of FIGS. 5 to 10 are exemplary matrices used to describe the spirit and scope of the present invention. It will be sufficiently understood by those of ordinary skill in the art that it is possible to generate various matrices with the sizes of the matrices of FIGS. 5 to 10, in addition to the matrices shown in FIGS. 5 to 10 by optimization of degree distribution and cycle distribution.
  • FIGS. 11 to 13 respectively illustrate examples of parity-check matrices with 912, 1368, and 1824 bits which support five code rates.
  • FIGS. 11 to 13 respectively illustrate the parity-check matrices H , H , and H of FIG. 3.
  • an information block C of FIG. 12 is obtained by applying the row- J 2 j splitting technique to an information block C .
  • the parity blocks of the parity-check matrices H , H , and H are generated by extending the parity block of the parity-check matrix H while maintaining the structure thereof. That is, the parity block P of FIG. 11 includes zero cyclic -permutation matrices at locations of (0, 0), (12, 0), and (23, 0) and locations of (m, m-1) and (m, m) in a range of 1 ⁇ m ⁇ 23 as elements. The parity block P includes zero matrices at the other locations. Accordingly, the parity block P of FIG. 11 has the same structure as the parity block P illustrated in FIG. 5. In addition, the parity block P of FIG.
  • the parity block P of FIG. 12 includes zero cyclic-permutation matrices at locations of (0, 0), (18, 0), and (35, 0) and locations of (m, m-1) and (m, m) in a range of 1 ⁇ m ⁇ 35 as elements.
  • the parity block P includes zero matrices at the other locations. Accordingly, the parity block P of FIG. 12 has the same structure as the parity block P illustrated in FIG. 5.
  • the parity block P of FIG. 13 includes zero cyclic-permutation matrices at locations of (0, 0), (24, 0), and (47, 0) and locations of (m, m-1) and (m, m) in a range of 1 ⁇ m ⁇ 47 as elements.
  • the parity block P includes zero matrices at the other locations. Accordingly, the parity block P of FIG. 13 has the same structure as the parity block P illustrated in FIG. 5.
  • the exponents of FIGS. 6 to 10 are used to generate information blocks of the parity-check matrices H , H , and H by applying the row-splitting technique to the information blocks of the parity-check matrix H .
  • the row-splitting technique according to an embodiment of the present invention is performed by using Equation 1 of FIG. 14.
  • FIG. 14 illustrates Equation 1 which represents a row-splitting technique according to an embodiment of the present invention.
  • a new parity-check matrix that is different from the parity-check matrix in the information length or code rate is generated by adding a second information block to the parity- check matrix constructed with the first information block and the parity block.
  • a new parity-check matrix that is different from the basic parity-check matrix in the information length or code rate is generated by generating an extended information block by applying the row- splitting technique to the basic information block and an extended parity block with the same structure as the basic parity block by extending the basic parity block.
  • An embodiment C is obtained by combining the embodiment A with the embodiment B.
  • the information block to which the row-splitting technique is applied is referred to as a basic information block
  • the information block obtained as the result of row- splitting is referred to as an extended information block.
  • the parity block to be extended is referred to as a basic parity block
  • the parity block obtained as the result of extension is referred to as an extended parity block.
  • parity-check matrices are generated by extending an information block in a state where the parity block is fixed, the information block is extended so as to generate a parity-check matrix with a high quality in degree distribution and cycle distribution.
  • the embodiment B will be additionally described as follows.
  • An extended parity- check matrix that is different from the basic parity-check matrix is generated by the row-splitting of the information block included in the basic parity-check matrix.
  • a row-splitting technique is applied for generating a parity-check matrix with high quality degree distribution and cycle distribution.
  • the embodiment B it is possible to generate a reduced parity-check matrix corresponding to the aforementioned extended parity-check matrix by generating a large- sized basic parity-check matrix, applying a row combining technique that is the inverse procedure of the row-splitting technique to the information block of the generated basic parity-check matrix, and applying parity part switching that uses only a part of the parity block of the generated basic parity-check matrix.
  • the row combining with respect to the information block may be represented as parity combining of an information part.
  • the parity part switching may be represented as parity combining of a parity part.
  • FIG. 15 illustrates a concept whereby an information shortening technique and a puncturing technique are applied to a parity-check matrix. Specifically, there is described an example in which the information shortening by k-k bits and the puncturing with respect to n numbers of parity bits are applied to a k x n parity-check
  • the k x n parity-check matrix basically supports a code rate of k/n and an information length of k.
  • a left uppermost vector that is a k x 1 input message vector includes information words, which are constructed with k eff numbers of information bits, and k-k eff numbers of O's which are filled with information shortenings, that is, the information length according to the current embodiment is k .
  • An n-bit codeword is generated by multiplying the input message vector by the parity-check matrix. Then, n numbers of
  • FIG. 15 illustrates a case where the information shortening technique and the puncturing technique with respect to the parity bits are applied
  • a parity-check matrix with a size k x (n - k + k - n ) is obtained by removing keff numbers of leftmost eff eff p columns, np numbers of rightmost columns, and k numbers of uppermost rows from the k x n parity-check matrix.
  • FIG. 16 is a block diagram illustrating a structure of an apparatus for generating a parity-check matrix according to an embodiment of the present invention.
  • the apparatus for generating a parity-check matrix includes a first parity-check matrix generation unit 101, a second parity-check matrix generation unit 102, a third parity- check matrix generation unit 103, a fourth parity-check matrix generation unit 104, a fifth parity-check matrix generation unit 105, an information shortening unit 110, and a puncturing unit 120.
  • FIG. 16 The embodiment of FIG. 16 will be described as follows with reference to FIGS. 4 to 10.
  • the first parity-check matrix generation unit 101 generates a first parity-check matrix
  • the second parity-check matrix generation unit 102 generates a second parity-check matrix [C C P ] by adding the second information block C of FIG. 7 to the
  • the third parity-check matrix generation unit 103 generates a third parity-check matrix [C 1 C 1 C 1 P 1 ] by adding the third information block C 1 of FIG. 8 to the
  • the fourth parity-check matrix generation unit 104 generates a fourth parity-check matrix [C 1 C 1 C 1 P 1 ] by adding the fourth information block C 1 of FIG. 9 to
  • the fifth parity-check matrix generation unit 105 generates a fifth parity-check matrix [C 1 4 C 1 3 C 1 2 C 1 1 C 1 0 P 1 ] by adding the fifth information block C 1 4 of FIG. 10 to the generated fourth parity-check matrix [C C C C P ].
  • the information shortening unit 110 generates at least one parity-check matrix different from the first to fifth parity-check matrices by applying the information shortening technique to at least one of the first to fifth parity-check matrices.
  • the puncturing unit 120 generates at least one parity-check matrix different form the first to fifth parity-check matrices by applying the puncturing technique to at least one of the first through fifth parity-check matrices.
  • FIG. 17 is a block diagram illustrating a structure of an apparatus for generating a parity-check matrix according to another embodiment of the present invention.
  • the apparatus for generating a parity-check matrix includes a basic parity-check matrix generation unit 200, an extended parity-check matrix generation unit 210, an information shortening unit 220, and a puncturing unit 230.
  • FIG. 17 represents an embodiment in which the parity-check matrices H , H , and H respectively illustrated in FIGS. 11 to 13 are generated from the parity-check matrix H of FIG. 4.
  • the basic parity-check matrix generation unit 200 generates at least one parity-check matrix, for convenience of explanation, the embodiment of FIG. 16 will be described with the assumption that a basic parity-check matrix [C P ] is generated.
  • the extended parity-check matrix generation unit 210 generates an information block C by applying the row-splitting technique to an information block C of the basic
  • parity-check matrix [C P ] 1 1 9 parity-check matrix [C P ] and generates a parity block P with the same structure as the parity block P by extending the parity block P of the basic parity-check matrix [C P ]. As a result, an extended parity-check matrix [C P ] is generated.
  • the information shortening unit 220 generates at least one parity-check matrix, which is different from the basic parity-check matrix [C P ] and the extended parity- check matrix [C P ], by applying information shortening to at least one of the basic parity-check matrix [C P ] and the extended parity-check matrix [C P ].
  • the puncturing unit 230 generates at least one parity-check matrix, which is different from the basic parity-check matrix [C P ] and the extended parity-check matrix [C P ] , by applying the puncturing technique to at least one of the basic parity-check matrix [C P ] and the extended parity-check matrix [C P ].
  • the extended parity-check matrix generation unit 210 can generate extended parity- check matrices [C 2 Q P 2 ], [C 2 ; C 2 Q P 2 ], [C 2 2 C 2 ; C 2 Q P 2 ], [C 2 3 C 2 2 C 2 ; C 2 Q P 2 ], and [C 2
  • FIG. 18 is a block diagram illustrating an LDPC encoding apparatus which supports a variable information length and a variable code rate according to an embodiment of the present invention.
  • the LDPC encoding apparatus includes a parity-check matrix selection unit 300 and an encoding unit 310.
  • the parity-check matrix selection unit 300 selects a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity-check matrices.
  • the plurality of parity-check matrices indicate parity-check matrices generated as described in FIGS. 16 and 17.
  • the input encoding parameter is used to select a parity-check matrix. Examples of the input encoding parameter include an information length and a code rate. However, since the input encoding parameter has only to enable determination of a parity-check matrix, the input encoding parameter does not have to be limited to the aforementioned examples.
  • the encoding unit 310 encodes an input information word based on the selected parity-check matrix.
  • FIG. 19 is a block diagram illustrating an LDPC decoding apparatus which supports a variable information length and a variable code rate according to an embodiment of the present invention.
  • the LDPC decoding apparatus includes a parity-check matrix selection unit 400 and a decoding unit 410.
  • the parity-check matrix selection unit 400 selects a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity-check matrices.
  • the plurality of parity-check matrices indicate parity-check matrices generated as described in FIGS. 16 and 17.
  • the input decoding parameter is used to select a parity-check matrix. Examples of the input decoding parameter include a code rate and an information length of a received codeword. However, since the input decoding parameter has only to determine a parity-check matrix, the input decoding parameter does not have to be limited to the aforementioned examples.
  • the decoding unit 410 decodes the received codeword based on the selected parity- check matrix.
  • An example of a decoding algorithm is a message passing algorithm (MPA).
  • MPA message passing algorithm
  • the decoding unit 410 sets a probability that the information shortening bit has a value of 0 to 1 and performs decoding.
  • the decoding unit 410 sets a probability that the punctured bit has a value of 1 to 0.5 and starts decoding.
  • FIG. 20 is a flowchart illustrating a method of generating a parity-check matrix according to an embodiment of the present invention.
  • the method of generating a parity-check matrix according to the current embodiment includes a sequence of processes performed by the apparatus for generating a parity-check matrix of FIG. 16. Accordingly, although a detailed de- scription is omitted, the aforementioned description of the apparatus for generating a parity-check matrix of FIG. 16 also applies to the method of generating a parity-check matrix according to the embodiment.
  • FIG. 20 The embodiment of FIG. 20 will be described as follows with reference to FIG. 16.
  • the first parity-check matrix generation unit 101 generates a first parity-check matrix constructed with the first information block and the parity block.
  • the second parity-check matrix generation unit 102 generates a second parity-check matrix by adding the second information block to the generated first parity-check matrix.
  • the third parity-check matrix generation unit 103 generates a third parity-check matrix by adding the third information block to the generated second parity-check matrix.
  • the fourth parity-check matrix generation unit 104 generates a fourth parity-check matrix by adding the fourth information block to the generated third parity-check matrix.
  • the fifth parity-check matrix generation unit 105 generates a fifth parity-check matrix by adding the fifth information block to the generated fourth parity-check matrix.
  • the information shortening unit 110 and the puncturing unit 120 generate at least one parity-check matrix that is different from the first to fifth parity- check matrices by respectively applying the information shortening and puncturing techniques to at least one of the first to fifth parity-check matrices.
  • FIG. 21 is a flowchart illustrating a method of generating a parity-check matrix according to another embodiment of the present invention.
  • the method of generating a parity-check matrix according to the current embodiment includes a sequence of processes performed by the apparatus for generating a parity-check matrix of FIG. 17. Accordingly, although a detailed description is omitted, the aforementioned description of the apparatus for generating a parity-check matrix of FIG. 17 also applies to the method of generating a parity-check matrix according to the embodiment.
  • FIG. 21 The embodiment of FIG. 21 will be described as follows with reference to FIG. 17.
  • the basic parity-check matrix generation unit 200 generates at least one parity-check matrix.
  • the extended parity-check matrix generation unit 210 generates at least one extended parity-check matrix by applying the row-splitting technique to an information block of the basic parity-check matrix and extending the parity block of the basic parity-check matrix.
  • the information shortening unit 220 and the puncturing unit 230 generate at least one parity-check matrix, which is different from the basic parity- check matrix and the extended parity-check matrix, by respectively applying the information shortening and puncturing techniques to at least one of the basic parity- check matrix and the extended parity-check matrix.
  • FIG. 22 is a flowchart illustrating an LDPC encoding method which supports a variable information length and a variable code rate according to an embodiment of the present invention.
  • the method of generating a parity-check matrix according to the current embodiment includes a sequence of processes performed by the LDPC encoding apparatus which supports a variable information length and a variable code rate of FIG. 18. Accordingly, although a detailed description is omitted, the aforementioned description of the LDPC encoding apparatus which supports a variable information length and a variable code rate of FIG. 18 also applies to the method of generating a parity-check matrix according to the current embodiment.
  • FIG. 22 The embodiment of FIG. 22 will be described as follows with reference to FIG. 18.
  • the parity-check matrix selection unit 300 selects a parity-check matrix corresponding to an input encoding parameter from among a plurality of parity- check matrices.
  • the plurality of parity-check matrices indicate parity-check matrices generated as described in FIGS. 16 and 17.
  • the encoding unit 310 encodes an input information word based on the selected parity-check matrix.
  • FIG. 23 is a flowchart illustrating an LDPC decoding method which supports a variable information length and a variable code rate according to an embodiment of the present invention.
  • the method of generating a parity-check matrix according to the current embodiment includes a sequence of processes performed by the LDPC decoding apparatus which supports a variable information length and a variable code rate of FIG. 19. Accordingly, although a detailed description is omitted, the aforementioned description of the LDPC decoding apparatus which supports a variable information length and a variable code rate of FIG. 19 also applies to the method of generating a parity-check matrix according to the current embodiment.
  • FIG. 23 The embodiment of FIG. 23 will be described as follows with reference to FIG. 19.
  • the parity-check matrix selection unit 400 selects a parity-check matrix corresponding to an input decoding parameter from among a plurality of parity- check matrices.
  • the plurality of parity-check matrices indicate parity-check matrices generated as described in FIGS. 16 and 17.
  • the invention can also be embodied as computer readable codes on a computer readable recording medium.
  • the computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the Internet).
  • the computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. Also, functional programs, codes, and code segments for accomplishing the present invention can be easily construed by programmers of ordinary skill in the art to which the present invention pertains.

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Abstract

La présente invention concerne un procédé de génération d'une matrice de contrôle de parité d'un code de contrôle de parité à faible densité (LDPC) à longueur d'informations variable et à vitesse de codage variable, un procédé de codage/décodage et un appareil utilisant ce dernier. Le procédé de génération d'une matrice de contrôle de parité d'un code LDPC comprend: un premier processus de génération d'une matrice de contrôle de parité construite avec un premier bloc d'informations et un bloc de parité; et un processus de génération d'une énième matrice de contrôle de parité par un énième bloc d'informations pour une énième moins 1 (m-1) matrice de contrôle de parité générée (1 < m ≤ M, où M représente un nombre entier naturel égal ou supérieur à deux). Il est ainsi possible de disposer d'un code LDPC à longueur d'informations variable et à vitesse de codage variable qui est peu complexe pour le codage/décodage et d'une qualité élevée de correction et de détection des erreurs.
PCT/KR2007/005478 2006-12-05 2007-10-31 Procédé de génération d'une matrice de contrôle de parité, procédé de codage/décodage pour un code de contrôle de parité à faible densité à longueur d'informations variable et à vitesse de codage variable, appareil utilisant ce dernier WO2008069460A1 (fr)

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EP2148445A1 (fr) * 2008-07-22 2010-01-27 Nokia Siemens Networks S.p.A. Génération de matrices exponentielles pour codes LDPC
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