WO2009078229A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2009078229A1
WO2009078229A1 PCT/JP2008/070318 JP2008070318W WO2009078229A1 WO 2009078229 A1 WO2009078229 A1 WO 2009078229A1 JP 2008070318 W JP2008070318 W JP 2008070318W WO 2009078229 A1 WO2009078229 A1 WO 2009078229A1
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WIPO (PCT)
Prior art keywords
semiconductor device
thin film
manufacturing
wiring board
mounting wiring
Prior art date
Application number
PCT/JP2008/070318
Other languages
English (en)
French (fr)
Inventor
Masayoshi Takeuchi
Original Assignee
Alps Electric Co. Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co. Ltd. filed Critical Alps Electric Co. Ltd.
Publication of WO2009078229A1 publication Critical patent/WO2009078229A1/ja

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

【課題】小型化および製造時間の短縮化を図ることができる半導体装置およびその製造方法を提供する。 【解決手段】本発明の半導体装置１は、実装配線板２、複数の半導体チップ３および複数の薄膜配線４を備えている。薄膜配線４はその接続前においてベースフィルム１０に貼付されている。接続ヘッド１１によってベースフィルム１０を吸着し、第１の接続端子５および第２の接続端子６が接合するように接続ヘッド１０を実装配線板２および複数の半導体チップ３の配設方向に押下すると、複数の薄膜配線４が実装配線板２および複数の半導体チップ３に一回で同時に接続される。ベースフィルムは薄膜配線４の接続後に接続ヘッドによて剥離される。
PCT/JP2008/070318 2007-12-18 2008-11-07 半導体装置およびその製造方法 WO2009078229A1 (ja)

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JP2007325937A JP2011040418A (ja) 2007-12-18 2007-12-18 半導体装置およびその製造方法

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US9209165B2 (en) * 2013-10-21 2015-12-08 Oracle International Corporation Technique for controlling positions of stacked dies

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156546A (ja) * 1988-12-08 1990-06-15 Sumitomo Metal Ind Ltd 半導体装置の製造方法
JPH06310565A (ja) * 1993-04-20 1994-11-04 Fujitsu Ltd フリップチップボンディング方法
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
WO2006028155A1 (ja) * 2004-09-08 2006-03-16 Nec Corporation モジュール型電子部品及び電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02156546A (ja) * 1988-12-08 1990-06-15 Sumitomo Metal Ind Ltd 半導体装置の製造方法
JPH06310565A (ja) * 1993-04-20 1994-11-04 Fujitsu Ltd フリップチップボンディング方法
JP2004063569A (ja) * 2002-07-25 2004-02-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
WO2006028155A1 (ja) * 2004-09-08 2006-03-16 Nec Corporation モジュール型電子部品及び電子機器

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