WO2007051142A3 - Metal cuboid semiconductor device and method - Google Patents

Metal cuboid semiconductor device and method Download PDF

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Publication number
WO2007051142A3
WO2007051142A3 PCT/US2006/060265 US2006060265W WO2007051142A3 WO 2007051142 A3 WO2007051142 A3 WO 2007051142A3 US 2006060265 W US2006060265 W US 2006060265W WO 2007051142 A3 WO2007051142 A3 WO 2007051142A3
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WO
WIPO (PCT)
Prior art keywords
cuboids
cuboid
copper
height
sides
Prior art date
Application number
PCT/US2006/060265
Other languages
French (fr)
Other versions
WO2007051142A2 (en
Inventor
Donald C Abbott
Original Assignee
Texas Instruments Inc
Donald C Abbott
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Donald C Abbott filed Critical Texas Instruments Inc
Priority to JP2008538167A priority Critical patent/JP2009514237A/en
Priority to EP06839559.9A priority patent/EP1952440B1/en
Publication of WO2007051142A2 publication Critical patent/WO2007051142A2/en
Publication of WO2007051142A3 publication Critical patent/WO2007051142A3/en

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    • H01L2924/01—Chemical elements
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    • H01L2924/01—Chemical elements
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device comprising a semiconductor chip (101) assembled on a first copper cuboid (110); the cuboid has sides of a height (111). The device further has a plurality of second copper cuboids (120) suitable for wire bond attachment; the second cuboids have sides of a height (121) substantially equal to the height of the first cuboid. The back surfaces of all cuboids are aligned in a plane (130). Encapsulation compound (140) is adhering to and embedding the chip, the wire bonds, and the sides of all cuboids so that the compound forms a first surface (140b) aligned with the plane of the back cuboid surfaces and a second surface (140a) above the embedded wires. For devices intended for stacking, the devices further comprise a plurality of vias (160) through the encapsulation compound from the first to the second compound surfaces; the vias are filled with copper, and the via locations are matching between the devices-to-be-stacked.
PCT/US2006/060265 2005-10-26 2006-10-26 Metal cuboid semiconductor device and method WO2007051142A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008538167A JP2009514237A (en) 2005-10-26 2006-10-26 Metal cubic semiconductor device and method
EP06839559.9A EP1952440B1 (en) 2005-10-26 2006-10-26 Metal cuboid semiconductor device and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/259,015 US7504716B2 (en) 2005-10-26 2005-10-26 Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
US11/259,015 2005-10-26

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WO2007051142A2 WO2007051142A2 (en) 2007-05-03
WO2007051142A3 true WO2007051142A3 (en) 2008-09-25

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EP (1) EP1952440B1 (en)
JP (1) JP2009514237A (en)
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WO (1) WO2007051142A2 (en)

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EP1952440B1 (en) 2019-12-11
WO2007051142A2 (en) 2007-05-03
EP1952440A4 (en) 2010-10-06
US20070090524A1 (en) 2007-04-26
CN101361163A (en) 2009-02-04
US7504716B2 (en) 2009-03-17
JP2009514237A (en) 2009-04-02
EP1952440A2 (en) 2008-08-06

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