WO2009077024A1 - Système de pesage numérique - Google Patents

Système de pesage numérique Download PDF

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Publication number
WO2009077024A1
WO2009077024A1 PCT/EP2008/008611 EP2008008611W WO2009077024A1 WO 2009077024 A1 WO2009077024 A1 WO 2009077024A1 EP 2008008611 W EP2008008611 W EP 2008008611W WO 2009077024 A1 WO2009077024 A1 WO 2009077024A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
integrator
module
comparator
pulse
Prior art date
Application number
PCT/EP2008/008611
Other languages
German (de)
English (en)
Inventor
Christian Oldendorf
Thomas Schink
Original Assignee
Sartorius Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sartorius Ag filed Critical Sartorius Ag
Publication of WO2009077024A1 publication Critical patent/WO2009077024A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01G—WEIGHING
    • G01G3/00—Weighing apparatus characterised by the use of elastically-deformable members, e.g. spring balances
    • G01G3/12—Weighing apparatus characterised by the use of elastically-deformable members, e.g. spring balances wherein the weighing element is in the form of a solid body stressed by pressure or tension during weighing
    • G01G3/14—Weighing apparatus characterised by the use of elastically-deformable members, e.g. spring balances wherein the weighing element is in the form of a solid body stressed by pressure or tension during weighing measuring variations of electrical resistance
    • G01G3/142—Circuits specially adapted therefor
    • G01G3/147—Circuits specially adapted therefor involving digital counting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/52—Input signal integrated with linear return to datum

Definitions

  • the invention relates to a digital weighing device, comprising a force transducer which generates an analog sensor signal corresponding to an introduced force, an integrator which transmits the sensor signal as a measurement signal permanently applied to it during operation and a working level of a sensor temporarily applied to it
  • Integrated reference signal a integrator downstream comparator, the one
  • Integrator output signal with a threshold value and, when the threshold value is reached, each compares a pulse edge of a pulse signal on one
  • Shift control means which, depending on the
  • Pulse signal a switch for temporary application of the
  • Value determination means based on a
  • Intervals during which the working level of the Reference signal is applied to the integrator determine the sensor signal representing weight values.
  • Such weighing devices are well known. These are weighing devices with a so-called integrating A / D converter for analog / digital conversion of the analog sensor signal.
  • the principle of the integrating A / D converter has long been known in many variants. Examples which may be mentioned here are DE 21 14 141, DE 28 20 601 C2 and DE 100 40 373 A1.
  • the measurement signal is applied to an input of an operational amplifier connected as an integrator.
  • the output of the operational amplifier is connected via a capacitor with its measuring signal input.
  • the supply line for a DC reference signal is also connected to the measuring signal input of the operational amplifier. This reference signal is only temporarily switched to a working level.
  • the capacitor is charged by the amplified in the operational amplifier measurement signal. If, after a predetermined period of time, the operating level of the reference signal is switched on, the capacitor discharges during a second clock component, as a result of which the integrator output signal drops.
  • the time of a zero crossing, or more generally a threshold crossing of the Integrator output signal is detected by means of a downstream comparator.
  • the duration of the second clock component ie the period during which the operating level of the reference signal is present at the integrator, is measured by suitable time-measuring means, for example a clocked counter.
  • the measured duration referred to here as the measurement interval, represents a measure of the charging of the capacitor in the first clock component and thus of the level of the measurement signal.
  • the counter value can be used directly as a digital measure of the measurement signal.
  • the sensors are analog sensors that produce an analog electrical voltage at their output.
  • Parallel connection of all analogue load cells supporting the weighing platform corresponds to a summation of the voltages to one
  • the analog combination voltage is typically digitized in such devices and forwarded as a sequence of digital values for further processing or evaluation.
  • Digital load cells generate digital measured values at specific measuring times.
  • the digital load cell sensor also includes one or more analog force transducers, such as strain gauges, that generate an analog voltage that is converted by an analog-to-digital converter of the sensor into a series of individual digital measurements, each digital measurement at the time of measurement represents the load acting on the force transducer.
  • analog force transducers such as strain gauges
  • the measured values for shipping units that can be sent via the data communication line.
  • a widespread interface standard of digital load cells is the serial RS 485 interface via which the information concerning the measured values is sent according to a standardized protocol.
  • Other interface or bus systems are also possible, with the processing of the measured values for shipping units always having to be carried out in adaptation to the communication network used.
  • the timing of the values to be combined is of particular importance.
  • the digital weighing cells therefore typically operate synchronized, the synchronization taking place, for example, by a synchronization pulse from the central control unit, which simultaneously requests all weighing cells to generate a digital measured value and then sequentially interrogates the measured values buffered in the individual measuring cells.
  • the sequentially interrogated measured values are then processed in the central control unit to a combination value, which is assigned to the synchronization time.
  • a sequence of individual time-associated combination values which represent a sampled course of the weight force acting on the weighing platform, is produced.
  • a disadvantage of this system is the considerable length of the interval between individual combination values, which increases with the number of increasing load cells increases. This is disadvantageous for dynamic weighing processes as well as for metering processes, in which an accurate and rapid predictability of the course of the weight force acting on the weighing devices is essential.
  • the above article suggests at least a partial return to analog weighing cells.
  • it is proposed to route the analog signals over a short analog line path to a multi-channel A / D converter to avoid interference, which digitizes the analog input signals synchronously on all channels and combines the generated digital values.
  • Disadvantages of this concept are the loss of modularity gained through the introduction of digital load cells and the reintroduction of analog line sections with their known interference and calibration problems. task
  • the core of the present invention lies in a special assignment of functional elements to different modules.
  • functional elements in the case of classical digital load cells, it is known to carry out the entire force absorption and digitization in the load cell and to transmit the digital weight value to a central processing unit.
  • the present invention makes another division of the functional elements.
  • the elements to be assigned to the functional unit of the A / D converter are split and assigned to different modules. In particular, all those elements to which analog signals are fed and / or which do not output digital signals are assigned to the first module, whereas all other functional elements are assigned to the second module.
  • Comparator pulse line and a switching line connecting the switching control means and the switch comprises. Both lines are purely digital in nature.
  • a digital line is understood here to be a line via which an information signal comprising only two levels is transmitted.
  • Such lines are known to be particularly resistant to interference, which explains their significant advantage over analog lines, in which the information content of the transmitted signal is in the continuous level profile.
  • the line pair between the load cell and be your digital module is also known to be particularly resistant to interference, which explains their significant advantage over analog lines, in which the information content of the transmitted signal is in the continuous level profile.
  • the line pair between the load cell and be your digital module Correspondingly long, the line pair between the load cell and be your digital module. This has a particularly advantageous effect in systems which represent a preferred development of the invention and comprise a plurality of first modules which are mechanically connected to a weighing platform and are each connected via a line pair to a second module common to the first modules. Because of the interference resistance of the digital line pairs, in the construction of such systems, the spatial
  • the problem discussed above of synchronizing a plurality of load cells can also be solved in a simple manner.
  • an output of a switching signal which causes the application of the operating level of the reference signal to the integrator, takes place simultaneously from the common second module to the first modules on all switching lines.
  • the switching lines or the switching signals output via the switching lines it is possible to easily synchronize the switching lines or the switching signals output via the switching lines. Therefore, no separate synchronization signal is required for all load cells; Rather, the respective Abintegrationsphase immediately triggering switching signal is output from the common second module on all first modules.
  • different functional elements of the second module have been given different names.
  • a counter is provided in the microprocessor and, for each connected first module, a register coupled to the count output, whose count corresponds to the count at the time of the pulse edge of the associated clock
  • Comparative pulse signal corresponding content at a caused by the pulse edge change of the associated switching signal is retained and read out as a measure of the sensor signal of the associated sensor.
  • the switching signal is set and transmitted via the switching line to the switch, which applies the working level of the reference signal to the integrator. Thereafter, the counter runs high, with its count is written to each of the registers.
  • the comparator pulse signal At the end of the Abintegrationsphase, which usually ends for each of the load cells according to the respectively introduced force at another time, the comparator pulse signal generates a change of the switching signal, which freezes the value of the respective associated register in the short term, so that this value as a measure of the Sensor value of each associated load cell can be read. If the corresponding values of all load cells are available, the microprocessor can make a suitable combination of the individual values for calculating the total weight value.
  • Figure 1 is a schematic block diagram of a first embodiment of the invention
  • Figure 2 is a schematic block diagram of a second embodiment of the invention.
  • Figure 3 a schematic timing diagram for
  • FIG. 1 shows a schematic block diagram of an embodiment of the present invention.
  • three load cells 1, 2, 3 are connected to a shared digital module 4.
  • the number of load cells is not essential to the present invention. In particular, more, less or even a single load cell can be realized.
  • the load cells 1, 2, 3 are mechanically connected to a weighing platform which receives an object to be weighed. Below, only the details of the load cells 1 will be discussed, which is substantially identical to the other load cells 2, 3, so that a transmission for the expert is easy, especially as corresponding reference numerals designate corresponding components.
  • a resistor 10 which is connected to the output of a force transducer, not shown in Figure 1, one of the introduced into the force transducer weight force of an object to be weighed corresponding current is introduced into the inverting input of an operational amplifier.
  • the operational amplifier 12 is connected as an integrator, ie its output is fed back via a capacitor 14 to the inverting input.
  • This is additionally connected via a resistor 16 and a switch 18 to a reference voltage source, not shown.
  • the connection is switchable by means of the switch 18 between a floating state and a state connected to a reference potential.
  • the switch 18 may also toggle between two different levels of a reference signal.
  • a comparator 20 Connected downstream of the output of the operational amplifier 12 is a comparator 20, which compares the signal INTl supplied by the integrator with a threshold value (here the ground potential) and outputs a pulse edge of a comparator pulse signal KIP1 on a comparator pulse line 22 when the threshold value is reached, which is introduced into a digital module 4 becomes.
  • the digital module 4 is preferably designed as a microprocessor. In the illustration of Figure 1, two of the implemented in the microprocessor functionalities, namely the switching control means 28, which drive the switch 18, and a counter 32 are shown separately.
  • the representation of the switching control means 28 takes place in accordance with the functionality of a clocked flip-flop, but a comparable functionality with other components and in particular with integration of Switching control means can be achieved in the microprocessor.
  • the switching control means 28 In response to the comparator pulse signal KIPl and a zero setting of the counter 32 indicative output of the counter 32, the switching control means 28, the output of which are connected to a switching line 30, generate a switching signal AOPl, which controls the switch 18.
  • a digital weighing device is basically known, so that the details of the switch control and the digital value determination need not be carried out in depth here.
  • the preferably used multiple ramp method for digitizing an analog measured value which is preferably used within the scope of the invention, is known in principle to the person skilled in the art.
  • FIG. 3 shows a timing diagram, which schematically shows the integrator signals INT1, INT2, INT3, the
  • the signals INT1, KIP1 and AOP1 belonging to a first load cell will be explained.
  • the other signals shown in Figure 3 are to be understood accordingly.
  • an integration phase Iup during which the switching signal AOP1 has an LO level and the switch 18 is open, only the measuring signal is present at the operational amplifier 12.
  • the integrator signal INT increases accordingly.
  • the integration phase Iup ends and the counter 32 is set to zero and started.
  • a set signal is sent to the set input of the flip-flop 28, which is thereby set, ie its output, the switching signal AOPL goes at HI level so that the switch 18 is closed and the charge accumulated in the capacitor 14 is dissipated.
  • the integrator signal INTl falls accordingly.
  • the period of time required to lower the integrator signal INT1 below a predetermined threshold and during which the counter 32 counts up is representative of the previously integrated charge and thus of the measurement signal.
  • the reaching of the threshold value is signaled by the comparator 20 by outputting a pulse edge of the comparator pulse signal KIP1. This pulse edge resets the flip-flop 28, so that its output signal, the switching signal AOPl goes back to LO level. This transition stops the counter 32.
  • the duration of this Abintegrations- or measuring interval Im can thus be read on not separately illustrated count output of the counter 32.
  • the timing diagram shown in FIG. 3 represents only a variant of possible actuations of the A / D conversion. Other variants may benefit from the present invention. It is essential that a time interval representative of the measurement signal can be determined by means of the pulse edge generated by the comparator 20 and the switching signal AOP1 or a control signal preceding it. Accordingly, the other signals shown in Figure 3 are to be understood, where INT2, KIP2 and AOP2 illustrate the case of a smaller and INT3, KIP3 and A0P3 the case of a larger weighing value of the associated load cell.
  • Figure 2 shows substantially the same structure as Figure 1, but with the digital module being organized in a particularly advantageous manner.
  • the count value output of the counter 32 is connected to the measuring cells respectively assigned registers.
  • the set signal when zeroing the counter 32 in Figure 2 takes place simultaneously for all switching control means or flip-flops 28.
  • the Abintegrationsphase therefore begins in each measuring point 1, 2, 3 simultaneously.
  • the Abintegrationsphase in the individual load cells 1, 2, 3 according to the different measurement signals of the load cells 1, 2, 3 end at different times.
  • the respective associated comparator generates the pulse edge which resets the associated switching control means 28, as a result of which the associated switching signal again goes to the LO level.
  • This transition latches the associated register 34, which is connected to the count output of the associated counter 32.
  • the register 34 can then be read out and the read value suitable be further processed. In this way, it is achieved that without special synchronization measures all load cells 1, 2, 3 synchronously measure and the respective measurement results in the digital module further processed and can be combined in particular to a total value of weight.
  • the digital module 4 is preferably designed as a microprocessor with multiple inputs, wherein the concrete realized logic is achieved by a combination of its hardware and software.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Force In General (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

Système de pesage numérique, qui comprend un capteur de force produisant un signal de capteur analogique correspondant à une force appliquée, un intégrateur intégrant le signal de capteur, en tant que signal de mesure appliqué de façon permanente à l'intégrateur en fonctionnement, ainsi qu'un niveau de travail d'un signal de référence, lequel niveau est appliqué temporairement audit intégrateur, un comparateur (20) monté en aval de l'intégrateur, lequel comparateur compare un signal de sortie de l'intégrateur à une valeur seuil et, lorsque la valeur seuil est atteinte, produit un flanc d'impulsion d'un signal d'impulsion sur une ligne d'impulsions (22) du comparateur, des moyens de commande de commutation, qui commandent, en fonction du signal d'impulsion, un commutateur (18) permettant l'application temporaire du niveau de travail du signal de référence à l'intégrateur, ainsi que des moyens de détermination de valeurs qui déterminent des valeurs de pesée représentant le signal de capteur sur la base d'une durée des intervalles au cours desquels le niveau de travail du signal de référence est appliqué à l'intégrateur, laquelle durée est acquise par des moyens de détermination de temps. Selon l'invention, le capteur de force, l'intégrateur, le comparateur (20) et le commutateur (18) sont regroupés en un premier module et les moyens de commande de commutation, les moyens de détermination de temps et les moyens de détermination de valeurs sont regroupés en un second module séparé.
PCT/EP2008/008611 2007-12-19 2008-10-11 Système de pesage numérique WO2009077024A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200710061786 DE102007061786B4 (de) 2007-12-19 2007-12-19 Digitale Wägevorrichtung
DE102007061786.2 2007-12-19

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WO2009077024A1 true WO2009077024A1 (fr) 2009-06-25

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2114141A1 (de) * 1971-03-24 1972-09-28 Gruetzediek H Analog-Digital-Umsetzer mit einem integrierenden Verstaerker nach dem Mehrfach-Rampen-Verfahren
DE2820601A1 (de) * 1971-03-24 1979-11-15 Hartmut Dipl Phys Gruetzediek Analog-digital-umsetzer nach dem mehrfach-rampenverfahren
DE10040373A1 (de) * 1999-08-20 2001-02-22 Sartorius Gmbh Analog/Digital-Umsetzer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19732974A1 (de) * 1997-07-31 1999-02-04 Ulf Dipl Ing Bernhardt Integrierter Meßsignalanpasser für leistungsschwache Sensorsignale bestehend aus einem Analog-Digital-Umsetzer der nach einem kompensierendem Verfahren arbeitet und einer Telemetriestrecke
US6243034B1 (en) * 1998-10-29 2001-06-05 National Instruments Corporation Integrating analog to digital converter with improved resolution

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2114141A1 (de) * 1971-03-24 1972-09-28 Gruetzediek H Analog-Digital-Umsetzer mit einem integrierenden Verstaerker nach dem Mehrfach-Rampen-Verfahren
DE2820601A1 (de) * 1971-03-24 1979-11-15 Hartmut Dipl Phys Gruetzediek Analog-digital-umsetzer nach dem mehrfach-rampenverfahren
DE10040373A1 (de) * 1999-08-20 2001-02-22 Sartorius Gmbh Analog/Digital-Umsetzer

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DE102007061786B4 (de) 2011-09-22
DE102007061786A1 (de) 2009-06-25

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