WO2009072544A1 - 電極構造及びその製造方法、回路基板、半導体モジュール - Google Patents

電極構造及びその製造方法、回路基板、半導体モジュール Download PDF

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Publication number
WO2009072544A1
WO2009072544A1 PCT/JP2008/072019 JP2008072019W WO2009072544A1 WO 2009072544 A1 WO2009072544 A1 WO 2009072544A1 JP 2008072019 W JP2008072019 W JP 2008072019W WO 2009072544 A1 WO2009072544 A1 WO 2009072544A1
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Prior art keywords
circuit board
layer
electrode structure
semiconductor module
bonding
Prior art date
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PCT/JP2008/072019
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English (en)
French (fr)
Inventor
Setsuo Andoh
Fumitake Taniguchi
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Hitachi Metals, Ltd.
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Publication date
Application filed by Hitachi Metals, Ltd. filed Critical Hitachi Metals, Ltd.
Priority to US12/746,056 priority Critical patent/US8710679B2/en
Priority to JP2009544701A priority patent/JP5585080B2/ja
Publication of WO2009072544A1 publication Critical patent/WO2009072544A1/ja

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

 電気的接合部における充分な接合強度をもち、高い信頼性をもった半導体モジュールを得る。この半導体モジュール10においては、回路基板20上に半導体チップ11が搭載される。回路基板20においては、絶縁性のセラミックス基板21上に、金属回路板22が形成され、半導体チップ11が搭載される。半導体チップ11と金属回路板22とはアルミニウム(Al)製のボンディングワイヤ23で接続される。金属回路板22とボンディングワイヤ23との接続部分には、これらの間の接合を良好にするための被覆層24が設けられている。被覆層24は、図1における拡大図に示されるように、下側からニッケル(Ni)層241、リン(P)分布パラジウム(Pd)層242、金(Au)層243で構成される。P分布Pd層242にはリン(P)が添加されており、特にこのP濃度は、Ni層241側よりも、Au層243側で高くなっている。
PCT/JP2008/072019 2007-12-04 2008-12-04 電極構造及びその製造方法、回路基板、半導体モジュール WO2009072544A1 (ja)

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US12/746,056 US8710679B2 (en) 2007-12-04 2008-12-04 Electrode structure and its manufacturing method, and semiconductor module
JP2009544701A JP5585080B2 (ja) 2007-12-04 2008-12-04 電極構造及びその製造方法、回路基板、半導体モジュール

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CN106558564B (zh) * 2015-09-29 2019-08-27 稳懋半导体股份有限公司 半导体元件背面铜金属的改良结构
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WO2021049235A1 (ja) * 2019-09-13 2021-03-18 昭和電工株式会社 積層体およびその製造方法
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