WO2009072182A1 - 回路基板および電子機器 - Google Patents
回路基板および電子機器 Download PDFInfo
- Publication number
- WO2009072182A1 WO2009072182A1 PCT/JP2007/073381 JP2007073381W WO2009072182A1 WO 2009072182 A1 WO2009072182 A1 WO 2009072182A1 JP 2007073381 W JP2007073381 W JP 2007073381W WO 2009072182 A1 WO2009072182 A1 WO 2009072182A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit board
- patterns
- electronic device
- layer
- slit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/04—Assemblies of printed circuits
- H05K2201/044—Details of backplane or midplane for mounting orthogonal PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09245—Crossing layout
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Structure Of Printed Boards (AREA)
Abstract
本発明は、10層構造を有する回路基板150において、第10層151_10に形成された、互いに平行に延びる複数本の導体パターンであって、各々の導体パターンが接地パターンとして用いられるスリット状グラウンドパターン151bと、第1層151_1に、回路基板150に垂直な方向から投影したときの、第1層151_1における上記の表面におけるスリット状グラウンドパターン151bが形成された領域と重なる領域に形成された、互いに平行に延びる複数本の導体パターンであって信号線として用いられるスリット状配線パターン151aとを備えた。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/073381 WO2009072182A1 (ja) | 2007-12-04 | 2007-12-04 | 回路基板および電子機器 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/073381 WO2009072182A1 (ja) | 2007-12-04 | 2007-12-04 | 回路基板および電子機器 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009072182A1 true WO2009072182A1 (ja) | 2009-06-11 |
Family
ID=40717368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/073381 WO2009072182A1 (ja) | 2007-12-04 | 2007-12-04 | 回路基板および電子機器 |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2009072182A1 (ja) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS522153U (ja) * | 1975-06-24 | 1977-01-08 | ||
JPS6154651A (ja) * | 1984-07-30 | 1986-03-18 | ゼネラル・エレクトリツク・カンパニイ | 低損失の多レベルのシリコン回路板 |
JPH0260185A (ja) * | 1988-08-26 | 1990-02-28 | Seiko Keiyo Kogyo Kk | 回路基板 |
JPH05299786A (ja) * | 1992-04-20 | 1993-11-12 | Ibiden Co Ltd | プリント配線板 |
JPH11112142A (ja) * | 1997-10-01 | 1999-04-23 | Kyocera Corp | 多層配線基板 |
JPH11145569A (ja) * | 1997-11-04 | 1999-05-28 | Canon Inc | プリント配線板及びその設計方法 |
JP2000244133A (ja) * | 1999-02-24 | 2000-09-08 | Kyocera Corp | 多層配線基板 |
JP2001053454A (ja) * | 1999-08-10 | 2001-02-23 | Nec Corp | 多層プリント配線板 |
JP2002063958A (ja) * | 2000-08-17 | 2002-02-28 | Seiko Epson Corp | 電気光学装置および電子機器 |
-
2007
- 2007-12-04 WO PCT/JP2007/073381 patent/WO2009072182A1/ja active Application Filing
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS522153U (ja) * | 1975-06-24 | 1977-01-08 | ||
JPS6154651A (ja) * | 1984-07-30 | 1986-03-18 | ゼネラル・エレクトリツク・カンパニイ | 低損失の多レベルのシリコン回路板 |
JPH0260185A (ja) * | 1988-08-26 | 1990-02-28 | Seiko Keiyo Kogyo Kk | 回路基板 |
JPH05299786A (ja) * | 1992-04-20 | 1993-11-12 | Ibiden Co Ltd | プリント配線板 |
JPH11112142A (ja) * | 1997-10-01 | 1999-04-23 | Kyocera Corp | 多層配線基板 |
JPH11145569A (ja) * | 1997-11-04 | 1999-05-28 | Canon Inc | プリント配線板及びその設計方法 |
JP2000244133A (ja) * | 1999-02-24 | 2000-09-08 | Kyocera Corp | 多層配線基板 |
JP2001053454A (ja) * | 1999-08-10 | 2001-02-23 | Nec Corp | 多層プリント配線板 |
JP2002063958A (ja) * | 2000-08-17 | 2002-02-28 | Seiko Epson Corp | 電気光学装置および電子機器 |
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