WO2009070322A1 - Systems and methods for read data buffering - Google Patents

Systems and methods for read data buffering Download PDF

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Publication number
WO2009070322A1
WO2009070322A1 PCT/US2008/013186 US2008013186W WO2009070322A1 WO 2009070322 A1 WO2009070322 A1 WO 2009070322A1 US 2008013186 W US2008013186 W US 2008013186W WO 2009070322 A1 WO2009070322 A1 WO 2009070322A1
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WO
WIPO (PCT)
Prior art keywords
data
data storage
master controller
storage node
read
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/013186
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English (en)
French (fr)
Inventor
Roger Dwain Isaac
Seiji Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
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Spansion LLC
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Priority to JP2010534980A priority Critical patent/JP2011505037A/ja
Publication of WO2009070322A1 publication Critical patent/WO2009070322A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses

Definitions

  • provisional patent application serial number 61/004,362 filed on November 26, 2007, entitled A SYSTEM AND METHOD FOR ACCESSING MEMORY (attorney docket number SPSN- AF02874.PRO), which is hereby incorporated by reference into this specification in its entirety and co- pending U.S. provisional patent application serial number 61/004,412, filed on November 26, 2007, entitled A METHOD FOR SETTING PARAMETERS AND DETERMINING LATENCY IN A CHAINED DEVICE SYSTEM (attorney docket number SPSN-AF02875.PRO), which is hereby incorporated by reference into this specification in its entirety.
  • the present invention relates to the field of data storage node management. More particularly, the present invention relates to an efficient and effective system and method for accessing memory node resources.
  • Systems and methods for controlling buffering are disclosed.
  • core operations are performed in response to a receipt of a read command from a master controller and a communication buffer of a data storage node is selected to forward information to the master controller.
  • the data storage node is selected based upon constraints and contents of one or more communication buffers.
  • Information is forwarded from the selected communication buffer to the master controller.
  • Figure 1 is a block diagram data storage system that includes a system for controlling read data buffering according to one embodiment of the present invention.
  • Figure 2 is a graph that illustrates the operation of a data storage system according to one embodiment of the present invention.
  • Figure 3 is a block diagram for controlling read data buffering according to one embodiment of the present invention.
  • Figure 4A shows a flowchart of an exemplary method for controlling read data buffering according to one embodiment of the present invention.
  • Figure 4B shows a flowchart of an exemplary method for selecting a read data buffer on which to send information to the master controller according to one embodiment of the present invention.
  • Figure 5 shows a flowchart of an exemplary method for operating an internal controller of data storage node according to one embodiment of the present invention.
  • Figure 6 shows a flowchart of an exemplary method for operating an internal controller of data storage node according to one embodiment of the present invention.
  • Figure 1 shows a data storage system 100 that includes a system 115 for controlling read data buffering according to one embodiment of the present invention.
  • system 115 implements an algorithm that operates to shorten latency and improve effective bandwidth of data storage system 100.
  • data storage nodes are disclosed that include internal and external communication buffers.
  • communication buffers include internal read data buffers and external read data buffers.
  • Figure 1 shows master controller 101, data storage node 103, data storage node 105, data storage node 107, read communication 111 (read command), read response 113 and system 115.
  • data storage nodes 103, 105 and 107 include internal read data buffers 103a, 105a and 107a respectively, external read data buffers 103b, 105b and 107b respectively and internal controllers 103c, 105c and 107c respectively.
  • master controller 101 controls read and write commands to data storage nodes 103, 105 and 107.
  • read commands 111 can be adjusted such that the flow of data to master controller 101 is controlled.
  • read responses 113 can be forwarded to master controller 101 in a manner such that when space is available between read responses 113 forwarded from internal read data buffer 103a of data storage node 103 to master controller 101 , read data responses from an external read data buffer 103b of data storage node 103 can be opportunistically squeezed into the space and forwarded to master controller 101 (see discussion made with reference to Figure 2 and also the discussion of the operation of system 115 below).
  • Data storage nodes 103, 105 and 107 are coupled to master controller 101 in a daisy chain arrangement.
  • data storage nodes 103, 105 and 107 comprise internal and external read data buffers 103a-107a and 103b- 107b respectively.
  • internal and external read data buffers 103a- 107a and 103b-107b buffer data that is to be forwarded to master controller 101 in response to read communications 111 that are issued from master controller 101.
  • various algorithms can be employed to determine priority for purposes of forwarding data held in internal read data buffers 103a-107a and external read data 103b- 107b to master controller
  • Internal controllers 103c, 105c and 107c control operations such as the forwarding of data from respective data storage nodes to master controller 101, and the execution of internal reads of respective data storage nodes.
  • components and operations of system 115 can be associated with and support components and operations of internal controllers 103c, 105c and 107c.
  • these components and operations can implement various algorithms and operate cooperatively with the components and operations of internal controllers 103c, 105c and 107c to determine priority as it regards the forwarding of data to master controller 101. These algorithms are discussed in detail herein (e.g., see exemplary algorithms in Figures 6 and 7).
  • System 115 acts cooperatively with components and operations of master controller 101 to control read data buffering by directing the issuance of reads based on the latency associated with particular read operations.
  • components and operations of system 115 act cooperatively with components and operations of internal controllers 103-107c to control the flow of information from data storage nodes 103, 105 and 107 to master controller 101.
  • some components and operations of system 115 can be integrated with master controller 101 and other components and operations of system 115 can be integrated with internal controllers 103c-107c. See Figure 1 which shows some components of system 115 located in master controller 101 and some components of system 115 located in internal controllers 103c-107c.
  • components and operations of system 115 can be separate from components and operations of master controller 101 and internal controller 103c-107c, but operate cooperatively therewith.
  • system 115 determines whether an internal read data buffer 103a-107a or an external read data buffer 103b-107b of one of the data storage nodes 103, 105 and 107 is to send information to master controller 101. In one embodiment, the determination is based on various algorithms. More specifically, in one embodiment, the determination is based upon constraints and contents of the read data buffers. And, in addition, in one embodiment, system 115 can direct that a burst of data from external read data buffer 103b be squeezed into a space between data transmissions to master controller 101 from an internal read data buffer 103a. An exemplary operation of system 115 is discussed in detail below in the following section.
  • Figure 2 is a graph that illustrates an example of the affect that system 115 has on the forwarding of data to master controller 101 and on read operations that are executed by master controller 101 according to one embodiment of the present invention. It should be appreciated that, the discussion of Figure 2 below makes reference to relevant elements of Figure 1.
  • Figure 2 shows graphical representations for clock signal 201, read commands 203, internal read buffer data 205, external read buffer data 207, read data 209. In the Figure 2 example, seven read operations readO-read ⁇ , with latencies ranging from 7 to 9 cycles, are shown.
  • system 115 can cause a burst of external read buffer data 207 to be forwarded to master controller 101 between bursts of internal read buffer data 205 that are forwarded to master controller 101 (e.g., a burst of external read buffer data 207 is placed between bursts of internal read buffer data 205 that is sent to master controller 101).
  • system 115 can cause the issuance of read operation read ⁇ to be shifted by two cycles.
  • components and operations of system 115 can implement various algorithms that act cooperatively with components and operations of internal controllers 103c, 105c and 107c under certain conditions. These algorithms are discussed in detail below and with reference to Figures 6 and 7.
  • a round robin algorithm may be implemented that chooses between local data (read responses) coming from data storage node 103 and data that is coming from downstream devices (data storage node 105 and data storage node 107). In this manner a fair arbitration policy ensures that no device is starved for a prolonged period of time.
  • a simple one bit counter (e.g., called RNDRBN) may be used to indicate whether local data packets (e.g., RNDRBN "1") or downstream data packets (e.g., RNDRBN "0") are given preference to send data to the master controller 101.
  • RNDRBN simple one bit counter
  • RNDRBN is set to "0°. 5. If none of the above conditions are satisfied, RNDRBN remains a "0".
  • an algorithm that selects external traffic over internal traffic in a static decision and prioritizes data from further data storage nodes over data from nearer data storage nodes can be employed.
  • Figure 3 shows components of a system 115 for controlling read data buffering according to one embodiment of the present invention.
  • system 115 implements an algorithm for read data buffering based on various algorithms.
  • system 115 includes read command scheduler 301, read command communicator 303, read data buffer selector 305, and data forwarder 307.
  • components and operations of system 115 can be implemented in hardware or software or in a combination of both.
  • components and operations of system 115 can be encompassed by components and operations of one or more computer programs (e.g., program of master controller or data storage nodes such as their internal controllers).
  • components and operations of system 115 can be separate from the aforementioned one or more computer programs but can operate cooperatively with components and operations thereof.
  • read command scheduler 301 schedules the timing of the issuance of read commands to a plurality of daisy chained data storage nodes (e.g., 103-107 in Figure 1). In one embodiment, the aforementioned scheduling of the timing of the issuance of read commands to data storage nodes can include adjusting a read command to be executed earlier or later based upon a determined latency of the read command.
  • Read command communicator 303 communicates or directs the communication of read commands to the plurality of daisy chained storage nodes (e.g., 103-107 in Figure 1). In one embodiment, read command communicator 303 directs the communication of read commands based on the timing determined by read command scheduler 301.
  • Read data buffer selector 305 determines the internal or external read data buffer of one of the plurality of daisy chained storage nodes, that is to forward data to the data storage system master controller (e.g., 101 in Figure 1). In one embodiment, the determination is based upon communication buffer constraints and contents. In one embodiment, an algorithm can be used to determine what data is to be forwarded to the master controller (see discussions made with reference to Figures 5 and 6).
  • read data buffer selector 305 can direct that a burst of data from an external read data buffer of a storage node be squeezed into a space between data transmissions to master controller (e.g., 101 in Figure 1) from an internal read data buffer of a storage node (e.g., 103 in Figure 1) in order to optimize the flow of data to master controller (reduce latency).
  • master controller e.g., 101 in Figure 1
  • internal read data buffer of a storage node e.g., 103 in Figure 1
  • Data forwarder 307 forwards or directs the forwarding of data from an internal or external communication buffer of a data storage node to the master controller (e.g., 101 in Figure 1). In one embodiment, data forwarder 307 forwards data that is selected to be forwarded by read data buffer selector 305.
  • FIG. 4A shows a flowchart 400A of the steps performed in a method for controlling read data buffering according to one embodiment.
  • the flowchart includes processes that, in one embodiment can be carried out by processors and electrical components under the control of computer-readable and computer-executable instructions. Although specific steps are disclosed in the flowcharts, such steps are exemplary. That is the present invention is well suited to performing various other steps or variations of the steps recited in the flowcharts. Within various embodiments, it should be appreciated that the steps of the flowcharts can be performed by software, by hardware or by a combination of both.
  • the timing of the forwarding of read commands to an identified data storage node is determined.
  • a read command scheduler e.g., 301 in Figure 3
  • the timing of the forwarding of read commands can be based on the latency that is associated with read operations to the identified data storage node.
  • determining the timing of the forwarding of read commands to data storage nodes can include adjusting a read command to be executed earlier or later based upon the determined latency.
  • a read command is sent to one of a plurality of daisy chained storage nodes.
  • a read command communicator e.g., 303 in Figure 3
  • a read data buffer is selected to send information to the master controller (e.g., 101 in Figure 1).
  • a read data buffer selector e.g., 305 in Figure 3
  • the determination may be based upon internal and external read data buffer constraints and contents.
  • an algorithm can be used to determine what data is to be forwarded to the master controller (see discussions made with reference to Figures 5 and 6).
  • a data forwarder (e.g., 307 in Figure 3) can be used to forward data that is selected to be forwarded by the read data buffer selector (e.g., 305 in Figure 3).
  • Figure 4B shows a flowchart 400B of the steps performed in a method for selecting a read data buffer to forward data to the master controller such as is performed at step 430 of the method discussed with reference to Figure 4A according to one embodiment.
  • core operations in support of a read command received from the master controller are performed.
  • a read data buffer is selected from which to forward data to the master controller.
  • the selection of the internal or external communication buffer is based upon constraints and contents of one or more communication buffers of one or more data storage nodes.
  • the selection is based upon an algorithm such as that discussed below with reference to Figure 5 that takes such constraints and contents into account. In another embodiment, the selection is based upon an algorithm such as that discussed below with reference to Figure 6.
  • the data from the read data buffer selected at step 433 is forwarded to the master controller.
  • Figure 5 shows a flowchart 500 of the steps performed in a method for operating an internal controller of data storage node 103 of Figure 1 in accordance with an algorithm implemented by system 115 according to one embodiment of the present invention.
  • system 115 an algorithm implemented by system 115 according to one embodiment of the present invention.
  • relevant elements of Figure 1 e.g., master controller 101 and data storage nodes 103 and 105.
  • FIG. 5 it is determined whether or not data exists in the internal read buffer (e.g., 103a) of data storage node 103. If data exists in data storage node 103, then data is sent at 503 to master controller 101 in a First-In-First-Out (FIFO) manner. At 505 if it is determined that data storage node 103 has data that is ready to be sent to master controller 101 by an internal read of data storage node 103, data is stored at 507 in the internal read buffer (e.g., 103a) of data storage node 103 at the next available entry. If it is determined at 509 that the adjacent data storage node 105 is sending data to data storage node 103, this data is stored in the external read buffer (e.g., 103b) of data storage node 103 at the next available entry at 511.
  • the internal read buffer e.g., 103a
  • data storage node 105 is also sending data to data storage node 103, then this data is stored in the external read buffer (e.g., 103b) of data storage node 103 at the next available entry at 519.
  • external read buffer e.g., 103b
  • Figure 6 shows a flowchart 600 of the steps performed in a method for operating an internal controller of data storage node 103 of Figure 1 in accordance with another algorithm implemented by system 115 according to one embodiment of the present invention.
  • system 115 implements another algorithm implemented by system 115 according to one embodiment of the present invention.
  • relevant elements of Figure 1 e.g., master controller 101 and data storage nodes 103 and 105.
  • an external read buffer e.g., 103b
  • data is sent at 603 to master controller 101 in a First-In-First-Out (FIFO) manner.
  • FIFO First-In-First-Out
  • data from an internal read of data storage node 103 is ready to be sent to master controller 101, if so, this data is stored at 607 in the internal read buffer (e.g., 103a) of data storage node 103 at the next available entry. If it is determined at 609 that adjacent data storage node 105 is sending data to data storage node 103, this data is stored in the external read buffer (e.g., 103b) of data storage node 103 at the next available entry at 611.
  • an algorithm that selects external traffic over internal traffic in a static decision and prioritizes data from further data storage nodes over data from data storage nodes that are nearer can be employed.
  • methods for controlling read data buffering are disclosed.
  • core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller.
  • the data storage node is selected based upon constraints and contents of one or more communication buffers.
  • Information is forwarded from the selected internal or external communication buffer to the master controller.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
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PCT/US2008/013186 2007-11-26 2008-11-25 Systems and methods for read data buffering Ceased WO2009070322A1 (en)

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Application Number Priority Date Filing Date Title
JP2010534980A JP2011505037A (ja) 2007-11-26 2008-11-25 読出しデータバッファリングのシステム及び方法

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US441207P 2007-11-26 2007-11-26
US436207P 2007-11-26 2007-11-26
US436107P 2007-11-26 2007-11-26
US443407P 2007-11-26 2007-11-26
US61/004,412 2007-11-26
US61/004,434 2007-11-26
US61/004,361 2007-11-26
US61/004,362 2007-11-26
US12/276,010 2008-11-21
US12/276,061 US8930593B2 (en) 2007-11-26 2008-11-21 Method for setting parameters and determining latency in a chained device system
US12/276,116 US8601181B2 (en) 2007-11-26 2008-11-21 System and method for read data buffering wherein an arbitration policy determines whether internal or external buffers are given preference
US12/276,010 US8732360B2 (en) 2007-11-26 2008-11-21 System and method for accessing memory
US12/276,143 2008-11-21
US12/276,143 US8874810B2 (en) 2007-11-26 2008-11-21 System and method for read data buffering wherein analyzing policy determines whether to decrement or increment the count of internal or external buffers
US12/276,116 2008-11-21
US12/276,061 2008-11-21

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PCT/US2008/013186 Ceased WO2009070322A1 (en) 2007-11-26 2008-11-25 Systems and methods for read data buffering
PCT/US2008/013188 Ceased WO2009070324A1 (en) 2007-11-26 2008-11-25 A method for setting parameters and determining latency in a chained device system
PCT/US2008/013194 Ceased WO2009070326A1 (en) 2007-11-26 2008-11-25 A system and method for accessing memory

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US20090138624A1 (en) 2009-05-28
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