WO2009069620A1 - Dispositif et procédé de traitement de données - Google Patents

Dispositif et procédé de traitement de données Download PDF

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Publication number
WO2009069620A1
WO2009069620A1 PCT/JP2008/071387 JP2008071387W WO2009069620A1 WO 2009069620 A1 WO2009069620 A1 WO 2009069620A1 JP 2008071387 W JP2008071387 W JP 2008071387W WO 2009069620 A1 WO2009069620 A1 WO 2009069620A1
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
ldpc
parity
code
processing device
Prior art date
Application number
PCT/JP2008/071387
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Yokokawa
Makiko Yamamoto
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Publication of WO2009069620A1 publication Critical patent/WO2009069620A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention concerne un dispositif et un procédé de traitement de données dont la résistance à une erreur de bit de code d'un code LDPC telle qu'une erreur de rafale ou une erreur d'effacement peut être améliorée. L'unité de codage (21) LDPC émet le code LDPC par exécution d'un codage LDPC en fonction d'une matrice de vérification dont la matrice de parité qui constitue une partie correspondant au bit de parité du code LDPC (vérification de parité à faible densité) possède une structure en escalier. Un entrelaceur (23) de parité exécute un entrelaçage de parité qui entrelace le bit de parité du code LDPC émis par l'unité de codage (21) LDPC au niveau de la position d'un autre bit de parité. Le dispositif et le procédé de traitement des données peuvent s'appliquer, par exemple, à un dispositif de transmission destiné à transmettre un code LDPC.
PCT/JP2008/071387 2007-11-26 2008-11-26 Dispositif et procédé de traitement de données WO2009069620A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007304689 2007-11-26
JP2007-304689 2007-11-26
JP2007309914 2007-11-30
JP2007-309914 2007-11-30

Publications (1)

Publication Number Publication Date
WO2009069620A1 true WO2009069620A1 (fr) 2009-06-04

Family

ID=40678515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071387 WO2009069620A1 (fr) 2007-11-26 2008-11-26 Dispositif et procédé de traitement de données

Country Status (2)

Country Link
TW (1) TW201010295A (fr)
WO (1) WO2009069620A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105376008A (zh) * 2014-08-13 2016-03-02 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织映射方法及解交织解映射方法
CN105376030A (zh) * 2014-08-29 2016-03-02 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织和映射方法及解交织解映射方法
CN105450336A (zh) * 2014-08-29 2016-03-30 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织和映射方法及解交织解映射方法
CN111628849A (zh) * 2014-05-22 2020-09-04 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织映射方法及解交织解映射方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5630278B2 (ja) 2010-12-28 2014-11-26 ソニー株式会社 データ処理装置、及びデータ処理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352252A (ja) * 2000-06-08 2001-12-21 Sony Corp 符号化装置及び符号化方法、並びに、復号装置及び復号方法
JP2005051469A (ja) * 2003-07-28 2005-02-24 Sony Corp 符号化装置および符号化方法、並びにプログラム
JP2006254466A (ja) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd 低密度のパリティ検査符号を用いる通信システムにおけるチャンネルインタリービング／デインタリービング装置およびその制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352252A (ja) * 2000-06-08 2001-12-21 Sony Corp 符号化装置及び符号化方法、並びに、復号装置及び復号方法
JP2005051469A (ja) * 2003-07-28 2005-02-24 Sony Corp 符号化装置および符号化方法、並びにプログラム
JP2006254466A (ja) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd 低密度のパリティ検査符号を用いる通信システムにおけるチャンネルインタリービング／デインタリービング装置およびその制御方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111628849A (zh) * 2014-05-22 2020-09-04 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织映射方法及解交织解映射方法
CN105376008A (zh) * 2014-08-13 2016-03-02 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织映射方法及解交织解映射方法
CN105376030A (zh) * 2014-08-29 2016-03-02 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织和映射方法及解交织解映射方法
CN105450336A (zh) * 2014-08-29 2016-03-30 上海数字电视国家工程研究中心有限公司 Ldpc码字的交织和映射方法及解交织解映射方法

Also Published As

Publication number Publication date
TW201010295A (en) 2010-03-01

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