WO2009069620A1 - Data processing device and data processing method - Google Patents

Data processing device and data processing method Download PDF

Info

Publication number
WO2009069620A1
WO2009069620A1 PCT/JP2008/071387 JP2008071387W WO2009069620A1 WO 2009069620 A1 WO2009069620 A1 WO 2009069620A1 JP 2008071387 W JP2008071387 W JP 2008071387W WO 2009069620 A1 WO2009069620 A1 WO 2009069620A1
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
ldpc
parity
code
processing device
Prior art date
Application number
PCT/JP2008/071387
Other languages
French (fr)
Japanese (ja)
Inventor
Takashi Yokokawa
Makiko Yamamoto
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Publication of WO2009069620A1 publication Critical patent/WO2009069620A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving

Abstract

A data processing device and method in which resistance to an error of the code bit of an LDPC code such as a burst error or an erasure can be improved. An LDPC coding section (21) outputs the LDPC code by performing LDPC coding in accordance with a check matrix whose parity matrix which is the part corresponding to the parity bit of the LDPC (Low Density Parity Check) code has a staircase structure. A parity interleaver (23) performs parity interleaving which interleaves the parity bit of the LDPC code outputted by the LDPC coding section (21) into the position of another parity bit. The data processing device and method can be applied to, e.g., a transmitter to transmit an LDPC code.
PCT/JP2008/071387 2007-11-26 2008-11-26 Data processing device and data processing method WO2009069620A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-304689 2007-11-26
JP2007304689 2007-11-26
JP2007-309914 2007-11-30
JP2007309914 2007-11-30

Publications (1)

Publication Number Publication Date
WO2009069620A1 true WO2009069620A1 (en) 2009-06-04

Family

ID=40678515

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071387 WO2009069620A1 (en) 2007-11-26 2008-11-26 Data processing device and data processing method

Country Status (2)

Country Link
TW (1) TW201010295A (en)
WO (1) WO2009069620A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105376030A (en) * 2014-08-29 2016-03-02 上海数字电视国家工程研究中心有限公司 Interleaving and mapping method of LDPC code words and de-interleaving and de-mapping method
CN105376008A (en) * 2014-08-13 2016-03-02 上海数字电视国家工程研究中心有限公司 Low density parity check code (LDPC) word interleaving mapping method and LDPC word de-interleaving demapping method
CN105450336A (en) * 2014-08-29 2016-03-30 上海数字电视国家工程研究中心有限公司 LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method
CN111628849A (en) * 2014-05-22 2020-09-04 上海数字电视国家工程研究中心有限公司 Interleaving mapping method and de-interleaving de-mapping method of LDPC code words

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5630278B2 (en) * 2010-12-28 2014-11-26 ソニー株式会社 Data processing apparatus and data processing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352252A (en) * 2000-06-08 2001-12-21 Sony Corp Encoder and encoding method, and decoder and decoding method
JP2005051469A (en) * 2003-07-28 2005-02-24 Sony Corp Encoding device and encoding method, and program
JP2006254466A (en) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd Apparatus for channel interleaving/deinterleaving in communication system using low density parity check code and control method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352252A (en) * 2000-06-08 2001-12-21 Sony Corp Encoder and encoding method, and decoder and decoding method
JP2005051469A (en) * 2003-07-28 2005-02-24 Sony Corp Encoding device and encoding method, and program
JP2006254466A (en) * 2005-03-11 2006-09-21 Samsung Electronics Co Ltd Apparatus for channel interleaving/deinterleaving in communication system using low density parity check code and control method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111628849A (en) * 2014-05-22 2020-09-04 上海数字电视国家工程研究中心有限公司 Interleaving mapping method and de-interleaving de-mapping method of LDPC code words
CN105376008A (en) * 2014-08-13 2016-03-02 上海数字电视国家工程研究中心有限公司 Low density parity check code (LDPC) word interleaving mapping method and LDPC word de-interleaving demapping method
CN105376030A (en) * 2014-08-29 2016-03-02 上海数字电视国家工程研究中心有限公司 Interleaving and mapping method of LDPC code words and de-interleaving and de-mapping method
CN105450336A (en) * 2014-08-29 2016-03-30 上海数字电视国家工程研究中心有限公司 LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method

Also Published As

Publication number Publication date
TW201010295A (en) 2010-03-01

Similar Documents

Publication Publication Date Title
MY158260A (en) Data processing apparatus and data processing method
WO2009069618A1 (en) Data processing device and data processing method
WO2007142476A3 (en) Method of encoding/decoding using low density check code matrix
EP2086114A3 (en) Concatenated codes combining Reed-Solomon codes, LDPC codes and parity codes for encoding/decoding devices
WO2009069628A1 (en) Data processing device, data processing method, and program
WO2009028886A3 (en) Apparatus and method for transmitting and receiving data in a communication system using low density parity check codes
WO2008149216A3 (en) Computationally efficient convolutional coding with rate-matching
EP1801982A3 (en) Encoder, decoder, methods of encoding and decoding
TW200746653A (en) Systems and methods for achieving higher coding rate using parity interleaving
TW200737737A (en) Encoding and decoding methods and systems
TW200637172A (en) Pruned bit-reversal interleaver
WO2006016751A3 (en) Method of encoding and decoding using low density parity check matrix
WO2010074537A3 (en) Convolutional turbo coding method and device for implementing the coding method
MX2019008248A (en) Coding and decoding of a polar code concatenated with interleaving with an outer systematic code.
WO2008086236A3 (en) Fec code rate selection based on packet size
WO2009036004A3 (en) Multi-layer cyclic redundancy check code in wireless communication system
WO2009069620A1 (en) Data processing device and data processing method
WO2016140516A3 (en) Transmitter and parity permutation method thereof
WO2008124966A8 (en) Radio communication apparatus and redundancy version transmission control method
EP2178217A3 (en) Encoding apparatus and method for low density parity check (LDPC) codes
WO2009053825A3 (en) Method and apparatus for providing adaptive cyclic redundancy check computation
WO2010058994A3 (en) Channel-encoding/decoding apparatus and method using low-density parity-check codes
EP1659727A3 (en) Iterative decoding of packet data
EP2136474A3 (en) Encoding and decoding of low density parity (LDPC) codes for frequency selective channels
MX2015009838A (en) Data processing device and data processing method.

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08855181

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08855181

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP